arch/m32r/platforms/m32700ut/setup.c

   1 /*
   2  *  linux/arch/m32r/platforms/m32700ut/setup.c
   3  *
   4  *  Setup routines for Renesas M32700UT Board
   5  *
   6  *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
   7  *                           Hitoshi Yamamoto, Takeo Takahashi
   8  *
   9  *  This file is subject to the terms and conditions of the GNU General
  10  *  Public License.  See the file "COPYING" in the main directory of this
  11  *  archive for more details.
  12  */
  13
  14 #include <linux/irq.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/platform_device.h>
  18
  19 #include <asm/system.h>
  20 #include <asm/m32r.h>
  21 #include <asm/io.h>
  22
  23 /*
  24  * M32700 Interrupt Control Unit (Level 1)
  25  */
  26 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
  27
  28 icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
  29
  30 static void disable_m32700ut_irq(unsigned int irq)
  31 {
  32         unsigned long port, data;
  33
  34         port = irq2port(irq);
  35         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
  36         outl(data, port);
  37 }
  38
  39 static void enable_m32700ut_irq(unsigned int irq)
  40 {
  41         unsigned long port, data;
  42
  43         port = irq2port(irq);
  44         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
  45         outl(data, port);
  46 }
  47
  48 static void mask_and_ack_m32700ut(unsigned int irq)
  49 {
  50         disable_m32700ut_irq(irq);
  51 }
  52
  53 static void end_m32700ut_irq(unsigned int irq)
  54 {
  55         enable_m32700ut_irq(irq);
  56 }
  57
  58 static unsigned int startup_m32700ut_irq(unsigned int irq)
  59 {
  60         enable_m32700ut_irq(irq);
  61         return (0);
  62 }
  63
  64 static void shutdown_m32700ut_irq(unsigned int irq)
  65 {
  66         unsigned long port;
  67
  68         port = irq2port(irq);
  69         outl(M32R_ICUCR_ILEVEL7, port);
  70 }
  71
  72 static struct irq_chip m32700ut_irq_type =
  73 {
  74         .name = "M32700UT-IRQ",
  75         .startup = startup_m32700ut_irq,
  76         .shutdown = shutdown_m32700ut_irq,
  77         .enable = enable_m32700ut_irq,
  78         .disable = disable_m32700ut_irq,
  79         .ack = mask_and_ack_m32700ut,
  80         .end = end_m32700ut_irq
  81 };
  82
  83 /*
  84  * Interrupt Control Unit of PLD on M32700UT (Level 2)
  85  */
  86 #define irq2pldirq(x)           ((x) - M32700UT_PLD_IRQ_BASE)
  87 #define pldirq2port(x)          (unsigned long)((int)PLD_ICUCR1 + \
  88                                  (((x) - 1) * sizeof(unsigned short)))
  89
  90 typedef struct {
  91         unsigned short icucr;  /* ICU Control Register */
  92 } pld_icu_data_t;
  93
  94 static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
  95
  96 static void disable_m32700ut_pld_irq(unsigned int irq)
  97 {
  98         unsigned long port, data;
  99         unsigned int pldirq;
 100
 101         pldirq = irq2pldirq(irq);
 102 //      disable_m32700ut_irq(M32R_IRQ_INT1);
 103         port = pldirq2port(pldirq);
 104         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
 105         outw(data, port);
 106 }
 107
 108 static void enable_m32700ut_pld_irq(unsigned int irq)
 109 {
 110         unsigned long port, data;
 111         unsigned int pldirq;
 112
 113         pldirq = irq2pldirq(irq);
 114 //      enable_m32700ut_irq(M32R_IRQ_INT1);
 115         port = pldirq2port(pldirq);
 116         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 117         outw(data, port);
 118 }
 119
 120 static void mask_and_ack_m32700ut_pld(unsigned int irq)
 121 {
 122         disable_m32700ut_pld_irq(irq);
 123 //      mask_and_ack_m32700ut(M32R_IRQ_INT1);
 124 }
 125
 126 static void end_m32700ut_pld_irq(unsigned int irq)
 127 {
 128         enable_m32700ut_pld_irq(irq);
 129         end_m32700ut_irq(M32R_IRQ_INT1);
 130 }
 131
 132 static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
 133 {
 134         enable_m32700ut_pld_irq(irq);
 135         return (0);
 136 }
 137
 138 static void shutdown_m32700ut_pld_irq(unsigned int irq)
 139 {
 140         unsigned long port;
 141         unsigned int pldirq;
 142
 143         pldirq = irq2pldirq(irq);
 144 //      shutdown_m32700ut_irq(M32R_IRQ_INT1);
 145         port = pldirq2port(pldirq);
 146         outw(PLD_ICUCR_ILEVEL7, port);
 147 }
 148
 149 static struct irq_chip m32700ut_pld_irq_type =
 150 {
 151         .name = "M32700UT-PLD-IRQ",
 152         .startup = startup_m32700ut_pld_irq,
 153         .shutdown = shutdown_m32700ut_pld_irq,
 154         .enable = enable_m32700ut_pld_irq,
 155         .disable = disable_m32700ut_pld_irq,
 156         .ack = mask_and_ack_m32700ut_pld,
 157         .end = end_m32700ut_pld_irq
 158 };
 159
 160 /*
 161  * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
 162  */
 163 #define irq2lanpldirq(x)        ((x) - M32700UT_LAN_PLD_IRQ_BASE)
 164 #define lanpldirq2port(x)       (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
 165                                  (((x) - 1) * sizeof(unsigned short)))
 166
 167 static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
 168
 169 static void disable_m32700ut_lanpld_irq(unsigned int irq)
 170 {
 171         unsigned long port, data;
 172         unsigned int pldirq;
 173
 174         pldirq = irq2lanpldirq(irq);
 175         port = lanpldirq2port(pldirq);
 176         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
 177         outw(data, port);
 178 }
 179
 180 static void enable_m32700ut_lanpld_irq(unsigned int irq)
 181 {
 182         unsigned long port, data;
 183         unsigned int pldirq;
 184
 185         pldirq = irq2lanpldirq(irq);
 186         port = lanpldirq2port(pldirq);
 187         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 188         outw(data, port);
 189 }
 190
 191 static void mask_and_ack_m32700ut_lanpld(unsigned int irq)
 192 {
 193         disable_m32700ut_lanpld_irq(irq);
 194 }
 195
 196 static void end_m32700ut_lanpld_irq(unsigned int irq)
 197 {
 198         enable_m32700ut_lanpld_irq(irq);
 199         end_m32700ut_irq(M32R_IRQ_INT0);
 200 }
 201
 202 static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
 203 {
 204         enable_m32700ut_lanpld_irq(irq);
 205         return (0);
 206 }
 207
 208 static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
 209 {
 210         unsigned long port;
 211         unsigned int pldirq;
 212
 213         pldirq = irq2lanpldirq(irq);
 214         port = lanpldirq2port(pldirq);
 215         outw(PLD_ICUCR_ILEVEL7, port);
 216 }
 217
 218 static struct irq_chip m32700ut_lanpld_irq_type =
 219 {
 220         .name = "M32700UT-PLD-LAN-IRQ",
 221         .startup = startup_m32700ut_lanpld_irq,
 222         .shutdown = shutdown_m32700ut_lanpld_irq,
 223         .enable = enable_m32700ut_lanpld_irq,
 224         .disable = disable_m32700ut_lanpld_irq,
 225         .ack = mask_and_ack_m32700ut_lanpld,
 226         .end = end_m32700ut_lanpld_irq
 227 };
 228
 229 /*
 230  * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
 231  */
 232 #define irq2lcdpldirq(x)        ((x) - M32700UT_LCD_PLD_IRQ_BASE)
 233 #define lcdpldirq2port(x)       (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
 234                                  (((x) - 1) * sizeof(unsigned short)))
 235
 236 static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
 237
 238 static void disable_m32700ut_lcdpld_irq(unsigned int irq)
 239 {
 240         unsigned long port, data;
 241         unsigned int pldirq;
 242
 243         pldirq = irq2lcdpldirq(irq);
 244         port = lcdpldirq2port(pldirq);
 245         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
 246         outw(data, port);
 247 }
 248
 249 static void enable_m32700ut_lcdpld_irq(unsigned int irq)
 250 {
 251         unsigned long port, data;
 252         unsigned int pldirq;
 253
 254         pldirq = irq2lcdpldirq(irq);
 255         port = lcdpldirq2port(pldirq);
 256         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 257         outw(data, port);
 258 }
 259
 260 static void mask_and_ack_m32700ut_lcdpld(unsigned int irq)
 261 {
 262         disable_m32700ut_lcdpld_irq(irq);
 263 }
 264
 265 static void end_m32700ut_lcdpld_irq(unsigned int irq)
 266 {
 267         enable_m32700ut_lcdpld_irq(irq);
 268         end_m32700ut_irq(M32R_IRQ_INT2);
 269 }
 270
 271 static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
 272 {
 273         enable_m32700ut_lcdpld_irq(irq);
 274         return (0);
 275 }
 276
 277 static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
 278 {
 279         unsigned long port;
 280         unsigned int pldirq;
 281
 282         pldirq = irq2lcdpldirq(irq);
 283         port = lcdpldirq2port(pldirq);
 284         outw(PLD_ICUCR_ILEVEL7, port);
 285 }
 286
 287 static struct irq_chip m32700ut_lcdpld_irq_type =
 288 {
 289         .name = "M32700UT-PLD-LCD-IRQ",
 290         .startup = startup_m32700ut_lcdpld_irq,
 291         .shutdown = shutdown_m32700ut_lcdpld_irq,
 292         .enable = enable_m32700ut_lcdpld_irq,
 293         .disable = disable_m32700ut_lcdpld_irq,
 294         .ack = mask_and_ack_m32700ut_lcdpld,
 295         .end = end_m32700ut_lcdpld_irq
 296 };
 297
 298 void __init init_IRQ(void)
 299 {
 300 #if defined(CONFIG_SMC91X)
 301         /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
 302         set_irq_chip(M32700UT_LAN_IRQ_LAN, &m32700ut_lanpld_irq_type);
 303         lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;   /* "H" edge sense */
 304         disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
 305 #endif  /* CONFIG_SMC91X */
 306
 307         /* MFT2 : system timer */
 308         set_irq_chip(M32R_IRQ_MFT2, &m32700ut_irq_type);
 309         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
 310         disable_m32700ut_irq(M32R_IRQ_MFT2);
 311
 312         /* SIO0 : receive */
 313         set_irq_chip(M32R_IRQ_SIO0_R, &m32700ut_irq_type);
 314         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
 315         disable_m32700ut_irq(M32R_IRQ_SIO0_R);
 316
 317         /* SIO0 : send */
 318         set_irq_chip(M32R_IRQ_SIO0_S, &m32700ut_irq_type);
 319         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
 320         disable_m32700ut_irq(M32R_IRQ_SIO0_S);
 321
 322         /* SIO1 : receive */
 323         set_irq_chip(M32R_IRQ_SIO1_R, &m32700ut_irq_type);
 324         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
 325         disable_m32700ut_irq(M32R_IRQ_SIO1_R);
 326
 327         /* SIO1 : send */
 328         set_irq_chip(M32R_IRQ_SIO1_S, &m32700ut_irq_type);
 329         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
 330         disable_m32700ut_irq(M32R_IRQ_SIO1_S);
 331
 332         /* DMA1 : */
 333         set_irq_chip(M32R_IRQ_DMA1, &m32700ut_irq_type);
 334         icu_data[M32R_IRQ_DMA1].icucr = 0;
 335         disable_m32700ut_irq(M32R_IRQ_DMA1);
 336
 337 #ifdef CONFIG_SERIAL_M32R_PLDSIO
 338         /* INT#1: SIO0 Receive on PLD */
 339         set_irq_chip(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type);
 340         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
 341         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
 342
 343         /* INT#1: SIO0 Send on PLD */
 344         set_irq_chip(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type);
 345         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
 346         disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
 347 #endif  /* CONFIG_SERIAL_M32R_PLDSIO */
 348
 349         /* INT#1: CFC IREQ on PLD */
 350         set_irq_chip(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type);
 351         pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;       /* 'L' level sense */
 352         disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
 353
 354         /* INT#1: CFC Insert on PLD */
 355         set_irq_chip(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type);
 356         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;   /* 'L' edge sense */
 357         disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
 358
 359         /* INT#1: CFC Eject on PLD */
 360         set_irq_chip(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type);
 361         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;    /* 'H' edge sense */
 362         disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
 363
 364         /*
 365          * INT0# is used for LAN, DIO
 366          * We enable it here.
 367          */
 368         icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
 369         enable_m32700ut_irq(M32R_IRQ_INT0);
 370
 371         /*
 372          * INT1# is used for UART, MMC, CF Controller in FPGA.
 373          * We enable it here.
 374          */
 375         icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
 376         enable_m32700ut_irq(M32R_IRQ_INT1);
 377
 378 #if defined(CONFIG_USB)
 379         outw(USBCR_OTGS, USBCR);        /* USBCR: non-OTG */
 380         set_irq_chip(M32700UT_LCD_IRQ_USB_INT1, &m32700ut_lcdpld_irq_type);
 381
 382         lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;      /* "L" level sense */
 383         disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
 384 #endif
 385         /*
 386          * INT2# is used for BAT, USB, AUDIO
 387          * We enable it here.
 388          */
 389         icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
 390         enable_m32700ut_irq(M32R_IRQ_INT2);
 391
 392 #if defined(CONFIG_VIDEO_M32R_AR)
 393         /*
 394          * INT3# is used for AR
 395          */
 396         set_irq_chip(M32R_IRQ_INT3, &m32700ut_irq_type);
 397         icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
 398         disable_m32700ut_irq(M32R_IRQ_INT3);
 399 #endif  /* CONFIG_VIDEO_M32R_AR */
 400 }
 401
 402 #if defined(CONFIG_SMC91X)
 403
 404 #define LAN_IOSTART     0x300
 405 #define LAN_IOEND       0x320
 406 static struct resource smc91x_resources[] = {
 407         [0] = {
 408                 .start  = (LAN_IOSTART),
 409                 .end    = (LAN_IOEND),
 410                 .flags  = IORESOURCE_MEM,
 411         },
 412         [1] = {
 413                 .start  = M32700UT_LAN_IRQ_LAN,
 414                 .end    = M32700UT_LAN_IRQ_LAN,
 415                 .flags  = IORESOURCE_IRQ,
 416         }
 417 };
 418
 419 static struct platform_device smc91x_device = {
 420         .name           = "smc91x",
 421         .id             = 0,
 422         .num_resources  = ARRAY_SIZE(smc91x_resources),
 423         .resource       = smc91x_resources,
 424 };
 425 #endif
 426
 427 #if defined(CONFIG_FB_S1D13XXX)
 428
 429 #include <video/s1d13xxxfb.h>
 430 #include <asm/s1d13806.h>
 431
 432 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
 433         .initregs               = s1d13xxxfb_initregs,
 434         .initregssize           = ARRAY_SIZE(s1d13xxxfb_initregs),
 435         .platform_init_video    = NULL,
 436 #ifdef CONFIG_PM
 437         .platform_suspend_video = NULL,
 438         .platform_resume_video  = NULL,
 439 #endif
 440 };
 441
 442 static struct resource s1d13xxxfb_resources[] = {
 443         [0] = {
 444                 .start  = 0x10600000UL,
 445                 .end    = 0x1073FFFFUL,
 446                 .flags  = IORESOURCE_MEM,
 447         },
 448         [1] = {
 449                 .start  = 0x10400000UL,
 450                 .end    = 0x104001FFUL,
 451                 .flags  = IORESOURCE_MEM,
 452         }
 453 };
 454
 455 static struct platform_device s1d13xxxfb_device = {
 456         .name           = S1D_DEVICENAME,
 457         .id             = 0,
 458         .dev            = {
 459                 .platform_data  = &s1d13xxxfb_data,
 460         },
 461         .num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
 462         .resource       = s1d13xxxfb_resources,
 463 };
 464 #endif
 465
 466 static int __init platform_init(void)
 467 {
 468 #if defined(CONFIG_SMC91X)
 469         platform_device_register(&smc91x_device);
 470 #endif
 471 #if defined(CONFIG_FB_S1D13XXX)
 472         platform_device_register(&s1d13xxxfb_device);
 473 #endif
 474         return 0;
 475 }
 476 arch_initcall(platform_init);