2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__FUNCTION__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work
= 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit
= 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
65 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
68 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
69 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
70 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72 #define R8169_REGS_SIZE 256
73 #define R8169_NAPI_WEIGHT 64
74 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
75 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
76 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
77 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
78 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80 #define RTL8169_TX_TIMEOUT (6*HZ)
81 #define RTL8169_PHY_TIMEOUT (10*HZ)
83 /* write/read MMIO register */
84 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
85 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
86 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
87 #define RTL_R8(reg) readb (ioaddr + (reg))
88 #define RTL_R16(reg) readw (ioaddr + (reg))
89 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
92 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
93 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
94 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
95 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
96 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
97 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
98 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
99 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
100 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
101 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
102 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
103 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
104 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
105 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
106 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
107 RTL_GIGA_MAC_VER_20
= 0x14 // 8168C
110 #define _R(NAME,MAC,MASK) \
111 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
113 static const struct {
116 u32 RxConfigMask
; /* Clears the bits supported by this chip */
117 } rtl_chip_info
[] = {
118 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
119 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
120 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
121 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
122 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
123 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
124 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
125 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
126 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
127 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
128 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
129 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
130 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
131 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
132 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
133 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880) // PCI-E
143 static void rtl_hw_start_8169(struct net_device
*);
144 static void rtl_hw_start_8168(struct net_device
*);
145 static void rtl_hw_start_8101(struct net_device
*);
147 static struct pci_device_id rtl8169_pci_tbl
[] = {
148 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
149 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
150 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
151 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
152 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
153 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
154 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
155 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
156 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
157 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
159 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
163 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
165 static int rx_copybreak
= 200;
172 MAC0
= 0, /* Ethernet hardware address. */
174 MAR0
= 8, /* Multicast filter. */
175 CounterAddrLow
= 0x10,
176 CounterAddrHigh
= 0x14,
177 TxDescStartAddrLow
= 0x20,
178 TxDescStartAddrHigh
= 0x24,
179 TxHDescStartAddrLow
= 0x28,
180 TxHDescStartAddrHigh
= 0x2c,
206 RxDescAddrLow
= 0xe4,
207 RxDescAddrHigh
= 0xe8,
210 FuncEventMask
= 0xf4,
211 FuncPresetState
= 0xf8,
212 FuncForceEvent
= 0xfc,
215 enum rtl_register_content
{
216 /* InterruptStatusBits */
220 TxDescUnavail
= 0x0080,
242 /* TXPoll register p.5 */
243 HPQ
= 0x80, /* Poll cmd on the high prio queue */
244 NPQ
= 0x40, /* Poll cmd on the low prio queue */
245 FSWInt
= 0x01, /* Forced software interrupt */
249 Cfg9346_Unlock
= 0xc0,
254 AcceptBroadcast
= 0x08,
255 AcceptMulticast
= 0x04,
257 AcceptAllPhys
= 0x01,
264 TxInterFrameGapShift
= 24,
265 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
267 /* Config1 register p.24 */
268 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
269 PMEnable
= (1 << 0), /* Power Management Enable */
271 /* Config2 register p. 25 */
272 PCI_Clock_66MHz
= 0x01,
273 PCI_Clock_33MHz
= 0x00,
275 /* Config3 register p.25 */
276 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
277 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
279 /* Config5 register p.27 */
280 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
282 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
283 LanWake
= (1 << 1), /* LanWake enable/disable */
284 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
287 TBIReset
= 0x80000000,
288 TBILoopback
= 0x40000000,
289 TBINwEnable
= 0x20000000,
290 TBINwRestart
= 0x10000000,
291 TBILinkOk
= 0x02000000,
292 TBINwComplete
= 0x01000000,
295 PktCntrDisable
= (1 << 7), // 8168
300 INTT_0
= 0x0000, // 8168
301 INTT_1
= 0x0001, // 8168
302 INTT_2
= 0x0002, // 8168
303 INTT_3
= 0x0003, // 8168
305 /* rtl8169_PHYstatus */
316 TBILinkOK
= 0x02000000,
318 /* DumpCounterCommand */
322 enum desc_status_bit
{
323 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
324 RingEnd
= (1 << 30), /* End of descriptor ring */
325 FirstFrag
= (1 << 29), /* First segment of a packet */
326 LastFrag
= (1 << 28), /* Final segment of a packet */
329 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
330 MSSShift
= 16, /* MSS value position */
331 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
332 IPCS
= (1 << 18), /* Calculate IP checksum */
333 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
334 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
335 TxVlanTag
= (1 << 17), /* Add VLAN tag */
338 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
339 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
341 #define RxProtoUDP (PID1)
342 #define RxProtoTCP (PID0)
343 #define RxProtoIP (PID1 | PID0)
344 #define RxProtoMask RxProtoIP
346 IPFail
= (1 << 16), /* IP checksum failed */
347 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
348 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
349 RxVlanTag
= (1 << 16), /* VLAN tag available */
352 #define RsvdMask 0x3fffc000
369 u8 __pad
[sizeof(void *) - sizeof(u32
)];
373 RTL_FEATURE_WOL
= (1 << 0),
374 RTL_FEATURE_MSI
= (1 << 1),
375 RTL_FEATURE_GMII
= (1 << 2),
378 struct rtl8169_private
{
379 void __iomem
*mmio_addr
; /* memory map physical address */
380 struct pci_dev
*pci_dev
; /* Index of PCI device */
381 struct net_device
*dev
;
382 struct napi_struct napi
;
383 spinlock_t lock
; /* spin lock flag */
387 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
388 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
391 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
392 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
393 dma_addr_t TxPhyAddr
;
394 dma_addr_t RxPhyAddr
;
395 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
396 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
399 struct timer_list timer
;
404 int phy_auto_nego_reg
;
405 int phy_1000_ctrl_reg
;
406 #ifdef CONFIG_R8169_VLAN
407 struct vlan_group
*vlgrp
;
409 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
410 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
411 void (*phy_reset_enable
)(void __iomem
*);
412 void (*hw_start
)(struct net_device
*);
413 unsigned int (*phy_reset_pending
)(void __iomem
*);
414 unsigned int (*link_ok
)(void __iomem
*);
415 struct delayed_work task
;
418 struct mii_if_info mii
;
421 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
422 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
423 module_param(rx_copybreak
, int, 0);
424 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
425 module_param(use_dac
, int, 0);
426 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
427 module_param_named(debug
, debug
.msg_enable
, int, 0);
428 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
429 MODULE_LICENSE("GPL");
430 MODULE_VERSION(RTL8169_VERSION
);
432 static int rtl8169_open(struct net_device
*dev
);
433 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
434 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
435 static int rtl8169_init_ring(struct net_device
*dev
);
436 static void rtl_hw_start(struct net_device
*dev
);
437 static int rtl8169_close(struct net_device
*dev
);
438 static void rtl_set_rx_mode(struct net_device
*dev
);
439 static void rtl8169_tx_timeout(struct net_device
*dev
);
440 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
441 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
442 void __iomem
*, u32 budget
);
443 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
444 static void rtl8169_down(struct net_device
*dev
);
445 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
446 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
448 static const unsigned int rtl8169_rx_config
=
449 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
451 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
455 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
457 for (i
= 20; i
> 0; i
--) {
459 * Check if the RTL8169 has completed writing to the specified
462 if (!(RTL_R32(PHYAR
) & 0x80000000))
468 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
472 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
474 for (i
= 20; i
> 0; i
--) {
476 * Check if the RTL8169 has completed retrieving data from
477 * the specified MII register.
479 if (RTL_R32(PHYAR
) & 0x80000000) {
480 value
= RTL_R32(PHYAR
) & 0xffff;
488 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
491 struct rtl8169_private
*tp
= netdev_priv(dev
);
492 void __iomem
*ioaddr
= tp
->mmio_addr
;
494 mdio_write(ioaddr
, location
, val
);
497 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
499 struct rtl8169_private
*tp
= netdev_priv(dev
);
500 void __iomem
*ioaddr
= tp
->mmio_addr
;
502 return mdio_read(ioaddr
, location
);
505 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
507 RTL_W16(IntrMask
, 0x0000);
509 RTL_W16(IntrStatus
, 0xffff);
512 static void rtl8169_asic_down(void __iomem
*ioaddr
)
514 RTL_W8(ChipCmd
, 0x00);
515 rtl8169_irq_mask_and_ack(ioaddr
);
519 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
521 return RTL_R32(TBICSR
) & TBIReset
;
524 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
526 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
529 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
531 return RTL_R32(TBICSR
) & TBILinkOk
;
534 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
536 return RTL_R8(PHYstatus
) & LinkStatus
;
539 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
541 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
544 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
548 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
549 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
552 static void rtl8169_check_link_status(struct net_device
*dev
,
553 struct rtl8169_private
*tp
,
554 void __iomem
*ioaddr
)
558 spin_lock_irqsave(&tp
->lock
, flags
);
559 if (tp
->link_ok(ioaddr
)) {
560 netif_carrier_on(dev
);
561 if (netif_msg_ifup(tp
))
562 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
564 if (netif_msg_ifdown(tp
))
565 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
566 netif_carrier_off(dev
);
568 spin_unlock_irqrestore(&tp
->lock
, flags
);
571 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
573 struct rtl8169_private
*tp
= netdev_priv(dev
);
574 void __iomem
*ioaddr
= tp
->mmio_addr
;
579 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
580 wol
->supported
= WAKE_ANY
;
582 spin_lock_irq(&tp
->lock
);
584 options
= RTL_R8(Config1
);
585 if (!(options
& PMEnable
))
588 options
= RTL_R8(Config3
);
589 if (options
& LinkUp
)
590 wol
->wolopts
|= WAKE_PHY
;
591 if (options
& MagicPacket
)
592 wol
->wolopts
|= WAKE_MAGIC
;
594 options
= RTL_R8(Config5
);
596 wol
->wolopts
|= WAKE_UCAST
;
598 wol
->wolopts
|= WAKE_BCAST
;
600 wol
->wolopts
|= WAKE_MCAST
;
603 spin_unlock_irq(&tp
->lock
);
606 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
608 struct rtl8169_private
*tp
= netdev_priv(dev
);
609 void __iomem
*ioaddr
= tp
->mmio_addr
;
616 { WAKE_ANY
, Config1
, PMEnable
},
617 { WAKE_PHY
, Config3
, LinkUp
},
618 { WAKE_MAGIC
, Config3
, MagicPacket
},
619 { WAKE_UCAST
, Config5
, UWF
},
620 { WAKE_BCAST
, Config5
, BWF
},
621 { WAKE_MCAST
, Config5
, MWF
},
622 { WAKE_ANY
, Config5
, LanWake
}
625 spin_lock_irq(&tp
->lock
);
627 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
629 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
630 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
631 if (wol
->wolopts
& cfg
[i
].opt
)
632 options
|= cfg
[i
].mask
;
633 RTL_W8(cfg
[i
].reg
, options
);
636 RTL_W8(Cfg9346
, Cfg9346_Lock
);
639 tp
->features
|= RTL_FEATURE_WOL
;
641 tp
->features
&= ~RTL_FEATURE_WOL
;
643 spin_unlock_irq(&tp
->lock
);
648 static void rtl8169_get_drvinfo(struct net_device
*dev
,
649 struct ethtool_drvinfo
*info
)
651 struct rtl8169_private
*tp
= netdev_priv(dev
);
653 strcpy(info
->driver
, MODULENAME
);
654 strcpy(info
->version
, RTL8169_VERSION
);
655 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
658 static int rtl8169_get_regs_len(struct net_device
*dev
)
660 return R8169_REGS_SIZE
;
663 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
664 u8 autoneg
, u16 speed
, u8 duplex
)
666 struct rtl8169_private
*tp
= netdev_priv(dev
);
667 void __iomem
*ioaddr
= tp
->mmio_addr
;
671 reg
= RTL_R32(TBICSR
);
672 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
673 (duplex
== DUPLEX_FULL
)) {
674 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
675 } else if (autoneg
== AUTONEG_ENABLE
)
676 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
678 if (netif_msg_link(tp
)) {
679 printk(KERN_WARNING
"%s: "
680 "incorrect speed setting refused in TBI mode\n",
689 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
690 u8 autoneg
, u16 speed
, u8 duplex
)
692 struct rtl8169_private
*tp
= netdev_priv(dev
);
693 void __iomem
*ioaddr
= tp
->mmio_addr
;
694 int auto_nego
, giga_ctrl
;
696 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
697 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
698 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
699 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
700 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
702 if (autoneg
== AUTONEG_ENABLE
) {
703 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
704 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
705 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
707 if (speed
== SPEED_10
)
708 auto_nego
|= ADVERTISE_10HALF
| ADVERTISE_10FULL
;
709 else if (speed
== SPEED_100
)
710 auto_nego
|= ADVERTISE_100HALF
| ADVERTISE_100FULL
;
711 else if (speed
== SPEED_1000
)
712 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
714 if (duplex
== DUPLEX_HALF
)
715 auto_nego
&= ~(ADVERTISE_10FULL
| ADVERTISE_100FULL
);
717 if (duplex
== DUPLEX_FULL
)
718 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_100HALF
);
720 /* This tweak comes straight from Realtek's driver. */
721 if ((speed
== SPEED_100
) && (duplex
== DUPLEX_HALF
) &&
722 ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
723 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
))) {
724 auto_nego
= ADVERTISE_100HALF
| ADVERTISE_CSMA
;
728 /* The 8100e/8101e do Fast Ethernet only. */
729 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
730 (tp
->mac_version
== RTL_GIGA_MAC_VER_14
) ||
731 (tp
->mac_version
== RTL_GIGA_MAC_VER_15
) ||
732 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
733 if ((giga_ctrl
& (ADVERTISE_1000FULL
| ADVERTISE_1000HALF
)) &&
734 netif_msg_link(tp
)) {
735 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
738 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
741 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
743 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
744 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
745 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
748 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
750 mdio_write(ioaddr
, 0x1f, 0x0000);
751 mdio_write(ioaddr
, 0x0e, 0x0000);
754 tp
->phy_auto_nego_reg
= auto_nego
;
755 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
757 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
758 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
759 mdio_write(ioaddr
, MII_BMCR
, BMCR_ANENABLE
| BMCR_ANRESTART
);
763 static int rtl8169_set_speed(struct net_device
*dev
,
764 u8 autoneg
, u16 speed
, u8 duplex
)
766 struct rtl8169_private
*tp
= netdev_priv(dev
);
769 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
771 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
772 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
777 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
779 struct rtl8169_private
*tp
= netdev_priv(dev
);
783 spin_lock_irqsave(&tp
->lock
, flags
);
784 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
785 spin_unlock_irqrestore(&tp
->lock
, flags
);
790 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
792 struct rtl8169_private
*tp
= netdev_priv(dev
);
794 return tp
->cp_cmd
& RxChkSum
;
797 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
799 struct rtl8169_private
*tp
= netdev_priv(dev
);
800 void __iomem
*ioaddr
= tp
->mmio_addr
;
803 spin_lock_irqsave(&tp
->lock
, flags
);
806 tp
->cp_cmd
|= RxChkSum
;
808 tp
->cp_cmd
&= ~RxChkSum
;
810 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
813 spin_unlock_irqrestore(&tp
->lock
, flags
);
818 #ifdef CONFIG_R8169_VLAN
820 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
823 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
824 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
827 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
828 struct vlan_group
*grp
)
830 struct rtl8169_private
*tp
= netdev_priv(dev
);
831 void __iomem
*ioaddr
= tp
->mmio_addr
;
834 spin_lock_irqsave(&tp
->lock
, flags
);
837 tp
->cp_cmd
|= RxVlan
;
839 tp
->cp_cmd
&= ~RxVlan
;
840 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
842 spin_unlock_irqrestore(&tp
->lock
, flags
);
845 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
848 u32 opts2
= le32_to_cpu(desc
->opts2
);
849 struct vlan_group
*vlgrp
= tp
->vlgrp
;
852 if (vlgrp
&& (opts2
& RxVlanTag
)) {
853 vlan_hwaccel_receive_skb(skb
, vlgrp
, swab16(opts2
& 0xffff));
861 #else /* !CONFIG_R8169_VLAN */
863 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
869 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
877 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
879 struct rtl8169_private
*tp
= netdev_priv(dev
);
880 void __iomem
*ioaddr
= tp
->mmio_addr
;
884 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
885 cmd
->port
= PORT_FIBRE
;
886 cmd
->transceiver
= XCVR_INTERNAL
;
888 status
= RTL_R32(TBICSR
);
889 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
890 cmd
->autoneg
= !!(status
& TBINwEnable
);
892 cmd
->speed
= SPEED_1000
;
893 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
898 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
900 struct rtl8169_private
*tp
= netdev_priv(dev
);
902 return mii_ethtool_gset(&tp
->mii
, cmd
);
905 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
907 struct rtl8169_private
*tp
= netdev_priv(dev
);
911 spin_lock_irqsave(&tp
->lock
, flags
);
913 rc
= tp
->get_settings(dev
, cmd
);
915 spin_unlock_irqrestore(&tp
->lock
, flags
);
919 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
922 struct rtl8169_private
*tp
= netdev_priv(dev
);
925 if (regs
->len
> R8169_REGS_SIZE
)
926 regs
->len
= R8169_REGS_SIZE
;
928 spin_lock_irqsave(&tp
->lock
, flags
);
929 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
930 spin_unlock_irqrestore(&tp
->lock
, flags
);
933 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
935 struct rtl8169_private
*tp
= netdev_priv(dev
);
937 return tp
->msg_enable
;
940 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
942 struct rtl8169_private
*tp
= netdev_priv(dev
);
944 tp
->msg_enable
= value
;
947 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
954 "tx_single_collisions",
955 "tx_multi_collisions",
963 struct rtl8169_counters
{
970 __le32 tx_one_collision
;
971 __le32 tx_multi_collision
;
979 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
983 return ARRAY_SIZE(rtl8169_gstrings
);
989 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
990 struct ethtool_stats
*stats
, u64
*data
)
992 struct rtl8169_private
*tp
= netdev_priv(dev
);
993 void __iomem
*ioaddr
= tp
->mmio_addr
;
994 struct rtl8169_counters
*counters
;
1000 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1004 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1005 cmd
= (u64
)paddr
& DMA_32BIT_MASK
;
1006 RTL_W32(CounterAddrLow
, cmd
);
1007 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1009 while (RTL_R32(CounterAddrLow
) & CounterDump
) {
1010 if (msleep_interruptible(1))
1014 RTL_W32(CounterAddrLow
, 0);
1015 RTL_W32(CounterAddrHigh
, 0);
1017 data
[0] = le64_to_cpu(counters
->tx_packets
);
1018 data
[1] = le64_to_cpu(counters
->rx_packets
);
1019 data
[2] = le64_to_cpu(counters
->tx_errors
);
1020 data
[3] = le32_to_cpu(counters
->rx_errors
);
1021 data
[4] = le16_to_cpu(counters
->rx_missed
);
1022 data
[5] = le16_to_cpu(counters
->align_errors
);
1023 data
[6] = le32_to_cpu(counters
->tx_one_collision
);
1024 data
[7] = le32_to_cpu(counters
->tx_multi_collision
);
1025 data
[8] = le64_to_cpu(counters
->rx_unicast
);
1026 data
[9] = le64_to_cpu(counters
->rx_broadcast
);
1027 data
[10] = le32_to_cpu(counters
->rx_multicast
);
1028 data
[11] = le16_to_cpu(counters
->tx_aborted
);
1029 data
[12] = le16_to_cpu(counters
->tx_underun
);
1031 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1034 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1038 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1043 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1044 .get_drvinfo
= rtl8169_get_drvinfo
,
1045 .get_regs_len
= rtl8169_get_regs_len
,
1046 .get_link
= ethtool_op_get_link
,
1047 .get_settings
= rtl8169_get_settings
,
1048 .set_settings
= rtl8169_set_settings
,
1049 .get_msglevel
= rtl8169_get_msglevel
,
1050 .set_msglevel
= rtl8169_set_msglevel
,
1051 .get_rx_csum
= rtl8169_get_rx_csum
,
1052 .set_rx_csum
= rtl8169_set_rx_csum
,
1053 .set_tx_csum
= ethtool_op_set_tx_csum
,
1054 .set_sg
= ethtool_op_set_sg
,
1055 .set_tso
= ethtool_op_set_tso
,
1056 .get_regs
= rtl8169_get_regs
,
1057 .get_wol
= rtl8169_get_wol
,
1058 .set_wol
= rtl8169_set_wol
,
1059 .get_strings
= rtl8169_get_strings
,
1060 .get_sset_count
= rtl8169_get_sset_count
,
1061 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1064 static void rtl8169_write_gmii_reg_bit(void __iomem
*ioaddr
, int reg
,
1065 int bitnum
, int bitval
)
1069 val
= mdio_read(ioaddr
, reg
);
1070 val
= (bitval
== 1) ?
1071 val
| (bitval
<< bitnum
) : val
& ~(0x0001 << bitnum
);
1072 mdio_write(ioaddr
, reg
, val
& 0xffff);
1075 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1076 void __iomem
*ioaddr
)
1079 * The driver currently handles the 8168Bf and the 8168Be identically
1080 * but they can be identified more specifically through the test below
1083 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1085 * Same thing for the 8101Eb and the 8101Ec:
1087 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1095 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1096 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1097 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1098 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20
},
1101 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1102 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1103 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1104 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1107 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1108 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1109 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1110 /* FIXME: where did these entries come from ? -- FR */
1111 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1112 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1115 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1116 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1117 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1118 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1119 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1120 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1122 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01
} /* Catch-all */
1126 reg
= RTL_R32(TxConfig
);
1127 while ((reg
& p
->mask
) != p
->val
)
1129 tp
->mac_version
= p
->mac_version
;
1131 if (p
->mask
== 0x00000000) {
1132 struct pci_dev
*pdev
= tp
->pci_dev
;
1134 dev_info(&pdev
->dev
, "unknown MAC (%08x)\n", reg
);
1138 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1140 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1148 static void rtl_phy_write(void __iomem
*ioaddr
, struct phy_reg
*regs
, int len
)
1151 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1156 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1159 u16 regs
[5]; /* Beware of bit-sign propagation */
1160 } phy_magic
[5] = { {
1161 { 0x0000, //w 4 15 12 0
1162 0x00a1, //w 3 15 0 00a1
1163 0x0008, //w 2 15 0 0008
1164 0x1020, //w 1 15 0 1020
1165 0x1000 } },{ //w 0 15 0 1000
1166 { 0x7000, //w 4 15 12 7
1167 0xff41, //w 3 15 0 ff41
1168 0xde60, //w 2 15 0 de60
1169 0x0140, //w 1 15 0 0140
1170 0x0077 } },{ //w 0 15 0 0077
1171 { 0xa000, //w 4 15 12 a
1172 0xdf01, //w 3 15 0 df01
1173 0xdf20, //w 2 15 0 df20
1174 0xff95, //w 1 15 0 ff95
1175 0xfa00 } },{ //w 0 15 0 fa00
1176 { 0xb000, //w 4 15 12 b
1177 0xff41, //w 3 15 0 ff41
1178 0xde20, //w 2 15 0 de20
1179 0x0140, //w 1 15 0 0140
1180 0x00bb } },{ //w 0 15 0 00bb
1181 { 0xf000, //w 4 15 12 f
1182 0xdf01, //w 3 15 0 df01
1183 0xdf20, //w 2 15 0 df20
1184 0xff95, //w 1 15 0 ff95
1185 0xbf00 } //w 0 15 0 bf00
1190 mdio_write(ioaddr
, 0x1f, 0x0001); //w 31 2 0 1
1191 mdio_write(ioaddr
, 0x15, 0x1000); //w 21 15 0 1000
1192 mdio_write(ioaddr
, 0x18, 0x65c7); //w 24 15 0 65c7
1193 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1195 for (i
= 0; i
< ARRAY_SIZE(phy_magic
); i
++, p
++) {
1198 val
= (mdio_read(ioaddr
, pos
) & 0x0fff) | (p
->regs
[0] & 0xffff);
1199 mdio_write(ioaddr
, pos
, val
);
1201 mdio_write(ioaddr
, pos
, p
->regs
[4 - pos
] & 0xffff);
1202 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 1); //w 4 11 11 1
1203 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1205 mdio_write(ioaddr
, 0x1f, 0x0000); //w 31 2 0 0
1208 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1210 struct phy_reg phy_reg_init
[] = {
1216 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1219 static void rtl8168cp_hw_phy_config(void __iomem
*ioaddr
)
1221 struct phy_reg phy_reg_init
[] = {
1229 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1232 static void rtl8168c_hw_phy_config(void __iomem
*ioaddr
)
1234 struct phy_reg phy_reg_init
[] = {
1251 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1254 static void rtl8168cx_hw_phy_config(void __iomem
*ioaddr
)
1256 struct phy_reg phy_reg_init
[] = {
1267 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1270 static void rtl_hw_phy_config(struct net_device
*dev
)
1272 struct rtl8169_private
*tp
= netdev_priv(dev
);
1273 void __iomem
*ioaddr
= tp
->mmio_addr
;
1275 rtl8169_print_mac_version(tp
);
1277 switch (tp
->mac_version
) {
1278 case RTL_GIGA_MAC_VER_01
:
1280 case RTL_GIGA_MAC_VER_02
:
1281 case RTL_GIGA_MAC_VER_03
:
1282 rtl8169s_hw_phy_config(ioaddr
);
1284 case RTL_GIGA_MAC_VER_04
:
1285 rtl8169sb_hw_phy_config(ioaddr
);
1287 case RTL_GIGA_MAC_VER_18
:
1288 rtl8168cp_hw_phy_config(ioaddr
);
1290 case RTL_GIGA_MAC_VER_19
:
1291 rtl8168c_hw_phy_config(ioaddr
);
1293 case RTL_GIGA_MAC_VER_20
:
1294 rtl8168cx_hw_phy_config(ioaddr
);
1301 static void rtl8169_phy_timer(unsigned long __opaque
)
1303 struct net_device
*dev
= (struct net_device
*)__opaque
;
1304 struct rtl8169_private
*tp
= netdev_priv(dev
);
1305 struct timer_list
*timer
= &tp
->timer
;
1306 void __iomem
*ioaddr
= tp
->mmio_addr
;
1307 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
1309 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
1311 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
1314 spin_lock_irq(&tp
->lock
);
1316 if (tp
->phy_reset_pending(ioaddr
)) {
1318 * A busy loop could burn quite a few cycles on nowadays CPU.
1319 * Let's delay the execution of the timer for a few ticks.
1325 if (tp
->link_ok(ioaddr
))
1328 if (netif_msg_link(tp
))
1329 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
1331 tp
->phy_reset_enable(ioaddr
);
1334 mod_timer(timer
, jiffies
+ timeout
);
1336 spin_unlock_irq(&tp
->lock
);
1339 static inline void rtl8169_delete_timer(struct net_device
*dev
)
1341 struct rtl8169_private
*tp
= netdev_priv(dev
);
1342 struct timer_list
*timer
= &tp
->timer
;
1344 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1347 del_timer_sync(timer
);
1350 static inline void rtl8169_request_timer(struct net_device
*dev
)
1352 struct rtl8169_private
*tp
= netdev_priv(dev
);
1353 struct timer_list
*timer
= &tp
->timer
;
1355 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1358 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1361 #ifdef CONFIG_NET_POLL_CONTROLLER
1363 * Polling 'interrupt' - used by things like netconsole to send skbs
1364 * without having to re-enable interrupts. It's not called while
1365 * the interrupt routine is executing.
1367 static void rtl8169_netpoll(struct net_device
*dev
)
1369 struct rtl8169_private
*tp
= netdev_priv(dev
);
1370 struct pci_dev
*pdev
= tp
->pci_dev
;
1372 disable_irq(pdev
->irq
);
1373 rtl8169_interrupt(pdev
->irq
, dev
);
1374 enable_irq(pdev
->irq
);
1378 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
1379 void __iomem
*ioaddr
)
1382 pci_release_regions(pdev
);
1383 pci_disable_device(pdev
);
1387 static void rtl8169_phy_reset(struct net_device
*dev
,
1388 struct rtl8169_private
*tp
)
1390 void __iomem
*ioaddr
= tp
->mmio_addr
;
1393 tp
->phy_reset_enable(ioaddr
);
1394 for (i
= 0; i
< 100; i
++) {
1395 if (!tp
->phy_reset_pending(ioaddr
))
1399 if (netif_msg_link(tp
))
1400 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
1403 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
1405 void __iomem
*ioaddr
= tp
->mmio_addr
;
1407 rtl_hw_phy_config(dev
);
1409 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
1410 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1414 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
1416 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
1417 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
1419 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
1420 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1422 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1423 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
1426 rtl8169_phy_reset(dev
, tp
);
1429 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1430 * only 8101. Don't panic.
1432 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
1434 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
1435 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
1438 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
1440 void __iomem
*ioaddr
= tp
->mmio_addr
;
1444 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
1445 high
= addr
[4] | (addr
[5] << 8);
1447 spin_lock_irq(&tp
->lock
);
1449 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1451 RTL_W32(MAC4
, high
);
1452 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1454 spin_unlock_irq(&tp
->lock
);
1457 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
1459 struct rtl8169_private
*tp
= netdev_priv(dev
);
1460 struct sockaddr
*addr
= p
;
1462 if (!is_valid_ether_addr(addr
->sa_data
))
1463 return -EADDRNOTAVAIL
;
1465 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1467 rtl_rar_set(tp
, dev
->dev_addr
);
1472 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1474 struct rtl8169_private
*tp
= netdev_priv(dev
);
1475 struct mii_ioctl_data
*data
= if_mii(ifr
);
1477 if (!netif_running(dev
))
1482 data
->phy_id
= 32; /* Internal PHY */
1486 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
1490 if (!capable(CAP_NET_ADMIN
))
1492 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
1498 static const struct rtl_cfg_info
{
1499 void (*hw_start
)(struct net_device
*);
1500 unsigned int region
;
1505 } rtl_cfg_infos
[] = {
1507 .hw_start
= rtl_hw_start_8169
,
1510 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1511 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1512 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1513 .features
= RTL_FEATURE_GMII
1516 .hw_start
= rtl_hw_start_8168
,
1519 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1520 TxErr
| TxOK
| RxOK
| RxErr
,
1521 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
1522 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
1525 .hw_start
= rtl_hw_start_8101
,
1528 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
1529 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1530 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1531 .features
= RTL_FEATURE_MSI
1535 /* Cfg9346_Unlock assumed. */
1536 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
1537 const struct rtl_cfg_info
*cfg
)
1542 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
1543 if (cfg
->features
& RTL_FEATURE_MSI
) {
1544 if (pci_enable_msi(pdev
)) {
1545 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
1548 msi
= RTL_FEATURE_MSI
;
1551 RTL_W8(Config2
, cfg2
);
1555 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
1557 if (tp
->features
& RTL_FEATURE_MSI
) {
1558 pci_disable_msi(pdev
);
1559 tp
->features
&= ~RTL_FEATURE_MSI
;
1563 static int __devinit
1564 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1566 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
1567 const unsigned int region
= cfg
->region
;
1568 struct rtl8169_private
*tp
;
1569 struct mii_if_info
*mii
;
1570 struct net_device
*dev
;
1571 void __iomem
*ioaddr
;
1575 if (netif_msg_drv(&debug
)) {
1576 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
1577 MODULENAME
, RTL8169_VERSION
);
1580 dev
= alloc_etherdev(sizeof (*tp
));
1582 if (netif_msg_drv(&debug
))
1583 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
1588 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1589 tp
= netdev_priv(dev
);
1592 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
1596 mii
->mdio_read
= rtl_mdio_read
;
1597 mii
->mdio_write
= rtl_mdio_write
;
1598 mii
->phy_id_mask
= 0x1f;
1599 mii
->reg_num_mask
= 0x1f;
1600 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
1602 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1603 rc
= pci_enable_device(pdev
);
1605 if (netif_msg_probe(tp
))
1606 dev_err(&pdev
->dev
, "enable failure\n");
1607 goto err_out_free_dev_1
;
1610 rc
= pci_set_mwi(pdev
);
1612 goto err_out_disable_2
;
1614 /* make sure PCI base addr 1 is MMIO */
1615 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
1616 if (netif_msg_probe(tp
)) {
1618 "region #%d not an MMIO resource, aborting\n",
1625 /* check for weird/broken PCI region reporting */
1626 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
1627 if (netif_msg_probe(tp
)) {
1629 "Invalid PCI region size(s), aborting\n");
1635 rc
= pci_request_regions(pdev
, MODULENAME
);
1637 if (netif_msg_probe(tp
))
1638 dev_err(&pdev
->dev
, "could not request regions.\n");
1642 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
1644 if ((sizeof(dma_addr_t
) > 4) &&
1645 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
) && use_dac
) {
1646 tp
->cp_cmd
|= PCIDAC
;
1647 dev
->features
|= NETIF_F_HIGHDMA
;
1649 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1651 if (netif_msg_probe(tp
)) {
1653 "DMA configuration failed.\n");
1655 goto err_out_free_res_4
;
1659 pci_set_master(pdev
);
1661 /* ioremap MMIO region */
1662 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
1664 if (netif_msg_probe(tp
))
1665 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
1667 goto err_out_free_res_4
;
1670 /* Unneeded ? Don't mess with Mrs. Murphy. */
1671 rtl8169_irq_mask_and_ack(ioaddr
);
1673 /* Soft reset the chip. */
1674 RTL_W8(ChipCmd
, CmdReset
);
1676 /* Check that the chip has finished the reset. */
1677 for (i
= 0; i
< 100; i
++) {
1678 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
1680 msleep_interruptible(1);
1683 /* Identify chip attached to board */
1684 rtl8169_get_mac_version(tp
, ioaddr
);
1686 rtl8169_print_mac_version(tp
);
1688 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
1689 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
1692 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
1693 /* Unknown chip: assume array element #0, original RTL-8169 */
1694 if (netif_msg_probe(tp
)) {
1695 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1696 "unknown chip version, assuming %s\n",
1697 rtl_chip_info
[0].name
);
1703 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1704 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
1705 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
1706 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
1707 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1709 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
1710 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
1711 tp
->set_speed
= rtl8169_set_speed_tbi
;
1712 tp
->get_settings
= rtl8169_gset_tbi
;
1713 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
1714 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
1715 tp
->link_ok
= rtl8169_tbi_link_ok
;
1717 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
1719 tp
->set_speed
= rtl8169_set_speed_xmii
;
1720 tp
->get_settings
= rtl8169_gset_xmii
;
1721 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
1722 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
1723 tp
->link_ok
= rtl8169_xmii_link_ok
;
1725 dev
->do_ioctl
= rtl8169_ioctl
;
1728 /* Get MAC address. FIXME: read EEPROM */
1729 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
1730 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
1731 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
1733 dev
->open
= rtl8169_open
;
1734 dev
->hard_start_xmit
= rtl8169_start_xmit
;
1735 dev
->get_stats
= rtl8169_get_stats
;
1736 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
1737 dev
->stop
= rtl8169_close
;
1738 dev
->tx_timeout
= rtl8169_tx_timeout
;
1739 dev
->set_multicast_list
= rtl_set_rx_mode
;
1740 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
1741 dev
->irq
= pdev
->irq
;
1742 dev
->base_addr
= (unsigned long) ioaddr
;
1743 dev
->change_mtu
= rtl8169_change_mtu
;
1744 dev
->set_mac_address
= rtl_set_mac_address
;
1746 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
1748 #ifdef CONFIG_R8169_VLAN
1749 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
1750 dev
->vlan_rx_register
= rtl8169_vlan_rx_register
;
1753 #ifdef CONFIG_NET_POLL_CONTROLLER
1754 dev
->poll_controller
= rtl8169_netpoll
;
1757 tp
->intr_mask
= 0xffff;
1758 tp
->mmio_addr
= ioaddr
;
1759 tp
->align
= cfg
->align
;
1760 tp
->hw_start
= cfg
->hw_start
;
1761 tp
->intr_event
= cfg
->intr_event
;
1762 tp
->napi_event
= cfg
->napi_event
;
1764 init_timer(&tp
->timer
);
1765 tp
->timer
.data
= (unsigned long) dev
;
1766 tp
->timer
.function
= rtl8169_phy_timer
;
1768 spin_lock_init(&tp
->lock
);
1770 rc
= register_netdev(dev
);
1774 pci_set_drvdata(pdev
, dev
);
1776 if (netif_msg_probe(tp
)) {
1777 u32 xid
= RTL_R32(TxConfig
) & 0x7cf0f8ff;
1779 printk(KERN_INFO
"%s: %s at 0x%lx, "
1780 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1781 "XID %08x IRQ %d\n",
1783 rtl_chip_info
[tp
->chipset
].name
,
1785 dev
->dev_addr
[0], dev
->dev_addr
[1],
1786 dev
->dev_addr
[2], dev
->dev_addr
[3],
1787 dev
->dev_addr
[4], dev
->dev_addr
[5], xid
, dev
->irq
);
1790 rtl8169_init_phy(dev
, tp
);
1796 rtl_disable_msi(pdev
, tp
);
1799 pci_release_regions(pdev
);
1801 pci_clear_mwi(pdev
);
1803 pci_disable_device(pdev
);
1809 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
1811 struct net_device
*dev
= pci_get_drvdata(pdev
);
1812 struct rtl8169_private
*tp
= netdev_priv(dev
);
1814 flush_scheduled_work();
1816 unregister_netdev(dev
);
1817 rtl_disable_msi(pdev
, tp
);
1818 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
1819 pci_set_drvdata(pdev
, NULL
);
1822 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
1823 struct net_device
*dev
)
1825 unsigned int mtu
= dev
->mtu
;
1827 tp
->rx_buf_sz
= (mtu
> RX_BUF_SIZE
) ? mtu
+ ETH_HLEN
+ 8 : RX_BUF_SIZE
;
1830 static int rtl8169_open(struct net_device
*dev
)
1832 struct rtl8169_private
*tp
= netdev_priv(dev
);
1833 struct pci_dev
*pdev
= tp
->pci_dev
;
1834 int retval
= -ENOMEM
;
1837 rtl8169_set_rxbufsize(tp
, dev
);
1840 * Rx and Tx desscriptors needs 256 bytes alignment.
1841 * pci_alloc_consistent provides more.
1843 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
1845 if (!tp
->TxDescArray
)
1848 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
1850 if (!tp
->RxDescArray
)
1853 retval
= rtl8169_init_ring(dev
);
1857 INIT_DELAYED_WORK(&tp
->task
, NULL
);
1861 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
1862 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
1865 goto err_release_ring_2
;
1867 napi_enable(&tp
->napi
);
1871 rtl8169_request_timer(dev
);
1873 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
1878 rtl8169_rx_clear(tp
);
1880 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
1883 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
1888 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
1890 /* Disable interrupts */
1891 rtl8169_irq_mask_and_ack(ioaddr
);
1893 /* Reset the chipset */
1894 RTL_W8(ChipCmd
, CmdReset
);
1900 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
1902 void __iomem
*ioaddr
= tp
->mmio_addr
;
1903 u32 cfg
= rtl8169_rx_config
;
1905 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
1906 RTL_W32(RxConfig
, cfg
);
1908 /* Set DMA burst size and Interframe Gap Time */
1909 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
1910 (InterFrameGap
<< TxInterFrameGapShift
));
1913 static void rtl_hw_start(struct net_device
*dev
)
1915 struct rtl8169_private
*tp
= netdev_priv(dev
);
1916 void __iomem
*ioaddr
= tp
->mmio_addr
;
1919 /* Soft reset the chip. */
1920 RTL_W8(ChipCmd
, CmdReset
);
1922 /* Check that the chip has finished the reset. */
1923 for (i
= 0; i
< 100; i
++) {
1924 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
1926 msleep_interruptible(1);
1931 netif_start_queue(dev
);
1935 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
1936 void __iomem
*ioaddr
)
1939 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1940 * register to be written before TxDescAddrLow to work.
1941 * Switching from MMIO to I/O access fixes the issue as well.
1943 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
1944 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_32BIT_MASK
);
1945 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
1946 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_32BIT_MASK
);
1949 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
1953 cmd
= RTL_R16(CPlusCmd
);
1954 RTL_W16(CPlusCmd
, cmd
);
1958 static void rtl_set_rx_max_size(void __iomem
*ioaddr
)
1960 /* Low hurts. Let's disable the filtering. */
1961 RTL_W16(RxMaxSize
, 16383);
1964 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
1971 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
1972 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
1973 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
1974 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
1979 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
1980 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
1981 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
1982 RTL_W32(0x7c, p
->val
);
1988 static void rtl_hw_start_8169(struct net_device
*dev
)
1990 struct rtl8169_private
*tp
= netdev_priv(dev
);
1991 void __iomem
*ioaddr
= tp
->mmio_addr
;
1992 struct pci_dev
*pdev
= tp
->pci_dev
;
1994 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
1995 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
1996 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
1999 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2000 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2001 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2002 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2003 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2004 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2006 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2008 rtl_set_rx_max_size(ioaddr
);
2010 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2011 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2012 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2013 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2014 rtl_set_rx_tx_config_registers(tp
);
2016 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2018 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2019 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
2020 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2021 "Bit-3 and bit-14 MUST be 1\n");
2022 tp
->cp_cmd
|= (1 << 14);
2025 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2027 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
2030 * Undocumented corner. Supposedly:
2031 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2033 RTL_W16(IntrMitigate
, 0x0000);
2035 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2037 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
2038 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
2039 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
2040 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
2041 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2042 rtl_set_rx_tx_config_registers(tp
);
2045 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2047 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2050 RTL_W32(RxMissed
, 0);
2052 rtl_set_rx_mode(dev
);
2054 /* no early-rx interrupts */
2055 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2057 /* Enable all known interrupts by setting the interrupt mask. */
2058 RTL_W16(IntrMask
, tp
->intr_event
);
2061 static void rtl_hw_start_8168(struct net_device
*dev
)
2063 struct rtl8169_private
*tp
= netdev_priv(dev
);
2064 void __iomem
*ioaddr
= tp
->mmio_addr
;
2065 struct pci_dev
*pdev
= tp
->pci_dev
;
2068 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2070 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2072 rtl_set_rx_max_size(ioaddr
);
2074 rtl_set_rx_tx_config_registers(tp
);
2076 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
2078 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2080 /* Tx performance tweak. */
2081 pci_read_config_byte(pdev
, 0x69, &ctl
);
2082 ctl
= (ctl
& ~0x70) | 0x50;
2083 pci_write_config_byte(pdev
, 0x69, ctl
);
2085 RTL_W16(IntrMitigate
, 0x5151);
2087 /* Work around for RxFIFO overflow. */
2088 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
2089 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
2090 tp
->intr_event
&= ~RxOverflow
;
2093 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2095 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2099 rtl_set_rx_mode(dev
);
2101 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2103 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2105 RTL_W16(IntrMask
, tp
->intr_event
);
2108 static void rtl_hw_start_8101(struct net_device
*dev
)
2110 struct rtl8169_private
*tp
= netdev_priv(dev
);
2111 void __iomem
*ioaddr
= tp
->mmio_addr
;
2112 struct pci_dev
*pdev
= tp
->pci_dev
;
2114 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
2115 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
2116 pci_write_config_word(pdev
, 0x68, 0x00);
2117 pci_write_config_word(pdev
, 0x69, 0x08);
2120 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2122 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2124 rtl_set_rx_max_size(ioaddr
);
2126 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2128 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2130 RTL_W16(IntrMitigate
, 0x0000);
2132 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2134 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2135 rtl_set_rx_tx_config_registers(tp
);
2137 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2141 rtl_set_rx_mode(dev
);
2143 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2145 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
2147 RTL_W16(IntrMask
, tp
->intr_event
);
2150 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
2152 struct rtl8169_private
*tp
= netdev_priv(dev
);
2155 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
2160 if (!netif_running(dev
))
2165 rtl8169_set_rxbufsize(tp
, dev
);
2167 ret
= rtl8169_init_ring(dev
);
2171 napi_enable(&tp
->napi
);
2175 rtl8169_request_timer(dev
);
2181 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
2183 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
2184 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
2187 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
2188 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
2190 struct pci_dev
*pdev
= tp
->pci_dev
;
2192 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
2193 PCI_DMA_FROMDEVICE
);
2194 dev_kfree_skb(*sk_buff
);
2196 rtl8169_make_unusable_by_asic(desc
);
2199 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
2201 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
2203 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
2206 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
2209 desc
->addr
= cpu_to_le64(mapping
);
2211 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
2214 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
2215 struct net_device
*dev
,
2216 struct RxDesc
*desc
, int rx_buf_sz
,
2219 struct sk_buff
*skb
;
2223 pad
= align
? align
: NET_IP_ALIGN
;
2225 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ pad
);
2229 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
2231 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
2232 PCI_DMA_FROMDEVICE
);
2234 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
2239 rtl8169_make_unusable_by_asic(desc
);
2243 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
2247 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
2248 if (tp
->Rx_skbuff
[i
]) {
2249 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
2250 tp
->RxDescArray
+ i
);
2255 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
2260 for (cur
= start
; end
- cur
!= 0; cur
++) {
2261 struct sk_buff
*skb
;
2262 unsigned int i
= cur
% NUM_RX_DESC
;
2264 WARN_ON((s32
)(end
- cur
) < 0);
2266 if (tp
->Rx_skbuff
[i
])
2269 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
2270 tp
->RxDescArray
+ i
,
2271 tp
->rx_buf_sz
, tp
->align
);
2275 tp
->Rx_skbuff
[i
] = skb
;
2280 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
2282 desc
->opts1
|= cpu_to_le32(RingEnd
);
2285 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
2287 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
2290 static int rtl8169_init_ring(struct net_device
*dev
)
2292 struct rtl8169_private
*tp
= netdev_priv(dev
);
2294 rtl8169_init_ring_indexes(tp
);
2296 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
2297 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
2299 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
2302 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
2307 rtl8169_rx_clear(tp
);
2311 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
2312 struct TxDesc
*desc
)
2314 unsigned int len
= tx_skb
->len
;
2316 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
2323 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
2327 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
2328 unsigned int entry
= i
% NUM_TX_DESC
;
2329 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
2330 unsigned int len
= tx_skb
->len
;
2333 struct sk_buff
*skb
= tx_skb
->skb
;
2335 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
2336 tp
->TxDescArray
+ entry
);
2341 tp
->dev
->stats
.tx_dropped
++;
2344 tp
->cur_tx
= tp
->dirty_tx
= 0;
2347 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
2349 struct rtl8169_private
*tp
= netdev_priv(dev
);
2351 PREPARE_DELAYED_WORK(&tp
->task
, task
);
2352 schedule_delayed_work(&tp
->task
, 4);
2355 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
2357 struct rtl8169_private
*tp
= netdev_priv(dev
);
2358 void __iomem
*ioaddr
= tp
->mmio_addr
;
2360 synchronize_irq(dev
->irq
);
2362 /* Wait for any pending NAPI task to complete */
2363 napi_disable(&tp
->napi
);
2365 rtl8169_irq_mask_and_ack(ioaddr
);
2367 tp
->intr_mask
= 0xffff;
2368 RTL_W16(IntrMask
, tp
->intr_event
);
2369 napi_enable(&tp
->napi
);
2372 static void rtl8169_reinit_task(struct work_struct
*work
)
2374 struct rtl8169_private
*tp
=
2375 container_of(work
, struct rtl8169_private
, task
.work
);
2376 struct net_device
*dev
= tp
->dev
;
2381 if (!netif_running(dev
))
2384 rtl8169_wait_for_quiescence(dev
);
2387 ret
= rtl8169_open(dev
);
2388 if (unlikely(ret
< 0)) {
2389 if (net_ratelimit() && netif_msg_drv(tp
)) {
2390 printk(KERN_ERR PFX
"%s: reinit failure (status = %d)."
2391 " Rescheduling.\n", dev
->name
, ret
);
2393 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
2400 static void rtl8169_reset_task(struct work_struct
*work
)
2402 struct rtl8169_private
*tp
=
2403 container_of(work
, struct rtl8169_private
, task
.work
);
2404 struct net_device
*dev
= tp
->dev
;
2408 if (!netif_running(dev
))
2411 rtl8169_wait_for_quiescence(dev
);
2413 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
2414 rtl8169_tx_clear(tp
);
2416 if (tp
->dirty_rx
== tp
->cur_rx
) {
2417 rtl8169_init_ring_indexes(tp
);
2419 netif_wake_queue(dev
);
2420 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
2422 if (net_ratelimit() && netif_msg_intr(tp
)) {
2423 printk(KERN_EMERG PFX
"%s: Rx buffers shortage\n",
2426 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
2433 static void rtl8169_tx_timeout(struct net_device
*dev
)
2435 struct rtl8169_private
*tp
= netdev_priv(dev
);
2437 rtl8169_hw_reset(tp
->mmio_addr
);
2439 /* Let's wait a bit while any (async) irq lands on */
2440 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
2443 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
2446 struct skb_shared_info
*info
= skb_shinfo(skb
);
2447 unsigned int cur_frag
, entry
;
2448 struct TxDesc
* uninitialized_var(txd
);
2451 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
2452 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
2457 entry
= (entry
+ 1) % NUM_TX_DESC
;
2459 txd
= tp
->TxDescArray
+ entry
;
2461 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
2462 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
2464 /* anti gcc 2.95.3 bugware (sic) */
2465 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
2467 txd
->opts1
= cpu_to_le32(status
);
2468 txd
->addr
= cpu_to_le64(mapping
);
2470 tp
->tx_skb
[entry
].len
= len
;
2474 tp
->tx_skb
[entry
].skb
= skb
;
2475 txd
->opts1
|= cpu_to_le32(LastFrag
);
2481 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
2483 if (dev
->features
& NETIF_F_TSO
) {
2484 u32 mss
= skb_shinfo(skb
)->gso_size
;
2487 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
2489 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2490 const struct iphdr
*ip
= ip_hdr(skb
);
2492 if (ip
->protocol
== IPPROTO_TCP
)
2493 return IPCS
| TCPCS
;
2494 else if (ip
->protocol
== IPPROTO_UDP
)
2495 return IPCS
| UDPCS
;
2496 WARN_ON(1); /* we need a WARN() */
2501 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2503 struct rtl8169_private
*tp
= netdev_priv(dev
);
2504 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
2505 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
2506 void __iomem
*ioaddr
= tp
->mmio_addr
;
2510 int ret
= NETDEV_TX_OK
;
2512 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
2513 if (netif_msg_drv(tp
)) {
2515 "%s: BUG! Tx Ring full when queue awake!\n",
2521 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
2524 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
2526 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
2528 len
= skb_headlen(skb
);
2533 if (unlikely(len
< ETH_ZLEN
)) {
2534 if (skb_padto(skb
, ETH_ZLEN
))
2535 goto err_update_stats
;
2539 opts1
|= FirstFrag
| LastFrag
;
2540 tp
->tx_skb
[entry
].skb
= skb
;
2543 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
2545 tp
->tx_skb
[entry
].len
= len
;
2546 txd
->addr
= cpu_to_le64(mapping
);
2547 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
2551 /* anti gcc 2.95.3 bugware (sic) */
2552 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
2553 txd
->opts1
= cpu_to_le32(status
);
2555 dev
->trans_start
= jiffies
;
2557 tp
->cur_tx
+= frags
+ 1;
2561 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
2563 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
2564 netif_stop_queue(dev
);
2566 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
2567 netif_wake_queue(dev
);
2574 netif_stop_queue(dev
);
2575 ret
= NETDEV_TX_BUSY
;
2577 dev
->stats
.tx_dropped
++;
2581 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
2583 struct rtl8169_private
*tp
= netdev_priv(dev
);
2584 struct pci_dev
*pdev
= tp
->pci_dev
;
2585 void __iomem
*ioaddr
= tp
->mmio_addr
;
2586 u16 pci_status
, pci_cmd
;
2588 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
2589 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
2591 if (netif_msg_intr(tp
)) {
2593 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2594 dev
->name
, pci_cmd
, pci_status
);
2598 * The recovery sequence below admits a very elaborated explanation:
2599 * - it seems to work;
2600 * - I did not see what else could be done;
2601 * - it makes iop3xx happy.
2603 * Feel free to adjust to your needs.
2605 if (pdev
->broken_parity_status
)
2606 pci_cmd
&= ~PCI_COMMAND_PARITY
;
2608 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
2610 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
2612 pci_write_config_word(pdev
, PCI_STATUS
,
2613 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
2614 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
2615 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
2617 /* The infamous DAC f*ckup only happens at boot time */
2618 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
2619 if (netif_msg_intr(tp
))
2620 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
2621 tp
->cp_cmd
&= ~PCIDAC
;
2622 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2623 dev
->features
&= ~NETIF_F_HIGHDMA
;
2626 rtl8169_hw_reset(ioaddr
);
2628 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
2631 static void rtl8169_tx_interrupt(struct net_device
*dev
,
2632 struct rtl8169_private
*tp
,
2633 void __iomem
*ioaddr
)
2635 unsigned int dirty_tx
, tx_left
;
2637 dirty_tx
= tp
->dirty_tx
;
2639 tx_left
= tp
->cur_tx
- dirty_tx
;
2641 while (tx_left
> 0) {
2642 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
2643 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
2644 u32 len
= tx_skb
->len
;
2648 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
2649 if (status
& DescOwn
)
2652 dev
->stats
.tx_bytes
+= len
;
2653 dev
->stats
.tx_packets
++;
2655 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
2657 if (status
& LastFrag
) {
2658 dev_kfree_skb_irq(tx_skb
->skb
);
2665 if (tp
->dirty_tx
!= dirty_tx
) {
2666 tp
->dirty_tx
= dirty_tx
;
2668 if (netif_queue_stopped(dev
) &&
2669 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
2670 netif_wake_queue(dev
);
2673 * 8168 hack: TxPoll requests are lost when the Tx packets are
2674 * too close. Let's kick an extra TxPoll request when a burst
2675 * of start_xmit activity is detected (if it is not detected,
2676 * it is slow enough). -- FR
2679 if (tp
->cur_tx
!= dirty_tx
)
2680 RTL_W8(TxPoll
, NPQ
);
2684 static inline int rtl8169_fragmented_frame(u32 status
)
2686 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
2689 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
2691 u32 opts1
= le32_to_cpu(desc
->opts1
);
2692 u32 status
= opts1
& RxProtoMask
;
2694 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
2695 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
2696 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
2697 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2699 skb
->ip_summed
= CHECKSUM_NONE
;
2702 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
,
2703 struct rtl8169_private
*tp
, int pkt_size
,
2706 struct sk_buff
*skb
;
2709 if (pkt_size
>= rx_copybreak
)
2712 skb
= netdev_alloc_skb(tp
->dev
, pkt_size
+ NET_IP_ALIGN
);
2716 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
2717 PCI_DMA_FROMDEVICE
);
2718 skb_reserve(skb
, NET_IP_ALIGN
);
2719 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
2726 static int rtl8169_rx_interrupt(struct net_device
*dev
,
2727 struct rtl8169_private
*tp
,
2728 void __iomem
*ioaddr
, u32 budget
)
2730 unsigned int cur_rx
, rx_left
;
2731 unsigned int delta
, count
;
2733 cur_rx
= tp
->cur_rx
;
2734 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
2735 rx_left
= min(rx_left
, budget
);
2737 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
2738 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
2739 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
2743 status
= le32_to_cpu(desc
->opts1
);
2745 if (status
& DescOwn
)
2747 if (unlikely(status
& RxRES
)) {
2748 if (netif_msg_rx_err(tp
)) {
2750 "%s: Rx ERROR. status = %08x\n",
2753 dev
->stats
.rx_errors
++;
2754 if (status
& (RxRWT
| RxRUNT
))
2755 dev
->stats
.rx_length_errors
++;
2757 dev
->stats
.rx_crc_errors
++;
2758 if (status
& RxFOVF
) {
2759 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
2760 dev
->stats
.rx_fifo_errors
++;
2762 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
2764 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
2765 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
2766 int pkt_size
= (status
& 0x00001FFF) - 4;
2767 struct pci_dev
*pdev
= tp
->pci_dev
;
2770 * The driver does not support incoming fragmented
2771 * frames. They are seen as a symptom of over-mtu
2774 if (unlikely(rtl8169_fragmented_frame(status
))) {
2775 dev
->stats
.rx_dropped
++;
2776 dev
->stats
.rx_length_errors
++;
2777 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
2781 rtl8169_rx_csum(skb
, desc
);
2783 if (rtl8169_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
2784 pci_dma_sync_single_for_device(pdev
, addr
,
2785 pkt_size
, PCI_DMA_FROMDEVICE
);
2786 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
2788 pci_unmap_single(pdev
, addr
, tp
->rx_buf_sz
,
2789 PCI_DMA_FROMDEVICE
);
2790 tp
->Rx_skbuff
[entry
] = NULL
;
2793 skb_put(skb
, pkt_size
);
2794 skb
->protocol
= eth_type_trans(skb
, dev
);
2796 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
) < 0)
2797 netif_receive_skb(skb
);
2799 dev
->last_rx
= jiffies
;
2800 dev
->stats
.rx_bytes
+= pkt_size
;
2801 dev
->stats
.rx_packets
++;
2804 /* Work around for AMD plateform. */
2805 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
2806 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
2812 count
= cur_rx
- tp
->cur_rx
;
2813 tp
->cur_rx
= cur_rx
;
2815 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
2816 if (!delta
&& count
&& netif_msg_intr(tp
))
2817 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
2818 tp
->dirty_rx
+= delta
;
2821 * FIXME: until there is periodic timer to try and refill the ring,
2822 * a temporary shortage may definitely kill the Rx process.
2823 * - disable the asic to try and avoid an overflow and kick it again
2825 * - how do others driver handle this condition (Uh oh...).
2827 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
2828 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
2833 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
2835 struct net_device
*dev
= dev_instance
;
2836 struct rtl8169_private
*tp
= netdev_priv(dev
);
2837 void __iomem
*ioaddr
= tp
->mmio_addr
;
2841 status
= RTL_R16(IntrStatus
);
2843 /* hotplug/major error/no more work/shared irq */
2844 if ((status
== 0xffff) || !status
)
2849 if (unlikely(!netif_running(dev
))) {
2850 rtl8169_asic_down(ioaddr
);
2854 status
&= tp
->intr_mask
;
2856 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
2858 if (!(status
& tp
->intr_event
))
2861 /* Work around for rx fifo overflow */
2862 if (unlikely(status
& RxFIFOOver
) &&
2863 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
2864 netif_stop_queue(dev
);
2865 rtl8169_tx_timeout(dev
);
2869 if (unlikely(status
& SYSErr
)) {
2870 rtl8169_pcierr_interrupt(dev
);
2874 if (status
& LinkChg
)
2875 rtl8169_check_link_status(dev
, tp
, ioaddr
);
2877 if (status
& tp
->napi_event
) {
2878 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
2879 tp
->intr_mask
= ~tp
->napi_event
;
2881 if (likely(netif_rx_schedule_prep(dev
, &tp
->napi
)))
2882 __netif_rx_schedule(dev
, &tp
->napi
);
2883 else if (netif_msg_intr(tp
)) {
2884 printk(KERN_INFO
"%s: interrupt %04x in poll\n",
2889 return IRQ_RETVAL(handled
);
2892 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
2894 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
2895 struct net_device
*dev
= tp
->dev
;
2896 void __iomem
*ioaddr
= tp
->mmio_addr
;
2899 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
2900 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
2902 if (work_done
< budget
) {
2903 netif_rx_complete(dev
, napi
);
2904 tp
->intr_mask
= 0xffff;
2906 * 20040426: the barrier is not strictly required but the
2907 * behavior of the irq handler could be less predictable
2908 * without it. Btw, the lack of flush for the posted pci
2909 * write is safe - FR
2912 RTL_W16(IntrMask
, tp
->intr_event
);
2918 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
2920 struct rtl8169_private
*tp
= netdev_priv(dev
);
2922 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
2925 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
2926 RTL_W32(RxMissed
, 0);
2929 static void rtl8169_down(struct net_device
*dev
)
2931 struct rtl8169_private
*tp
= netdev_priv(dev
);
2932 void __iomem
*ioaddr
= tp
->mmio_addr
;
2933 unsigned int intrmask
;
2935 rtl8169_delete_timer(dev
);
2937 netif_stop_queue(dev
);
2939 napi_disable(&tp
->napi
);
2942 spin_lock_irq(&tp
->lock
);
2944 rtl8169_asic_down(ioaddr
);
2946 rtl8169_rx_missed(dev
, ioaddr
);
2948 spin_unlock_irq(&tp
->lock
);
2950 synchronize_irq(dev
->irq
);
2952 /* Give a racing hard_start_xmit a few cycles to complete. */
2953 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2956 * And now for the 50k$ question: are IRQ disabled or not ?
2958 * Two paths lead here:
2960 * -> netif_running() is available to sync the current code and the
2961 * IRQ handler. See rtl8169_interrupt for details.
2962 * 2) dev->change_mtu
2963 * -> rtl8169_poll can not be issued again and re-enable the
2964 * interruptions. Let's simply issue the IRQ down sequence again.
2966 * No loop if hotpluged or major error (0xffff).
2968 intrmask
= RTL_R16(IntrMask
);
2969 if (intrmask
&& (intrmask
!= 0xffff))
2972 rtl8169_tx_clear(tp
);
2974 rtl8169_rx_clear(tp
);
2977 static int rtl8169_close(struct net_device
*dev
)
2979 struct rtl8169_private
*tp
= netdev_priv(dev
);
2980 struct pci_dev
*pdev
= tp
->pci_dev
;
2984 free_irq(dev
->irq
, dev
);
2986 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
2988 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
2990 tp
->TxDescArray
= NULL
;
2991 tp
->RxDescArray
= NULL
;
2996 static void rtl_set_rx_mode(struct net_device
*dev
)
2998 struct rtl8169_private
*tp
= netdev_priv(dev
);
2999 void __iomem
*ioaddr
= tp
->mmio_addr
;
3000 unsigned long flags
;
3001 u32 mc_filter
[2]; /* Multicast hash filter */
3005 if (dev
->flags
& IFF_PROMISC
) {
3006 /* Unconditionally log net taps. */
3007 if (netif_msg_link(tp
)) {
3008 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
3012 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
3014 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3015 } else if ((dev
->mc_count
> multicast_filter_limit
)
3016 || (dev
->flags
& IFF_ALLMULTI
)) {
3017 /* Too many to filter perfectly -- accept all multicasts. */
3018 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
3019 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3021 struct dev_mc_list
*mclist
;
3024 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
3025 mc_filter
[1] = mc_filter
[0] = 0;
3026 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
3027 i
++, mclist
= mclist
->next
) {
3028 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
3029 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
3030 rx_mode
|= AcceptMulticast
;
3034 spin_lock_irqsave(&tp
->lock
, flags
);
3036 tmp
= rtl8169_rx_config
| rx_mode
|
3037 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3039 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
3040 u32 data
= mc_filter
[0];
3042 mc_filter
[0] = swab32(mc_filter
[1]);
3043 mc_filter
[1] = swab32(data
);
3046 RTL_W32(MAR0
+ 0, mc_filter
[0]);
3047 RTL_W32(MAR0
+ 4, mc_filter
[1]);
3049 RTL_W32(RxConfig
, tmp
);
3051 spin_unlock_irqrestore(&tp
->lock
, flags
);
3055 * rtl8169_get_stats - Get rtl8169 read/write statistics
3056 * @dev: The Ethernet Device to get statistics for
3058 * Get TX/RX statistics for rtl8169
3060 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
3062 struct rtl8169_private
*tp
= netdev_priv(dev
);
3063 void __iomem
*ioaddr
= tp
->mmio_addr
;
3064 unsigned long flags
;
3066 if (netif_running(dev
)) {
3067 spin_lock_irqsave(&tp
->lock
, flags
);
3068 rtl8169_rx_missed(dev
, ioaddr
);
3069 spin_unlock_irqrestore(&tp
->lock
, flags
);
3077 static int rtl8169_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3079 struct net_device
*dev
= pci_get_drvdata(pdev
);
3080 struct rtl8169_private
*tp
= netdev_priv(dev
);
3081 void __iomem
*ioaddr
= tp
->mmio_addr
;
3083 if (!netif_running(dev
))
3084 goto out_pci_suspend
;
3086 netif_device_detach(dev
);
3087 netif_stop_queue(dev
);
3089 spin_lock_irq(&tp
->lock
);
3091 rtl8169_asic_down(ioaddr
);
3093 rtl8169_rx_missed(dev
, ioaddr
);
3095 spin_unlock_irq(&tp
->lock
);
3098 pci_save_state(pdev
);
3099 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
),
3100 (tp
->features
& RTL_FEATURE_WOL
) ? 1 : 0);
3101 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3106 static int rtl8169_resume(struct pci_dev
*pdev
)
3108 struct net_device
*dev
= pci_get_drvdata(pdev
);
3110 pci_set_power_state(pdev
, PCI_D0
);
3111 pci_restore_state(pdev
);
3112 pci_enable_wake(pdev
, PCI_D0
, 0);
3114 if (!netif_running(dev
))
3117 netif_device_attach(dev
);
3119 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3124 #endif /* CONFIG_PM */
3126 static struct pci_driver rtl8169_pci_driver
= {
3128 .id_table
= rtl8169_pci_tbl
,
3129 .probe
= rtl8169_init_one
,
3130 .remove
= __devexit_p(rtl8169_remove_one
),
3132 .suspend
= rtl8169_suspend
,
3133 .resume
= rtl8169_resume
,
3137 static int __init
rtl8169_init_module(void)
3139 return pci_register_driver(&rtl8169_pci_driver
);
3142 static void __exit
rtl8169_cleanup_module(void)
3144 pci_unregister_driver(&rtl8169_pci_driver
);
3147 module_init(rtl8169_init_module
);
3148 module_exit(rtl8169_cleanup_module
);