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firewire: ohci: fix buffer overflow in AR split packet handling
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / firewire / ohci.c
blob5826ae333b19ed7e3a58a0c12c18ce92315e19fd
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/bug.h>
22 #include <linux/compiler.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/firewire.h>
27 #include <linux/firewire-constants.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/mm.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/mutex.h>
37 #include <linux/pci.h>
38 #include <linux/pci_ids.h>
39 #include <linux/slab.h>
40 #include <linux/spinlock.h>
41 #include <linux/string.h>
42 #include <linux/time.h>
43
44 #include <asm/byteorder.h>
45 #include <asm/page.h>
46 #include <asm/system.h>
47
48 #ifdef CONFIG_PPC_PMAC
49 #include <asm/pmac_feature.h>
50 #endif
51
52 #include "core.h"
53 #include "ohci.h"
54
55 #define DESCRIPTOR_OUTPUT_MORE 0
56 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
57 #define DESCRIPTOR_INPUT_MORE (2 << 12)
58 #define DESCRIPTOR_INPUT_LAST (3 << 12)
59 #define DESCRIPTOR_STATUS (1 << 11)
60 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
61 #define DESCRIPTOR_PING (1 << 7)
62 #define DESCRIPTOR_YY (1 << 6)
63 #define DESCRIPTOR_NO_IRQ (0 << 4)
64 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
65 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
66 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
67 #define DESCRIPTOR_WAIT (3 << 0)
68
69 struct descriptor {
70 __le16 req_count;
71 __le16 control;
72 __le32 data_address;
73 __le32 branch_address;
74 __le16 res_count;
75 __le16 transfer_status;
76 } __attribute__((aligned(16)));
77
78 #define CONTROL_SET(regs) (regs)
79 #define CONTROL_CLEAR(regs) ((regs) + 4)
80 #define COMMAND_PTR(regs) ((regs) + 12)
81 #define CONTEXT_MATCH(regs) ((regs) + 16)
82
83 struct ar_buffer {
84 struct descriptor descriptor;
85 struct ar_buffer *next;
86 __le32 data[0];
87 };
88
89 struct ar_context {
90 struct fw_ohci *ohci;
91 struct ar_buffer *current_buffer;
92 struct ar_buffer *last_buffer;
93 void *pointer;
94 u32 regs;
95 struct tasklet_struct tasklet;
96 };
97
98 struct context;
99
100 typedef int (*descriptor_callback_t)(struct context *ctx,
101 struct descriptor *d,
102 struct descriptor *last);
103
104 /*
105 * A buffer that contains a block of DMA-able coherent memory used for
106 * storing a portion of a DMA descriptor program.
107 */
108 struct descriptor_buffer {
109 struct list_head list;
110 dma_addr_t buffer_bus;
111 size_t buffer_size;
112 size_t used;
113 struct descriptor buffer[0];
114 };
115
116 struct context {
117 struct fw_ohci *ohci;
118 u32 regs;
119 int total_allocation;
120
121 /*
122 * List of page-sized buffers for storing DMA descriptors.
123 * Head of list contains buffers in use and tail of list contains
124 * free buffers.
125 */
126 struct list_head buffer_list;
127
128 /*
129 * Pointer to a buffer inside buffer_list that contains the tail
130 * end of the current DMA program.
131 */
132 struct descriptor_buffer *buffer_tail;
133
134 /*
135 * The descriptor containing the branch address of the first
136 * descriptor that has not yet been filled by the device.
137 */
138 struct descriptor *last;
139
140 /*
141 * The last descriptor in the DMA program. It contains the branch
142 * address that must be updated upon appending a new descriptor.
143 */
144 struct descriptor *prev;
145
146 descriptor_callback_t callback;
147
148 struct tasklet_struct tasklet;
149 };
150
151 #define IT_HEADER_SY(v) ((v) << 0)
152 #define IT_HEADER_TCODE(v) ((v) << 4)
153 #define IT_HEADER_CHANNEL(v) ((v) << 8)
154 #define IT_HEADER_TAG(v) ((v) << 14)
155 #define IT_HEADER_SPEED(v) ((v) << 16)
156 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
157
158 struct iso_context {
159 struct fw_iso_context base;
160 struct context context;
161 int excess_bytes;
162 void *header;
163 size_t header_length;
164 };
165
166 #define CONFIG_ROM_SIZE 1024
167
168 struct fw_ohci {
169 struct fw_card card;
170
171 __iomem char *registers;
172 int node_id;
173 int generation;
174 int request_generation; /* for timestamping incoming requests */
175 unsigned quirks;
176 unsigned int pri_req_max;
177 u32 bus_time;
178 bool is_root;
179 bool csr_state_setclear_abdicate;
180
181 /*
182 * Spinlock for accessing fw_ohci data. Never call out of
183 * this driver with this lock held.
184 */
185 spinlock_t lock;
186
187 struct mutex phy_reg_mutex;
188
189 struct ar_context ar_request_ctx;
190 struct ar_context ar_response_ctx;
191 struct context at_request_ctx;
192 struct context at_response_ctx;
193
194 u32 it_context_mask; /* unoccupied IT contexts */
195 struct iso_context *it_context_list;
196 u64 ir_context_channels; /* unoccupied channels */
197 u32 ir_context_mask; /* unoccupied IR contexts */
198 struct iso_context *ir_context_list;
199 u64 mc_channels; /* channels in use by the multichannel IR context */
200 bool mc_allocated;
201
202 __be32 *config_rom;
203 dma_addr_t config_rom_bus;
204 __be32 *next_config_rom;
205 dma_addr_t next_config_rom_bus;
206 __be32 next_header;
207
208 __le32 *self_id_cpu;
209 dma_addr_t self_id_bus;
210 struct tasklet_struct bus_reset_tasklet;
211
212 u32 self_id_buffer[512];
213 };
214
215 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
216 {
217 return container_of(card, struct fw_ohci, card);
218 }
219
220 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
221 #define IR_CONTEXT_BUFFER_FILL 0x80000000
222 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
223 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
224 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
225 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
226
227 #define CONTEXT_RUN 0x8000
228 #define CONTEXT_WAKE 0x1000
229 #define CONTEXT_DEAD 0x0800
230 #define CONTEXT_ACTIVE 0x0400
231
232 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
233 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
234 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
235
236 #define OHCI1394_REGISTER_SIZE 0x800
237 #define OHCI_LOOP_COUNT 500
238 #define OHCI1394_PCI_HCI_Control 0x40
239 #define SELF_ID_BUF_SIZE 0x800
240 #define OHCI_TCODE_PHY_PACKET 0x0e
241 #define OHCI_VERSION_1_1 0x010010
242
243 static char ohci_driver_name[] = KBUILD_MODNAME;
244
245 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
246 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
247
248 #define QUIRK_CYCLE_TIMER 1
249 #define QUIRK_RESET_PACKET 2
250 #define QUIRK_BE_HEADERS 4
251 #define QUIRK_NO_1394A 8
252 #define QUIRK_NO_MSI 16
253
254 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
255 static const struct {
256 unsigned short vendor, device, flags;
257 } ohci_quirks[] = {
258 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
259 QUIRK_RESET_PACKET |
260 QUIRK_NO_1394A},
261 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
262 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
263 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
264 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
265 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
266 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
267 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
268 };
269
270 /* This overrides anything that was found in ohci_quirks[]. */
271 static int param_quirks;
272 module_param_named(quirks, param_quirks, int, 0644);
273 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
274 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
275 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
276 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
277 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
278 ", disable MSI = " __stringify(QUIRK_NO_MSI)
279 ")");
280
281 #define OHCI_PARAM_DEBUG_AT_AR 1
282 #define OHCI_PARAM_DEBUG_SELFIDS 2
283 #define OHCI_PARAM_DEBUG_IRQS 4
284 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
285
286 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
287
288 static int param_debug;
289 module_param_named(debug, param_debug, int, 0644);
290 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
291 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
292 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
293 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
294 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
295 ", or a combination, or all = -1)");
296
297 static void log_irqs(u32 evt)
298 {
299 if (likely(!(param_debug &
300 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
301 return;
302
303 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
304 !(evt & OHCI1394_busReset))
305 return;
306
307 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
308 evt & OHCI1394_selfIDComplete ? " selfID" : "",
309 evt & OHCI1394_RQPkt ? " AR_req" : "",
310 evt & OHCI1394_RSPkt ? " AR_resp" : "",
311 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
312 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
313 evt & OHCI1394_isochRx ? " IR" : "",
314 evt & OHCI1394_isochTx ? " IT" : "",
315 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
316 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
317 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
318 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
319 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
320 evt & OHCI1394_busReset ? " busReset" : "",
321 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
322 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
323 OHCI1394_respTxComplete | OHCI1394_isochRx |
324 OHCI1394_isochTx | OHCI1394_postedWriteErr |
325 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
326 OHCI1394_cycleInconsistent |
327 OHCI1394_regAccessFail | OHCI1394_busReset)
328 ? " ?" : "");
329 }
330
331 static const char *speed[] = {
332 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
333 };
334 static const char *power[] = {
335 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
336 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
337 };
338 static const char port[] = { '.', '-', 'p', 'c', };
339
340 static char _p(u32 *s, int shift)
341 {
342 return port[*s >> shift & 3];
343 }
344
345 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
346 {
347 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
348 return;
349
350 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
351 self_id_count, generation, node_id);
352
353 for (; self_id_count--; ++s)
354 if ((*s & 1 << 23) == 0)
355 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
356 "%s gc=%d %s %s%s%s\n",
357 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
358 speed[*s >> 14 & 3], *s >> 16 & 63,
359 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
360 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
361 else
362 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
363 *s, *s >> 24 & 63,
364 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
365 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
366 }
367
368 static const char *evts[] = {
369 [0x00] = "evt_no_status", [0x01] = "-reserved-",
370 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
371 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
372 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
373 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
374 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
375 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
376 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
377 [0x10] = "-reserved-", [0x11] = "ack_complete",
378 [0x12] = "ack_pending ", [0x13] = "-reserved-",
379 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
380 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
381 [0x18] = "-reserved-", [0x19] = "-reserved-",
382 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
383 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
384 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
385 [0x20] = "pending/cancelled",
386 };
387 static const char *tcodes[] = {
388 [0x0] = "QW req", [0x1] = "BW req",
389 [0x2] = "W resp", [0x3] = "-reserved-",
390 [0x4] = "QR req", [0x5] = "BR req",
391 [0x6] = "QR resp", [0x7] = "BR resp",
392 [0x8] = "cycle start", [0x9] = "Lk req",
393 [0xa] = "async stream packet", [0xb] = "Lk resp",
394 [0xc] = "-reserved-", [0xd] = "-reserved-",
395 [0xe] = "link internal", [0xf] = "-reserved-",
396 };
397 static const char *phys[] = {
398 [0x0] = "phy config packet", [0x1] = "link-on packet",
399 [0x2] = "self-id packet", [0x3] = "-reserved-",
400 };
401
402 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
403 {
404 int tcode = header[0] >> 4 & 0xf;
405 char specific[12];
406
407 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
408 return;
409
410 if (unlikely(evt >= ARRAY_SIZE(evts)))
411 evt = 0x1f;
412
413 if (evt == OHCI1394_evt_bus_reset) {
414 fw_notify("A%c evt_bus_reset, generation %d\n",
415 dir, (header[2] >> 16) & 0xff);
416 return;
417 }
418
419 if (header[0] == ~header[1]) {
420 fw_notify("A%c %s, %s, %08x\n",
421 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
422 return;
423 }
424
425 switch (tcode) {
426 case 0x0: case 0x6: case 0x8:
427 snprintf(specific, sizeof(specific), " = %08x",
428 be32_to_cpu((__force __be32)header[3]));
429 break;
430 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
431 snprintf(specific, sizeof(specific), " %x,%x",
432 header[3] >> 16, header[3] & 0xffff);
433 break;
434 default:
435 specific[0] = '\0';
436 }
437
438 switch (tcode) {
439 case 0xe: case 0xa:
440 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
441 break;
442 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
443 fw_notify("A%c spd %x tl %02x, "
444 "%04x -> %04x, %s, "
445 "%s, %04x%08x%s\n",
446 dir, speed, header[0] >> 10 & 0x3f,
447 header[1] >> 16, header[0] >> 16, evts[evt],
448 tcodes[tcode], header[1] & 0xffff, header[2], specific);
449 break;
450 default:
451 fw_notify("A%c spd %x tl %02x, "
452 "%04x -> %04x, %s, "
453 "%s%s\n",
454 dir, speed, header[0] >> 10 & 0x3f,
455 header[1] >> 16, header[0] >> 16, evts[evt],
456 tcodes[tcode], specific);
457 }
458 }
459
460 #else
461
462 #define param_debug 0
463 static inline void log_irqs(u32 evt) {}
464 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
465 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
466
467 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
468
469 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
470 {
471 writel(data, ohci->registers + offset);
472 }
473
474 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
475 {
476 return readl(ohci->registers + offset);
477 }
478
479 static inline void flush_writes(const struct fw_ohci *ohci)
480 {
481 /* Do a dummy read to flush writes. */
482 reg_read(ohci, OHCI1394_Version);
483 }
484
485 static int read_phy_reg(struct fw_ohci *ohci, int addr)
486 {
487 u32 val;
488 int i;
489
490 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
491 for (i = 0; i < 3 + 100; i++) {
492 val = reg_read(ohci, OHCI1394_PhyControl);
493 if (val & OHCI1394_PhyControl_ReadDone)
494 return OHCI1394_PhyControl_ReadData(val);
495
496 /*
497 * Try a few times without waiting. Sleeping is necessary
498 * only when the link/PHY interface is busy.
499 */
500 if (i >= 3)
501 msleep(1);
502 }
503 fw_error("failed to read phy reg\n");
504
505 return -EBUSY;
506 }
507
508 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
509 {
510 int i;
511
512 reg_write(ohci, OHCI1394_PhyControl,
513 OHCI1394_PhyControl_Write(addr, val));
514 for (i = 0; i < 3 + 100; i++) {
515 val = reg_read(ohci, OHCI1394_PhyControl);
516 if (!(val & OHCI1394_PhyControl_WritePending))
517 return 0;
518
519 if (i >= 3)
520 msleep(1);
521 }
522 fw_error("failed to write phy reg\n");
523
524 return -EBUSY;
525 }
526
527 static int update_phy_reg(struct fw_ohci *ohci, int addr,
528 int clear_bits, int set_bits)
529 {
530 int ret = read_phy_reg(ohci, addr);
531 if (ret < 0)
532 return ret;
533
534 /*
535 * The interrupt status bits are cleared by writing a one bit.
536 * Avoid clearing them unless explicitly requested in set_bits.
537 */
538 if (addr == 5)
539 clear_bits |= PHY_INT_STATUS_BITS;
540
541 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
542 }
543
544 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
545 {
546 int ret;
547
548 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
549 if (ret < 0)
550 return ret;
551
552 return read_phy_reg(ohci, addr);
553 }
554
555 static int ohci_read_phy_reg(struct fw_card *card, int addr)
556 {
557 struct fw_ohci *ohci = fw_ohci(card);
558 int ret;
559
560 mutex_lock(&ohci->phy_reg_mutex);
561 ret = read_phy_reg(ohci, addr);
562 mutex_unlock(&ohci->phy_reg_mutex);
563
564 return ret;
565 }
566
567 static int ohci_update_phy_reg(struct fw_card *card, int addr,
568 int clear_bits, int set_bits)
569 {
570 struct fw_ohci *ohci = fw_ohci(card);
571 int ret;
572
573 mutex_lock(&ohci->phy_reg_mutex);
574 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
575 mutex_unlock(&ohci->phy_reg_mutex);
576
577 return ret;
578 }
579
580 static int ar_context_add_page(struct ar_context *ctx)
581 {
582 struct device *dev = ctx->ohci->card.device;
583 struct ar_buffer *ab;
584 dma_addr_t uninitialized_var(ab_bus);
585 size_t offset;
586
587 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
588 if (ab == NULL)
589 return -ENOMEM;
590
591 ab->next = NULL;
592 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
593 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
594 DESCRIPTOR_STATUS |
595 DESCRIPTOR_BRANCH_ALWAYS);
596 offset = offsetof(struct ar_buffer, data);
597 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
598 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
599 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
600 ab->descriptor.branch_address = 0;
601
602 wmb(); /* finish init of new descriptors before branch_address update */
603 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
604 ctx->last_buffer->next = ab;
605 ctx->last_buffer = ab;
606
607 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
608 flush_writes(ctx->ohci);
609
610 return 0;
611 }
612
613 static void ar_context_release(struct ar_context *ctx)
614 {
615 struct ar_buffer *ab, *ab_next;
616 size_t offset;
617 dma_addr_t ab_bus;
618
619 for (ab = ctx->current_buffer; ab; ab = ab_next) {
620 ab_next = ab->next;
621 offset = offsetof(struct ar_buffer, data);
622 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
623 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
624 ab, ab_bus);
625 }
626 }
627
628 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
629 #define cond_le32_to_cpu(v) \
630 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
631 #else
632 #define cond_le32_to_cpu(v) le32_to_cpu(v)
633 #endif
634
635 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
636 {
637 struct fw_ohci *ohci = ctx->ohci;
638 struct fw_packet p;
639 u32 status, length, tcode;
640 int evt;
641
642 p.header[0] = cond_le32_to_cpu(buffer[0]);
643 p.header[1] = cond_le32_to_cpu(buffer[1]);
644 p.header[2] = cond_le32_to_cpu(buffer[2]);
645
646 tcode = (p.header[0] >> 4) & 0x0f;
647 switch (tcode) {
648 case TCODE_WRITE_QUADLET_REQUEST:
649 case TCODE_READ_QUADLET_RESPONSE:
650 p.header[3] = (__force __u32) buffer[3];
651 p.header_length = 16;
652 p.payload_length = 0;
653 break;
654
655 case TCODE_READ_BLOCK_REQUEST :
656 p.header[3] = cond_le32_to_cpu(buffer[3]);
657 p.header_length = 16;
658 p.payload_length = 0;
659 break;
660
661 case TCODE_WRITE_BLOCK_REQUEST:
662 case TCODE_READ_BLOCK_RESPONSE:
663 case TCODE_LOCK_REQUEST:
664 case TCODE_LOCK_RESPONSE:
665 p.header[3] = cond_le32_to_cpu(buffer[3]);
666 p.header_length = 16;
667 p.payload_length = p.header[3] >> 16;
668 break;
669
670 case TCODE_WRITE_RESPONSE:
671 case TCODE_READ_QUADLET_REQUEST:
672 case OHCI_TCODE_PHY_PACKET:
673 p.header_length = 12;
674 p.payload_length = 0;
675 break;
676
677 default:
678 /* FIXME: Stop context, discard everything, and restart? */
679 p.header_length = 0;
680 p.payload_length = 0;
681 }
682
683 p.payload = (void *) buffer + p.header_length;
684
685 /* FIXME: What to do about evt_* errors? */
686 length = (p.header_length + p.payload_length + 3) / 4;
687 status = cond_le32_to_cpu(buffer[length]);
688 evt = (status >> 16) & 0x1f;
689
690 p.ack = evt - 16;
691 p.speed = (status >> 21) & 0x7;
692 p.timestamp = status & 0xffff;
693 p.generation = ohci->request_generation;
694
695 log_ar_at_event('R', p.speed, p.header, evt);
696
697 /*
698 * Several controllers, notably from NEC and VIA, forget to
699 * write ack_complete status at PHY packet reception.
700 */
701 if (evt == OHCI1394_evt_no_status &&
702 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
703 p.ack = ACK_COMPLETE;
704
705 /*
706 * The OHCI bus reset handler synthesizes a PHY packet with
707 * the new generation number when a bus reset happens (see
708 * section 8.4.2.3). This helps us determine when a request
709 * was received and make sure we send the response in the same
710 * generation. We only need this for requests; for responses
711 * we use the unique tlabel for finding the matching
712 * request.
713 *
714 * Alas some chips sometimes emit bus reset packets with a
715 * wrong generation. We set the correct generation for these
716 * at a slightly incorrect time (in bus_reset_tasklet).
717 */
718 if (evt == OHCI1394_evt_bus_reset) {
719 if (!(ohci->quirks & QUIRK_RESET_PACKET))
720 ohci->request_generation = (p.header[2] >> 16) & 0xff;
721 } else if (ctx == &ohci->ar_request_ctx) {
722 fw_core_handle_request(&ohci->card, &p);
723 } else {
724 fw_core_handle_response(&ohci->card, &p);
725 }
726
727 return buffer + length + 1;
728 }
729
730 static void ar_context_tasklet(unsigned long data)
731 {
732 struct ar_context *ctx = (struct ar_context *)data;
733 struct fw_ohci *ohci = ctx->ohci;
734 struct ar_buffer *ab;
735 struct descriptor *d;
736 void *buffer, *end;
737
738 ab = ctx->current_buffer;
739 d = &ab->descriptor;
740
741 if (d->res_count == 0) {
742 size_t size, size2, rest, pktsize, size3, offset;
743 dma_addr_t start_bus;
744 void *start;
745
746 /*
747 * This descriptor is finished and we may have a
748 * packet split across this and the next buffer. We
749 * reuse the page for reassembling the split packet.
750 */
751
752 offset = offsetof(struct ar_buffer, data);
753 start = buffer = ab;
754 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
755
756 ab = ab->next;
757 d = &ab->descriptor;
758 size = buffer + PAGE_SIZE - ctx->pointer;
759 /* valid buffer data in the next page */
760 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
761 /* what actually fits in this page */
762 size2 = min(rest, (size_t)PAGE_SIZE - size);
763 memmove(buffer, ctx->pointer, size);
764 memcpy(buffer + size, ab->data, size2);
765 ctx->current_buffer = ab;
766 ctx->pointer = (void *) ab->data + rest;
767
768 while (size > 0) {
769 void *next = handle_ar_packet(ctx, buffer);
770 pktsize = next - buffer;
771 if (pktsize >= size) {
772 /*
773 * We have handled all the data that was
774 * originally in this page, so we can now
775 * continue in the next page.
776 */
777 buffer = next;
778 break;
779 }
780 /* move the next packet to the start of the buffer */
781 memmove(buffer, next, size + size2 - pktsize);
782 size -= pktsize;
783 /* fill up this page again */
784 size3 = min(rest - size2,
785 (size_t)PAGE_SIZE - size - size2);
786 memcpy(buffer + size + size2,
787 (void *) ab->data + size2, size3);
788 size2 += size3;
789 }
790
791 /* handle the packets that are fully in the next page */
792 buffer = (void *) ab->data + (buffer - (start + size));
793 end = (void *) ab->data + rest;
794
795 while (buffer < end)
796 buffer = handle_ar_packet(ctx, buffer);
797
798 dma_free_coherent(ohci->card.device, PAGE_SIZE,
799 start, start_bus);
800 ar_context_add_page(ctx);
801 } else {
802 buffer = ctx->pointer;
803 ctx->pointer = end =
804 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
805
806 while (buffer < end)
807 buffer = handle_ar_packet(ctx, buffer);
808 }
809 }
810
811 static int ar_context_init(struct ar_context *ctx,
812 struct fw_ohci *ohci, u32 regs)
813 {
814 struct ar_buffer ab;
815
816 ctx->regs = regs;
817 ctx->ohci = ohci;
818 ctx->last_buffer = &ab;
819 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
820
821 ar_context_add_page(ctx);
822 ar_context_add_page(ctx);
823 ctx->current_buffer = ab.next;
824 ctx->pointer = ctx->current_buffer->data;
825
826 return 0;
827 }
828
829 static void ar_context_run(struct ar_context *ctx)
830 {
831 struct ar_buffer *ab = ctx->current_buffer;
832 dma_addr_t ab_bus;
833 size_t offset;
834
835 offset = offsetof(struct ar_buffer, data);
836 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
837
838 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
839 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
840 flush_writes(ctx->ohci);
841 }
842
843 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
844 {
845 int b, key;
846
847 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
848 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
849
850 /* figure out which descriptor the branch address goes in */
851 if (z == 2 && (b == 3 || key == 2))
852 return d;
853 else
854 return d + z - 1;
855 }
856
857 static void context_tasklet(unsigned long data)
858 {
859 struct context *ctx = (struct context *) data;
860 struct descriptor *d, *last;
861 u32 address;
862 int z;
863 struct descriptor_buffer *desc;
864
865 desc = list_entry(ctx->buffer_list.next,
866 struct descriptor_buffer, list);
867 last = ctx->last;
868 while (last->branch_address != 0) {
869 struct descriptor_buffer *old_desc = desc;
870 address = le32_to_cpu(last->branch_address);
871 z = address & 0xf;
872 address &= ~0xf;
873
874 /* If the branch address points to a buffer outside of the
875 * current buffer, advance to the next buffer. */
876 if (address < desc->buffer_bus ||
877 address >= desc->buffer_bus + desc->used)
878 desc = list_entry(desc->list.next,
879 struct descriptor_buffer, list);
880 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
881 last = find_branch_descriptor(d, z);
882
883 if (!ctx->callback(ctx, d, last))
884 break;
885
886 if (old_desc != desc) {
887 /* If we've advanced to the next buffer, move the
888 * previous buffer to the free list. */
889 unsigned long flags;
890 old_desc->used = 0;
891 spin_lock_irqsave(&ctx->ohci->lock, flags);
892 list_move_tail(&old_desc->list, &ctx->buffer_list);
893 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
894 }
895 ctx->last = last;
896 }
897 }
898
899 /*
900 * Allocate a new buffer and add it to the list of free buffers for this
901 * context. Must be called with ohci->lock held.
902 */
903 static int context_add_buffer(struct context *ctx)
904 {
905 struct descriptor_buffer *desc;
906 dma_addr_t uninitialized_var(bus_addr);
907 int offset;
908
909 /*
910 * 16MB of descriptors should be far more than enough for any DMA
911 * program. This will catch run-away userspace or DoS attacks.
912 */
913 if (ctx->total_allocation >= 16*1024*1024)
914 return -ENOMEM;
915
916 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
917 &bus_addr, GFP_ATOMIC);
918 if (!desc)
919 return -ENOMEM;
920
921 offset = (void *)&desc->buffer - (void *)desc;
922 desc->buffer_size = PAGE_SIZE - offset;
923 desc->buffer_bus = bus_addr + offset;
924 desc->used = 0;
925
926 list_add_tail(&desc->list, &ctx->buffer_list);
927 ctx->total_allocation += PAGE_SIZE;
928
929 return 0;
930 }
931
932 static int context_init(struct context *ctx, struct fw_ohci *ohci,
933 u32 regs, descriptor_callback_t callback)
934 {
935 ctx->ohci = ohci;
936 ctx->regs = regs;
937 ctx->total_allocation = 0;
938
939 INIT_LIST_HEAD(&ctx->buffer_list);
940 if (context_add_buffer(ctx) < 0)
941 return -ENOMEM;
942
943 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
944 struct descriptor_buffer, list);
945
946 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
947 ctx->callback = callback;
948
949 /*
950 * We put a dummy descriptor in the buffer that has a NULL
951 * branch address and looks like it's been sent. That way we
952 * have a descriptor to append DMA programs to.
953 */
954 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
955 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
956 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
957 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
958 ctx->last = ctx->buffer_tail->buffer;
959 ctx->prev = ctx->buffer_tail->buffer;
960
961 return 0;
962 }
963
964 static void context_release(struct context *ctx)
965 {
966 struct fw_card *card = &ctx->ohci->card;
967 struct descriptor_buffer *desc, *tmp;
968
969 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
970 dma_free_coherent(card->device, PAGE_SIZE, desc,
971 desc->buffer_bus -
972 ((void *)&desc->buffer - (void *)desc));
973 }
974
975 /* Must be called with ohci->lock held */
976 static struct descriptor *context_get_descriptors(struct context *ctx,
977 int z, dma_addr_t *d_bus)
978 {
979 struct descriptor *d = NULL;
980 struct descriptor_buffer *desc = ctx->buffer_tail;
981
982 if (z * sizeof(*d) > desc->buffer_size)
983 return NULL;
984
985 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
986 /* No room for the descriptor in this buffer, so advance to the
987 * next one. */
988
989 if (desc->list.next == &ctx->buffer_list) {
990 /* If there is no free buffer next in the list,
991 * allocate one. */
992 if (context_add_buffer(ctx) < 0)
993 return NULL;
994 }
995 desc = list_entry(desc->list.next,
996 struct descriptor_buffer, list);
997 ctx->buffer_tail = desc;
998 }
999
1000 d = desc->buffer + desc->used / sizeof(*d);
1001 memset(d, 0, z * sizeof(*d));
1002 *d_bus = desc->buffer_bus + desc->used;
1003
1004 return d;
1005 }
1006
1007 static void context_run(struct context *ctx, u32 extra)
1008 {
1009 struct fw_ohci *ohci = ctx->ohci;
1010
1011 reg_write(ohci, COMMAND_PTR(ctx->regs),
1012 le32_to_cpu(ctx->last->branch_address));
1013 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1014 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1015 flush_writes(ohci);
1016 }
1017
1018 static void context_append(struct context *ctx,
1019 struct descriptor *d, int z, int extra)
1020 {
1021 dma_addr_t d_bus;
1022 struct descriptor_buffer *desc = ctx->buffer_tail;
1023
1024 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1025
1026 desc->used += (z + extra) * sizeof(*d);
1027
1028 wmb(); /* finish init of new descriptors before branch_address update */
1029 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1030 ctx->prev = find_branch_descriptor(d, z);
1031
1032 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1033 flush_writes(ctx->ohci);
1034 }
1035
1036 static void context_stop(struct context *ctx)
1037 {
1038 u32 reg;
1039 int i;
1040
1041 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1042 flush_writes(ctx->ohci);
1043
1044 for (i = 0; i < 10; i++) {
1045 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1046 if ((reg & CONTEXT_ACTIVE) == 0)
1047 return;
1048
1049 mdelay(1);
1050 }
1051 fw_error("Error: DMA context still active (0x%08x)\n", reg);
1052 }
1053
1054 struct driver_data {
1055 struct fw_packet *packet;
1056 };
1057
1058 /*
1059 * This function apppends a packet to the DMA queue for transmission.
1060 * Must always be called with the ochi->lock held to ensure proper
1061 * generation handling and locking around packet queue manipulation.
1062 */
1063 static int at_context_queue_packet(struct context *ctx,
1064 struct fw_packet *packet)
1065 {
1066 struct fw_ohci *ohci = ctx->ohci;
1067 dma_addr_t d_bus, uninitialized_var(payload_bus);
1068 struct driver_data *driver_data;
1069 struct descriptor *d, *last;
1070 __le32 *header;
1071 int z, tcode;
1072 u32 reg;
1073
1074 d = context_get_descriptors(ctx, 4, &d_bus);
1075 if (d == NULL) {
1076 packet->ack = RCODE_SEND_ERROR;
1077 return -1;
1078 }
1079
1080 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1081 d[0].res_count = cpu_to_le16(packet->timestamp);
1082
1083 /*
1084 * The DMA format for asyncronous link packets is different
1085 * from the IEEE1394 layout, so shift the fields around
1086 * accordingly. If header_length is 8, it's a PHY packet, to
1087 * which we need to prepend an extra quadlet.
1088 */
1089
1090 header = (__le32 *) &d[1];
1091 switch (packet->header_length) {
1092 case 16:
1093 case 12:
1094 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1095 (packet->speed << 16));
1096 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1097 (packet->header[0] & 0xffff0000));
1098 header[2] = cpu_to_le32(packet->header[2]);
1099
1100 tcode = (packet->header[0] >> 4) & 0x0f;
1101 if (TCODE_IS_BLOCK_PACKET(tcode))
1102 header[3] = cpu_to_le32(packet->header[3]);
1103 else
1104 header[3] = (__force __le32) packet->header[3];
1105
1106 d[0].req_count = cpu_to_le16(packet->header_length);
1107 break;
1108
1109 case 8:
1110 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1111 (packet->speed << 16));
1112 header[1] = cpu_to_le32(packet->header[0]);
1113 header[2] = cpu_to_le32(packet->header[1]);
1114 d[0].req_count = cpu_to_le16(12);
1115
1116 if (is_ping_packet(packet->header))
1117 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1118 break;
1119
1120 case 4:
1121 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1122 (packet->speed << 16));
1123 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1124 d[0].req_count = cpu_to_le16(8);
1125 break;
1126
1127 default:
1128 /* BUG(); */
1129 packet->ack = RCODE_SEND_ERROR;
1130 return -1;
1131 }
1132
1133 driver_data = (struct driver_data *) &d[3];
1134 driver_data->packet = packet;
1135 packet->driver_data = driver_data;
1136
1137 if (packet->payload_length > 0) {
1138 payload_bus =
1139 dma_map_single(ohci->card.device, packet->payload,
1140 packet->payload_length, DMA_TO_DEVICE);
1141 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1142 packet->ack = RCODE_SEND_ERROR;
1143 return -1;
1144 }
1145 packet->payload_bus = payload_bus;
1146 packet->payload_mapped = true;
1147
1148 d[2].req_count = cpu_to_le16(packet->payload_length);
1149 d[2].data_address = cpu_to_le32(payload_bus);
1150 last = &d[2];
1151 z = 3;
1152 } else {
1153 last = &d[0];
1154 z = 2;
1155 }
1156
1157 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1158 DESCRIPTOR_IRQ_ALWAYS |
1159 DESCRIPTOR_BRANCH_ALWAYS);
1160
1161 /*
1162 * If the controller and packet generations don't match, we need to
1163 * bail out and try again. If IntEvent.busReset is set, the AT context
1164 * is halted, so appending to the context and trying to run it is
1165 * futile. Most controllers do the right thing and just flush the AT
1166 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1167 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1168 * up stalling out. So we just bail out in software and try again
1169 * later, and everyone is happy.
1170 * FIXME: Document how the locking works.
1171 */
1172 if (ohci->generation != packet->generation ||
1173 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1174 if (packet->payload_mapped)
1175 dma_unmap_single(ohci->card.device, payload_bus,
1176 packet->payload_length, DMA_TO_DEVICE);
1177 packet->ack = RCODE_GENERATION;
1178 return -1;
1179 }
1180
1181 context_append(ctx, d, z, 4 - z);
1182
1183 /* If the context isn't already running, start it up. */
1184 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1185 if ((reg & CONTEXT_RUN) == 0)
1186 context_run(ctx, 0);
1187
1188 return 0;
1189 }
1190
1191 static int handle_at_packet(struct context *context,
1192 struct descriptor *d,
1193 struct descriptor *last)
1194 {
1195 struct driver_data *driver_data;
1196 struct fw_packet *packet;
1197 struct fw_ohci *ohci = context->ohci;
1198 int evt;
1199
1200 if (last->transfer_status == 0)
1201 /* This descriptor isn't done yet, stop iteration. */
1202 return 0;
1203
1204 driver_data = (struct driver_data *) &d[3];
1205 packet = driver_data->packet;
1206 if (packet == NULL)
1207 /* This packet was cancelled, just continue. */
1208 return 1;
1209
1210 if (packet->payload_mapped)
1211 dma_unmap_single(ohci->card.device, packet->payload_bus,
1212 packet->payload_length, DMA_TO_DEVICE);
1213
1214 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1215 packet->timestamp = le16_to_cpu(last->res_count);
1216
1217 log_ar_at_event('T', packet->speed, packet->header, evt);
1218
1219 switch (evt) {
1220 case OHCI1394_evt_timeout:
1221 /* Async response transmit timed out. */
1222 packet->ack = RCODE_CANCELLED;
1223 break;
1224
1225 case OHCI1394_evt_flushed:
1226 /*
1227 * The packet was flushed should give same error as
1228 * when we try to use a stale generation count.
1229 */
1230 packet->ack = RCODE_GENERATION;
1231 break;
1232
1233 case OHCI1394_evt_missing_ack:
1234 /*
1235 * Using a valid (current) generation count, but the
1236 * node is not on the bus or not sending acks.
1237 */
1238 packet->ack = RCODE_NO_ACK;
1239 break;
1240
1241 case ACK_COMPLETE + 0x10:
1242 case ACK_PENDING + 0x10:
1243 case ACK_BUSY_X + 0x10:
1244 case ACK_BUSY_A + 0x10:
1245 case ACK_BUSY_B + 0x10:
1246 case ACK_DATA_ERROR + 0x10:
1247 case ACK_TYPE_ERROR + 0x10:
1248 packet->ack = evt - 0x10;
1249 break;
1250
1251 default:
1252 packet->ack = RCODE_SEND_ERROR;
1253 break;
1254 }
1255
1256 packet->callback(packet, &ohci->card, packet->ack);
1257
1258 return 1;
1259 }
1260
1261 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1262 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1263 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1264 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1265 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1266
1267 static void handle_local_rom(struct fw_ohci *ohci,
1268 struct fw_packet *packet, u32 csr)
1269 {
1270 struct fw_packet response;
1271 int tcode, length, i;
1272
1273 tcode = HEADER_GET_TCODE(packet->header[0]);
1274 if (TCODE_IS_BLOCK_PACKET(tcode))
1275 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1276 else
1277 length = 4;
1278
1279 i = csr - CSR_CONFIG_ROM;
1280 if (i + length > CONFIG_ROM_SIZE) {
1281 fw_fill_response(&response, packet->header,
1282 RCODE_ADDRESS_ERROR, NULL, 0);
1283 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1284 fw_fill_response(&response, packet->header,
1285 RCODE_TYPE_ERROR, NULL, 0);
1286 } else {
1287 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1288 (void *) ohci->config_rom + i, length);
1289 }
1290
1291 fw_core_handle_response(&ohci->card, &response);
1292 }
1293
1294 static void handle_local_lock(struct fw_ohci *ohci,
1295 struct fw_packet *packet, u32 csr)
1296 {
1297 struct fw_packet response;
1298 int tcode, length, ext_tcode, sel, try;
1299 __be32 *payload, lock_old;
1300 u32 lock_arg, lock_data;
1301
1302 tcode = HEADER_GET_TCODE(packet->header[0]);
1303 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1304 payload = packet->payload;
1305 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1306
1307 if (tcode == TCODE_LOCK_REQUEST &&
1308 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1309 lock_arg = be32_to_cpu(payload[0]);
1310 lock_data = be32_to_cpu(payload[1]);
1311 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1312 lock_arg = 0;
1313 lock_data = 0;
1314 } else {
1315 fw_fill_response(&response, packet->header,
1316 RCODE_TYPE_ERROR, NULL, 0);
1317 goto out;
1318 }
1319
1320 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1321 reg_write(ohci, OHCI1394_CSRData, lock_data);
1322 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1323 reg_write(ohci, OHCI1394_CSRControl, sel);
1324
1325 for (try = 0; try < 20; try++)
1326 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1327 lock_old = cpu_to_be32(reg_read(ohci,
1328 OHCI1394_CSRData));
1329 fw_fill_response(&response, packet->header,
1330 RCODE_COMPLETE,
1331 &lock_old, sizeof(lock_old));
1332 goto out;
1333 }
1334
1335 fw_error("swap not done (CSR lock timeout)\n");
1336 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1337
1338 out:
1339 fw_core_handle_response(&ohci->card, &response);
1340 }
1341
1342 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1343 {
1344 u64 offset, csr;
1345
1346 if (ctx == &ctx->ohci->at_request_ctx) {
1347 packet->ack = ACK_PENDING;
1348 packet->callback(packet, &ctx->ohci->card, packet->ack);
1349 }
1350
1351 offset =
1352 ((unsigned long long)
1353 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1354 packet->header[2];
1355 csr = offset - CSR_REGISTER_BASE;
1356
1357 /* Handle config rom reads. */
1358 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1359 handle_local_rom(ctx->ohci, packet, csr);
1360 else switch (csr) {
1361 case CSR_BUS_MANAGER_ID:
1362 case CSR_BANDWIDTH_AVAILABLE:
1363 case CSR_CHANNELS_AVAILABLE_HI:
1364 case CSR_CHANNELS_AVAILABLE_LO:
1365 handle_local_lock(ctx->ohci, packet, csr);
1366 break;
1367 default:
1368 if (ctx == &ctx->ohci->at_request_ctx)
1369 fw_core_handle_request(&ctx->ohci->card, packet);
1370 else
1371 fw_core_handle_response(&ctx->ohci->card, packet);
1372 break;
1373 }
1374
1375 if (ctx == &ctx->ohci->at_response_ctx) {
1376 packet->ack = ACK_COMPLETE;
1377 packet->callback(packet, &ctx->ohci->card, packet->ack);
1378 }
1379 }
1380
1381 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1382 {
1383 unsigned long flags;
1384 int ret;
1385
1386 spin_lock_irqsave(&ctx->ohci->lock, flags);
1387
1388 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1389 ctx->ohci->generation == packet->generation) {
1390 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1391 handle_local_request(ctx, packet);
1392 return;
1393 }
1394
1395 ret = at_context_queue_packet(ctx, packet);
1396 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1397
1398 if (ret < 0)
1399 packet->callback(packet, &ctx->ohci->card, packet->ack);
1400
1401 }
1402
1403 static u32 cycle_timer_ticks(u32 cycle_timer)
1404 {
1405 u32 ticks;
1406
1407 ticks = cycle_timer & 0xfff;
1408 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1409 ticks += (3072 * 8000) * (cycle_timer >> 25);
1410
1411 return ticks;
1412 }
1413
1414 /*
1415 * Some controllers exhibit one or more of the following bugs when updating the
1416 * iso cycle timer register:
1417 * - When the lowest six bits are wrapping around to zero, a read that happens
1418 * at the same time will return garbage in the lowest ten bits.
1419 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1420 * not incremented for about 60 ns.
1421 * - Occasionally, the entire register reads zero.
1422 *
1423 * To catch these, we read the register three times and ensure that the
1424 * difference between each two consecutive reads is approximately the same, i.e.
1425 * less than twice the other. Furthermore, any negative difference indicates an
1426 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1427 * execute, so we have enough precision to compute the ratio of the differences.)
1428 */
1429 static u32 get_cycle_time(struct fw_ohci *ohci)
1430 {
1431 u32 c0, c1, c2;
1432 u32 t0, t1, t2;
1433 s32 diff01, diff12;
1434 int i;
1435
1436 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1437
1438 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1439 i = 0;
1440 c1 = c2;
1441 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1442 do {
1443 c0 = c1;
1444 c1 = c2;
1445 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1446 t0 = cycle_timer_ticks(c0);
1447 t1 = cycle_timer_ticks(c1);
1448 t2 = cycle_timer_ticks(c2);
1449 diff01 = t1 - t0;
1450 diff12 = t2 - t1;
1451 } while ((diff01 <= 0 || diff12 <= 0 ||
1452 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1453 && i++ < 20);
1454 }
1455
1456 return c2;
1457 }
1458
1459 /*
1460 * This function has to be called at least every 64 seconds. The bus_time
1461 * field stores not only the upper 25 bits of the BUS_TIME register but also
1462 * the most significant bit of the cycle timer in bit 6 so that we can detect
1463 * changes in this bit.
1464 */
1465 static u32 update_bus_time(struct fw_ohci *ohci)
1466 {
1467 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1468
1469 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1470 ohci->bus_time += 0x40;
1471
1472 return ohci->bus_time | cycle_time_seconds;
1473 }
1474
1475 static void bus_reset_tasklet(unsigned long data)
1476 {
1477 struct fw_ohci *ohci = (struct fw_ohci *)data;
1478 int self_id_count, i, j, reg;
1479 int generation, new_generation;
1480 unsigned long flags;
1481 void *free_rom = NULL;
1482 dma_addr_t free_rom_bus = 0;
1483 bool is_new_root;
1484
1485 reg = reg_read(ohci, OHCI1394_NodeID);
1486 if (!(reg & OHCI1394_NodeID_idValid)) {
1487 fw_notify("node ID not valid, new bus reset in progress\n");
1488 return;
1489 }
1490 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1491 fw_notify("malconfigured bus\n");
1492 return;
1493 }
1494 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1495 OHCI1394_NodeID_nodeNumber);
1496
1497 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1498 if (!(ohci->is_root && is_new_root))
1499 reg_write(ohci, OHCI1394_LinkControlSet,
1500 OHCI1394_LinkControl_cycleMaster);
1501 ohci->is_root = is_new_root;
1502
1503 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1504 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1505 fw_notify("inconsistent self IDs\n");
1506 return;
1507 }
1508 /*
1509 * The count in the SelfIDCount register is the number of
1510 * bytes in the self ID receive buffer. Since we also receive
1511 * the inverted quadlets and a header quadlet, we shift one
1512 * bit extra to get the actual number of self IDs.
1513 */
1514 self_id_count = (reg >> 3) & 0xff;
1515 if (self_id_count == 0 || self_id_count > 252) {
1516 fw_notify("inconsistent self IDs\n");
1517 return;
1518 }
1519 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1520 rmb();
1521
1522 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1523 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1524 fw_notify("inconsistent self IDs\n");
1525 return;
1526 }
1527 ohci->self_id_buffer[j] =
1528 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1529 }
1530 rmb();
1531
1532 /*
1533 * Check the consistency of the self IDs we just read. The
1534 * problem we face is that a new bus reset can start while we
1535 * read out the self IDs from the DMA buffer. If this happens,
1536 * the DMA buffer will be overwritten with new self IDs and we
1537 * will read out inconsistent data. The OHCI specification
1538 * (section 11.2) recommends a technique similar to
1539 * linux/seqlock.h, where we remember the generation of the
1540 * self IDs in the buffer before reading them out and compare
1541 * it to the current generation after reading them out. If
1542 * the two generations match we know we have a consistent set
1543 * of self IDs.
1544 */
1545
1546 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1547 if (new_generation != generation) {
1548 fw_notify("recursive bus reset detected, "
1549 "discarding self ids\n");
1550 return;
1551 }
1552
1553 /* FIXME: Document how the locking works. */
1554 spin_lock_irqsave(&ohci->lock, flags);
1555
1556 ohci->generation = generation;
1557 context_stop(&ohci->at_request_ctx);
1558 context_stop(&ohci->at_response_ctx);
1559 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1560
1561 if (ohci->quirks & QUIRK_RESET_PACKET)
1562 ohci->request_generation = generation;
1563
1564 /*
1565 * This next bit is unrelated to the AT context stuff but we
1566 * have to do it under the spinlock also. If a new config rom
1567 * was set up before this reset, the old one is now no longer
1568 * in use and we can free it. Update the config rom pointers
1569 * to point to the current config rom and clear the
1570 * next_config_rom pointer so a new update can take place.
1571 */
1572
1573 if (ohci->next_config_rom != NULL) {
1574 if (ohci->next_config_rom != ohci->config_rom) {
1575 free_rom = ohci->config_rom;
1576 free_rom_bus = ohci->config_rom_bus;
1577 }
1578 ohci->config_rom = ohci->next_config_rom;
1579 ohci->config_rom_bus = ohci->next_config_rom_bus;
1580 ohci->next_config_rom = NULL;
1581
1582 /*
1583 * Restore config_rom image and manually update
1584 * config_rom registers. Writing the header quadlet
1585 * will indicate that the config rom is ready, so we
1586 * do that last.
1587 */
1588 reg_write(ohci, OHCI1394_BusOptions,
1589 be32_to_cpu(ohci->config_rom[2]));
1590 ohci->config_rom[0] = ohci->next_header;
1591 reg_write(ohci, OHCI1394_ConfigROMhdr,
1592 be32_to_cpu(ohci->next_header));
1593 }
1594
1595 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1596 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1597 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1598 #endif
1599
1600 spin_unlock_irqrestore(&ohci->lock, flags);
1601
1602 if (free_rom)
1603 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1604 free_rom, free_rom_bus);
1605
1606 log_selfids(ohci->node_id, generation,
1607 self_id_count, ohci->self_id_buffer);
1608
1609 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1610 self_id_count, ohci->self_id_buffer,
1611 ohci->csr_state_setclear_abdicate);
1612 ohci->csr_state_setclear_abdicate = false;
1613 }
1614
1615 static irqreturn_t irq_handler(int irq, void *data)
1616 {
1617 struct fw_ohci *ohci = data;
1618 u32 event, iso_event;
1619 int i;
1620
1621 event = reg_read(ohci, OHCI1394_IntEventClear);
1622
1623 if (!event || !~event)
1624 return IRQ_NONE;
1625
1626 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1627 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1628 log_irqs(event);
1629
1630 if (event & OHCI1394_selfIDComplete)
1631 tasklet_schedule(&ohci->bus_reset_tasklet);
1632
1633 if (event & OHCI1394_RQPkt)
1634 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1635
1636 if (event & OHCI1394_RSPkt)
1637 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1638
1639 if (event & OHCI1394_reqTxComplete)
1640 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1641
1642 if (event & OHCI1394_respTxComplete)
1643 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1644
1645 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1646 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1647
1648 while (iso_event) {
1649 i = ffs(iso_event) - 1;
1650 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1651 iso_event &= ~(1 << i);
1652 }
1653
1654 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1655 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1656
1657 while (iso_event) {
1658 i = ffs(iso_event) - 1;
1659 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1660 iso_event &= ~(1 << i);
1661 }
1662
1663 if (unlikely(event & OHCI1394_regAccessFail))
1664 fw_error("Register access failure - "
1665 "please notify linux1394-devel@lists.sf.net\n");
1666
1667 if (unlikely(event & OHCI1394_postedWriteErr))
1668 fw_error("PCI posted write error\n");
1669
1670 if (unlikely(event & OHCI1394_cycleTooLong)) {
1671 if (printk_ratelimit())
1672 fw_notify("isochronous cycle too long\n");
1673 reg_write(ohci, OHCI1394_LinkControlSet,
1674 OHCI1394_LinkControl_cycleMaster);
1675 }
1676
1677 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1678 /*
1679 * We need to clear this event bit in order to make
1680 * cycleMatch isochronous I/O work. In theory we should
1681 * stop active cycleMatch iso contexts now and restart
1682 * them at least two cycles later. (FIXME?)
1683 */
1684 if (printk_ratelimit())
1685 fw_notify("isochronous cycle inconsistent\n");
1686 }
1687
1688 if (event & OHCI1394_cycle64Seconds) {
1689 spin_lock(&ohci->lock);
1690 update_bus_time(ohci);
1691 spin_unlock(&ohci->lock);
1692 }
1693
1694 return IRQ_HANDLED;
1695 }
1696
1697 static int software_reset(struct fw_ohci *ohci)
1698 {
1699 int i;
1700
1701 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1702
1703 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1704 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1705 OHCI1394_HCControl_softReset) == 0)
1706 return 0;
1707 msleep(1);
1708 }
1709
1710 return -EBUSY;
1711 }
1712
1713 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1714 {
1715 size_t size = length * 4;
1716
1717 memcpy(dest, src, size);
1718 if (size < CONFIG_ROM_SIZE)
1719 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1720 }
1721
1722 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1723 {
1724 bool enable_1394a;
1725 int ret, clear, set, offset;
1726
1727 /* Check if the driver should configure link and PHY. */
1728 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1729 OHCI1394_HCControl_programPhyEnable))
1730 return 0;
1731
1732 /* Paranoia: check whether the PHY supports 1394a, too. */
1733 enable_1394a = false;
1734 ret = read_phy_reg(ohci, 2);
1735 if (ret < 0)
1736 return ret;
1737 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1738 ret = read_paged_phy_reg(ohci, 1, 8);
1739 if (ret < 0)
1740 return ret;
1741 if (ret >= 1)
1742 enable_1394a = true;
1743 }
1744
1745 if (ohci->quirks & QUIRK_NO_1394A)
1746 enable_1394a = false;
1747
1748 /* Configure PHY and link consistently. */
1749 if (enable_1394a) {
1750 clear = 0;
1751 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1752 } else {
1753 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1754 set = 0;
1755 }
1756 ret = update_phy_reg(ohci, 5, clear, set);
1757 if (ret < 0)
1758 return ret;
1759
1760 if (enable_1394a)
1761 offset = OHCI1394_HCControlSet;
1762 else
1763 offset = OHCI1394_HCControlClear;
1764 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1765
1766 /* Clean up: configuration has been taken care of. */
1767 reg_write(ohci, OHCI1394_HCControlClear,
1768 OHCI1394_HCControl_programPhyEnable);
1769
1770 return 0;
1771 }
1772
1773 static int ohci_enable(struct fw_card *card,
1774 const __be32 *config_rom, size_t length)
1775 {
1776 struct fw_ohci *ohci = fw_ohci(card);
1777 struct pci_dev *dev = to_pci_dev(card->device);
1778 u32 lps, seconds, version, irqs;
1779 int i, ret;
1780
1781 if (software_reset(ohci)) {
1782 fw_error("Failed to reset ohci card.\n");
1783 return -EBUSY;
1784 }
1785
1786 /*
1787 * Now enable LPS, which we need in order to start accessing
1788 * most of the registers. In fact, on some cards (ALI M5251),
1789 * accessing registers in the SClk domain without LPS enabled
1790 * will lock up the machine. Wait 50msec to make sure we have
1791 * full link enabled. However, with some cards (well, at least
1792 * a JMicron PCIe card), we have to try again sometimes.
1793 */
1794 reg_write(ohci, OHCI1394_HCControlSet,
1795 OHCI1394_HCControl_LPS |
1796 OHCI1394_HCControl_postedWriteEnable);
1797 flush_writes(ohci);
1798
1799 for (lps = 0, i = 0; !lps && i < 3; i++) {
1800 msleep(50);
1801 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1802 OHCI1394_HCControl_LPS;
1803 }
1804
1805 if (!lps) {
1806 fw_error("Failed to set Link Power Status\n");
1807 return -EIO;
1808 }
1809
1810 reg_write(ohci, OHCI1394_HCControlClear,
1811 OHCI1394_HCControl_noByteSwapData);
1812
1813 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1814 reg_write(ohci, OHCI1394_LinkControlSet,
1815 OHCI1394_LinkControl_rcvSelfID |
1816 OHCI1394_LinkControl_rcvPhyPkt |
1817 OHCI1394_LinkControl_cycleTimerEnable |
1818 OHCI1394_LinkControl_cycleMaster);
1819
1820 reg_write(ohci, OHCI1394_ATRetries,
1821 OHCI1394_MAX_AT_REQ_RETRIES |
1822 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1823 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1824 (200 << 16));
1825
1826 seconds = lower_32_bits(get_seconds());
1827 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1828 ohci->bus_time = seconds & ~0x3f;
1829
1830 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1831 if (version >= OHCI_VERSION_1_1) {
1832 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
1833 0xfffffffe);
1834 card->broadcast_channel_auto_allocated = true;
1835 }
1836
1837 /* Get implemented bits of the priority arbitration request counter. */
1838 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
1839 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
1840 reg_write(ohci, OHCI1394_FairnessControl, 0);
1841 card->priority_budget_implemented = ohci->pri_req_max != 0;
1842
1843 ar_context_run(&ohci->ar_request_ctx);
1844 ar_context_run(&ohci->ar_response_ctx);
1845
1846 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1847 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1848 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1849
1850 ret = configure_1394a_enhancements(ohci);
1851 if (ret < 0)
1852 return ret;
1853
1854 /* Activate link_on bit and contender bit in our self ID packets.*/
1855 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1856 if (ret < 0)
1857 return ret;
1858
1859 /*
1860 * When the link is not yet enabled, the atomic config rom
1861 * update mechanism described below in ohci_set_config_rom()
1862 * is not active. We have to update ConfigRomHeader and
1863 * BusOptions manually, and the write to ConfigROMmap takes
1864 * effect immediately. We tie this to the enabling of the
1865 * link, so we have a valid config rom before enabling - the
1866 * OHCI requires that ConfigROMhdr and BusOptions have valid
1867 * values before enabling.
1868 *
1869 * However, when the ConfigROMmap is written, some controllers
1870 * always read back quadlets 0 and 2 from the config rom to
1871 * the ConfigRomHeader and BusOptions registers on bus reset.
1872 * They shouldn't do that in this initial case where the link
1873 * isn't enabled. This means we have to use the same
1874 * workaround here, setting the bus header to 0 and then write
1875 * the right values in the bus reset tasklet.
1876 */
1877
1878 if (config_rom) {
1879 ohci->next_config_rom =
1880 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1881 &ohci->next_config_rom_bus,
1882 GFP_KERNEL);
1883 if (ohci->next_config_rom == NULL)
1884 return -ENOMEM;
1885
1886 copy_config_rom(ohci->next_config_rom, config_rom, length);
1887 } else {
1888 /*
1889 * In the suspend case, config_rom is NULL, which
1890 * means that we just reuse the old config rom.
1891 */
1892 ohci->next_config_rom = ohci->config_rom;
1893 ohci->next_config_rom_bus = ohci->config_rom_bus;
1894 }
1895
1896 ohci->next_header = ohci->next_config_rom[0];
1897 ohci->next_config_rom[0] = 0;
1898 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1899 reg_write(ohci, OHCI1394_BusOptions,
1900 be32_to_cpu(ohci->next_config_rom[2]));
1901 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1902
1903 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1904
1905 if (!(ohci->quirks & QUIRK_NO_MSI))
1906 pci_enable_msi(dev);
1907 if (request_irq(dev->irq, irq_handler,
1908 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1909 ohci_driver_name, ohci)) {
1910 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1911 pci_disable_msi(dev);
1912 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1913 ohci->config_rom, ohci->config_rom_bus);
1914 return -EIO;
1915 }
1916
1917 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1918 OHCI1394_RQPkt | OHCI1394_RSPkt |
1919 OHCI1394_isochTx | OHCI1394_isochRx |
1920 OHCI1394_postedWriteErr |
1921 OHCI1394_selfIDComplete |
1922 OHCI1394_regAccessFail |
1923 OHCI1394_cycle64Seconds |
1924 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1925 OHCI1394_masterIntEnable;
1926 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1927 irqs |= OHCI1394_busReset;
1928 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1929
1930 reg_write(ohci, OHCI1394_HCControlSet,
1931 OHCI1394_HCControl_linkEnable |
1932 OHCI1394_HCControl_BIBimageValid);
1933 flush_writes(ohci);
1934
1935 /* We are ready to go, reset bus to finish initialization. */
1936 fw_schedule_bus_reset(&ohci->card, false, true);
1937
1938 return 0;
1939 }
1940
1941 static int ohci_set_config_rom(struct fw_card *card,
1942 const __be32 *config_rom, size_t length)
1943 {
1944 struct fw_ohci *ohci;
1945 unsigned long flags;
1946 int ret = -EBUSY;
1947 __be32 *next_config_rom;
1948 dma_addr_t uninitialized_var(next_config_rom_bus);
1949
1950 ohci = fw_ohci(card);
1951
1952 /*
1953 * When the OHCI controller is enabled, the config rom update
1954 * mechanism is a bit tricky, but easy enough to use. See
1955 * section 5.5.6 in the OHCI specification.
1956 *
1957 * The OHCI controller caches the new config rom address in a
1958 * shadow register (ConfigROMmapNext) and needs a bus reset
1959 * for the changes to take place. When the bus reset is
1960 * detected, the controller loads the new values for the
1961 * ConfigRomHeader and BusOptions registers from the specified
1962 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1963 * shadow register. All automatically and atomically.
1964 *
1965 * Now, there's a twist to this story. The automatic load of
1966 * ConfigRomHeader and BusOptions doesn't honor the
1967 * noByteSwapData bit, so with a be32 config rom, the
1968 * controller will load be32 values in to these registers
1969 * during the atomic update, even on litte endian
1970 * architectures. The workaround we use is to put a 0 in the
1971 * header quadlet; 0 is endian agnostic and means that the
1972 * config rom isn't ready yet. In the bus reset tasklet we
1973 * then set up the real values for the two registers.
1974 *
1975 * We use ohci->lock to avoid racing with the code that sets
1976 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1977 */
1978
1979 next_config_rom =
1980 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1981 &next_config_rom_bus, GFP_KERNEL);
1982 if (next_config_rom == NULL)
1983 return -ENOMEM;
1984
1985 spin_lock_irqsave(&ohci->lock, flags);
1986
1987 if (ohci->next_config_rom == NULL) {
1988 ohci->next_config_rom = next_config_rom;
1989 ohci->next_config_rom_bus = next_config_rom_bus;
1990
1991 copy_config_rom(ohci->next_config_rom, config_rom, length);
1992
1993 ohci->next_header = config_rom[0];
1994 ohci->next_config_rom[0] = 0;
1995
1996 reg_write(ohci, OHCI1394_ConfigROMmap,
1997 ohci->next_config_rom_bus);
1998 ret = 0;
1999 }
2000
2001 spin_unlock_irqrestore(&ohci->lock, flags);
2002
2003 /*
2004 * Now initiate a bus reset to have the changes take
2005 * effect. We clean up the old config rom memory and DMA
2006 * mappings in the bus reset tasklet, since the OHCI
2007 * controller could need to access it before the bus reset
2008 * takes effect.
2009 */
2010 if (ret == 0)
2011 fw_schedule_bus_reset(&ohci->card, true, true);
2012 else
2013 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2014 next_config_rom, next_config_rom_bus);
2015
2016 return ret;
2017 }
2018
2019 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2020 {
2021 struct fw_ohci *ohci = fw_ohci(card);
2022
2023 at_context_transmit(&ohci->at_request_ctx, packet);
2024 }
2025
2026 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2027 {
2028 struct fw_ohci *ohci = fw_ohci(card);
2029
2030 at_context_transmit(&ohci->at_response_ctx, packet);
2031 }
2032
2033 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2034 {
2035 struct fw_ohci *ohci = fw_ohci(card);
2036 struct context *ctx = &ohci->at_request_ctx;
2037 struct driver_data *driver_data = packet->driver_data;
2038 int ret = -ENOENT;
2039
2040 tasklet_disable(&ctx->tasklet);
2041
2042 if (packet->ack != 0)
2043 goto out;
2044
2045 if (packet->payload_mapped)
2046 dma_unmap_single(ohci->card.device, packet->payload_bus,
2047 packet->payload_length, DMA_TO_DEVICE);
2048
2049 log_ar_at_event('T', packet->speed, packet->header, 0x20);
2050 driver_data->packet = NULL;
2051 packet->ack = RCODE_CANCELLED;
2052 packet->callback(packet, &ohci->card, packet->ack);
2053 ret = 0;
2054 out:
2055 tasklet_enable(&ctx->tasklet);
2056
2057 return ret;
2058 }
2059
2060 static int ohci_enable_phys_dma(struct fw_card *card,
2061 int node_id, int generation)
2062 {
2063 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2064 return 0;
2065 #else
2066 struct fw_ohci *ohci = fw_ohci(card);
2067 unsigned long flags;
2068 int n, ret = 0;
2069
2070 /*
2071 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2072 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2073 */
2074
2075 spin_lock_irqsave(&ohci->lock, flags);
2076
2077 if (ohci->generation != generation) {
2078 ret = -ESTALE;
2079 goto out;
2080 }
2081
2082 /*
2083 * Note, if the node ID contains a non-local bus ID, physical DMA is
2084 * enabled for _all_ nodes on remote buses.
2085 */
2086
2087 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2088 if (n < 32)
2089 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2090 else
2091 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2092
2093 flush_writes(ohci);
2094 out:
2095 spin_unlock_irqrestore(&ohci->lock, flags);
2096
2097 return ret;
2098 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2099 }
2100
2101 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2102 {
2103 struct fw_ohci *ohci = fw_ohci(card);
2104 unsigned long flags;
2105 u32 value;
2106
2107 switch (csr_offset) {
2108 case CSR_STATE_CLEAR:
2109 case CSR_STATE_SET:
2110 if (ohci->is_root &&
2111 (reg_read(ohci, OHCI1394_LinkControlSet) &
2112 OHCI1394_LinkControl_cycleMaster))
2113 value = CSR_STATE_BIT_CMSTR;
2114 else
2115 value = 0;
2116 if (ohci->csr_state_setclear_abdicate)
2117 value |= CSR_STATE_BIT_ABDICATE;
2118
2119 return value;
2120
2121 case CSR_NODE_IDS:
2122 return reg_read(ohci, OHCI1394_NodeID) << 16;
2123
2124 case CSR_CYCLE_TIME:
2125 return get_cycle_time(ohci);
2126
2127 case CSR_BUS_TIME:
2128 /*
2129 * We might be called just after the cycle timer has wrapped
2130 * around but just before the cycle64Seconds handler, so we
2131 * better check here, too, if the bus time needs to be updated.
2132 */
2133 spin_lock_irqsave(&ohci->lock, flags);
2134 value = update_bus_time(ohci);
2135 spin_unlock_irqrestore(&ohci->lock, flags);
2136 return value;
2137
2138 case CSR_BUSY_TIMEOUT:
2139 value = reg_read(ohci, OHCI1394_ATRetries);
2140 return (value >> 4) & 0x0ffff00f;
2141
2142 case CSR_PRIORITY_BUDGET:
2143 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2144 (ohci->pri_req_max << 8);
2145
2146 default:
2147 WARN_ON(1);
2148 return 0;
2149 }
2150 }
2151
2152 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2153 {
2154 struct fw_ohci *ohci = fw_ohci(card);
2155 unsigned long flags;
2156
2157 switch (csr_offset) {
2158 case CSR_STATE_CLEAR:
2159 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2160 reg_write(ohci, OHCI1394_LinkControlClear,
2161 OHCI1394_LinkControl_cycleMaster);
2162 flush_writes(ohci);
2163 }
2164 if (value & CSR_STATE_BIT_ABDICATE)
2165 ohci->csr_state_setclear_abdicate = false;
2166 break;
2167
2168 case CSR_STATE_SET:
2169 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2170 reg_write(ohci, OHCI1394_LinkControlSet,
2171 OHCI1394_LinkControl_cycleMaster);
2172 flush_writes(ohci);
2173 }
2174 if (value & CSR_STATE_BIT_ABDICATE)
2175 ohci->csr_state_setclear_abdicate = true;
2176 break;
2177
2178 case CSR_NODE_IDS:
2179 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2180 flush_writes(ohci);
2181 break;
2182
2183 case CSR_CYCLE_TIME:
2184 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2185 reg_write(ohci, OHCI1394_IntEventSet,
2186 OHCI1394_cycleInconsistent);
2187 flush_writes(ohci);
2188 break;
2189
2190 case CSR_BUS_TIME:
2191 spin_lock_irqsave(&ohci->lock, flags);
2192 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2193 spin_unlock_irqrestore(&ohci->lock, flags);
2194 break;
2195
2196 case CSR_BUSY_TIMEOUT:
2197 value = (value & 0xf) | ((value & 0xf) << 4) |
2198 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2199 reg_write(ohci, OHCI1394_ATRetries, value);
2200 flush_writes(ohci);
2201 break;
2202
2203 case CSR_PRIORITY_BUDGET:
2204 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2205 flush_writes(ohci);
2206 break;
2207
2208 default:
2209 WARN_ON(1);
2210 break;
2211 }
2212 }
2213
2214 static void copy_iso_headers(struct iso_context *ctx, void *p)
2215 {
2216 int i = ctx->header_length;
2217
2218 if (i + ctx->base.header_size > PAGE_SIZE)
2219 return;
2220
2221 /*
2222 * The iso header is byteswapped to little endian by
2223 * the controller, but the remaining header quadlets
2224 * are big endian. We want to present all the headers
2225 * as big endian, so we have to swap the first quadlet.
2226 */
2227 if (ctx->base.header_size > 0)
2228 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2229 if (ctx->base.header_size > 4)
2230 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2231 if (ctx->base.header_size > 8)
2232 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2233 ctx->header_length += ctx->base.header_size;
2234 }
2235
2236 static int handle_ir_packet_per_buffer(struct context *context,
2237 struct descriptor *d,
2238 struct descriptor *last)
2239 {
2240 struct iso_context *ctx =
2241 container_of(context, struct iso_context, context);
2242 struct descriptor *pd;
2243 __le32 *ir_header;
2244 void *p;
2245
2246 for (pd = d; pd <= last; pd++)
2247 if (pd->transfer_status)
2248 break;
2249 if (pd > last)
2250 /* Descriptor(s) not done yet, stop iteration */
2251 return 0;
2252
2253 p = last + 1;
2254 copy_iso_headers(ctx, p);
2255
2256 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2257 ir_header = (__le32 *) p;
2258 ctx->base.callback.sc(&ctx->base,
2259 le32_to_cpu(ir_header[0]) & 0xffff,
2260 ctx->header_length, ctx->header,
2261 ctx->base.callback_data);
2262 ctx->header_length = 0;
2263 }
2264
2265 return 1;
2266 }
2267
2268 /* d == last because each descriptor block is only a single descriptor. */
2269 static int handle_ir_buffer_fill(struct context *context,
2270 struct descriptor *d,
2271 struct descriptor *last)
2272 {
2273 struct iso_context *ctx =
2274 container_of(context, struct iso_context, context);
2275
2276 if (!last->transfer_status)
2277 /* Descriptor(s) not done yet, stop iteration */
2278 return 0;
2279
2280 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2281 ctx->base.callback.mc(&ctx->base,
2282 le32_to_cpu(last->data_address) +
2283 le16_to_cpu(last->req_count) -
2284 le16_to_cpu(last->res_count),
2285 ctx->base.callback_data);
2286
2287 return 1;
2288 }
2289
2290 static int handle_it_packet(struct context *context,
2291 struct descriptor *d,
2292 struct descriptor *last)
2293 {
2294 struct iso_context *ctx =
2295 container_of(context, struct iso_context, context);
2296 int i;
2297 struct descriptor *pd;
2298
2299 for (pd = d; pd <= last; pd++)
2300 if (pd->transfer_status)
2301 break;
2302 if (pd > last)
2303 /* Descriptor(s) not done yet, stop iteration */
2304 return 0;
2305
2306 i = ctx->header_length;
2307 if (i + 4 < PAGE_SIZE) {
2308 /* Present this value as big-endian to match the receive code */
2309 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2310 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2311 le16_to_cpu(pd->res_count));
2312 ctx->header_length += 4;
2313 }
2314 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2315 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2316 ctx->header_length, ctx->header,
2317 ctx->base.callback_data);
2318 ctx->header_length = 0;
2319 }
2320 return 1;
2321 }
2322
2323 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2324 {
2325 u32 hi = channels >> 32, lo = channels;
2326
2327 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2328 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2329 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2330 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2331 mmiowb();
2332 ohci->mc_channels = channels;
2333 }
2334
2335 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2336 int type, int channel, size_t header_size)
2337 {
2338 struct fw_ohci *ohci = fw_ohci(card);
2339 struct iso_context *uninitialized_var(ctx);
2340 descriptor_callback_t uninitialized_var(callback);
2341 u64 *uninitialized_var(channels);
2342 u32 *uninitialized_var(mask), uninitialized_var(regs);
2343 unsigned long flags;
2344 int index, ret = -EBUSY;
2345
2346 spin_lock_irqsave(&ohci->lock, flags);
2347
2348 switch (type) {
2349 case FW_ISO_CONTEXT_TRANSMIT:
2350 mask = &ohci->it_context_mask;
2351 callback = handle_it_packet;
2352 index = ffs(*mask) - 1;
2353 if (index >= 0) {
2354 *mask &= ~(1 << index);
2355 regs = OHCI1394_IsoXmitContextBase(index);
2356 ctx = &ohci->it_context_list[index];
2357 }
2358 break;
2359
2360 case FW_ISO_CONTEXT_RECEIVE:
2361 channels = &ohci->ir_context_channels;
2362 mask = &ohci->ir_context_mask;
2363 callback = handle_ir_packet_per_buffer;
2364 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2365 if (index >= 0) {
2366 *channels &= ~(1ULL << channel);
2367 *mask &= ~(1 << index);
2368 regs = OHCI1394_IsoRcvContextBase(index);
2369 ctx = &ohci->ir_context_list[index];
2370 }
2371 break;
2372
2373 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2374 mask = &ohci->ir_context_mask;
2375 callback = handle_ir_buffer_fill;
2376 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2377 if (index >= 0) {
2378 ohci->mc_allocated = true;
2379 *mask &= ~(1 << index);
2380 regs = OHCI1394_IsoRcvContextBase(index);
2381 ctx = &ohci->ir_context_list[index];
2382 }
2383 break;
2384
2385 default:
2386 index = -1;
2387 ret = -ENOSYS;
2388 }
2389
2390 spin_unlock_irqrestore(&ohci->lock, flags);
2391
2392 if (index < 0)
2393 return ERR_PTR(ret);
2394
2395 memset(ctx, 0, sizeof(*ctx));
2396 ctx->header_length = 0;
2397 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2398 if (ctx->header == NULL) {
2399 ret = -ENOMEM;
2400 goto out;
2401 }
2402 ret = context_init(&ctx->context, ohci, regs, callback);
2403 if (ret < 0)
2404 goto out_with_header;
2405
2406 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2407 set_multichannel_mask(ohci, 0);
2408
2409 return &ctx->base;
2410
2411 out_with_header:
2412 free_page((unsigned long)ctx->header);
2413 out:
2414 spin_lock_irqsave(&ohci->lock, flags);
2415
2416 switch (type) {
2417 case FW_ISO_CONTEXT_RECEIVE:
2418 *channels |= 1ULL << channel;
2419 break;
2420
2421 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2422 ohci->mc_allocated = false;
2423 break;
2424 }
2425 *mask |= 1 << index;
2426
2427 spin_unlock_irqrestore(&ohci->lock, flags);
2428
2429 return ERR_PTR(ret);
2430 }
2431
2432 static int ohci_start_iso(struct fw_iso_context *base,
2433 s32 cycle, u32 sync, u32 tags)
2434 {
2435 struct iso_context *ctx = container_of(base, struct iso_context, base);
2436 struct fw_ohci *ohci = ctx->context.ohci;
2437 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2438 int index;
2439
2440 switch (ctx->base.type) {
2441 case FW_ISO_CONTEXT_TRANSMIT:
2442 index = ctx - ohci->it_context_list;
2443 match = 0;
2444 if (cycle >= 0)
2445 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2446 (cycle & 0x7fff) << 16;
2447
2448 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2449 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2450 context_run(&ctx->context, match);
2451 break;
2452
2453 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2454 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2455 /* fall through */
2456 case FW_ISO_CONTEXT_RECEIVE:
2457 index = ctx - ohci->ir_context_list;
2458 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2459 if (cycle >= 0) {
2460 match |= (cycle & 0x07fff) << 12;
2461 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2462 }
2463
2464 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2465 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2466 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2467 context_run(&ctx->context, control);
2468 break;
2469 }
2470
2471 return 0;
2472 }
2473
2474 static int ohci_stop_iso(struct fw_iso_context *base)
2475 {
2476 struct fw_ohci *ohci = fw_ohci(base->card);
2477 struct iso_context *ctx = container_of(base, struct iso_context, base);
2478 int index;
2479
2480 switch (ctx->base.type) {
2481 case FW_ISO_CONTEXT_TRANSMIT:
2482 index = ctx - ohci->it_context_list;
2483 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2484 break;
2485
2486 case FW_ISO_CONTEXT_RECEIVE:
2487 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2488 index = ctx - ohci->ir_context_list;
2489 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2490 break;
2491 }
2492 flush_writes(ohci);
2493 context_stop(&ctx->context);
2494
2495 return 0;
2496 }
2497
2498 static void ohci_free_iso_context(struct fw_iso_context *base)
2499 {
2500 struct fw_ohci *ohci = fw_ohci(base->card);
2501 struct iso_context *ctx = container_of(base, struct iso_context, base);
2502 unsigned long flags;
2503 int index;
2504
2505 ohci_stop_iso(base);
2506 context_release(&ctx->context);
2507 free_page((unsigned long)ctx->header);
2508
2509 spin_lock_irqsave(&ohci->lock, flags);
2510
2511 switch (base->type) {
2512 case FW_ISO_CONTEXT_TRANSMIT:
2513 index = ctx - ohci->it_context_list;
2514 ohci->it_context_mask |= 1 << index;
2515 break;
2516
2517 case FW_ISO_CONTEXT_RECEIVE:
2518 index = ctx - ohci->ir_context_list;
2519 ohci->ir_context_mask |= 1 << index;
2520 ohci->ir_context_channels |= 1ULL << base->channel;
2521 break;
2522
2523 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2524 index = ctx - ohci->ir_context_list;
2525 ohci->ir_context_mask |= 1 << index;
2526 ohci->ir_context_channels |= ohci->mc_channels;
2527 ohci->mc_channels = 0;
2528 ohci->mc_allocated = false;
2529 break;
2530 }
2531
2532 spin_unlock_irqrestore(&ohci->lock, flags);
2533 }
2534
2535 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2536 {
2537 struct fw_ohci *ohci = fw_ohci(base->card);
2538 unsigned long flags;
2539 int ret;
2540
2541 switch (base->type) {
2542 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2543
2544 spin_lock_irqsave(&ohci->lock, flags);
2545
2546 /* Don't allow multichannel to grab other contexts' channels. */
2547 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2548 *channels = ohci->ir_context_channels;
2549 ret = -EBUSY;
2550 } else {
2551 set_multichannel_mask(ohci, *channels);
2552 ret = 0;
2553 }
2554
2555 spin_unlock_irqrestore(&ohci->lock, flags);
2556
2557 break;
2558 default:
2559 ret = -EINVAL;
2560 }
2561
2562 return ret;
2563 }
2564
2565 static int queue_iso_transmit(struct iso_context *ctx,
2566 struct fw_iso_packet *packet,
2567 struct fw_iso_buffer *buffer,
2568 unsigned long payload)
2569 {
2570 struct descriptor *d, *last, *pd;
2571 struct fw_iso_packet *p;
2572 __le32 *header;
2573 dma_addr_t d_bus, page_bus;
2574 u32 z, header_z, payload_z, irq;
2575 u32 payload_index, payload_end_index, next_page_index;
2576 int page, end_page, i, length, offset;
2577
2578 p = packet;
2579 payload_index = payload;
2580
2581 if (p->skip)
2582 z = 1;
2583 else
2584 z = 2;
2585 if (p->header_length > 0)
2586 z++;
2587
2588 /* Determine the first page the payload isn't contained in. */
2589 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2590 if (p->payload_length > 0)
2591 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2592 else
2593 payload_z = 0;
2594
2595 z += payload_z;
2596
2597 /* Get header size in number of descriptors. */
2598 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2599
2600 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2601 if (d == NULL)
2602 return -ENOMEM;
2603
2604 if (!p->skip) {
2605 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2606 d[0].req_count = cpu_to_le16(8);
2607 /*
2608 * Link the skip address to this descriptor itself. This causes
2609 * a context to skip a cycle whenever lost cycles or FIFO
2610 * overruns occur, without dropping the data. The application
2611 * should then decide whether this is an error condition or not.
2612 * FIXME: Make the context's cycle-lost behaviour configurable?
2613 */
2614 d[0].branch_address = cpu_to_le32(d_bus | z);
2615
2616 header = (__le32 *) &d[1];
2617 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2618 IT_HEADER_TAG(p->tag) |
2619 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2620 IT_HEADER_CHANNEL(ctx->base.channel) |
2621 IT_HEADER_SPEED(ctx->base.speed));
2622 header[1] =
2623 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2624 p->payload_length));
2625 }
2626
2627 if (p->header_length > 0) {
2628 d[2].req_count = cpu_to_le16(p->header_length);
2629 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2630 memcpy(&d[z], p->header, p->header_length);
2631 }
2632
2633 pd = d + z - payload_z;
2634 payload_end_index = payload_index + p->payload_length;
2635 for (i = 0; i < payload_z; i++) {
2636 page = payload_index >> PAGE_SHIFT;
2637 offset = payload_index & ~PAGE_MASK;
2638 next_page_index = (page + 1) << PAGE_SHIFT;
2639 length =
2640 min(next_page_index, payload_end_index) - payload_index;
2641 pd[i].req_count = cpu_to_le16(length);
2642
2643 page_bus = page_private(buffer->pages[page]);
2644 pd[i].data_address = cpu_to_le32(page_bus + offset);
2645
2646 payload_index += length;
2647 }
2648
2649 if (p->interrupt)
2650 irq = DESCRIPTOR_IRQ_ALWAYS;
2651 else
2652 irq = DESCRIPTOR_NO_IRQ;
2653
2654 last = z == 2 ? d : d + z - 1;
2655 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2656 DESCRIPTOR_STATUS |
2657 DESCRIPTOR_BRANCH_ALWAYS |
2658 irq);
2659
2660 context_append(&ctx->context, d, z, header_z);
2661
2662 return 0;
2663 }
2664
2665 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2666 struct fw_iso_packet *packet,
2667 struct fw_iso_buffer *buffer,
2668 unsigned long payload)
2669 {
2670 struct descriptor *d, *pd;
2671 dma_addr_t d_bus, page_bus;
2672 u32 z, header_z, rest;
2673 int i, j, length;
2674 int page, offset, packet_count, header_size, payload_per_buffer;
2675
2676 /*
2677 * The OHCI controller puts the isochronous header and trailer in the
2678 * buffer, so we need at least 8 bytes.
2679 */
2680 packet_count = packet->header_length / ctx->base.header_size;
2681 header_size = max(ctx->base.header_size, (size_t)8);
2682
2683 /* Get header size in number of descriptors. */
2684 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2685 page = payload >> PAGE_SHIFT;
2686 offset = payload & ~PAGE_MASK;
2687 payload_per_buffer = packet->payload_length / packet_count;
2688
2689 for (i = 0; i < packet_count; i++) {
2690 /* d points to the header descriptor */
2691 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2692 d = context_get_descriptors(&ctx->context,
2693 z + header_z, &d_bus);
2694 if (d == NULL)
2695 return -ENOMEM;
2696
2697 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2698 DESCRIPTOR_INPUT_MORE);
2699 if (packet->skip && i == 0)
2700 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2701 d->req_count = cpu_to_le16(header_size);
2702 d->res_count = d->req_count;
2703 d->transfer_status = 0;
2704 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2705
2706 rest = payload_per_buffer;
2707 pd = d;
2708 for (j = 1; j < z; j++) {
2709 pd++;
2710 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2711 DESCRIPTOR_INPUT_MORE);
2712
2713 if (offset + rest < PAGE_SIZE)
2714 length = rest;
2715 else
2716 length = PAGE_SIZE - offset;
2717 pd->req_count = cpu_to_le16(length);
2718 pd->res_count = pd->req_count;
2719 pd->transfer_status = 0;
2720
2721 page_bus = page_private(buffer->pages[page]);
2722 pd->data_address = cpu_to_le32(page_bus + offset);
2723
2724 offset = (offset + length) & ~PAGE_MASK;
2725 rest -= length;
2726 if (offset == 0)
2727 page++;
2728 }
2729 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2730 DESCRIPTOR_INPUT_LAST |
2731 DESCRIPTOR_BRANCH_ALWAYS);
2732 if (packet->interrupt && i == packet_count - 1)
2733 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2734
2735 context_append(&ctx->context, d, z, header_z);
2736 }
2737
2738 return 0;
2739 }
2740
2741 static int queue_iso_buffer_fill(struct iso_context *ctx,
2742 struct fw_iso_packet *packet,
2743 struct fw_iso_buffer *buffer,
2744 unsigned long payload)
2745 {
2746 struct descriptor *d;
2747 dma_addr_t d_bus, page_bus;
2748 int page, offset, rest, z, i, length;
2749
2750 page = payload >> PAGE_SHIFT;
2751 offset = payload & ~PAGE_MASK;
2752 rest = packet->payload_length;
2753
2754 /* We need one descriptor for each page in the buffer. */
2755 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
2756
2757 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
2758 return -EFAULT;
2759
2760 for (i = 0; i < z; i++) {
2761 d = context_get_descriptors(&ctx->context, 1, &d_bus);
2762 if (d == NULL)
2763 return -ENOMEM;
2764
2765 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
2766 DESCRIPTOR_BRANCH_ALWAYS);
2767 if (packet->skip && i == 0)
2768 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2769 if (packet->interrupt && i == z - 1)
2770 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2771
2772 if (offset + rest < PAGE_SIZE)
2773 length = rest;
2774 else
2775 length = PAGE_SIZE - offset;
2776 d->req_count = cpu_to_le16(length);
2777 d->res_count = d->req_count;
2778 d->transfer_status = 0;
2779
2780 page_bus = page_private(buffer->pages[page]);
2781 d->data_address = cpu_to_le32(page_bus + offset);
2782
2783 rest -= length;
2784 offset = 0;
2785 page++;
2786
2787 context_append(&ctx->context, d, 1, 0);
2788 }
2789
2790 return 0;
2791 }
2792
2793 static int ohci_queue_iso(struct fw_iso_context *base,
2794 struct fw_iso_packet *packet,
2795 struct fw_iso_buffer *buffer,
2796 unsigned long payload)
2797 {
2798 struct iso_context *ctx = container_of(base, struct iso_context, base);
2799 unsigned long flags;
2800 int ret = -ENOSYS;
2801
2802 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2803 switch (base->type) {
2804 case FW_ISO_CONTEXT_TRANSMIT:
2805 ret = queue_iso_transmit(ctx, packet, buffer, payload);
2806 break;
2807 case FW_ISO_CONTEXT_RECEIVE:
2808 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
2809 break;
2810 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2811 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
2812 break;
2813 }
2814 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2815
2816 return ret;
2817 }
2818
2819 static const struct fw_card_driver ohci_driver = {
2820 .enable = ohci_enable,
2821 .read_phy_reg = ohci_read_phy_reg,
2822 .update_phy_reg = ohci_update_phy_reg,
2823 .set_config_rom = ohci_set_config_rom,
2824 .send_request = ohci_send_request,
2825 .send_response = ohci_send_response,
2826 .cancel_packet = ohci_cancel_packet,
2827 .enable_phys_dma = ohci_enable_phys_dma,
2828 .read_csr = ohci_read_csr,
2829 .write_csr = ohci_write_csr,
2830
2831 .allocate_iso_context = ohci_allocate_iso_context,
2832 .free_iso_context = ohci_free_iso_context,
2833 .set_iso_channels = ohci_set_iso_channels,
2834 .queue_iso = ohci_queue_iso,
2835 .start_iso = ohci_start_iso,
2836 .stop_iso = ohci_stop_iso,
2837 };
2838
2839 #ifdef CONFIG_PPC_PMAC
2840 static void pmac_ohci_on(struct pci_dev *dev)
2841 {
2842 if (machine_is(powermac)) {
2843 struct device_node *ofn = pci_device_to_OF_node(dev);
2844
2845 if (ofn) {
2846 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2847 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2848 }
2849 }
2850 }
2851
2852 static void pmac_ohci_off(struct pci_dev *dev)
2853 {
2854 if (machine_is(powermac)) {
2855 struct device_node *ofn = pci_device_to_OF_node(dev);
2856
2857 if (ofn) {
2858 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2859 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2860 }
2861 }
2862 }
2863 #else
2864 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2865 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2866 #endif /* CONFIG_PPC_PMAC */
2867
2868 static int __devinit pci_probe(struct pci_dev *dev,
2869 const struct pci_device_id *ent)
2870 {
2871 struct fw_ohci *ohci;
2872 u32 bus_options, max_receive, link_speed, version;
2873 u64 guid;
2874 int i, err, n_ir, n_it;
2875 size_t size;
2876
2877 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2878 if (ohci == NULL) {
2879 err = -ENOMEM;
2880 goto fail;
2881 }
2882
2883 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2884
2885 pmac_ohci_on(dev);
2886
2887 err = pci_enable_device(dev);
2888 if (err) {
2889 fw_error("Failed to enable OHCI hardware\n");
2890 goto fail_free;
2891 }
2892
2893 pci_set_master(dev);
2894 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2895 pci_set_drvdata(dev, ohci);
2896
2897 spin_lock_init(&ohci->lock);
2898 mutex_init(&ohci->phy_reg_mutex);
2899
2900 tasklet_init(&ohci->bus_reset_tasklet,
2901 bus_reset_tasklet, (unsigned long)ohci);
2902
2903 err = pci_request_region(dev, 0, ohci_driver_name);
2904 if (err) {
2905 fw_error("MMIO resource unavailable\n");
2906 goto fail_disable;
2907 }
2908
2909 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2910 if (ohci->registers == NULL) {
2911 fw_error("Failed to remap registers\n");
2912 err = -ENXIO;
2913 goto fail_iomem;
2914 }
2915
2916 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2917 if (ohci_quirks[i].vendor == dev->vendor &&
2918 (ohci_quirks[i].device == dev->device ||
2919 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2920 ohci->quirks = ohci_quirks[i].flags;
2921 break;
2922 }
2923 if (param_quirks)
2924 ohci->quirks = param_quirks;
2925
2926 ar_context_init(&ohci->ar_request_ctx, ohci,
2927 OHCI1394_AsReqRcvContextControlSet);
2928
2929 ar_context_init(&ohci->ar_response_ctx, ohci,
2930 OHCI1394_AsRspRcvContextControlSet);
2931
2932 context_init(&ohci->at_request_ctx, ohci,
2933 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2934
2935 context_init(&ohci->at_response_ctx, ohci,
2936 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2937
2938 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2939 ohci->ir_context_channels = ~0ULL;
2940 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2941 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2942 n_ir = hweight32(ohci->ir_context_mask);
2943 size = sizeof(struct iso_context) * n_ir;
2944 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2945
2946 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2947 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2948 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2949 n_it = hweight32(ohci->it_context_mask);
2950 size = sizeof(struct iso_context) * n_it;
2951 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2952
2953 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2954 err = -ENOMEM;
2955 goto fail_contexts;
2956 }
2957
2958 /* self-id dma buffer allocation */
2959 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2960 SELF_ID_BUF_SIZE,
2961 &ohci->self_id_bus,
2962 GFP_KERNEL);
2963 if (ohci->self_id_cpu == NULL) {
2964 err = -ENOMEM;
2965 goto fail_contexts;
2966 }
2967
2968 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2969 max_receive = (bus_options >> 12) & 0xf;
2970 link_speed = bus_options & 0x7;
2971 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2972 reg_read(ohci, OHCI1394_GUIDLo);
2973
2974 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2975 if (err)
2976 goto fail_self_id;
2977
2978 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2979 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2980 "%d IR + %d IT contexts, quirks 0x%x\n",
2981 dev_name(&dev->dev), version >> 16, version & 0xff,
2982 n_ir, n_it, ohci->quirks);
2983
2984 return 0;
2985
2986 fail_self_id:
2987 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2988 ohci->self_id_cpu, ohci->self_id_bus);
2989 fail_contexts:
2990 kfree(ohci->ir_context_list);
2991 kfree(ohci->it_context_list);
2992 context_release(&ohci->at_response_ctx);
2993 context_release(&ohci->at_request_ctx);
2994 ar_context_release(&ohci->ar_response_ctx);
2995 ar_context_release(&ohci->ar_request_ctx);
2996 pci_iounmap(dev, ohci->registers);
2997 fail_iomem:
2998 pci_release_region(dev, 0);
2999 fail_disable:
3000 pci_disable_device(dev);
3001 fail_free:
3002 kfree(&ohci->card);
3003 pmac_ohci_off(dev);
3004 fail:
3005 if (err == -ENOMEM)
3006 fw_error("Out of memory\n");
3007
3008 return err;
3009 }
3010
3011 static void pci_remove(struct pci_dev *dev)
3012 {
3013 struct fw_ohci *ohci;
3014
3015 ohci = pci_get_drvdata(dev);
3016 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3017 flush_writes(ohci);
3018 fw_core_remove_card(&ohci->card);
3019
3020 /*
3021 * FIXME: Fail all pending packets here, now that the upper
3022 * layers can't queue any more.
3023 */
3024
3025 software_reset(ohci);
3026 free_irq(dev->irq, ohci);
3027
3028 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3029 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3030 ohci->next_config_rom, ohci->next_config_rom_bus);
3031 if (ohci->config_rom)
3032 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3033 ohci->config_rom, ohci->config_rom_bus);
3034 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3035 ohci->self_id_cpu, ohci->self_id_bus);
3036 ar_context_release(&ohci->ar_request_ctx);
3037 ar_context_release(&ohci->ar_response_ctx);
3038 context_release(&ohci->at_request_ctx);
3039 context_release(&ohci->at_response_ctx);
3040 kfree(ohci->it_context_list);
3041 kfree(ohci->ir_context_list);
3042 pci_disable_msi(dev);
3043 pci_iounmap(dev, ohci->registers);
3044 pci_release_region(dev, 0);
3045 pci_disable_device(dev);
3046 kfree(&ohci->card);
3047 pmac_ohci_off(dev);
3048
3049 fw_notify("Removed fw-ohci device.\n");
3050 }
3051
3052 #ifdef CONFIG_PM
3053 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3054 {
3055 struct fw_ohci *ohci = pci_get_drvdata(dev);
3056 int err;
3057
3058 software_reset(ohci);
3059 free_irq(dev->irq, ohci);
3060 pci_disable_msi(dev);
3061 err = pci_save_state(dev);
3062 if (err) {
3063 fw_error("pci_save_state failed\n");
3064 return err;
3065 }
3066 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3067 if (err)
3068 fw_error("pci_set_power_state failed with %d\n", err);
3069 pmac_ohci_off(dev);
3070
3071 return 0;
3072 }
3073
3074 static int pci_resume(struct pci_dev *dev)
3075 {
3076 struct fw_ohci *ohci = pci_get_drvdata(dev);
3077 int err;
3078
3079 pmac_ohci_on(dev);
3080 pci_set_power_state(dev, PCI_D0);
3081 pci_restore_state(dev);
3082 err = pci_enable_device(dev);
3083 if (err) {
3084 fw_error("pci_enable_device failed\n");
3085 return err;
3086 }
3087
3088 return ohci_enable(&ohci->card, NULL, 0);
3089 }
3090 #endif
3091
3092 static const struct pci_device_id pci_table[] = {
3093 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3094 { }
3095 };
3096
3097 MODULE_DEVICE_TABLE(pci, pci_table);
3098
3099 static struct pci_driver fw_ohci_pci_driver = {
3100 .name = ohci_driver_name,
3101 .id_table = pci_table,
3102 .probe = pci_probe,
3103 .remove = pci_remove,
3104 #ifdef CONFIG_PM
3105 .resume = pci_resume,
3106 .suspend = pci_suspend,
3107 #endif
3108 };
3109
3110 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3111 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3112 MODULE_LICENSE("GPL");
3113
3114 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3115 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3116 MODULE_ALIAS("ohci1394");
3117 #endif
3118
3119 static int __init fw_ohci_init(void)
3120 {
3121 return pci_register_driver(&fw_ohci_pci_driver);
3122 }
3123
3124 static void __exit fw_ohci_cleanup(void)
3125 {
3126 pci_unregister_driver(&fw_ohci_pci_driver);
3127 }
3128
3129 module_init(fw_ohci_init);
3130 module_exit(fw_ohci_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree