drm/i915: fix tiling limits for i915 class hw v2
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
blobaa8a4e99ac802d3e8b0e6758e7b8853b1ed22c4c
1 /*
2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 int write);
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
45 uint64_t offset,
46 uint64_t size);
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 unsigned alignment);
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62 unsigned long end)
64 drm_i915_private_t *dev_priv = dev->dev_private;
66 if (start >= end ||
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
69 return -EINVAL;
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
73 end - start);
75 dev->gtt_total = (uint32_t) (end - start);
77 return 0;
80 int
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
84 struct drm_i915_gem_init *args = data;
85 int ret;
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89 mutex_unlock(&dev->struct_mutex);
91 return ret;
94 int
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
98 struct drm_i915_gem_get_aperture *args = data;
100 if (!(dev->driver->driver_features & DRIVER_GEM))
101 return -ENODEV;
103 args->aper_size = dev->gtt_total;
104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
107 return 0;
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
120 int ret;
121 u32 handle;
123 args->size = roundup(args->size, PAGE_SIZE);
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
127 if (obj == NULL)
128 return -ENOMEM;
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
135 if (ret)
136 return ret;
138 args->handle = handle;
140 return 0;
143 static inline int
144 fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
146 char __user *data,
147 int length)
149 char __iomem *vaddr;
150 int unwritten;
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153 if (vaddr == NULL)
154 return -ENOMEM;
155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
156 kunmap_atomic(vaddr, KM_USER0);
158 if (unwritten)
159 return -EFAULT;
161 return 0;
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
173 static inline int
174 slow_shmem_copy(struct page *dst_page,
175 int dst_offset,
176 struct page *src_page,
177 int src_offset,
178 int length)
180 char *dst_vaddr, *src_vaddr;
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
184 return -ENOMEM;
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
189 return -ENOMEM;
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
197 return 0;
200 static inline int
201 slow_shmem_bit17_copy(struct page *gpu_page,
202 int gpu_offset,
203 struct page *cpu_page,
204 int cpu_offset,
205 int length,
206 int is_read)
208 char *gpu_vaddr, *cpu_vaddr;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212 if (is_read)
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
215 else
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
222 return -ENOMEM;
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
227 return -ENOMEM;
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
233 while (length > 0) {
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
238 if (is_read) {
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
241 this_length);
242 } else {
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
245 this_length);
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
255 return 0;
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
263 static int
264 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
269 ssize_t remain;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
273 int ret;
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
276 remain = args->size;
278 mutex_lock(&dev->struct_mutex);
280 ret = i915_gem_object_get_pages(obj, 0);
281 if (ret != 0)
282 goto fail_unlock;
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
285 args->size);
286 if (ret != 0)
287 goto fail_put_pages;
289 obj_priv = obj->driver_private;
290 offset = args->offset;
292 while (remain > 0) {
293 /* Operation in this page
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
308 if (ret)
309 goto fail_put_pages;
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
316 fail_put_pages:
317 i915_gem_object_put_pages(obj);
318 fail_unlock:
319 mutex_unlock(&dev->struct_mutex);
321 return ret;
324 static int
325 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
327 int ret;
329 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
331 /* If we've insufficient memory to map in the pages, attempt
332 * to make some space by throwing out some old buffers.
334 if (ret == -ENOMEM) {
335 struct drm_device *dev = obj->dev;
337 ret = i915_gem_evict_something(dev, obj->size);
338 if (ret)
339 return ret;
341 ret = i915_gem_object_get_pages(obj, 0);
344 return ret;
348 * This is the fallback shmem pread path, which allocates temporary storage
349 * in kernel space to copy_to_user into outside of the struct_mutex, so we
350 * can copy out of the object's backing pages while holding the struct mutex
351 * and not take page faults.
353 static int
354 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
355 struct drm_i915_gem_pread *args,
356 struct drm_file *file_priv)
358 struct drm_i915_gem_object *obj_priv = obj->driver_private;
359 struct mm_struct *mm = current->mm;
360 struct page **user_pages;
361 ssize_t remain;
362 loff_t offset, pinned_pages, i;
363 loff_t first_data_page, last_data_page, num_pages;
364 int shmem_page_index, shmem_page_offset;
365 int data_page_index, data_page_offset;
366 int page_length;
367 int ret;
368 uint64_t data_ptr = args->data_ptr;
369 int do_bit17_swizzling;
371 remain = args->size;
373 /* Pin the user pages containing the data. We can't fault while
374 * holding the struct mutex, yet we want to hold it while
375 * dereferencing the user data.
377 first_data_page = data_ptr / PAGE_SIZE;
378 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
379 num_pages = last_data_page - first_data_page + 1;
381 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
382 if (user_pages == NULL)
383 return -ENOMEM;
385 down_read(&mm->mmap_sem);
386 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
387 num_pages, 1, 0, user_pages, NULL);
388 up_read(&mm->mmap_sem);
389 if (pinned_pages < num_pages) {
390 ret = -EFAULT;
391 goto fail_put_user_pages;
394 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
396 mutex_lock(&dev->struct_mutex);
398 ret = i915_gem_object_get_pages_or_evict(obj);
399 if (ret)
400 goto fail_unlock;
402 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
403 args->size);
404 if (ret != 0)
405 goto fail_put_pages;
407 obj_priv = obj->driver_private;
408 offset = args->offset;
410 while (remain > 0) {
411 /* Operation in this page
413 * shmem_page_index = page number within shmem file
414 * shmem_page_offset = offset within page in shmem file
415 * data_page_index = page number in get_user_pages return
416 * data_page_offset = offset with data_page_index page.
417 * page_length = bytes to copy for this page
419 shmem_page_index = offset / PAGE_SIZE;
420 shmem_page_offset = offset & ~PAGE_MASK;
421 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
422 data_page_offset = data_ptr & ~PAGE_MASK;
424 page_length = remain;
425 if ((shmem_page_offset + page_length) > PAGE_SIZE)
426 page_length = PAGE_SIZE - shmem_page_offset;
427 if ((data_page_offset + page_length) > PAGE_SIZE)
428 page_length = PAGE_SIZE - data_page_offset;
430 if (do_bit17_swizzling) {
431 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
432 shmem_page_offset,
433 user_pages[data_page_index],
434 data_page_offset,
435 page_length,
437 } else {
438 ret = slow_shmem_copy(user_pages[data_page_index],
439 data_page_offset,
440 obj_priv->pages[shmem_page_index],
441 shmem_page_offset,
442 page_length);
444 if (ret)
445 goto fail_put_pages;
447 remain -= page_length;
448 data_ptr += page_length;
449 offset += page_length;
452 fail_put_pages:
453 i915_gem_object_put_pages(obj);
454 fail_unlock:
455 mutex_unlock(&dev->struct_mutex);
456 fail_put_user_pages:
457 for (i = 0; i < pinned_pages; i++) {
458 SetPageDirty(user_pages[i]);
459 page_cache_release(user_pages[i]);
461 drm_free_large(user_pages);
463 return ret;
467 * Reads data from the object referenced by handle.
469 * On error, the contents of *data are undefined.
472 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
473 struct drm_file *file_priv)
475 struct drm_i915_gem_pread *args = data;
476 struct drm_gem_object *obj;
477 struct drm_i915_gem_object *obj_priv;
478 int ret;
480 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
481 if (obj == NULL)
482 return -EBADF;
483 obj_priv = obj->driver_private;
485 /* Bounds check source.
487 * XXX: This could use review for overflow issues...
489 if (args->offset > obj->size || args->size > obj->size ||
490 args->offset + args->size > obj->size) {
491 drm_gem_object_unreference(obj);
492 return -EINVAL;
495 if (i915_gem_object_needs_bit17_swizzle(obj)) {
496 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
497 } else {
498 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
499 if (ret != 0)
500 ret = i915_gem_shmem_pread_slow(dev, obj, args,
501 file_priv);
504 drm_gem_object_unreference(obj);
506 return ret;
509 /* This is the fast write path which cannot handle
510 * page faults in the source data
513 static inline int
514 fast_user_write(struct io_mapping *mapping,
515 loff_t page_base, int page_offset,
516 char __user *user_data,
517 int length)
519 char *vaddr_atomic;
520 unsigned long unwritten;
522 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
523 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
524 user_data, length);
525 io_mapping_unmap_atomic(vaddr_atomic);
526 if (unwritten)
527 return -EFAULT;
528 return 0;
531 /* Here's the write path which can sleep for
532 * page faults
535 static inline int
536 slow_kernel_write(struct io_mapping *mapping,
537 loff_t gtt_base, int gtt_offset,
538 struct page *user_page, int user_offset,
539 int length)
541 char *src_vaddr, *dst_vaddr;
542 unsigned long unwritten;
544 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
545 src_vaddr = kmap_atomic(user_page, KM_USER1);
546 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
547 src_vaddr + user_offset,
548 length);
549 kunmap_atomic(src_vaddr, KM_USER1);
550 io_mapping_unmap_atomic(dst_vaddr);
551 if (unwritten)
552 return -EFAULT;
553 return 0;
556 static inline int
557 fast_shmem_write(struct page **pages,
558 loff_t page_base, int page_offset,
559 char __user *data,
560 int length)
562 char __iomem *vaddr;
563 unsigned long unwritten;
565 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
566 if (vaddr == NULL)
567 return -ENOMEM;
568 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
569 kunmap_atomic(vaddr, KM_USER0);
571 if (unwritten)
572 return -EFAULT;
573 return 0;
577 * This is the fast pwrite path, where we copy the data directly from the
578 * user into the GTT, uncached.
580 static int
581 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
582 struct drm_i915_gem_pwrite *args,
583 struct drm_file *file_priv)
585 struct drm_i915_gem_object *obj_priv = obj->driver_private;
586 drm_i915_private_t *dev_priv = dev->dev_private;
587 ssize_t remain;
588 loff_t offset, page_base;
589 char __user *user_data;
590 int page_offset, page_length;
591 int ret;
593 user_data = (char __user *) (uintptr_t) args->data_ptr;
594 remain = args->size;
595 if (!access_ok(VERIFY_READ, user_data, remain))
596 return -EFAULT;
599 mutex_lock(&dev->struct_mutex);
600 ret = i915_gem_object_pin(obj, 0);
601 if (ret) {
602 mutex_unlock(&dev->struct_mutex);
603 return ret;
605 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
606 if (ret)
607 goto fail;
609 obj_priv = obj->driver_private;
610 offset = obj_priv->gtt_offset + args->offset;
612 while (remain > 0) {
613 /* Operation in this page
615 * page_base = page offset within aperture
616 * page_offset = offset within page
617 * page_length = bytes to copy for this page
619 page_base = (offset & ~(PAGE_SIZE-1));
620 page_offset = offset & (PAGE_SIZE-1);
621 page_length = remain;
622 if ((page_offset + remain) > PAGE_SIZE)
623 page_length = PAGE_SIZE - page_offset;
625 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
626 page_offset, user_data, page_length);
628 /* If we get a fault while copying data, then (presumably) our
629 * source page isn't available. Return the error and we'll
630 * retry in the slow path.
632 if (ret)
633 goto fail;
635 remain -= page_length;
636 user_data += page_length;
637 offset += page_length;
640 fail:
641 i915_gem_object_unpin(obj);
642 mutex_unlock(&dev->struct_mutex);
644 return ret;
648 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
649 * the memory and maps it using kmap_atomic for copying.
651 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
652 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
654 static int
655 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
656 struct drm_i915_gem_pwrite *args,
657 struct drm_file *file_priv)
659 struct drm_i915_gem_object *obj_priv = obj->driver_private;
660 drm_i915_private_t *dev_priv = dev->dev_private;
661 ssize_t remain;
662 loff_t gtt_page_base, offset;
663 loff_t first_data_page, last_data_page, num_pages;
664 loff_t pinned_pages, i;
665 struct page **user_pages;
666 struct mm_struct *mm = current->mm;
667 int gtt_page_offset, data_page_offset, data_page_index, page_length;
668 int ret;
669 uint64_t data_ptr = args->data_ptr;
671 remain = args->size;
673 /* Pin the user pages containing the data. We can't fault while
674 * holding the struct mutex, and all of the pwrite implementations
675 * want to hold it while dereferencing the user data.
677 first_data_page = data_ptr / PAGE_SIZE;
678 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
679 num_pages = last_data_page - first_data_page + 1;
681 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
682 if (user_pages == NULL)
683 return -ENOMEM;
685 down_read(&mm->mmap_sem);
686 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
687 num_pages, 0, 0, user_pages, NULL);
688 up_read(&mm->mmap_sem);
689 if (pinned_pages < num_pages) {
690 ret = -EFAULT;
691 goto out_unpin_pages;
694 mutex_lock(&dev->struct_mutex);
695 ret = i915_gem_object_pin(obj, 0);
696 if (ret)
697 goto out_unlock;
699 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
700 if (ret)
701 goto out_unpin_object;
703 obj_priv = obj->driver_private;
704 offset = obj_priv->gtt_offset + args->offset;
706 while (remain > 0) {
707 /* Operation in this page
709 * gtt_page_base = page offset within aperture
710 * gtt_page_offset = offset within page in aperture
711 * data_page_index = page number in get_user_pages return
712 * data_page_offset = offset with data_page_index page.
713 * page_length = bytes to copy for this page
715 gtt_page_base = offset & PAGE_MASK;
716 gtt_page_offset = offset & ~PAGE_MASK;
717 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
718 data_page_offset = data_ptr & ~PAGE_MASK;
720 page_length = remain;
721 if ((gtt_page_offset + page_length) > PAGE_SIZE)
722 page_length = PAGE_SIZE - gtt_page_offset;
723 if ((data_page_offset + page_length) > PAGE_SIZE)
724 page_length = PAGE_SIZE - data_page_offset;
726 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
727 gtt_page_base, gtt_page_offset,
728 user_pages[data_page_index],
729 data_page_offset,
730 page_length);
732 /* If we get a fault while copying data, then (presumably) our
733 * source page isn't available. Return the error and we'll
734 * retry in the slow path.
736 if (ret)
737 goto out_unpin_object;
739 remain -= page_length;
740 offset += page_length;
741 data_ptr += page_length;
744 out_unpin_object:
745 i915_gem_object_unpin(obj);
746 out_unlock:
747 mutex_unlock(&dev->struct_mutex);
748 out_unpin_pages:
749 for (i = 0; i < pinned_pages; i++)
750 page_cache_release(user_pages[i]);
751 drm_free_large(user_pages);
753 return ret;
757 * This is the fast shmem pwrite path, which attempts to directly
758 * copy_from_user into the kmapped pages backing the object.
760 static int
761 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
762 struct drm_i915_gem_pwrite *args,
763 struct drm_file *file_priv)
765 struct drm_i915_gem_object *obj_priv = obj->driver_private;
766 ssize_t remain;
767 loff_t offset, page_base;
768 char __user *user_data;
769 int page_offset, page_length;
770 int ret;
772 user_data = (char __user *) (uintptr_t) args->data_ptr;
773 remain = args->size;
775 mutex_lock(&dev->struct_mutex);
777 ret = i915_gem_object_get_pages(obj, 0);
778 if (ret != 0)
779 goto fail_unlock;
781 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
782 if (ret != 0)
783 goto fail_put_pages;
785 obj_priv = obj->driver_private;
786 offset = args->offset;
787 obj_priv->dirty = 1;
789 while (remain > 0) {
790 /* Operation in this page
792 * page_base = page offset within aperture
793 * page_offset = offset within page
794 * page_length = bytes to copy for this page
796 page_base = (offset & ~(PAGE_SIZE-1));
797 page_offset = offset & (PAGE_SIZE-1);
798 page_length = remain;
799 if ((page_offset + remain) > PAGE_SIZE)
800 page_length = PAGE_SIZE - page_offset;
802 ret = fast_shmem_write(obj_priv->pages,
803 page_base, page_offset,
804 user_data, page_length);
805 if (ret)
806 goto fail_put_pages;
808 remain -= page_length;
809 user_data += page_length;
810 offset += page_length;
813 fail_put_pages:
814 i915_gem_object_put_pages(obj);
815 fail_unlock:
816 mutex_unlock(&dev->struct_mutex);
818 return ret;
822 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
823 * the memory and maps it using kmap_atomic for copying.
825 * This avoids taking mmap_sem for faulting on the user's address while the
826 * struct_mutex is held.
828 static int
829 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
830 struct drm_i915_gem_pwrite *args,
831 struct drm_file *file_priv)
833 struct drm_i915_gem_object *obj_priv = obj->driver_private;
834 struct mm_struct *mm = current->mm;
835 struct page **user_pages;
836 ssize_t remain;
837 loff_t offset, pinned_pages, i;
838 loff_t first_data_page, last_data_page, num_pages;
839 int shmem_page_index, shmem_page_offset;
840 int data_page_index, data_page_offset;
841 int page_length;
842 int ret;
843 uint64_t data_ptr = args->data_ptr;
844 int do_bit17_swizzling;
846 remain = args->size;
848 /* Pin the user pages containing the data. We can't fault while
849 * holding the struct mutex, and all of the pwrite implementations
850 * want to hold it while dereferencing the user data.
852 first_data_page = data_ptr / PAGE_SIZE;
853 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
854 num_pages = last_data_page - first_data_page + 1;
856 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
857 if (user_pages == NULL)
858 return -ENOMEM;
860 down_read(&mm->mmap_sem);
861 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
862 num_pages, 0, 0, user_pages, NULL);
863 up_read(&mm->mmap_sem);
864 if (pinned_pages < num_pages) {
865 ret = -EFAULT;
866 goto fail_put_user_pages;
869 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
871 mutex_lock(&dev->struct_mutex);
873 ret = i915_gem_object_get_pages_or_evict(obj);
874 if (ret)
875 goto fail_unlock;
877 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
878 if (ret != 0)
879 goto fail_put_pages;
881 obj_priv = obj->driver_private;
882 offset = args->offset;
883 obj_priv->dirty = 1;
885 while (remain > 0) {
886 /* Operation in this page
888 * shmem_page_index = page number within shmem file
889 * shmem_page_offset = offset within page in shmem file
890 * data_page_index = page number in get_user_pages return
891 * data_page_offset = offset with data_page_index page.
892 * page_length = bytes to copy for this page
894 shmem_page_index = offset / PAGE_SIZE;
895 shmem_page_offset = offset & ~PAGE_MASK;
896 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
897 data_page_offset = data_ptr & ~PAGE_MASK;
899 page_length = remain;
900 if ((shmem_page_offset + page_length) > PAGE_SIZE)
901 page_length = PAGE_SIZE - shmem_page_offset;
902 if ((data_page_offset + page_length) > PAGE_SIZE)
903 page_length = PAGE_SIZE - data_page_offset;
905 if (do_bit17_swizzling) {
906 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
907 shmem_page_offset,
908 user_pages[data_page_index],
909 data_page_offset,
910 page_length,
912 } else {
913 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
914 shmem_page_offset,
915 user_pages[data_page_index],
916 data_page_offset,
917 page_length);
919 if (ret)
920 goto fail_put_pages;
922 remain -= page_length;
923 data_ptr += page_length;
924 offset += page_length;
927 fail_put_pages:
928 i915_gem_object_put_pages(obj);
929 fail_unlock:
930 mutex_unlock(&dev->struct_mutex);
931 fail_put_user_pages:
932 for (i = 0; i < pinned_pages; i++)
933 page_cache_release(user_pages[i]);
934 drm_free_large(user_pages);
936 return ret;
940 * Writes data to the object referenced by handle.
942 * On error, the contents of the buffer that were to be modified are undefined.
945 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
946 struct drm_file *file_priv)
948 struct drm_i915_gem_pwrite *args = data;
949 struct drm_gem_object *obj;
950 struct drm_i915_gem_object *obj_priv;
951 int ret = 0;
953 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
954 if (obj == NULL)
955 return -EBADF;
956 obj_priv = obj->driver_private;
958 /* Bounds check destination.
960 * XXX: This could use review for overflow issues...
962 if (args->offset > obj->size || args->size > obj->size ||
963 args->offset + args->size > obj->size) {
964 drm_gem_object_unreference(obj);
965 return -EINVAL;
968 /* We can only do the GTT pwrite on untiled buffers, as otherwise
969 * it would end up going through the fenced access, and we'll get
970 * different detiling behavior between reading and writing.
971 * pread/pwrite currently are reading and writing from the CPU
972 * perspective, requiring manual detiling by the client.
974 if (obj_priv->phys_obj)
975 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
976 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
977 dev->gtt_total != 0) {
978 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
979 if (ret == -EFAULT) {
980 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
981 file_priv);
983 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
984 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
985 } else {
986 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
987 if (ret == -EFAULT) {
988 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
989 file_priv);
993 #if WATCH_PWRITE
994 if (ret)
995 DRM_INFO("pwrite failed %d\n", ret);
996 #endif
998 drm_gem_object_unreference(obj);
1000 return ret;
1004 * Called when user space prepares to use an object with the CPU, either
1005 * through the mmap ioctl's mapping or a GTT mapping.
1008 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1009 struct drm_file *file_priv)
1011 struct drm_i915_private *dev_priv = dev->dev_private;
1012 struct drm_i915_gem_set_domain *args = data;
1013 struct drm_gem_object *obj;
1014 struct drm_i915_gem_object *obj_priv;
1015 uint32_t read_domains = args->read_domains;
1016 uint32_t write_domain = args->write_domain;
1017 int ret;
1019 if (!(dev->driver->driver_features & DRIVER_GEM))
1020 return -ENODEV;
1022 /* Only handle setting domains to types used by the CPU. */
1023 if (write_domain & I915_GEM_GPU_DOMAINS)
1024 return -EINVAL;
1026 if (read_domains & I915_GEM_GPU_DOMAINS)
1027 return -EINVAL;
1029 /* Having something in the write domain implies it's in the read
1030 * domain, and only that read domain. Enforce that in the request.
1032 if (write_domain != 0 && read_domains != write_domain)
1033 return -EINVAL;
1035 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1036 if (obj == NULL)
1037 return -EBADF;
1038 obj_priv = obj->driver_private;
1040 mutex_lock(&dev->struct_mutex);
1042 intel_mark_busy(dev, obj);
1044 #if WATCH_BUF
1045 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1046 obj, obj->size, read_domains, write_domain);
1047 #endif
1048 if (read_domains & I915_GEM_DOMAIN_GTT) {
1049 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1051 /* Update the LRU on the fence for the CPU access that's
1052 * about to occur.
1054 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1055 list_move_tail(&obj_priv->fence_list,
1056 &dev_priv->mm.fence_list);
1059 /* Silently promote "you're not bound, there was nothing to do"
1060 * to success, since the client was just asking us to
1061 * make sure everything was done.
1063 if (ret == -EINVAL)
1064 ret = 0;
1065 } else {
1066 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1069 drm_gem_object_unreference(obj);
1070 mutex_unlock(&dev->struct_mutex);
1071 return ret;
1075 * Called when user space has done writes to this buffer
1078 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1079 struct drm_file *file_priv)
1081 struct drm_i915_gem_sw_finish *args = data;
1082 struct drm_gem_object *obj;
1083 struct drm_i915_gem_object *obj_priv;
1084 int ret = 0;
1086 if (!(dev->driver->driver_features & DRIVER_GEM))
1087 return -ENODEV;
1089 mutex_lock(&dev->struct_mutex);
1090 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1091 if (obj == NULL) {
1092 mutex_unlock(&dev->struct_mutex);
1093 return -EBADF;
1096 #if WATCH_BUF
1097 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1098 __func__, args->handle, obj, obj->size);
1099 #endif
1100 obj_priv = obj->driver_private;
1102 /* Pinned buffers may be scanout, so flush the cache */
1103 if (obj_priv->pin_count)
1104 i915_gem_object_flush_cpu_write_domain(obj);
1106 drm_gem_object_unreference(obj);
1107 mutex_unlock(&dev->struct_mutex);
1108 return ret;
1112 * Maps the contents of an object, returning the address it is mapped
1113 * into.
1115 * While the mapping holds a reference on the contents of the object, it doesn't
1116 * imply a ref on the object itself.
1119 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1120 struct drm_file *file_priv)
1122 struct drm_i915_gem_mmap *args = data;
1123 struct drm_gem_object *obj;
1124 loff_t offset;
1125 unsigned long addr;
1127 if (!(dev->driver->driver_features & DRIVER_GEM))
1128 return -ENODEV;
1130 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1131 if (obj == NULL)
1132 return -EBADF;
1134 offset = args->offset;
1136 down_write(&current->mm->mmap_sem);
1137 addr = do_mmap(obj->filp, 0, args->size,
1138 PROT_READ | PROT_WRITE, MAP_SHARED,
1139 args->offset);
1140 up_write(&current->mm->mmap_sem);
1141 mutex_lock(&dev->struct_mutex);
1142 drm_gem_object_unreference(obj);
1143 mutex_unlock(&dev->struct_mutex);
1144 if (IS_ERR((void *)addr))
1145 return addr;
1147 args->addr_ptr = (uint64_t) addr;
1149 return 0;
1153 * i915_gem_fault - fault a page into the GTT
1154 * vma: VMA in question
1155 * vmf: fault info
1157 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1158 * from userspace. The fault handler takes care of binding the object to
1159 * the GTT (if needed), allocating and programming a fence register (again,
1160 * only if needed based on whether the old reg is still valid or the object
1161 * is tiled) and inserting a new PTE into the faulting process.
1163 * Note that the faulting process may involve evicting existing objects
1164 * from the GTT and/or fence registers to make room. So performance may
1165 * suffer if the GTT working set is large or there are few fence registers
1166 * left.
1168 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1170 struct drm_gem_object *obj = vma->vm_private_data;
1171 struct drm_device *dev = obj->dev;
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1174 pgoff_t page_offset;
1175 unsigned long pfn;
1176 int ret = 0;
1177 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1179 /* We don't use vmf->pgoff since that has the fake offset */
1180 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1181 PAGE_SHIFT;
1183 /* Now bind it into the GTT if needed */
1184 mutex_lock(&dev->struct_mutex);
1185 if (!obj_priv->gtt_space) {
1186 ret = i915_gem_object_bind_to_gtt(obj, 0);
1187 if (ret)
1188 goto unlock;
1190 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1192 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1193 if (ret)
1194 goto unlock;
1197 /* Need a new fence register? */
1198 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1199 ret = i915_gem_object_get_fence_reg(obj);
1200 if (ret)
1201 goto unlock;
1204 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1205 page_offset;
1207 /* Finally, remap it using the new GTT offset */
1208 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1209 unlock:
1210 mutex_unlock(&dev->struct_mutex);
1212 switch (ret) {
1213 case 0:
1214 case -ERESTARTSYS:
1215 return VM_FAULT_NOPAGE;
1216 case -ENOMEM:
1217 case -EAGAIN:
1218 return VM_FAULT_OOM;
1219 default:
1220 return VM_FAULT_SIGBUS;
1225 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1226 * @obj: obj in question
1228 * GEM memory mapping works by handing back to userspace a fake mmap offset
1229 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1230 * up the object based on the offset and sets up the various memory mapping
1231 * structures.
1233 * This routine allocates and attaches a fake offset for @obj.
1235 static int
1236 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1238 struct drm_device *dev = obj->dev;
1239 struct drm_gem_mm *mm = dev->mm_private;
1240 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1241 struct drm_map_list *list;
1242 struct drm_local_map *map;
1243 int ret = 0;
1245 /* Set the object up for mmap'ing */
1246 list = &obj->map_list;
1247 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1248 if (!list->map)
1249 return -ENOMEM;
1251 map = list->map;
1252 map->type = _DRM_GEM;
1253 map->size = obj->size;
1254 map->handle = obj;
1256 /* Get a DRM GEM mmap offset allocated... */
1257 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1258 obj->size / PAGE_SIZE, 0, 0);
1259 if (!list->file_offset_node) {
1260 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1261 ret = -ENOMEM;
1262 goto out_free_list;
1265 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1266 obj->size / PAGE_SIZE, 0);
1267 if (!list->file_offset_node) {
1268 ret = -ENOMEM;
1269 goto out_free_list;
1272 list->hash.key = list->file_offset_node->start;
1273 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1274 DRM_ERROR("failed to add to map hash\n");
1275 ret = -ENOMEM;
1276 goto out_free_mm;
1279 /* By now we should be all set, any drm_mmap request on the offset
1280 * below will get to our mmap & fault handler */
1281 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1283 return 0;
1285 out_free_mm:
1286 drm_mm_put_block(list->file_offset_node);
1287 out_free_list:
1288 kfree(list->map);
1290 return ret;
1294 * i915_gem_release_mmap - remove physical page mappings
1295 * @obj: obj in question
1297 * Preserve the reservation of the mmaping with the DRM core code, but
1298 * relinquish ownership of the pages back to the system.
1300 * It is vital that we remove the page mapping if we have mapped a tiled
1301 * object through the GTT and then lose the fence register due to
1302 * resource pressure. Similarly if the object has been moved out of the
1303 * aperture, than pages mapped into userspace must be revoked. Removing the
1304 * mapping will then trigger a page fault on the next user access, allowing
1305 * fixup by i915_gem_fault().
1307 void
1308 i915_gem_release_mmap(struct drm_gem_object *obj)
1310 struct drm_device *dev = obj->dev;
1311 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1313 if (dev->dev_mapping)
1314 unmap_mapping_range(dev->dev_mapping,
1315 obj_priv->mmap_offset, obj->size, 1);
1318 static void
1319 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1321 struct drm_device *dev = obj->dev;
1322 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1323 struct drm_gem_mm *mm = dev->mm_private;
1324 struct drm_map_list *list;
1326 list = &obj->map_list;
1327 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1329 if (list->file_offset_node) {
1330 drm_mm_put_block(list->file_offset_node);
1331 list->file_offset_node = NULL;
1334 if (list->map) {
1335 kfree(list->map);
1336 list->map = NULL;
1339 obj_priv->mmap_offset = 0;
1343 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1344 * @obj: object to check
1346 * Return the required GTT alignment for an object, taking into account
1347 * potential fence register mapping if needed.
1349 static uint32_t
1350 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1352 struct drm_device *dev = obj->dev;
1353 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1354 int start, i;
1357 * Minimum alignment is 4k (GTT page size), but might be greater
1358 * if a fence register is needed for the object.
1360 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1361 return 4096;
1364 * Previous chips need to be aligned to the size of the smallest
1365 * fence register that can contain the object.
1367 if (IS_I9XX(dev))
1368 start = 1024*1024;
1369 else
1370 start = 512*1024;
1372 for (i = start; i < obj->size; i <<= 1)
1375 return i;
1379 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1380 * @dev: DRM device
1381 * @data: GTT mapping ioctl data
1382 * @file_priv: GEM object info
1384 * Simply returns the fake offset to userspace so it can mmap it.
1385 * The mmap call will end up in drm_gem_mmap(), which will set things
1386 * up so we can get faults in the handler above.
1388 * The fault handler will take care of binding the object into the GTT
1389 * (since it may have been evicted to make room for something), allocating
1390 * a fence register, and mapping the appropriate aperture address into
1391 * userspace.
1394 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1395 struct drm_file *file_priv)
1397 struct drm_i915_gem_mmap_gtt *args = data;
1398 struct drm_i915_private *dev_priv = dev->dev_private;
1399 struct drm_gem_object *obj;
1400 struct drm_i915_gem_object *obj_priv;
1401 int ret;
1403 if (!(dev->driver->driver_features & DRIVER_GEM))
1404 return -ENODEV;
1406 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1407 if (obj == NULL)
1408 return -EBADF;
1410 mutex_lock(&dev->struct_mutex);
1412 obj_priv = obj->driver_private;
1414 if (obj_priv->madv != I915_MADV_WILLNEED) {
1415 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1416 drm_gem_object_unreference(obj);
1417 mutex_unlock(&dev->struct_mutex);
1418 return -EINVAL;
1422 if (!obj_priv->mmap_offset) {
1423 ret = i915_gem_create_mmap_offset(obj);
1424 if (ret) {
1425 drm_gem_object_unreference(obj);
1426 mutex_unlock(&dev->struct_mutex);
1427 return ret;
1431 args->offset = obj_priv->mmap_offset;
1434 * Pull it into the GTT so that we have a page list (makes the
1435 * initial fault faster and any subsequent flushing possible).
1437 if (!obj_priv->agp_mem) {
1438 ret = i915_gem_object_bind_to_gtt(obj, 0);
1439 if (ret) {
1440 drm_gem_object_unreference(obj);
1441 mutex_unlock(&dev->struct_mutex);
1442 return ret;
1444 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1447 drm_gem_object_unreference(obj);
1448 mutex_unlock(&dev->struct_mutex);
1450 return 0;
1453 void
1454 i915_gem_object_put_pages(struct drm_gem_object *obj)
1456 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1457 int page_count = obj->size / PAGE_SIZE;
1458 int i;
1460 BUG_ON(obj_priv->pages_refcount == 0);
1461 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1463 if (--obj_priv->pages_refcount != 0)
1464 return;
1466 if (obj_priv->tiling_mode != I915_TILING_NONE)
1467 i915_gem_object_save_bit_17_swizzle(obj);
1469 if (obj_priv->madv == I915_MADV_DONTNEED)
1470 obj_priv->dirty = 0;
1472 for (i = 0; i < page_count; i++) {
1473 if (obj_priv->dirty)
1474 set_page_dirty(obj_priv->pages[i]);
1476 if (obj_priv->madv == I915_MADV_WILLNEED)
1477 mark_page_accessed(obj_priv->pages[i]);
1479 page_cache_release(obj_priv->pages[i]);
1481 obj_priv->dirty = 0;
1483 drm_free_large(obj_priv->pages);
1484 obj_priv->pages = NULL;
1487 static void
1488 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1490 struct drm_device *dev = obj->dev;
1491 drm_i915_private_t *dev_priv = dev->dev_private;
1492 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1494 /* Add a reference if we're newly entering the active list. */
1495 if (!obj_priv->active) {
1496 drm_gem_object_reference(obj);
1497 obj_priv->active = 1;
1499 /* Move from whatever list we were on to the tail of execution. */
1500 spin_lock(&dev_priv->mm.active_list_lock);
1501 list_move_tail(&obj_priv->list,
1502 &dev_priv->mm.active_list);
1503 spin_unlock(&dev_priv->mm.active_list_lock);
1504 obj_priv->last_rendering_seqno = seqno;
1507 static void
1508 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1510 struct drm_device *dev = obj->dev;
1511 drm_i915_private_t *dev_priv = dev->dev_private;
1512 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1514 BUG_ON(!obj_priv->active);
1515 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1516 obj_priv->last_rendering_seqno = 0;
1519 /* Immediately discard the backing storage */
1520 static void
1521 i915_gem_object_truncate(struct drm_gem_object *obj)
1523 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1524 struct inode *inode;
1526 inode = obj->filp->f_path.dentry->d_inode;
1527 if (inode->i_op->truncate)
1528 inode->i_op->truncate (inode);
1530 obj_priv->madv = __I915_MADV_PURGED;
1533 static inline int
1534 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1536 return obj_priv->madv == I915_MADV_DONTNEED;
1539 static void
1540 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1542 struct drm_device *dev = obj->dev;
1543 drm_i915_private_t *dev_priv = dev->dev_private;
1544 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1546 i915_verify_inactive(dev, __FILE__, __LINE__);
1547 if (obj_priv->pin_count != 0)
1548 list_del_init(&obj_priv->list);
1549 else
1550 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1552 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1554 obj_priv->last_rendering_seqno = 0;
1555 if (obj_priv->active) {
1556 obj_priv->active = 0;
1557 drm_gem_object_unreference(obj);
1559 i915_verify_inactive(dev, __FILE__, __LINE__);
1563 * Creates a new sequence number, emitting a write of it to the status page
1564 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1566 * Must be called with struct_lock held.
1568 * Returned sequence numbers are nonzero on success.
1570 static uint32_t
1571 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1572 uint32_t flush_domains)
1574 drm_i915_private_t *dev_priv = dev->dev_private;
1575 struct drm_i915_file_private *i915_file_priv = NULL;
1576 struct drm_i915_gem_request *request;
1577 uint32_t seqno;
1578 int was_empty;
1579 RING_LOCALS;
1581 if (file_priv != NULL)
1582 i915_file_priv = file_priv->driver_priv;
1584 request = kzalloc(sizeof(*request), GFP_KERNEL);
1585 if (request == NULL)
1586 return 0;
1588 /* Grab the seqno we're going to make this request be, and bump the
1589 * next (skipping 0 so it can be the reserved no-seqno value).
1591 seqno = dev_priv->mm.next_gem_seqno;
1592 dev_priv->mm.next_gem_seqno++;
1593 if (dev_priv->mm.next_gem_seqno == 0)
1594 dev_priv->mm.next_gem_seqno++;
1596 BEGIN_LP_RING(4);
1597 OUT_RING(MI_STORE_DWORD_INDEX);
1598 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1599 OUT_RING(seqno);
1601 OUT_RING(MI_USER_INTERRUPT);
1602 ADVANCE_LP_RING();
1604 DRM_DEBUG("%d\n", seqno);
1606 request->seqno = seqno;
1607 request->emitted_jiffies = jiffies;
1608 was_empty = list_empty(&dev_priv->mm.request_list);
1609 list_add_tail(&request->list, &dev_priv->mm.request_list);
1610 if (i915_file_priv) {
1611 list_add_tail(&request->client_list,
1612 &i915_file_priv->mm.request_list);
1613 } else {
1614 INIT_LIST_HEAD(&request->client_list);
1617 /* Associate any objects on the flushing list matching the write
1618 * domain we're flushing with our flush.
1620 if (flush_domains != 0) {
1621 struct drm_i915_gem_object *obj_priv, *next;
1623 list_for_each_entry_safe(obj_priv, next,
1624 &dev_priv->mm.gpu_write_list,
1625 gpu_write_list) {
1626 struct drm_gem_object *obj = obj_priv->obj;
1628 if ((obj->write_domain & flush_domains) ==
1629 obj->write_domain) {
1630 uint32_t old_write_domain = obj->write_domain;
1632 obj->write_domain = 0;
1633 list_del_init(&obj_priv->gpu_write_list);
1634 i915_gem_object_move_to_active(obj, seqno);
1636 trace_i915_gem_object_change_domain(obj,
1637 obj->read_domains,
1638 old_write_domain);
1644 if (!dev_priv->mm.suspended) {
1645 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1646 if (was_empty)
1647 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1649 return seqno;
1653 * Command execution barrier
1655 * Ensures that all commands in the ring are finished
1656 * before signalling the CPU
1658 static uint32_t
1659 i915_retire_commands(struct drm_device *dev)
1661 drm_i915_private_t *dev_priv = dev->dev_private;
1662 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1663 uint32_t flush_domains = 0;
1664 RING_LOCALS;
1666 /* The sampler always gets flushed on i965 (sigh) */
1667 if (IS_I965G(dev))
1668 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1669 BEGIN_LP_RING(2);
1670 OUT_RING(cmd);
1671 OUT_RING(0); /* noop */
1672 ADVANCE_LP_RING();
1673 return flush_domains;
1677 * Moves buffers associated only with the given active seqno from the active
1678 * to inactive list, potentially freeing them.
1680 static void
1681 i915_gem_retire_request(struct drm_device *dev,
1682 struct drm_i915_gem_request *request)
1684 drm_i915_private_t *dev_priv = dev->dev_private;
1686 trace_i915_gem_request_retire(dev, request->seqno);
1688 /* Move any buffers on the active list that are no longer referenced
1689 * by the ringbuffer to the flushing/inactive lists as appropriate.
1691 spin_lock(&dev_priv->mm.active_list_lock);
1692 while (!list_empty(&dev_priv->mm.active_list)) {
1693 struct drm_gem_object *obj;
1694 struct drm_i915_gem_object *obj_priv;
1696 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1697 struct drm_i915_gem_object,
1698 list);
1699 obj = obj_priv->obj;
1701 /* If the seqno being retired doesn't match the oldest in the
1702 * list, then the oldest in the list must still be newer than
1703 * this seqno.
1705 if (obj_priv->last_rendering_seqno != request->seqno)
1706 goto out;
1708 #if WATCH_LRU
1709 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1710 __func__, request->seqno, obj);
1711 #endif
1713 if (obj->write_domain != 0)
1714 i915_gem_object_move_to_flushing(obj);
1715 else {
1716 /* Take a reference on the object so it won't be
1717 * freed while the spinlock is held. The list
1718 * protection for this spinlock is safe when breaking
1719 * the lock like this since the next thing we do
1720 * is just get the head of the list again.
1722 drm_gem_object_reference(obj);
1723 i915_gem_object_move_to_inactive(obj);
1724 spin_unlock(&dev_priv->mm.active_list_lock);
1725 drm_gem_object_unreference(obj);
1726 spin_lock(&dev_priv->mm.active_list_lock);
1729 out:
1730 spin_unlock(&dev_priv->mm.active_list_lock);
1734 * Returns true if seq1 is later than seq2.
1736 bool
1737 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1739 return (int32_t)(seq1 - seq2) >= 0;
1742 uint32_t
1743 i915_get_gem_seqno(struct drm_device *dev)
1745 drm_i915_private_t *dev_priv = dev->dev_private;
1747 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1751 * This function clears the request list as sequence numbers are passed.
1753 void
1754 i915_gem_retire_requests(struct drm_device *dev)
1756 drm_i915_private_t *dev_priv = dev->dev_private;
1757 uint32_t seqno;
1759 if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1760 return;
1762 seqno = i915_get_gem_seqno(dev);
1764 while (!list_empty(&dev_priv->mm.request_list)) {
1765 struct drm_i915_gem_request *request;
1766 uint32_t retiring_seqno;
1768 request = list_first_entry(&dev_priv->mm.request_list,
1769 struct drm_i915_gem_request,
1770 list);
1771 retiring_seqno = request->seqno;
1773 if (i915_seqno_passed(seqno, retiring_seqno) ||
1774 atomic_read(&dev_priv->mm.wedged)) {
1775 i915_gem_retire_request(dev, request);
1777 list_del(&request->list);
1778 list_del(&request->client_list);
1779 kfree(request);
1780 } else
1781 break;
1784 if (unlikely (dev_priv->trace_irq_seqno &&
1785 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1786 i915_user_irq_put(dev);
1787 dev_priv->trace_irq_seqno = 0;
1791 void
1792 i915_gem_retire_work_handler(struct work_struct *work)
1794 drm_i915_private_t *dev_priv;
1795 struct drm_device *dev;
1797 dev_priv = container_of(work, drm_i915_private_t,
1798 mm.retire_work.work);
1799 dev = dev_priv->dev;
1801 mutex_lock(&dev->struct_mutex);
1802 i915_gem_retire_requests(dev);
1803 if (!dev_priv->mm.suspended &&
1804 !list_empty(&dev_priv->mm.request_list))
1805 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1806 mutex_unlock(&dev->struct_mutex);
1809 static int
1810 i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1812 drm_i915_private_t *dev_priv = dev->dev_private;
1813 u32 ier;
1814 int ret = 0;
1816 BUG_ON(seqno == 0);
1818 if (atomic_read(&dev_priv->mm.wedged))
1819 return -EIO;
1821 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1822 if (IS_IGDNG(dev))
1823 ier = I915_READ(DEIER) | I915_READ(GTIER);
1824 else
1825 ier = I915_READ(IER);
1826 if (!ier) {
1827 DRM_ERROR("something (likely vbetool) disabled "
1828 "interrupts, re-enabling\n");
1829 i915_driver_irq_preinstall(dev);
1830 i915_driver_irq_postinstall(dev);
1833 trace_i915_gem_request_wait_begin(dev, seqno);
1835 dev_priv->mm.waiting_gem_seqno = seqno;
1836 i915_user_irq_get(dev);
1837 if (interruptible)
1838 ret = wait_event_interruptible(dev_priv->irq_queue,
1839 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1840 atomic_read(&dev_priv->mm.wedged));
1841 else
1842 wait_event(dev_priv->irq_queue,
1843 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1844 atomic_read(&dev_priv->mm.wedged));
1846 i915_user_irq_put(dev);
1847 dev_priv->mm.waiting_gem_seqno = 0;
1849 trace_i915_gem_request_wait_end(dev, seqno);
1851 if (atomic_read(&dev_priv->mm.wedged))
1852 ret = -EIO;
1854 if (ret && ret != -ERESTARTSYS)
1855 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1856 __func__, ret, seqno, i915_get_gem_seqno(dev));
1858 /* Directly dispatch request retiring. While we have the work queue
1859 * to handle this, the waiter on a request often wants an associated
1860 * buffer to have made it to the inactive list, and we would need
1861 * a separate wait queue to handle that.
1863 if (ret == 0)
1864 i915_gem_retire_requests(dev);
1866 return ret;
1870 * Waits for a sequence number to be signaled, and cleans up the
1871 * request and object lists appropriately for that event.
1873 static int
1874 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1876 return i915_do_wait_request(dev, seqno, 1);
1880 * Waits for the ring to finish up to the latest request. Usefull for waiting
1881 * for flip events, e.g for the overlay support. */
1882 int i915_lp_ring_sync(struct drm_device *dev)
1884 uint32_t seqno;
1885 int ret;
1887 seqno = i915_add_request(dev, NULL, 0);
1889 if (seqno == 0)
1890 return -ENOMEM;
1892 ret = i915_do_wait_request(dev, seqno, 0);
1893 BUG_ON(ret == -ERESTARTSYS);
1894 return ret;
1897 static void
1898 i915_gem_flush(struct drm_device *dev,
1899 uint32_t invalidate_domains,
1900 uint32_t flush_domains)
1902 drm_i915_private_t *dev_priv = dev->dev_private;
1903 uint32_t cmd;
1904 RING_LOCALS;
1906 #if WATCH_EXEC
1907 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1908 invalidate_domains, flush_domains);
1909 #endif
1910 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1911 invalidate_domains, flush_domains);
1913 if (flush_domains & I915_GEM_DOMAIN_CPU)
1914 drm_agp_chipset_flush(dev);
1916 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1918 * read/write caches:
1920 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1921 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1922 * also flushed at 2d versus 3d pipeline switches.
1924 * read-only caches:
1926 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1927 * MI_READ_FLUSH is set, and is always flushed on 965.
1929 * I915_GEM_DOMAIN_COMMAND may not exist?
1931 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1932 * invalidated when MI_EXE_FLUSH is set.
1934 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1935 * invalidated with every MI_FLUSH.
1937 * TLBs:
1939 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1940 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1941 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1942 * are flushed at any MI_FLUSH.
1945 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1946 if ((invalidate_domains|flush_domains) &
1947 I915_GEM_DOMAIN_RENDER)
1948 cmd &= ~MI_NO_WRITE_FLUSH;
1949 if (!IS_I965G(dev)) {
1951 * On the 965, the sampler cache always gets flushed
1952 * and this bit is reserved.
1954 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1955 cmd |= MI_READ_FLUSH;
1957 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1958 cmd |= MI_EXE_FLUSH;
1960 #if WATCH_EXEC
1961 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1962 #endif
1963 BEGIN_LP_RING(2);
1964 OUT_RING(cmd);
1965 OUT_RING(MI_NOOP);
1966 ADVANCE_LP_RING();
1971 * Ensures that all rendering to the object has completed and the object is
1972 * safe to unbind from the GTT or access from the CPU.
1974 static int
1975 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1977 struct drm_device *dev = obj->dev;
1978 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1979 int ret;
1981 /* This function only exists to support waiting for existing rendering,
1982 * not for emitting required flushes.
1984 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1986 /* If there is rendering queued on the buffer being evicted, wait for
1987 * it.
1989 if (obj_priv->active) {
1990 #if WATCH_BUF
1991 DRM_INFO("%s: object %p wait for seqno %08x\n",
1992 __func__, obj, obj_priv->last_rendering_seqno);
1993 #endif
1994 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1995 if (ret != 0)
1996 return ret;
1999 return 0;
2003 * Unbinds an object from the GTT aperture.
2006 i915_gem_object_unbind(struct drm_gem_object *obj)
2008 struct drm_device *dev = obj->dev;
2009 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2010 int ret = 0;
2012 #if WATCH_BUF
2013 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
2014 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2015 #endif
2016 if (obj_priv->gtt_space == NULL)
2017 return 0;
2019 if (obj_priv->pin_count != 0) {
2020 DRM_ERROR("Attempting to unbind pinned buffer\n");
2021 return -EINVAL;
2024 /* blow away mappings if mapped through GTT */
2025 i915_gem_release_mmap(obj);
2027 /* Move the object to the CPU domain to ensure that
2028 * any possible CPU writes while it's not in the GTT
2029 * are flushed when we go to remap it. This will
2030 * also ensure that all pending GPU writes are finished
2031 * before we unbind.
2033 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2034 if (ret) {
2035 if (ret != -ERESTARTSYS)
2036 DRM_ERROR("set_domain failed: %d\n", ret);
2037 return ret;
2040 BUG_ON(obj_priv->active);
2042 /* release the fence reg _after_ flushing */
2043 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2044 i915_gem_clear_fence_reg(obj);
2046 if (obj_priv->agp_mem != NULL) {
2047 drm_unbind_agp(obj_priv->agp_mem);
2048 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2049 obj_priv->agp_mem = NULL;
2052 i915_gem_object_put_pages(obj);
2053 BUG_ON(obj_priv->pages_refcount);
2055 if (obj_priv->gtt_space) {
2056 atomic_dec(&dev->gtt_count);
2057 atomic_sub(obj->size, &dev->gtt_memory);
2059 drm_mm_put_block(obj_priv->gtt_space);
2060 obj_priv->gtt_space = NULL;
2063 /* Remove ourselves from the LRU list if present. */
2064 if (!list_empty(&obj_priv->list))
2065 list_del_init(&obj_priv->list);
2067 if (i915_gem_object_is_purgeable(obj_priv))
2068 i915_gem_object_truncate(obj);
2070 trace_i915_gem_object_unbind(obj);
2072 return 0;
2075 static struct drm_gem_object *
2076 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2078 drm_i915_private_t *dev_priv = dev->dev_private;
2079 struct drm_i915_gem_object *obj_priv;
2080 struct drm_gem_object *best = NULL;
2081 struct drm_gem_object *first = NULL;
2083 /* Try to find the smallest clean object */
2084 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2085 struct drm_gem_object *obj = obj_priv->obj;
2086 if (obj->size >= min_size) {
2087 if ((!obj_priv->dirty ||
2088 i915_gem_object_is_purgeable(obj_priv)) &&
2089 (!best || obj->size < best->size)) {
2090 best = obj;
2091 if (best->size == min_size)
2092 return best;
2094 if (!first)
2095 first = obj;
2099 return best ? best : first;
2102 static int
2103 i915_gem_evict_everything(struct drm_device *dev)
2105 drm_i915_private_t *dev_priv = dev->dev_private;
2106 int ret;
2107 uint32_t seqno;
2108 bool lists_empty;
2110 spin_lock(&dev_priv->mm.active_list_lock);
2111 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2112 list_empty(&dev_priv->mm.flushing_list) &&
2113 list_empty(&dev_priv->mm.active_list));
2114 spin_unlock(&dev_priv->mm.active_list_lock);
2116 if (lists_empty)
2117 return -ENOSPC;
2119 /* Flush everything (on to the inactive lists) and evict */
2120 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2121 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2122 if (seqno == 0)
2123 return -ENOMEM;
2125 ret = i915_wait_request(dev, seqno);
2126 if (ret)
2127 return ret;
2129 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2131 ret = i915_gem_evict_from_inactive_list(dev);
2132 if (ret)
2133 return ret;
2135 spin_lock(&dev_priv->mm.active_list_lock);
2136 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2137 list_empty(&dev_priv->mm.flushing_list) &&
2138 list_empty(&dev_priv->mm.active_list));
2139 spin_unlock(&dev_priv->mm.active_list_lock);
2140 BUG_ON(!lists_empty);
2142 return 0;
2145 static int
2146 i915_gem_evict_something(struct drm_device *dev, int min_size)
2148 drm_i915_private_t *dev_priv = dev->dev_private;
2149 struct drm_gem_object *obj;
2150 int ret;
2152 for (;;) {
2153 i915_gem_retire_requests(dev);
2155 /* If there's an inactive buffer available now, grab it
2156 * and be done.
2158 obj = i915_gem_find_inactive_object(dev, min_size);
2159 if (obj) {
2160 struct drm_i915_gem_object *obj_priv;
2162 #if WATCH_LRU
2163 DRM_INFO("%s: evicting %p\n", __func__, obj);
2164 #endif
2165 obj_priv = obj->driver_private;
2166 BUG_ON(obj_priv->pin_count != 0);
2167 BUG_ON(obj_priv->active);
2169 /* Wait on the rendering and unbind the buffer. */
2170 return i915_gem_object_unbind(obj);
2173 /* If we didn't get anything, but the ring is still processing
2174 * things, wait for the next to finish and hopefully leave us
2175 * a buffer to evict.
2177 if (!list_empty(&dev_priv->mm.request_list)) {
2178 struct drm_i915_gem_request *request;
2180 request = list_first_entry(&dev_priv->mm.request_list,
2181 struct drm_i915_gem_request,
2182 list);
2184 ret = i915_wait_request(dev, request->seqno);
2185 if (ret)
2186 return ret;
2188 continue;
2191 /* If we didn't have anything on the request list but there
2192 * are buffers awaiting a flush, emit one and try again.
2193 * When we wait on it, those buffers waiting for that flush
2194 * will get moved to inactive.
2196 if (!list_empty(&dev_priv->mm.flushing_list)) {
2197 struct drm_i915_gem_object *obj_priv;
2199 /* Find an object that we can immediately reuse */
2200 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2201 obj = obj_priv->obj;
2202 if (obj->size >= min_size)
2203 break;
2205 obj = NULL;
2208 if (obj != NULL) {
2209 uint32_t seqno;
2211 i915_gem_flush(dev,
2212 obj->write_domain,
2213 obj->write_domain);
2214 seqno = i915_add_request(dev, NULL, obj->write_domain);
2215 if (seqno == 0)
2216 return -ENOMEM;
2218 ret = i915_wait_request(dev, seqno);
2219 if (ret)
2220 return ret;
2222 continue;
2226 /* If we didn't do any of the above, there's no single buffer
2227 * large enough to swap out for the new one, so just evict
2228 * everything and start again. (This should be rare.)
2230 if (!list_empty (&dev_priv->mm.inactive_list))
2231 return i915_gem_evict_from_inactive_list(dev);
2232 else
2233 return i915_gem_evict_everything(dev);
2238 i915_gem_object_get_pages(struct drm_gem_object *obj,
2239 gfp_t gfpmask)
2241 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2242 int page_count, i;
2243 struct address_space *mapping;
2244 struct inode *inode;
2245 struct page *page;
2247 if (obj_priv->pages_refcount++ != 0)
2248 return 0;
2250 /* Get the list of pages out of our struct file. They'll be pinned
2251 * at this point until we release them.
2253 page_count = obj->size / PAGE_SIZE;
2254 BUG_ON(obj_priv->pages != NULL);
2255 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2256 if (obj_priv->pages == NULL) {
2257 obj_priv->pages_refcount--;
2258 return -ENOMEM;
2261 inode = obj->filp->f_path.dentry->d_inode;
2262 mapping = inode->i_mapping;
2263 for (i = 0; i < page_count; i++) {
2264 page = read_cache_page_gfp(mapping, i,
2265 mapping_gfp_mask (mapping) |
2266 __GFP_COLD |
2267 gfpmask);
2268 if (IS_ERR(page))
2269 goto err_pages;
2271 obj_priv->pages[i] = page;
2274 if (obj_priv->tiling_mode != I915_TILING_NONE)
2275 i915_gem_object_do_bit_17_swizzle(obj);
2277 return 0;
2279 err_pages:
2280 while (i--)
2281 page_cache_release(obj_priv->pages[i]);
2283 drm_free_large(obj_priv->pages);
2284 obj_priv->pages = NULL;
2285 obj_priv->pages_refcount--;
2286 return PTR_ERR(page);
2289 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2291 struct drm_gem_object *obj = reg->obj;
2292 struct drm_device *dev = obj->dev;
2293 drm_i915_private_t *dev_priv = dev->dev_private;
2294 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2295 int regnum = obj_priv->fence_reg;
2296 uint64_t val;
2298 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2299 0xfffff000) << 32;
2300 val |= obj_priv->gtt_offset & 0xfffff000;
2301 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2302 if (obj_priv->tiling_mode == I915_TILING_Y)
2303 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2304 val |= I965_FENCE_REG_VALID;
2306 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2309 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2311 struct drm_gem_object *obj = reg->obj;
2312 struct drm_device *dev = obj->dev;
2313 drm_i915_private_t *dev_priv = dev->dev_private;
2314 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2315 int regnum = obj_priv->fence_reg;
2316 int tile_width;
2317 uint32_t fence_reg, val;
2318 uint32_t pitch_val;
2320 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2321 (obj_priv->gtt_offset & (obj->size - 1))) {
2322 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2323 __func__, obj_priv->gtt_offset, obj->size);
2324 return;
2327 if (obj_priv->tiling_mode == I915_TILING_Y &&
2328 HAS_128_BYTE_Y_TILING(dev))
2329 tile_width = 128;
2330 else
2331 tile_width = 512;
2333 /* Note: pitch better be a power of two tile widths */
2334 pitch_val = obj_priv->stride / tile_width;
2335 pitch_val = ffs(pitch_val) - 1;
2337 if (obj_priv->tiling_mode == I915_TILING_Y &&
2338 HAS_128_BYTE_Y_TILING(dev))
2339 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2340 else
2341 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2343 val = obj_priv->gtt_offset;
2344 if (obj_priv->tiling_mode == I915_TILING_Y)
2345 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2346 val |= I915_FENCE_SIZE_BITS(obj->size);
2347 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2348 val |= I830_FENCE_REG_VALID;
2350 if (regnum < 8)
2351 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2352 else
2353 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2354 I915_WRITE(fence_reg, val);
2357 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2359 struct drm_gem_object *obj = reg->obj;
2360 struct drm_device *dev = obj->dev;
2361 drm_i915_private_t *dev_priv = dev->dev_private;
2362 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2363 int regnum = obj_priv->fence_reg;
2364 uint32_t val;
2365 uint32_t pitch_val;
2366 uint32_t fence_size_bits;
2368 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2369 (obj_priv->gtt_offset & (obj->size - 1))) {
2370 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2371 __func__, obj_priv->gtt_offset);
2372 return;
2375 pitch_val = obj_priv->stride / 128;
2376 pitch_val = ffs(pitch_val) - 1;
2377 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2379 val = obj_priv->gtt_offset;
2380 if (obj_priv->tiling_mode == I915_TILING_Y)
2381 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2382 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2383 WARN_ON(fence_size_bits & ~0x00000f00);
2384 val |= fence_size_bits;
2385 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2386 val |= I830_FENCE_REG_VALID;
2388 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2392 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2393 * @obj: object to map through a fence reg
2395 * When mapping objects through the GTT, userspace wants to be able to write
2396 * to them without having to worry about swizzling if the object is tiled.
2398 * This function walks the fence regs looking for a free one for @obj,
2399 * stealing one if it can't find any.
2401 * It then sets up the reg based on the object's properties: address, pitch
2402 * and tiling format.
2405 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2407 struct drm_device *dev = obj->dev;
2408 struct drm_i915_private *dev_priv = dev->dev_private;
2409 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2410 struct drm_i915_fence_reg *reg = NULL;
2411 struct drm_i915_gem_object *old_obj_priv = NULL;
2412 int i, ret, avail;
2414 /* Just update our place in the LRU if our fence is getting used. */
2415 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2416 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2417 return 0;
2420 switch (obj_priv->tiling_mode) {
2421 case I915_TILING_NONE:
2422 WARN(1, "allocating a fence for non-tiled object?\n");
2423 break;
2424 case I915_TILING_X:
2425 if (!obj_priv->stride)
2426 return -EINVAL;
2427 WARN((obj_priv->stride & (512 - 1)),
2428 "object 0x%08x is X tiled but has non-512B pitch\n",
2429 obj_priv->gtt_offset);
2430 break;
2431 case I915_TILING_Y:
2432 if (!obj_priv->stride)
2433 return -EINVAL;
2434 WARN((obj_priv->stride & (128 - 1)),
2435 "object 0x%08x is Y tiled but has non-128B pitch\n",
2436 obj_priv->gtt_offset);
2437 break;
2440 /* First try to find a free reg */
2441 avail = 0;
2442 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2443 reg = &dev_priv->fence_regs[i];
2444 if (!reg->obj)
2445 break;
2447 old_obj_priv = reg->obj->driver_private;
2448 if (!old_obj_priv->pin_count)
2449 avail++;
2452 /* None available, try to steal one or wait for a user to finish */
2453 if (i == dev_priv->num_fence_regs) {
2454 struct drm_gem_object *old_obj = NULL;
2456 if (avail == 0)
2457 return -ENOSPC;
2459 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2460 fence_list) {
2461 old_obj = old_obj_priv->obj;
2463 if (old_obj_priv->pin_count)
2464 continue;
2466 /* Take a reference, as otherwise the wait_rendering
2467 * below may cause the object to get freed out from
2468 * under us.
2470 drm_gem_object_reference(old_obj);
2472 /* i915 uses fences for GPU access to tiled buffers */
2473 if (IS_I965G(dev) || !old_obj_priv->active)
2474 break;
2476 /* This brings the object to the head of the LRU if it
2477 * had been written to. The only way this should
2478 * result in us waiting longer than the expected
2479 * optimal amount of time is if there was a
2480 * fence-using buffer later that was read-only.
2482 i915_gem_object_flush_gpu_write_domain(old_obj);
2483 ret = i915_gem_object_wait_rendering(old_obj);
2484 if (ret != 0) {
2485 drm_gem_object_unreference(old_obj);
2486 return ret;
2489 break;
2493 * Zap this virtual mapping so we can set up a fence again
2494 * for this object next time we need it.
2496 i915_gem_release_mmap(old_obj);
2498 i = old_obj_priv->fence_reg;
2499 reg = &dev_priv->fence_regs[i];
2501 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2502 list_del_init(&old_obj_priv->fence_list);
2504 drm_gem_object_unreference(old_obj);
2507 obj_priv->fence_reg = i;
2508 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2510 reg->obj = obj;
2512 if (IS_I965G(dev))
2513 i965_write_fence_reg(reg);
2514 else if (IS_I9XX(dev))
2515 i915_write_fence_reg(reg);
2516 else
2517 i830_write_fence_reg(reg);
2519 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2521 return 0;
2525 * i915_gem_clear_fence_reg - clear out fence register info
2526 * @obj: object to clear
2528 * Zeroes out the fence register itself and clears out the associated
2529 * data structures in dev_priv and obj_priv.
2531 static void
2532 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2534 struct drm_device *dev = obj->dev;
2535 drm_i915_private_t *dev_priv = dev->dev_private;
2536 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2538 if (IS_I965G(dev))
2539 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2540 else {
2541 uint32_t fence_reg;
2543 if (obj_priv->fence_reg < 8)
2544 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2545 else
2546 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2547 8) * 4;
2549 I915_WRITE(fence_reg, 0);
2552 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2553 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2554 list_del_init(&obj_priv->fence_list);
2558 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2559 * to the buffer to finish, and then resets the fence register.
2560 * @obj: tiled object holding a fence register.
2562 * Zeroes out the fence register itself and clears out the associated
2563 * data structures in dev_priv and obj_priv.
2566 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2568 struct drm_device *dev = obj->dev;
2569 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2571 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2572 return 0;
2574 /* On the i915, GPU access to tiled buffers is via a fence,
2575 * therefore we must wait for any outstanding access to complete
2576 * before clearing the fence.
2578 if (!IS_I965G(dev)) {
2579 int ret;
2581 i915_gem_object_flush_gpu_write_domain(obj);
2582 i915_gem_object_flush_gtt_write_domain(obj);
2583 ret = i915_gem_object_wait_rendering(obj);
2584 if (ret != 0)
2585 return ret;
2588 i915_gem_clear_fence_reg (obj);
2590 return 0;
2594 * Finds free space in the GTT aperture and binds the object there.
2596 static int
2597 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2599 struct drm_device *dev = obj->dev;
2600 drm_i915_private_t *dev_priv = dev->dev_private;
2601 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2602 struct drm_mm_node *free_space;
2603 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2604 int ret;
2606 if (obj_priv->madv != I915_MADV_WILLNEED) {
2607 DRM_ERROR("Attempting to bind a purgeable object\n");
2608 return -EINVAL;
2611 if (alignment == 0)
2612 alignment = i915_gem_get_gtt_alignment(obj);
2613 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2614 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2615 return -EINVAL;
2618 search_free:
2619 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2620 obj->size, alignment, 0);
2621 if (free_space != NULL) {
2622 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2623 alignment);
2624 if (obj_priv->gtt_space != NULL) {
2625 obj_priv->gtt_space->private = obj;
2626 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2629 if (obj_priv->gtt_space == NULL) {
2630 /* If the gtt is empty and we're still having trouble
2631 * fitting our object in, we're out of memory.
2633 #if WATCH_LRU
2634 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2635 #endif
2636 ret = i915_gem_evict_something(dev, obj->size);
2637 if (ret)
2638 return ret;
2640 goto search_free;
2643 #if WATCH_BUF
2644 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2645 obj->size, obj_priv->gtt_offset);
2646 #endif
2647 ret = i915_gem_object_get_pages(obj, gfpmask);
2648 if (ret) {
2649 drm_mm_put_block(obj_priv->gtt_space);
2650 obj_priv->gtt_space = NULL;
2652 if (ret == -ENOMEM) {
2653 /* first try to clear up some space from the GTT */
2654 ret = i915_gem_evict_something(dev, obj->size);
2655 if (ret) {
2656 /* now try to shrink everyone else */
2657 if (gfpmask) {
2658 gfpmask = 0;
2659 goto search_free;
2662 return ret;
2665 goto search_free;
2668 return ret;
2671 /* Create an AGP memory structure pointing at our pages, and bind it
2672 * into the GTT.
2674 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2675 obj_priv->pages,
2676 obj->size >> PAGE_SHIFT,
2677 obj_priv->gtt_offset,
2678 obj_priv->agp_type);
2679 if (obj_priv->agp_mem == NULL) {
2680 i915_gem_object_put_pages(obj);
2681 drm_mm_put_block(obj_priv->gtt_space);
2682 obj_priv->gtt_space = NULL;
2684 ret = i915_gem_evict_something(dev, obj->size);
2685 if (ret)
2686 return ret;
2688 goto search_free;
2690 atomic_inc(&dev->gtt_count);
2691 atomic_add(obj->size, &dev->gtt_memory);
2693 /* Assert that the object is not currently in any GPU domain. As it
2694 * wasn't in the GTT, there shouldn't be any way it could have been in
2695 * a GPU cache
2697 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2698 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2700 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2702 return 0;
2705 void
2706 i915_gem_clflush_object(struct drm_gem_object *obj)
2708 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2710 /* If we don't have a page list set up, then we're not pinned
2711 * to GPU, and we can ignore the cache flush because it'll happen
2712 * again at bind time.
2714 if (obj_priv->pages == NULL)
2715 return;
2717 trace_i915_gem_object_clflush(obj);
2719 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2722 /** Flushes any GPU write domain for the object if it's dirty. */
2723 static void
2724 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2726 struct drm_device *dev = obj->dev;
2727 uint32_t seqno;
2728 uint32_t old_write_domain;
2730 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2731 return;
2733 /* Queue the GPU write cache flushing we need. */
2734 old_write_domain = obj->write_domain;
2735 i915_gem_flush(dev, 0, obj->write_domain);
2736 seqno = i915_add_request(dev, NULL, obj->write_domain);
2737 BUG_ON(obj->write_domain);
2738 i915_gem_object_move_to_active(obj, seqno);
2740 trace_i915_gem_object_change_domain(obj,
2741 obj->read_domains,
2742 old_write_domain);
2745 /** Flushes the GTT write domain for the object if it's dirty. */
2746 static void
2747 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2749 uint32_t old_write_domain;
2751 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2752 return;
2754 /* No actual flushing is required for the GTT write domain. Writes
2755 * to it immediately go to main memory as far as we know, so there's
2756 * no chipset flush. It also doesn't land in render cache.
2758 old_write_domain = obj->write_domain;
2759 obj->write_domain = 0;
2761 trace_i915_gem_object_change_domain(obj,
2762 obj->read_domains,
2763 old_write_domain);
2766 /** Flushes the CPU write domain for the object if it's dirty. */
2767 static void
2768 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2770 struct drm_device *dev = obj->dev;
2771 uint32_t old_write_domain;
2773 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2774 return;
2776 i915_gem_clflush_object(obj);
2777 drm_agp_chipset_flush(dev);
2778 old_write_domain = obj->write_domain;
2779 obj->write_domain = 0;
2781 trace_i915_gem_object_change_domain(obj,
2782 obj->read_domains,
2783 old_write_domain);
2787 * Moves a single object to the GTT read, and possibly write domain.
2789 * This function returns when the move is complete, including waiting on
2790 * flushes to occur.
2793 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2795 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2796 uint32_t old_write_domain, old_read_domains;
2797 int ret;
2799 /* Not valid to be called on unbound objects. */
2800 if (obj_priv->gtt_space == NULL)
2801 return -EINVAL;
2803 i915_gem_object_flush_gpu_write_domain(obj);
2804 /* Wait on any GPU rendering and flushing to occur. */
2805 ret = i915_gem_object_wait_rendering(obj);
2806 if (ret != 0)
2807 return ret;
2809 old_write_domain = obj->write_domain;
2810 old_read_domains = obj->read_domains;
2812 /* If we're writing through the GTT domain, then CPU and GPU caches
2813 * will need to be invalidated at next use.
2815 if (write)
2816 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2818 i915_gem_object_flush_cpu_write_domain(obj);
2820 /* It should now be out of any other write domains, and we can update
2821 * the domain values for our changes.
2823 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2824 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2825 if (write) {
2826 obj->write_domain = I915_GEM_DOMAIN_GTT;
2827 obj_priv->dirty = 1;
2830 trace_i915_gem_object_change_domain(obj,
2831 old_read_domains,
2832 old_write_domain);
2834 return 0;
2838 * Prepare buffer for display plane. Use uninterruptible for possible flush
2839 * wait, as in modesetting process we're not supposed to be interrupted.
2842 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2844 struct drm_device *dev = obj->dev;
2845 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2846 uint32_t old_write_domain, old_read_domains;
2847 int ret;
2849 /* Not valid to be called on unbound objects. */
2850 if (obj_priv->gtt_space == NULL)
2851 return -EINVAL;
2853 i915_gem_object_flush_gpu_write_domain(obj);
2855 /* Wait on any GPU rendering and flushing to occur. */
2856 if (obj_priv->active) {
2857 #if WATCH_BUF
2858 DRM_INFO("%s: object %p wait for seqno %08x\n",
2859 __func__, obj, obj_priv->last_rendering_seqno);
2860 #endif
2861 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2862 if (ret != 0)
2863 return ret;
2866 old_write_domain = obj->write_domain;
2867 old_read_domains = obj->read_domains;
2869 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2871 i915_gem_object_flush_cpu_write_domain(obj);
2873 /* It should now be out of any other write domains, and we can update
2874 * the domain values for our changes.
2876 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2877 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2878 obj->write_domain = I915_GEM_DOMAIN_GTT;
2879 obj_priv->dirty = 1;
2881 trace_i915_gem_object_change_domain(obj,
2882 old_read_domains,
2883 old_write_domain);
2885 return 0;
2889 * Moves a single object to the CPU read, and possibly write domain.
2891 * This function returns when the move is complete, including waiting on
2892 * flushes to occur.
2894 static int
2895 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2897 uint32_t old_write_domain, old_read_domains;
2898 int ret;
2900 i915_gem_object_flush_gpu_write_domain(obj);
2901 /* Wait on any GPU rendering and flushing to occur. */
2902 ret = i915_gem_object_wait_rendering(obj);
2903 if (ret != 0)
2904 return ret;
2906 i915_gem_object_flush_gtt_write_domain(obj);
2908 /* If we have a partially-valid cache of the object in the CPU,
2909 * finish invalidating it and free the per-page flags.
2911 i915_gem_object_set_to_full_cpu_read_domain(obj);
2913 old_write_domain = obj->write_domain;
2914 old_read_domains = obj->read_domains;
2916 /* Flush the CPU cache if it's still invalid. */
2917 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2918 i915_gem_clflush_object(obj);
2920 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2923 /* It should now be out of any other write domains, and we can update
2924 * the domain values for our changes.
2926 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2928 /* If we're writing through the CPU, then the GPU read domains will
2929 * need to be invalidated at next use.
2931 if (write) {
2932 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2933 obj->write_domain = I915_GEM_DOMAIN_CPU;
2936 trace_i915_gem_object_change_domain(obj,
2937 old_read_domains,
2938 old_write_domain);
2940 return 0;
2944 * Set the next domain for the specified object. This
2945 * may not actually perform the necessary flushing/invaliding though,
2946 * as that may want to be batched with other set_domain operations
2948 * This is (we hope) the only really tricky part of gem. The goal
2949 * is fairly simple -- track which caches hold bits of the object
2950 * and make sure they remain coherent. A few concrete examples may
2951 * help to explain how it works. For shorthand, we use the notation
2952 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2953 * a pair of read and write domain masks.
2955 * Case 1: the batch buffer
2957 * 1. Allocated
2958 * 2. Written by CPU
2959 * 3. Mapped to GTT
2960 * 4. Read by GPU
2961 * 5. Unmapped from GTT
2962 * 6. Freed
2964 * Let's take these a step at a time
2966 * 1. Allocated
2967 * Pages allocated from the kernel may still have
2968 * cache contents, so we set them to (CPU, CPU) always.
2969 * 2. Written by CPU (using pwrite)
2970 * The pwrite function calls set_domain (CPU, CPU) and
2971 * this function does nothing (as nothing changes)
2972 * 3. Mapped by GTT
2973 * This function asserts that the object is not
2974 * currently in any GPU-based read or write domains
2975 * 4. Read by GPU
2976 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2977 * As write_domain is zero, this function adds in the
2978 * current read domains (CPU+COMMAND, 0).
2979 * flush_domains is set to CPU.
2980 * invalidate_domains is set to COMMAND
2981 * clflush is run to get data out of the CPU caches
2982 * then i915_dev_set_domain calls i915_gem_flush to
2983 * emit an MI_FLUSH and drm_agp_chipset_flush
2984 * 5. Unmapped from GTT
2985 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2986 * flush_domains and invalidate_domains end up both zero
2987 * so no flushing/invalidating happens
2988 * 6. Freed
2989 * yay, done
2991 * Case 2: The shared render buffer
2993 * 1. Allocated
2994 * 2. Mapped to GTT
2995 * 3. Read/written by GPU
2996 * 4. set_domain to (CPU,CPU)
2997 * 5. Read/written by CPU
2998 * 6. Read/written by GPU
3000 * 1. Allocated
3001 * Same as last example, (CPU, CPU)
3002 * 2. Mapped to GTT
3003 * Nothing changes (assertions find that it is not in the GPU)
3004 * 3. Read/written by GPU
3005 * execbuffer calls set_domain (RENDER, RENDER)
3006 * flush_domains gets CPU
3007 * invalidate_domains gets GPU
3008 * clflush (obj)
3009 * MI_FLUSH and drm_agp_chipset_flush
3010 * 4. set_domain (CPU, CPU)
3011 * flush_domains gets GPU
3012 * invalidate_domains gets CPU
3013 * wait_rendering (obj) to make sure all drawing is complete.
3014 * This will include an MI_FLUSH to get the data from GPU
3015 * to memory
3016 * clflush (obj) to invalidate the CPU cache
3017 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3018 * 5. Read/written by CPU
3019 * cache lines are loaded and dirtied
3020 * 6. Read written by GPU
3021 * Same as last GPU access
3023 * Case 3: The constant buffer
3025 * 1. Allocated
3026 * 2. Written by CPU
3027 * 3. Read by GPU
3028 * 4. Updated (written) by CPU again
3029 * 5. Read by GPU
3031 * 1. Allocated
3032 * (CPU, CPU)
3033 * 2. Written by CPU
3034 * (CPU, CPU)
3035 * 3. Read by GPU
3036 * (CPU+RENDER, 0)
3037 * flush_domains = CPU
3038 * invalidate_domains = RENDER
3039 * clflush (obj)
3040 * MI_FLUSH
3041 * drm_agp_chipset_flush
3042 * 4. Updated (written) by CPU again
3043 * (CPU, CPU)
3044 * flush_domains = 0 (no previous write domain)
3045 * invalidate_domains = 0 (no new read domains)
3046 * 5. Read by GPU
3047 * (CPU+RENDER, 0)
3048 * flush_domains = CPU
3049 * invalidate_domains = RENDER
3050 * clflush (obj)
3051 * MI_FLUSH
3052 * drm_agp_chipset_flush
3054 static void
3055 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3057 struct drm_device *dev = obj->dev;
3058 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3059 uint32_t invalidate_domains = 0;
3060 uint32_t flush_domains = 0;
3061 uint32_t old_read_domains;
3063 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3064 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3066 intel_mark_busy(dev, obj);
3068 #if WATCH_BUF
3069 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3070 __func__, obj,
3071 obj->read_domains, obj->pending_read_domains,
3072 obj->write_domain, obj->pending_write_domain);
3073 #endif
3075 * If the object isn't moving to a new write domain,
3076 * let the object stay in multiple read domains
3078 if (obj->pending_write_domain == 0)
3079 obj->pending_read_domains |= obj->read_domains;
3080 else
3081 obj_priv->dirty = 1;
3084 * Flush the current write domain if
3085 * the new read domains don't match. Invalidate
3086 * any read domains which differ from the old
3087 * write domain
3089 if (obj->write_domain &&
3090 obj->write_domain != obj->pending_read_domains) {
3091 flush_domains |= obj->write_domain;
3092 invalidate_domains |=
3093 obj->pending_read_domains & ~obj->write_domain;
3096 * Invalidate any read caches which may have
3097 * stale data. That is, any new read domains.
3099 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3100 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3101 #if WATCH_BUF
3102 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3103 __func__, flush_domains, invalidate_domains);
3104 #endif
3105 i915_gem_clflush_object(obj);
3108 old_read_domains = obj->read_domains;
3110 /* The actual obj->write_domain will be updated with
3111 * pending_write_domain after we emit the accumulated flush for all
3112 * of our domain changes in execbuffers (which clears objects'
3113 * write_domains). So if we have a current write domain that we
3114 * aren't changing, set pending_write_domain to that.
3116 if (flush_domains == 0 && obj->pending_write_domain == 0)
3117 obj->pending_write_domain = obj->write_domain;
3118 obj->read_domains = obj->pending_read_domains;
3120 dev->invalidate_domains |= invalidate_domains;
3121 dev->flush_domains |= flush_domains;
3122 #if WATCH_BUF
3123 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3124 __func__,
3125 obj->read_domains, obj->write_domain,
3126 dev->invalidate_domains, dev->flush_domains);
3127 #endif
3129 trace_i915_gem_object_change_domain(obj,
3130 old_read_domains,
3131 obj->write_domain);
3135 * Moves the object from a partially CPU read to a full one.
3137 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3138 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3140 static void
3141 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3143 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3145 if (!obj_priv->page_cpu_valid)
3146 return;
3148 /* If we're partially in the CPU read domain, finish moving it in.
3150 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3151 int i;
3153 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3154 if (obj_priv->page_cpu_valid[i])
3155 continue;
3156 drm_clflush_pages(obj_priv->pages + i, 1);
3160 /* Free the page_cpu_valid mappings which are now stale, whether
3161 * or not we've got I915_GEM_DOMAIN_CPU.
3163 kfree(obj_priv->page_cpu_valid);
3164 obj_priv->page_cpu_valid = NULL;
3168 * Set the CPU read domain on a range of the object.
3170 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3171 * not entirely valid. The page_cpu_valid member of the object flags which
3172 * pages have been flushed, and will be respected by
3173 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3174 * of the whole object.
3176 * This function returns when the move is complete, including waiting on
3177 * flushes to occur.
3179 static int
3180 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3181 uint64_t offset, uint64_t size)
3183 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3184 uint32_t old_read_domains;
3185 int i, ret;
3187 if (offset == 0 && size == obj->size)
3188 return i915_gem_object_set_to_cpu_domain(obj, 0);
3190 i915_gem_object_flush_gpu_write_domain(obj);
3191 /* Wait on any GPU rendering and flushing to occur. */
3192 ret = i915_gem_object_wait_rendering(obj);
3193 if (ret != 0)
3194 return ret;
3195 i915_gem_object_flush_gtt_write_domain(obj);
3197 /* If we're already fully in the CPU read domain, we're done. */
3198 if (obj_priv->page_cpu_valid == NULL &&
3199 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3200 return 0;
3202 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3203 * newly adding I915_GEM_DOMAIN_CPU
3205 if (obj_priv->page_cpu_valid == NULL) {
3206 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3207 GFP_KERNEL);
3208 if (obj_priv->page_cpu_valid == NULL)
3209 return -ENOMEM;
3210 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3211 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3213 /* Flush the cache on any pages that are still invalid from the CPU's
3214 * perspective.
3216 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3217 i++) {
3218 if (obj_priv->page_cpu_valid[i])
3219 continue;
3221 drm_clflush_pages(obj_priv->pages + i, 1);
3223 obj_priv->page_cpu_valid[i] = 1;
3226 /* It should now be out of any other write domains, and we can update
3227 * the domain values for our changes.
3229 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3231 old_read_domains = obj->read_domains;
3232 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3234 trace_i915_gem_object_change_domain(obj,
3235 old_read_domains,
3236 obj->write_domain);
3238 return 0;
3242 * Pin an object to the GTT and evaluate the relocations landing in it.
3244 static int
3245 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3246 struct drm_file *file_priv,
3247 struct drm_i915_gem_exec_object *entry,
3248 struct drm_i915_gem_relocation_entry *relocs)
3250 struct drm_device *dev = obj->dev;
3251 drm_i915_private_t *dev_priv = dev->dev_private;
3252 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3253 int i, ret;
3254 void __iomem *reloc_page;
3256 /* Choose the GTT offset for our buffer and put it there. */
3257 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3258 if (ret)
3259 return ret;
3261 entry->offset = obj_priv->gtt_offset;
3263 /* Apply the relocations, using the GTT aperture to avoid cache
3264 * flushing requirements.
3266 for (i = 0; i < entry->relocation_count; i++) {
3267 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3268 struct drm_gem_object *target_obj;
3269 struct drm_i915_gem_object *target_obj_priv;
3270 uint32_t reloc_val, reloc_offset;
3271 uint32_t __iomem *reloc_entry;
3273 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3274 reloc->target_handle);
3275 if (target_obj == NULL) {
3276 i915_gem_object_unpin(obj);
3277 return -EBADF;
3279 target_obj_priv = target_obj->driver_private;
3281 #if WATCH_RELOC
3282 DRM_INFO("%s: obj %p offset %08x target %d "
3283 "read %08x write %08x gtt %08x "
3284 "presumed %08x delta %08x\n",
3285 __func__,
3286 obj,
3287 (int) reloc->offset,
3288 (int) reloc->target_handle,
3289 (int) reloc->read_domains,
3290 (int) reloc->write_domain,
3291 (int) target_obj_priv->gtt_offset,
3292 (int) reloc->presumed_offset,
3293 reloc->delta);
3294 #endif
3296 /* The target buffer should have appeared before us in the
3297 * exec_object list, so it should have a GTT space bound by now.
3299 if (target_obj_priv->gtt_space == NULL) {
3300 DRM_ERROR("No GTT space found for object %d\n",
3301 reloc->target_handle);
3302 drm_gem_object_unreference(target_obj);
3303 i915_gem_object_unpin(obj);
3304 return -EINVAL;
3307 /* Validate that the target is in a valid r/w GPU domain */
3308 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3309 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3310 DRM_ERROR("reloc with read/write CPU domains: "
3311 "obj %p target %d offset %d "
3312 "read %08x write %08x",
3313 obj, reloc->target_handle,
3314 (int) reloc->offset,
3315 reloc->read_domains,
3316 reloc->write_domain);
3317 drm_gem_object_unreference(target_obj);
3318 i915_gem_object_unpin(obj);
3319 return -EINVAL;
3321 if (reloc->write_domain && target_obj->pending_write_domain &&
3322 reloc->write_domain != target_obj->pending_write_domain) {
3323 DRM_ERROR("Write domain conflict: "
3324 "obj %p target %d offset %d "
3325 "new %08x old %08x\n",
3326 obj, reloc->target_handle,
3327 (int) reloc->offset,
3328 reloc->write_domain,
3329 target_obj->pending_write_domain);
3330 drm_gem_object_unreference(target_obj);
3331 i915_gem_object_unpin(obj);
3332 return -EINVAL;
3335 target_obj->pending_read_domains |= reloc->read_domains;
3336 target_obj->pending_write_domain |= reloc->write_domain;
3338 /* If the relocation already has the right value in it, no
3339 * more work needs to be done.
3341 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3342 drm_gem_object_unreference(target_obj);
3343 continue;
3346 /* Check that the relocation address is valid... */
3347 if (reloc->offset > obj->size - 4) {
3348 DRM_ERROR("Relocation beyond object bounds: "
3349 "obj %p target %d offset %d size %d.\n",
3350 obj, reloc->target_handle,
3351 (int) reloc->offset, (int) obj->size);
3352 drm_gem_object_unreference(target_obj);
3353 i915_gem_object_unpin(obj);
3354 return -EINVAL;
3356 if (reloc->offset & 3) {
3357 DRM_ERROR("Relocation not 4-byte aligned: "
3358 "obj %p target %d offset %d.\n",
3359 obj, reloc->target_handle,
3360 (int) reloc->offset);
3361 drm_gem_object_unreference(target_obj);
3362 i915_gem_object_unpin(obj);
3363 return -EINVAL;
3366 /* and points to somewhere within the target object. */
3367 if (reloc->delta >= target_obj->size) {
3368 DRM_ERROR("Relocation beyond target object bounds: "
3369 "obj %p target %d delta %d size %d.\n",
3370 obj, reloc->target_handle,
3371 (int) reloc->delta, (int) target_obj->size);
3372 drm_gem_object_unreference(target_obj);
3373 i915_gem_object_unpin(obj);
3374 return -EINVAL;
3377 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3378 if (ret != 0) {
3379 drm_gem_object_unreference(target_obj);
3380 i915_gem_object_unpin(obj);
3381 return -EINVAL;
3384 /* Map the page containing the relocation we're going to
3385 * perform.
3387 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3388 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3389 (reloc_offset &
3390 ~(PAGE_SIZE - 1)));
3391 reloc_entry = (uint32_t __iomem *)(reloc_page +
3392 (reloc_offset & (PAGE_SIZE - 1)));
3393 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3395 #if WATCH_BUF
3396 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3397 obj, (unsigned int) reloc->offset,
3398 readl(reloc_entry), reloc_val);
3399 #endif
3400 writel(reloc_val, reloc_entry);
3401 io_mapping_unmap_atomic(reloc_page);
3403 /* The updated presumed offset for this entry will be
3404 * copied back out to the user.
3406 reloc->presumed_offset = target_obj_priv->gtt_offset;
3408 drm_gem_object_unreference(target_obj);
3411 #if WATCH_BUF
3412 if (0)
3413 i915_gem_dump_object(obj, 128, __func__, ~0);
3414 #endif
3415 return 0;
3418 /** Dispatch a batchbuffer to the ring
3420 static int
3421 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3422 struct drm_i915_gem_execbuffer *exec,
3423 struct drm_clip_rect *cliprects,
3424 uint64_t exec_offset)
3426 drm_i915_private_t *dev_priv = dev->dev_private;
3427 int nbox = exec->num_cliprects;
3428 int i = 0, count;
3429 uint32_t exec_start, exec_len;
3430 RING_LOCALS;
3432 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3433 exec_len = (uint32_t) exec->batch_len;
3435 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
3437 count = nbox ? nbox : 1;
3439 for (i = 0; i < count; i++) {
3440 if (i < nbox) {
3441 int ret = i915_emit_box(dev, cliprects, i,
3442 exec->DR1, exec->DR4);
3443 if (ret)
3444 return ret;
3447 if (IS_I830(dev) || IS_845G(dev)) {
3448 BEGIN_LP_RING(4);
3449 OUT_RING(MI_BATCH_BUFFER);
3450 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3451 OUT_RING(exec_start + exec_len - 4);
3452 OUT_RING(0);
3453 ADVANCE_LP_RING();
3454 } else {
3455 BEGIN_LP_RING(2);
3456 if (IS_I965G(dev)) {
3457 OUT_RING(MI_BATCH_BUFFER_START |
3458 (2 << 6) |
3459 MI_BATCH_NON_SECURE_I965);
3460 OUT_RING(exec_start);
3461 } else {
3462 OUT_RING(MI_BATCH_BUFFER_START |
3463 (2 << 6));
3464 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3466 ADVANCE_LP_RING();
3470 /* XXX breadcrumb */
3471 return 0;
3474 /* Throttle our rendering by waiting until the ring has completed our requests
3475 * emitted over 20 msec ago.
3477 * Note that if we were to use the current jiffies each time around the loop,
3478 * we wouldn't escape the function with any frames outstanding if the time to
3479 * render a frame was over 20ms.
3481 * This should get us reasonable parallelism between CPU and GPU but also
3482 * relatively low latency when blocking on a particular request to finish.
3484 static int
3485 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3487 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3488 int ret = 0;
3489 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3491 mutex_lock(&dev->struct_mutex);
3492 while (!list_empty(&i915_file_priv->mm.request_list)) {
3493 struct drm_i915_gem_request *request;
3495 request = list_first_entry(&i915_file_priv->mm.request_list,
3496 struct drm_i915_gem_request,
3497 client_list);
3499 if (time_after_eq(request->emitted_jiffies, recent_enough))
3500 break;
3502 ret = i915_wait_request(dev, request->seqno);
3503 if (ret != 0)
3504 break;
3506 mutex_unlock(&dev->struct_mutex);
3508 return ret;
3511 static int
3512 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3513 uint32_t buffer_count,
3514 struct drm_i915_gem_relocation_entry **relocs)
3516 uint32_t reloc_count = 0, reloc_index = 0, i;
3517 int ret;
3519 *relocs = NULL;
3520 for (i = 0; i < buffer_count; i++) {
3521 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3522 return -EINVAL;
3523 reloc_count += exec_list[i].relocation_count;
3526 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3527 if (*relocs == NULL)
3528 return -ENOMEM;
3530 for (i = 0; i < buffer_count; i++) {
3531 struct drm_i915_gem_relocation_entry __user *user_relocs;
3533 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3535 ret = copy_from_user(&(*relocs)[reloc_index],
3536 user_relocs,
3537 exec_list[i].relocation_count *
3538 sizeof(**relocs));
3539 if (ret != 0) {
3540 drm_free_large(*relocs);
3541 *relocs = NULL;
3542 return -EFAULT;
3545 reloc_index += exec_list[i].relocation_count;
3548 return 0;
3551 static int
3552 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3553 uint32_t buffer_count,
3554 struct drm_i915_gem_relocation_entry *relocs)
3556 uint32_t reloc_count = 0, i;
3557 int ret = 0;
3559 for (i = 0; i < buffer_count; i++) {
3560 struct drm_i915_gem_relocation_entry __user *user_relocs;
3561 int unwritten;
3563 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3565 unwritten = copy_to_user(user_relocs,
3566 &relocs[reloc_count],
3567 exec_list[i].relocation_count *
3568 sizeof(*relocs));
3570 if (unwritten) {
3571 ret = -EFAULT;
3572 goto err;
3575 reloc_count += exec_list[i].relocation_count;
3578 err:
3579 drm_free_large(relocs);
3581 return ret;
3584 static int
3585 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3586 uint64_t exec_offset)
3588 uint32_t exec_start, exec_len;
3590 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3591 exec_len = (uint32_t) exec->batch_len;
3593 if ((exec_start | exec_len) & 0x7)
3594 return -EINVAL;
3596 if (!exec_start)
3597 return -EINVAL;
3599 return 0;
3603 i915_gem_execbuffer(struct drm_device *dev, void *data,
3604 struct drm_file *file_priv)
3606 drm_i915_private_t *dev_priv = dev->dev_private;
3607 struct drm_i915_gem_execbuffer *args = data;
3608 struct drm_i915_gem_exec_object *exec_list = NULL;
3609 struct drm_gem_object **object_list = NULL;
3610 struct drm_gem_object *batch_obj;
3611 struct drm_i915_gem_object *obj_priv;
3612 struct drm_clip_rect *cliprects = NULL;
3613 struct drm_i915_gem_relocation_entry *relocs;
3614 int ret, ret2, i, pinned = 0;
3615 uint64_t exec_offset;
3616 uint32_t seqno, flush_domains, reloc_index;
3617 int pin_tries;
3619 #if WATCH_EXEC
3620 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3621 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3622 #endif
3624 if (args->buffer_count < 1) {
3625 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3626 return -EINVAL;
3628 /* Copy in the exec list from userland */
3629 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3630 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
3631 if (exec_list == NULL || object_list == NULL) {
3632 DRM_ERROR("Failed to allocate exec or object list "
3633 "for %d buffers\n",
3634 args->buffer_count);
3635 ret = -ENOMEM;
3636 goto pre_mutex_err;
3638 ret = copy_from_user(exec_list,
3639 (struct drm_i915_relocation_entry __user *)
3640 (uintptr_t) args->buffers_ptr,
3641 sizeof(*exec_list) * args->buffer_count);
3642 if (ret != 0) {
3643 DRM_ERROR("copy %d exec entries failed %d\n",
3644 args->buffer_count, ret);
3645 goto pre_mutex_err;
3648 if (args->num_cliprects != 0) {
3649 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3650 GFP_KERNEL);
3651 if (cliprects == NULL)
3652 goto pre_mutex_err;
3654 ret = copy_from_user(cliprects,
3655 (struct drm_clip_rect __user *)
3656 (uintptr_t) args->cliprects_ptr,
3657 sizeof(*cliprects) * args->num_cliprects);
3658 if (ret != 0) {
3659 DRM_ERROR("copy %d cliprects failed: %d\n",
3660 args->num_cliprects, ret);
3661 goto pre_mutex_err;
3665 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3666 &relocs);
3667 if (ret != 0)
3668 goto pre_mutex_err;
3670 mutex_lock(&dev->struct_mutex);
3672 i915_verify_inactive(dev, __FILE__, __LINE__);
3674 if (atomic_read(&dev_priv->mm.wedged)) {
3675 DRM_ERROR("Execbuf while wedged\n");
3676 mutex_unlock(&dev->struct_mutex);
3677 ret = -EIO;
3678 goto pre_mutex_err;
3681 if (dev_priv->mm.suspended) {
3682 DRM_ERROR("Execbuf while VT-switched.\n");
3683 mutex_unlock(&dev->struct_mutex);
3684 ret = -EBUSY;
3685 goto pre_mutex_err;
3688 /* Look up object handles */
3689 for (i = 0; i < args->buffer_count; i++) {
3690 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3691 exec_list[i].handle);
3692 if (object_list[i] == NULL) {
3693 DRM_ERROR("Invalid object handle %d at index %d\n",
3694 exec_list[i].handle, i);
3695 ret = -EBADF;
3696 goto err;
3699 obj_priv = object_list[i]->driver_private;
3700 if (obj_priv->in_execbuffer) {
3701 DRM_ERROR("Object %p appears more than once in object list\n",
3702 object_list[i]);
3703 ret = -EBADF;
3704 goto err;
3706 obj_priv->in_execbuffer = true;
3709 /* Pin and relocate */
3710 for (pin_tries = 0; ; pin_tries++) {
3711 ret = 0;
3712 reloc_index = 0;
3714 for (i = 0; i < args->buffer_count; i++) {
3715 object_list[i]->pending_read_domains = 0;
3716 object_list[i]->pending_write_domain = 0;
3717 ret = i915_gem_object_pin_and_relocate(object_list[i],
3718 file_priv,
3719 &exec_list[i],
3720 &relocs[reloc_index]);
3721 if (ret)
3722 break;
3723 pinned = i + 1;
3724 reloc_index += exec_list[i].relocation_count;
3726 /* success */
3727 if (ret == 0)
3728 break;
3730 /* error other than GTT full, or we've already tried again */
3731 if (ret != -ENOSPC || pin_tries >= 1) {
3732 if (ret != -ERESTARTSYS) {
3733 unsigned long long total_size = 0;
3734 for (i = 0; i < args->buffer_count; i++)
3735 total_size += object_list[i]->size;
3736 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3737 pinned+1, args->buffer_count,
3738 total_size, ret);
3739 DRM_ERROR("%d objects [%d pinned], "
3740 "%d object bytes [%d pinned], "
3741 "%d/%d gtt bytes\n",
3742 atomic_read(&dev->object_count),
3743 atomic_read(&dev->pin_count),
3744 atomic_read(&dev->object_memory),
3745 atomic_read(&dev->pin_memory),
3746 atomic_read(&dev->gtt_memory),
3747 dev->gtt_total);
3749 goto err;
3752 /* unpin all of our buffers */
3753 for (i = 0; i < pinned; i++)
3754 i915_gem_object_unpin(object_list[i]);
3755 pinned = 0;
3757 /* evict everyone we can from the aperture */
3758 ret = i915_gem_evict_everything(dev);
3759 if (ret && ret != -ENOSPC)
3760 goto err;
3763 /* Set the pending read domains for the batch buffer to COMMAND */
3764 batch_obj = object_list[args->buffer_count-1];
3765 if (batch_obj->pending_write_domain) {
3766 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3767 ret = -EINVAL;
3768 goto err;
3770 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3772 /* Sanity check the batch buffer, prior to moving objects */
3773 exec_offset = exec_list[args->buffer_count - 1].offset;
3774 ret = i915_gem_check_execbuffer (args, exec_offset);
3775 if (ret != 0) {
3776 DRM_ERROR("execbuf with invalid offset/length\n");
3777 goto err;
3780 i915_verify_inactive(dev, __FILE__, __LINE__);
3782 /* Zero the global flush/invalidate flags. These
3783 * will be modified as new domains are computed
3784 * for each object
3786 dev->invalidate_domains = 0;
3787 dev->flush_domains = 0;
3789 for (i = 0; i < args->buffer_count; i++) {
3790 struct drm_gem_object *obj = object_list[i];
3792 /* Compute new gpu domains and update invalidate/flush */
3793 i915_gem_object_set_to_gpu_domain(obj);
3796 i915_verify_inactive(dev, __FILE__, __LINE__);
3798 if (dev->invalidate_domains | dev->flush_domains) {
3799 #if WATCH_EXEC
3800 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3801 __func__,
3802 dev->invalidate_domains,
3803 dev->flush_domains);
3804 #endif
3805 i915_gem_flush(dev,
3806 dev->invalidate_domains,
3807 dev->flush_domains);
3808 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
3809 (void)i915_add_request(dev, file_priv,
3810 dev->flush_domains);
3813 for (i = 0; i < args->buffer_count; i++) {
3814 struct drm_gem_object *obj = object_list[i];
3815 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3816 uint32_t old_write_domain = obj->write_domain;
3818 obj->write_domain = obj->pending_write_domain;
3819 if (obj->write_domain)
3820 list_move_tail(&obj_priv->gpu_write_list,
3821 &dev_priv->mm.gpu_write_list);
3822 else
3823 list_del_init(&obj_priv->gpu_write_list);
3825 trace_i915_gem_object_change_domain(obj,
3826 obj->read_domains,
3827 old_write_domain);
3830 i915_verify_inactive(dev, __FILE__, __LINE__);
3832 #if WATCH_COHERENCY
3833 for (i = 0; i < args->buffer_count; i++) {
3834 i915_gem_object_check_coherency(object_list[i],
3835 exec_list[i].handle);
3837 #endif
3839 #if WATCH_EXEC
3840 i915_gem_dump_object(batch_obj,
3841 args->batch_len,
3842 __func__,
3843 ~0);
3844 #endif
3846 /* Exec the batchbuffer */
3847 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3848 if (ret) {
3849 DRM_ERROR("dispatch failed %d\n", ret);
3850 goto err;
3854 * Ensure that the commands in the batch buffer are
3855 * finished before the interrupt fires
3857 flush_domains = i915_retire_commands(dev);
3859 i915_verify_inactive(dev, __FILE__, __LINE__);
3862 * Get a seqno representing the execution of the current buffer,
3863 * which we can wait on. We would like to mitigate these interrupts,
3864 * likely by only creating seqnos occasionally (so that we have
3865 * *some* interrupts representing completion of buffers that we can
3866 * wait on when trying to clear up gtt space).
3868 seqno = i915_add_request(dev, file_priv, flush_domains);
3869 BUG_ON(seqno == 0);
3870 for (i = 0; i < args->buffer_count; i++) {
3871 struct drm_gem_object *obj = object_list[i];
3873 i915_gem_object_move_to_active(obj, seqno);
3874 #if WATCH_LRU
3875 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3876 #endif
3878 #if WATCH_LRU
3879 i915_dump_lru(dev, __func__);
3880 #endif
3882 i915_verify_inactive(dev, __FILE__, __LINE__);
3884 err:
3885 for (i = 0; i < pinned; i++)
3886 i915_gem_object_unpin(object_list[i]);
3888 for (i = 0; i < args->buffer_count; i++) {
3889 if (object_list[i]) {
3890 obj_priv = object_list[i]->driver_private;
3891 obj_priv->in_execbuffer = false;
3893 drm_gem_object_unreference(object_list[i]);
3896 mutex_unlock(&dev->struct_mutex);
3898 if (!ret) {
3899 /* Copy the new buffer offsets back to the user's exec list. */
3900 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3901 (uintptr_t) args->buffers_ptr,
3902 exec_list,
3903 sizeof(*exec_list) * args->buffer_count);
3904 if (ret) {
3905 ret = -EFAULT;
3906 DRM_ERROR("failed to copy %d exec entries "
3907 "back to user (%d)\n",
3908 args->buffer_count, ret);
3912 /* Copy the updated relocations out regardless of current error
3913 * state. Failure to update the relocs would mean that the next
3914 * time userland calls execbuf, it would do so with presumed offset
3915 * state that didn't match the actual object state.
3917 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3918 relocs);
3919 if (ret2 != 0) {
3920 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3922 if (ret == 0)
3923 ret = ret2;
3926 pre_mutex_err:
3927 drm_free_large(object_list);
3928 drm_free_large(exec_list);
3929 kfree(cliprects);
3931 return ret;
3935 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3937 struct drm_device *dev = obj->dev;
3938 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3939 int ret;
3941 i915_verify_inactive(dev, __FILE__, __LINE__);
3942 if (obj_priv->gtt_space == NULL) {
3943 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3944 if (ret)
3945 return ret;
3948 * Pre-965 chips need a fence register set up in order to
3949 * properly handle tiled surfaces.
3951 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
3952 ret = i915_gem_object_get_fence_reg(obj);
3953 if (ret != 0) {
3954 if (ret != -EBUSY && ret != -ERESTARTSYS)
3955 DRM_ERROR("Failure to install fence: %d\n",
3956 ret);
3957 return ret;
3960 obj_priv->pin_count++;
3962 /* If the object is not active and not pending a flush,
3963 * remove it from the inactive list
3965 if (obj_priv->pin_count == 1) {
3966 atomic_inc(&dev->pin_count);
3967 atomic_add(obj->size, &dev->pin_memory);
3968 if (!obj_priv->active &&
3969 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
3970 !list_empty(&obj_priv->list))
3971 list_del_init(&obj_priv->list);
3973 i915_verify_inactive(dev, __FILE__, __LINE__);
3975 return 0;
3978 void
3979 i915_gem_object_unpin(struct drm_gem_object *obj)
3981 struct drm_device *dev = obj->dev;
3982 drm_i915_private_t *dev_priv = dev->dev_private;
3983 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3985 i915_verify_inactive(dev, __FILE__, __LINE__);
3986 obj_priv->pin_count--;
3987 BUG_ON(obj_priv->pin_count < 0);
3988 BUG_ON(obj_priv->gtt_space == NULL);
3990 /* If the object is no longer pinned, and is
3991 * neither active nor being flushed, then stick it on
3992 * the inactive list
3994 if (obj_priv->pin_count == 0) {
3995 if (!obj_priv->active &&
3996 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
3997 list_move_tail(&obj_priv->list,
3998 &dev_priv->mm.inactive_list);
3999 atomic_dec(&dev->pin_count);
4000 atomic_sub(obj->size, &dev->pin_memory);
4002 i915_verify_inactive(dev, __FILE__, __LINE__);
4006 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4007 struct drm_file *file_priv)
4009 struct drm_i915_gem_pin *args = data;
4010 struct drm_gem_object *obj;
4011 struct drm_i915_gem_object *obj_priv;
4012 int ret;
4014 mutex_lock(&dev->struct_mutex);
4016 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4017 if (obj == NULL) {
4018 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4019 args->handle);
4020 mutex_unlock(&dev->struct_mutex);
4021 return -EBADF;
4023 obj_priv = obj->driver_private;
4025 if (obj_priv->madv != I915_MADV_WILLNEED) {
4026 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4027 drm_gem_object_unreference(obj);
4028 mutex_unlock(&dev->struct_mutex);
4029 return -EINVAL;
4032 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4033 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4034 args->handle);
4035 drm_gem_object_unreference(obj);
4036 mutex_unlock(&dev->struct_mutex);
4037 return -EINVAL;
4040 obj_priv->user_pin_count++;
4041 obj_priv->pin_filp = file_priv;
4042 if (obj_priv->user_pin_count == 1) {
4043 ret = i915_gem_object_pin(obj, args->alignment);
4044 if (ret != 0) {
4045 drm_gem_object_unreference(obj);
4046 mutex_unlock(&dev->struct_mutex);
4047 return ret;
4051 /* XXX - flush the CPU caches for pinned objects
4052 * as the X server doesn't manage domains yet
4054 i915_gem_object_flush_cpu_write_domain(obj);
4055 args->offset = obj_priv->gtt_offset;
4056 drm_gem_object_unreference(obj);
4057 mutex_unlock(&dev->struct_mutex);
4059 return 0;
4063 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4064 struct drm_file *file_priv)
4066 struct drm_i915_gem_pin *args = data;
4067 struct drm_gem_object *obj;
4068 struct drm_i915_gem_object *obj_priv;
4070 mutex_lock(&dev->struct_mutex);
4072 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4073 if (obj == NULL) {
4074 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4075 args->handle);
4076 mutex_unlock(&dev->struct_mutex);
4077 return -EBADF;
4080 obj_priv = obj->driver_private;
4081 if (obj_priv->pin_filp != file_priv) {
4082 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4083 args->handle);
4084 drm_gem_object_unreference(obj);
4085 mutex_unlock(&dev->struct_mutex);
4086 return -EINVAL;
4088 obj_priv->user_pin_count--;
4089 if (obj_priv->user_pin_count == 0) {
4090 obj_priv->pin_filp = NULL;
4091 i915_gem_object_unpin(obj);
4094 drm_gem_object_unreference(obj);
4095 mutex_unlock(&dev->struct_mutex);
4096 return 0;
4100 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4101 struct drm_file *file_priv)
4103 struct drm_i915_gem_busy *args = data;
4104 struct drm_gem_object *obj;
4105 struct drm_i915_gem_object *obj_priv;
4107 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4108 if (obj == NULL) {
4109 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4110 args->handle);
4111 return -EBADF;
4114 mutex_lock(&dev->struct_mutex);
4115 /* Update the active list for the hardware's current position.
4116 * Otherwise this only updates on a delayed timer or when irqs are
4117 * actually unmasked, and our working set ends up being larger than
4118 * required.
4120 i915_gem_retire_requests(dev);
4122 obj_priv = obj->driver_private;
4123 /* Don't count being on the flushing list against the object being
4124 * done. Otherwise, a buffer left on the flushing list but not getting
4125 * flushed (because nobody's flushing that domain) won't ever return
4126 * unbusy and get reused by libdrm's bo cache. The other expected
4127 * consumer of this interface, OpenGL's occlusion queries, also specs
4128 * that the objects get unbusy "eventually" without any interference.
4130 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4132 drm_gem_object_unreference(obj);
4133 mutex_unlock(&dev->struct_mutex);
4134 return 0;
4138 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4139 struct drm_file *file_priv)
4141 return i915_gem_ring_throttle(dev, file_priv);
4145 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4146 struct drm_file *file_priv)
4148 struct drm_i915_gem_madvise *args = data;
4149 struct drm_gem_object *obj;
4150 struct drm_i915_gem_object *obj_priv;
4152 switch (args->madv) {
4153 case I915_MADV_DONTNEED:
4154 case I915_MADV_WILLNEED:
4155 break;
4156 default:
4157 return -EINVAL;
4160 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4161 if (obj == NULL) {
4162 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4163 args->handle);
4164 return -EBADF;
4167 mutex_lock(&dev->struct_mutex);
4168 obj_priv = obj->driver_private;
4170 if (obj_priv->pin_count) {
4171 drm_gem_object_unreference(obj);
4172 mutex_unlock(&dev->struct_mutex);
4174 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4175 return -EINVAL;
4178 if (obj_priv->madv != __I915_MADV_PURGED)
4179 obj_priv->madv = args->madv;
4181 /* if the object is no longer bound, discard its backing storage */
4182 if (i915_gem_object_is_purgeable(obj_priv) &&
4183 obj_priv->gtt_space == NULL)
4184 i915_gem_object_truncate(obj);
4186 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4188 drm_gem_object_unreference(obj);
4189 mutex_unlock(&dev->struct_mutex);
4191 return 0;
4194 int i915_gem_init_object(struct drm_gem_object *obj)
4196 struct drm_i915_gem_object *obj_priv;
4198 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4199 if (obj_priv == NULL)
4200 return -ENOMEM;
4203 * We've just allocated pages from the kernel,
4204 * so they've just been written by the CPU with
4205 * zeros. They'll need to be clflushed before we
4206 * use them with the GPU.
4208 obj->write_domain = I915_GEM_DOMAIN_CPU;
4209 obj->read_domains = I915_GEM_DOMAIN_CPU;
4211 obj_priv->agp_type = AGP_USER_MEMORY;
4213 obj->driver_private = obj_priv;
4214 obj_priv->obj = obj;
4215 obj_priv->fence_reg = I915_FENCE_REG_NONE;
4216 INIT_LIST_HEAD(&obj_priv->list);
4217 INIT_LIST_HEAD(&obj_priv->gpu_write_list);
4218 INIT_LIST_HEAD(&obj_priv->fence_list);
4219 obj_priv->madv = I915_MADV_WILLNEED;
4221 trace_i915_gem_object_create(obj);
4223 return 0;
4226 void i915_gem_free_object(struct drm_gem_object *obj)
4228 struct drm_device *dev = obj->dev;
4229 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4231 trace_i915_gem_object_destroy(obj);
4233 while (obj_priv->pin_count > 0)
4234 i915_gem_object_unpin(obj);
4236 if (obj_priv->phys_obj)
4237 i915_gem_detach_phys_object(dev, obj);
4239 i915_gem_object_unbind(obj);
4241 if (obj_priv->mmap_offset)
4242 i915_gem_free_mmap_offset(obj);
4244 kfree(obj_priv->page_cpu_valid);
4245 kfree(obj_priv->bit_17);
4246 kfree(obj->driver_private);
4249 /** Unbinds all inactive objects. */
4250 static int
4251 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4253 drm_i915_private_t *dev_priv = dev->dev_private;
4255 while (!list_empty(&dev_priv->mm.inactive_list)) {
4256 struct drm_gem_object *obj;
4257 int ret;
4259 obj = list_first_entry(&dev_priv->mm.inactive_list,
4260 struct drm_i915_gem_object,
4261 list)->obj;
4263 ret = i915_gem_object_unbind(obj);
4264 if (ret != 0) {
4265 DRM_ERROR("Error unbinding object: %d\n", ret);
4266 return ret;
4270 return 0;
4274 i915_gem_idle(struct drm_device *dev)
4276 drm_i915_private_t *dev_priv = dev->dev_private;
4277 uint32_t seqno, cur_seqno, last_seqno;
4278 int stuck, ret;
4280 mutex_lock(&dev->struct_mutex);
4282 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4283 mutex_unlock(&dev->struct_mutex);
4284 return 0;
4287 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4288 * We need to replace this with a semaphore, or something.
4290 dev_priv->mm.suspended = 1;
4291 del_timer(&dev_priv->hangcheck_timer);
4293 /* Cancel the retire work handler, wait for it to finish if running
4295 mutex_unlock(&dev->struct_mutex);
4296 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4297 mutex_lock(&dev->struct_mutex);
4299 i915_kernel_lost_context(dev);
4301 /* Flush the GPU along with all non-CPU write domains
4303 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4304 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
4306 if (seqno == 0) {
4307 mutex_unlock(&dev->struct_mutex);
4308 return -ENOMEM;
4311 dev_priv->mm.waiting_gem_seqno = seqno;
4312 last_seqno = 0;
4313 stuck = 0;
4314 for (;;) {
4315 cur_seqno = i915_get_gem_seqno(dev);
4316 if (i915_seqno_passed(cur_seqno, seqno))
4317 break;
4318 if (last_seqno == cur_seqno) {
4319 if (stuck++ > 100) {
4320 DRM_ERROR("hardware wedged\n");
4321 atomic_set(&dev_priv->mm.wedged, 1);
4322 DRM_WAKEUP(&dev_priv->irq_queue);
4323 break;
4326 msleep(10);
4327 last_seqno = cur_seqno;
4329 dev_priv->mm.waiting_gem_seqno = 0;
4331 i915_gem_retire_requests(dev);
4333 spin_lock(&dev_priv->mm.active_list_lock);
4334 if (!atomic_read(&dev_priv->mm.wedged)) {
4335 /* Active and flushing should now be empty as we've
4336 * waited for a sequence higher than any pending execbuffer
4338 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4339 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4340 /* Request should now be empty as we've also waited
4341 * for the last request in the list
4343 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4346 /* Empty the active and flushing lists to inactive. If there's
4347 * anything left at this point, it means that we're wedged and
4348 * nothing good's going to happen by leaving them there. So strip
4349 * the GPU domains and just stuff them onto inactive.
4351 while (!list_empty(&dev_priv->mm.active_list)) {
4352 struct drm_gem_object *obj;
4353 uint32_t old_write_domain;
4355 obj = list_first_entry(&dev_priv->mm.active_list,
4356 struct drm_i915_gem_object,
4357 list)->obj;
4358 old_write_domain = obj->write_domain;
4359 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4360 i915_gem_object_move_to_inactive(obj);
4362 trace_i915_gem_object_change_domain(obj,
4363 obj->read_domains,
4364 old_write_domain);
4366 spin_unlock(&dev_priv->mm.active_list_lock);
4368 while (!list_empty(&dev_priv->mm.flushing_list)) {
4369 struct drm_gem_object *obj;
4370 uint32_t old_write_domain;
4372 obj = list_first_entry(&dev_priv->mm.flushing_list,
4373 struct drm_i915_gem_object,
4374 list)->obj;
4375 old_write_domain = obj->write_domain;
4376 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4377 i915_gem_object_move_to_inactive(obj);
4379 trace_i915_gem_object_change_domain(obj,
4380 obj->read_domains,
4381 old_write_domain);
4385 /* Move all inactive buffers out of the GTT. */
4386 ret = i915_gem_evict_from_inactive_list(dev);
4387 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
4388 if (ret) {
4389 mutex_unlock(&dev->struct_mutex);
4390 return ret;
4393 i915_gem_cleanup_ringbuffer(dev);
4394 mutex_unlock(&dev->struct_mutex);
4396 return 0;
4399 static int
4400 i915_gem_init_hws(struct drm_device *dev)
4402 drm_i915_private_t *dev_priv = dev->dev_private;
4403 struct drm_gem_object *obj;
4404 struct drm_i915_gem_object *obj_priv;
4405 int ret;
4407 /* If we need a physical address for the status page, it's already
4408 * initialized at driver load time.
4410 if (!I915_NEED_GFX_HWS(dev))
4411 return 0;
4413 obj = drm_gem_object_alloc(dev, 4096);
4414 if (obj == NULL) {
4415 DRM_ERROR("Failed to allocate status page\n");
4416 return -ENOMEM;
4418 obj_priv = obj->driver_private;
4419 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4421 ret = i915_gem_object_pin(obj, 4096);
4422 if (ret != 0) {
4423 drm_gem_object_unreference(obj);
4424 return ret;
4427 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4429 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4430 if (dev_priv->hw_status_page == NULL) {
4431 DRM_ERROR("Failed to map status page.\n");
4432 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4433 i915_gem_object_unpin(obj);
4434 drm_gem_object_unreference(obj);
4435 return -EINVAL;
4437 dev_priv->hws_obj = obj;
4438 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4439 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4440 I915_READ(HWS_PGA); /* posting read */
4441 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4443 return 0;
4446 static void
4447 i915_gem_cleanup_hws(struct drm_device *dev)
4449 drm_i915_private_t *dev_priv = dev->dev_private;
4450 struct drm_gem_object *obj;
4451 struct drm_i915_gem_object *obj_priv;
4453 if (dev_priv->hws_obj == NULL)
4454 return;
4456 obj = dev_priv->hws_obj;
4457 obj_priv = obj->driver_private;
4459 kunmap(obj_priv->pages[0]);
4460 i915_gem_object_unpin(obj);
4461 drm_gem_object_unreference(obj);
4462 dev_priv->hws_obj = NULL;
4464 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4465 dev_priv->hw_status_page = NULL;
4467 /* Write high address into HWS_PGA when disabling. */
4468 I915_WRITE(HWS_PGA, 0x1ffff000);
4472 i915_gem_init_ringbuffer(struct drm_device *dev)
4474 drm_i915_private_t *dev_priv = dev->dev_private;
4475 struct drm_gem_object *obj;
4476 struct drm_i915_gem_object *obj_priv;
4477 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4478 int ret;
4479 u32 head;
4481 ret = i915_gem_init_hws(dev);
4482 if (ret != 0)
4483 return ret;
4485 obj = drm_gem_object_alloc(dev, 128 * 1024);
4486 if (obj == NULL) {
4487 DRM_ERROR("Failed to allocate ringbuffer\n");
4488 i915_gem_cleanup_hws(dev);
4489 return -ENOMEM;
4491 obj_priv = obj->driver_private;
4493 ret = i915_gem_object_pin(obj, 4096);
4494 if (ret != 0) {
4495 drm_gem_object_unreference(obj);
4496 i915_gem_cleanup_hws(dev);
4497 return ret;
4500 /* Set up the kernel mapping for the ring. */
4501 ring->Size = obj->size;
4503 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4504 ring->map.size = obj->size;
4505 ring->map.type = 0;
4506 ring->map.flags = 0;
4507 ring->map.mtrr = 0;
4509 drm_core_ioremap_wc(&ring->map, dev);
4510 if (ring->map.handle == NULL) {
4511 DRM_ERROR("Failed to map ringbuffer.\n");
4512 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4513 i915_gem_object_unpin(obj);
4514 drm_gem_object_unreference(obj);
4515 i915_gem_cleanup_hws(dev);
4516 return -EINVAL;
4518 ring->ring_obj = obj;
4519 ring->virtual_start = ring->map.handle;
4521 /* Stop the ring if it's running. */
4522 I915_WRITE(PRB0_CTL, 0);
4523 I915_WRITE(PRB0_TAIL, 0);
4524 I915_WRITE(PRB0_HEAD, 0);
4526 /* Initialize the ring. */
4527 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4528 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4530 /* G45 ring initialization fails to reset head to zero */
4531 if (head != 0) {
4532 DRM_ERROR("Ring head not reset to zero "
4533 "ctl %08x head %08x tail %08x start %08x\n",
4534 I915_READ(PRB0_CTL),
4535 I915_READ(PRB0_HEAD),
4536 I915_READ(PRB0_TAIL),
4537 I915_READ(PRB0_START));
4538 I915_WRITE(PRB0_HEAD, 0);
4540 DRM_ERROR("Ring head forced to zero "
4541 "ctl %08x head %08x tail %08x start %08x\n",
4542 I915_READ(PRB0_CTL),
4543 I915_READ(PRB0_HEAD),
4544 I915_READ(PRB0_TAIL),
4545 I915_READ(PRB0_START));
4548 I915_WRITE(PRB0_CTL,
4549 ((obj->size - 4096) & RING_NR_PAGES) |
4550 RING_NO_REPORT |
4551 RING_VALID);
4553 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4555 /* If the head is still not zero, the ring is dead */
4556 if (head != 0) {
4557 DRM_ERROR("Ring initialization failed "
4558 "ctl %08x head %08x tail %08x start %08x\n",
4559 I915_READ(PRB0_CTL),
4560 I915_READ(PRB0_HEAD),
4561 I915_READ(PRB0_TAIL),
4562 I915_READ(PRB0_START));
4563 return -EIO;
4566 /* Update our cache of the ring state */
4567 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4568 i915_kernel_lost_context(dev);
4569 else {
4570 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4571 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4572 ring->space = ring->head - (ring->tail + 8);
4573 if (ring->space < 0)
4574 ring->space += ring->Size;
4577 return 0;
4580 void
4581 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4583 drm_i915_private_t *dev_priv = dev->dev_private;
4585 if (dev_priv->ring.ring_obj == NULL)
4586 return;
4588 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4590 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4591 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4592 dev_priv->ring.ring_obj = NULL;
4593 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4595 i915_gem_cleanup_hws(dev);
4599 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4600 struct drm_file *file_priv)
4602 drm_i915_private_t *dev_priv = dev->dev_private;
4603 int ret;
4605 if (drm_core_check_feature(dev, DRIVER_MODESET))
4606 return 0;
4608 if (atomic_read(&dev_priv->mm.wedged)) {
4609 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4610 atomic_set(&dev_priv->mm.wedged, 0);
4613 mutex_lock(&dev->struct_mutex);
4614 dev_priv->mm.suspended = 0;
4616 ret = i915_gem_init_ringbuffer(dev);
4617 if (ret != 0) {
4618 mutex_unlock(&dev->struct_mutex);
4619 return ret;
4622 spin_lock(&dev_priv->mm.active_list_lock);
4623 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4624 spin_unlock(&dev_priv->mm.active_list_lock);
4626 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4627 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4628 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4629 mutex_unlock(&dev->struct_mutex);
4631 drm_irq_install(dev);
4633 return 0;
4637 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4638 struct drm_file *file_priv)
4640 if (drm_core_check_feature(dev, DRIVER_MODESET))
4641 return 0;
4643 drm_irq_uninstall(dev);
4644 return i915_gem_idle(dev);
4647 void
4648 i915_gem_lastclose(struct drm_device *dev)
4650 int ret;
4652 if (drm_core_check_feature(dev, DRIVER_MODESET))
4653 return;
4655 ret = i915_gem_idle(dev);
4656 if (ret)
4657 DRM_ERROR("failed to idle hardware: %d\n", ret);
4660 void
4661 i915_gem_load(struct drm_device *dev)
4663 int i;
4664 drm_i915_private_t *dev_priv = dev->dev_private;
4666 spin_lock_init(&dev_priv->mm.active_list_lock);
4667 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4668 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4669 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4670 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4671 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4672 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4673 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4674 i915_gem_retire_work_handler);
4675 dev_priv->mm.next_gem_seqno = 1;
4677 spin_lock(&shrink_list_lock);
4678 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4679 spin_unlock(&shrink_list_lock);
4681 /* Old X drivers will take 0-2 for front, back, depth buffers */
4682 dev_priv->fence_reg_start = 3;
4684 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4685 dev_priv->num_fence_regs = 16;
4686 else
4687 dev_priv->num_fence_regs = 8;
4689 /* Initialize fence registers to zero */
4690 if (IS_I965G(dev)) {
4691 for (i = 0; i < 16; i++)
4692 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4693 } else {
4694 for (i = 0; i < 8; i++)
4695 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4696 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4697 for (i = 0; i < 8; i++)
4698 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4701 i915_gem_detect_bit_6_swizzle(dev);
4705 * Create a physically contiguous memory object for this object
4706 * e.g. for cursor + overlay regs
4708 int i915_gem_init_phys_object(struct drm_device *dev,
4709 int id, int size)
4711 drm_i915_private_t *dev_priv = dev->dev_private;
4712 struct drm_i915_gem_phys_object *phys_obj;
4713 int ret;
4715 if (dev_priv->mm.phys_objs[id - 1] || !size)
4716 return 0;
4718 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4719 if (!phys_obj)
4720 return -ENOMEM;
4722 phys_obj->id = id;
4724 phys_obj->handle = drm_pci_alloc(dev, size, 0);
4725 if (!phys_obj->handle) {
4726 ret = -ENOMEM;
4727 goto kfree_obj;
4729 #ifdef CONFIG_X86
4730 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4731 #endif
4733 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4735 return 0;
4736 kfree_obj:
4737 kfree(phys_obj);
4738 return ret;
4741 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4743 drm_i915_private_t *dev_priv = dev->dev_private;
4744 struct drm_i915_gem_phys_object *phys_obj;
4746 if (!dev_priv->mm.phys_objs[id - 1])
4747 return;
4749 phys_obj = dev_priv->mm.phys_objs[id - 1];
4750 if (phys_obj->cur_obj) {
4751 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4754 #ifdef CONFIG_X86
4755 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4756 #endif
4757 drm_pci_free(dev, phys_obj->handle);
4758 kfree(phys_obj);
4759 dev_priv->mm.phys_objs[id - 1] = NULL;
4762 void i915_gem_free_all_phys_object(struct drm_device *dev)
4764 int i;
4766 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4767 i915_gem_free_phys_object(dev, i);
4770 void i915_gem_detach_phys_object(struct drm_device *dev,
4771 struct drm_gem_object *obj)
4773 struct drm_i915_gem_object *obj_priv;
4774 int i;
4775 int ret;
4776 int page_count;
4778 obj_priv = obj->driver_private;
4779 if (!obj_priv->phys_obj)
4780 return;
4782 ret = i915_gem_object_get_pages(obj, 0);
4783 if (ret)
4784 goto out;
4786 page_count = obj->size / PAGE_SIZE;
4788 for (i = 0; i < page_count; i++) {
4789 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4790 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4792 memcpy(dst, src, PAGE_SIZE);
4793 kunmap_atomic(dst, KM_USER0);
4795 drm_clflush_pages(obj_priv->pages, page_count);
4796 drm_agp_chipset_flush(dev);
4798 i915_gem_object_put_pages(obj);
4799 out:
4800 obj_priv->phys_obj->cur_obj = NULL;
4801 obj_priv->phys_obj = NULL;
4805 i915_gem_attach_phys_object(struct drm_device *dev,
4806 struct drm_gem_object *obj, int id)
4808 drm_i915_private_t *dev_priv = dev->dev_private;
4809 struct drm_i915_gem_object *obj_priv;
4810 int ret = 0;
4811 int page_count;
4812 int i;
4814 if (id > I915_MAX_PHYS_OBJECT)
4815 return -EINVAL;
4817 obj_priv = obj->driver_private;
4819 if (obj_priv->phys_obj) {
4820 if (obj_priv->phys_obj->id == id)
4821 return 0;
4822 i915_gem_detach_phys_object(dev, obj);
4826 /* create a new object */
4827 if (!dev_priv->mm.phys_objs[id - 1]) {
4828 ret = i915_gem_init_phys_object(dev, id,
4829 obj->size);
4830 if (ret) {
4831 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4832 goto out;
4836 /* bind to the object */
4837 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4838 obj_priv->phys_obj->cur_obj = obj;
4840 ret = i915_gem_object_get_pages(obj, 0);
4841 if (ret) {
4842 DRM_ERROR("failed to get page list\n");
4843 goto out;
4846 page_count = obj->size / PAGE_SIZE;
4848 for (i = 0; i < page_count; i++) {
4849 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4850 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4852 memcpy(dst, src, PAGE_SIZE);
4853 kunmap_atomic(src, KM_USER0);
4856 i915_gem_object_put_pages(obj);
4858 return 0;
4859 out:
4860 return ret;
4863 static int
4864 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4865 struct drm_i915_gem_pwrite *args,
4866 struct drm_file *file_priv)
4868 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4869 void *obj_addr;
4870 int ret;
4871 char __user *user_data;
4873 user_data = (char __user *) (uintptr_t) args->data_ptr;
4874 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4876 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4877 ret = copy_from_user(obj_addr, user_data, args->size);
4878 if (ret)
4879 return -EFAULT;
4881 drm_agp_chipset_flush(dev);
4882 return 0;
4885 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4887 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4889 /* Clean up our request list when the client is going away, so that
4890 * later retire_requests won't dereference our soon-to-be-gone
4891 * file_priv.
4893 mutex_lock(&dev->struct_mutex);
4894 while (!list_empty(&i915_file_priv->mm.request_list))
4895 list_del_init(i915_file_priv->mm.request_list.next);
4896 mutex_unlock(&dev->struct_mutex);
4899 static int
4900 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4902 drm_i915_private_t *dev_priv, *next_dev;
4903 struct drm_i915_gem_object *obj_priv, *next_obj;
4904 int cnt = 0;
4905 int would_deadlock = 1;
4907 /* "fast-path" to count number of available objects */
4908 if (nr_to_scan == 0) {
4909 spin_lock(&shrink_list_lock);
4910 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4911 struct drm_device *dev = dev_priv->dev;
4913 if (mutex_trylock(&dev->struct_mutex)) {
4914 list_for_each_entry(obj_priv,
4915 &dev_priv->mm.inactive_list,
4916 list)
4917 cnt++;
4918 mutex_unlock(&dev->struct_mutex);
4921 spin_unlock(&shrink_list_lock);
4923 return (cnt / 100) * sysctl_vfs_cache_pressure;
4926 spin_lock(&shrink_list_lock);
4928 /* first scan for clean buffers */
4929 list_for_each_entry_safe(dev_priv, next_dev,
4930 &shrink_list, mm.shrink_list) {
4931 struct drm_device *dev = dev_priv->dev;
4933 if (! mutex_trylock(&dev->struct_mutex))
4934 continue;
4936 spin_unlock(&shrink_list_lock);
4938 i915_gem_retire_requests(dev);
4940 list_for_each_entry_safe(obj_priv, next_obj,
4941 &dev_priv->mm.inactive_list,
4942 list) {
4943 if (i915_gem_object_is_purgeable(obj_priv)) {
4944 i915_gem_object_unbind(obj_priv->obj);
4945 if (--nr_to_scan <= 0)
4946 break;
4950 spin_lock(&shrink_list_lock);
4951 mutex_unlock(&dev->struct_mutex);
4953 would_deadlock = 0;
4955 if (nr_to_scan <= 0)
4956 break;
4959 /* second pass, evict/count anything still on the inactive list */
4960 list_for_each_entry_safe(dev_priv, next_dev,
4961 &shrink_list, mm.shrink_list) {
4962 struct drm_device *dev = dev_priv->dev;
4964 if (! mutex_trylock(&dev->struct_mutex))
4965 continue;
4967 spin_unlock(&shrink_list_lock);
4969 list_for_each_entry_safe(obj_priv, next_obj,
4970 &dev_priv->mm.inactive_list,
4971 list) {
4972 if (nr_to_scan > 0) {
4973 i915_gem_object_unbind(obj_priv->obj);
4974 nr_to_scan--;
4975 } else
4976 cnt++;
4979 spin_lock(&shrink_list_lock);
4980 mutex_unlock(&dev->struct_mutex);
4982 would_deadlock = 0;
4985 spin_unlock(&shrink_list_lock);
4987 if (would_deadlock)
4988 return -1;
4989 else if (cnt > 0)
4990 return (cnt / 100) * sysctl_vfs_cache_pressure;
4991 else
4992 return 0;
4995 static struct shrinker shrinker = {
4996 .shrink = i915_gem_shrink,
4997 .seeks = DEFAULT_SEEKS,
5000 __init void
5001 i915_gem_shrinker_init(void)
5003 register_shrinker(&shrinker);
5006 __exit void
5007 i915_gem_shrinker_exit(void)
5009 unregister_shrinker(&shrinker);