2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
52 #define WAIT_FOR_BBP(__dev, __reg) \
53 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54 #define WAIT_FOR_RF(__dev, __reg) \
55 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
57 static void rt2400pci_bbp_write(struct rt2x00_dev
*rt2x00dev
,
58 const unsigned int word
, const u8 value
)
62 mutex_lock(&rt2x00dev
->csr_mutex
);
65 * Wait until the BBP becomes available, afterwards we
66 * can safely write the new data into the register.
68 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
70 rt2x00_set_field32(®
, BBPCSR_VALUE
, value
);
71 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
72 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
73 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 1);
75 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
78 mutex_unlock(&rt2x00dev
->csr_mutex
);
81 static void rt2400pci_bbp_read(struct rt2x00_dev
*rt2x00dev
,
82 const unsigned int word
, u8
*value
)
86 mutex_lock(&rt2x00dev
->csr_mutex
);
89 * Wait until the BBP becomes available, afterwards we
90 * can safely write the read request into the register.
91 * After the data has been written, we wait until hardware
92 * returns the correct value, if at any time the register
93 * doesn't become available in time, reg will be 0xffffffff
94 * which means we return 0xff to the caller.
96 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
98 rt2x00_set_field32(®
, BBPCSR_REGNUM
, word
);
99 rt2x00_set_field32(®
, BBPCSR_BUSY
, 1);
100 rt2x00_set_field32(®
, BBPCSR_WRITE_CONTROL
, 0);
102 rt2x00pci_register_write(rt2x00dev
, BBPCSR
, reg
);
104 WAIT_FOR_BBP(rt2x00dev
, ®
);
107 *value
= rt2x00_get_field32(reg
, BBPCSR_VALUE
);
109 mutex_unlock(&rt2x00dev
->csr_mutex
);
112 static void rt2400pci_rf_write(struct rt2x00_dev
*rt2x00dev
,
113 const unsigned int word
, const u32 value
)
117 mutex_lock(&rt2x00dev
->csr_mutex
);
120 * Wait until the RF becomes available, afterwards we
121 * can safely write the new data into the register.
123 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
125 rt2x00_set_field32(®
, RFCSR_VALUE
, value
);
126 rt2x00_set_field32(®
, RFCSR_NUMBER_OF_BITS
, 20);
127 rt2x00_set_field32(®
, RFCSR_IF_SELECT
, 0);
128 rt2x00_set_field32(®
, RFCSR_BUSY
, 1);
130 rt2x00pci_register_write(rt2x00dev
, RFCSR
, reg
);
131 rt2x00_rf_write(rt2x00dev
, word
, value
);
134 mutex_unlock(&rt2x00dev
->csr_mutex
);
137 static void rt2400pci_eepromregister_read(struct eeprom_93cx6
*eeprom
)
139 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
142 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
144 eeprom
->reg_data_in
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_IN
);
145 eeprom
->reg_data_out
= !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_OUT
);
146 eeprom
->reg_data_clock
=
147 !!rt2x00_get_field32(reg
, CSR21_EEPROM_DATA_CLOCK
);
148 eeprom
->reg_chip_select
=
149 !!rt2x00_get_field32(reg
, CSR21_EEPROM_CHIP_SELECT
);
152 static void rt2400pci_eepromregister_write(struct eeprom_93cx6
*eeprom
)
154 struct rt2x00_dev
*rt2x00dev
= eeprom
->data
;
157 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_IN
, !!eeprom
->reg_data_in
);
158 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_OUT
, !!eeprom
->reg_data_out
);
159 rt2x00_set_field32(®
, CSR21_EEPROM_DATA_CLOCK
,
160 !!eeprom
->reg_data_clock
);
161 rt2x00_set_field32(®
, CSR21_EEPROM_CHIP_SELECT
,
162 !!eeprom
->reg_chip_select
);
164 rt2x00pci_register_write(rt2x00dev
, CSR21
, reg
);
167 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
168 static const struct rt2x00debug rt2400pci_rt2x00debug
= {
169 .owner
= THIS_MODULE
,
171 .read
= rt2x00pci_register_read
,
172 .write
= rt2x00pci_register_write
,
173 .flags
= RT2X00DEBUGFS_OFFSET
,
174 .word_base
= CSR_REG_BASE
,
175 .word_size
= sizeof(u32
),
176 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
179 .read
= rt2x00_eeprom_read
,
180 .write
= rt2x00_eeprom_write
,
181 .word_base
= EEPROM_BASE
,
182 .word_size
= sizeof(u16
),
183 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
186 .read
= rt2400pci_bbp_read
,
187 .write
= rt2400pci_bbp_write
,
188 .word_base
= BBP_BASE
,
189 .word_size
= sizeof(u8
),
190 .word_count
= BBP_SIZE
/ sizeof(u8
),
193 .read
= rt2x00_rf_read
,
194 .write
= rt2400pci_rf_write
,
195 .word_base
= RF_BASE
,
196 .word_size
= sizeof(u32
),
197 .word_count
= RF_SIZE
/ sizeof(u32
),
200 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
202 static int rt2400pci_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
206 rt2x00pci_register_read(rt2x00dev
, GPIOCSR
, ®
);
207 return rt2x00_get_field32(reg
, GPIOCSR_BIT0
);
210 #ifdef CONFIG_RT2X00_LIB_LEDS
211 static void rt2400pci_brightness_set(struct led_classdev
*led_cdev
,
212 enum led_brightness brightness
)
214 struct rt2x00_led
*led
=
215 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
216 unsigned int enabled
= brightness
!= LED_OFF
;
219 rt2x00pci_register_read(led
->rt2x00dev
, LEDCSR
, ®
);
221 if (led
->type
== LED_TYPE_RADIO
|| led
->type
== LED_TYPE_ASSOC
)
222 rt2x00_set_field32(®
, LEDCSR_LINK
, enabled
);
223 else if (led
->type
== LED_TYPE_ACTIVITY
)
224 rt2x00_set_field32(®
, LEDCSR_ACTIVITY
, enabled
);
226 rt2x00pci_register_write(led
->rt2x00dev
, LEDCSR
, reg
);
229 static int rt2400pci_blink_set(struct led_classdev
*led_cdev
,
230 unsigned long *delay_on
,
231 unsigned long *delay_off
)
233 struct rt2x00_led
*led
=
234 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
237 rt2x00pci_register_read(led
->rt2x00dev
, LEDCSR
, ®
);
238 rt2x00_set_field32(®
, LEDCSR_ON_PERIOD
, *delay_on
);
239 rt2x00_set_field32(®
, LEDCSR_OFF_PERIOD
, *delay_off
);
240 rt2x00pci_register_write(led
->rt2x00dev
, LEDCSR
, reg
);
245 static void rt2400pci_init_led(struct rt2x00_dev
*rt2x00dev
,
246 struct rt2x00_led
*led
,
249 led
->rt2x00dev
= rt2x00dev
;
251 led
->led_dev
.brightness_set
= rt2400pci_brightness_set
;
252 led
->led_dev
.blink_set
= rt2400pci_blink_set
;
253 led
->flags
= LED_INITIALIZED
;
255 #endif /* CONFIG_RT2X00_LIB_LEDS */
258 * Configuration handlers.
260 static void rt2400pci_config_filter(struct rt2x00_dev
*rt2x00dev
,
261 const unsigned int filter_flags
)
266 * Start configuration steps.
267 * Note that the version error will always be dropped
268 * since there is no filter for it at this time.
270 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
271 rt2x00_set_field32(®
, RXCSR0_DROP_CRC
,
272 !(filter_flags
& FIF_FCSFAIL
));
273 rt2x00_set_field32(®
, RXCSR0_DROP_PHYSICAL
,
274 !(filter_flags
& FIF_PLCPFAIL
));
275 rt2x00_set_field32(®
, RXCSR0_DROP_CONTROL
,
276 !(filter_flags
& FIF_CONTROL
));
277 rt2x00_set_field32(®
, RXCSR0_DROP_NOT_TO_ME
,
278 !(filter_flags
& FIF_PROMISC_IN_BSS
));
279 rt2x00_set_field32(®
, RXCSR0_DROP_TODS
,
280 !(filter_flags
& FIF_PROMISC_IN_BSS
) &&
281 !rt2x00dev
->intf_ap_count
);
282 rt2x00_set_field32(®
, RXCSR0_DROP_VERSION_ERROR
, 1);
283 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
286 static void rt2400pci_config_intf(struct rt2x00_dev
*rt2x00dev
,
287 struct rt2x00_intf
*intf
,
288 struct rt2x00intf_conf
*conf
,
289 const unsigned int flags
)
291 unsigned int bcn_preload
;
294 if (flags
& CONFIG_UPDATE_TYPE
) {
296 * Enable beacon config
298 bcn_preload
= PREAMBLE
+ GET_DURATION(IEEE80211_HEADER
, 20);
299 rt2x00pci_register_read(rt2x00dev
, BCNCSR1
, ®
);
300 rt2x00_set_field32(®
, BCNCSR1_PRELOAD
, bcn_preload
);
301 rt2x00pci_register_write(rt2x00dev
, BCNCSR1
, reg
);
304 * Enable synchronisation.
306 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
307 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 1);
308 rt2x00_set_field32(®
, CSR14_TSF_SYNC
, conf
->sync
);
309 rt2x00_set_field32(®
, CSR14_TBCN
, 1);
310 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
313 if (flags
& CONFIG_UPDATE_MAC
)
314 rt2x00pci_register_multiwrite(rt2x00dev
, CSR3
,
315 conf
->mac
, sizeof(conf
->mac
));
317 if (flags
& CONFIG_UPDATE_BSSID
)
318 rt2x00pci_register_multiwrite(rt2x00dev
, CSR5
,
319 conf
->bssid
, sizeof(conf
->bssid
));
322 static void rt2400pci_config_erp(struct rt2x00_dev
*rt2x00dev
,
323 struct rt2x00lib_erp
*erp
)
329 * When short preamble is enabled, we should set bit 0x08
331 preamble_mask
= erp
->short_preamble
<< 3;
333 rt2x00pci_register_read(rt2x00dev
, TXCSR1
, ®
);
334 rt2x00_set_field32(®
, TXCSR1_ACK_TIMEOUT
, 0x1ff);
335 rt2x00_set_field32(®
, TXCSR1_ACK_CONSUME_TIME
, 0x13a);
336 rt2x00_set_field32(®
, TXCSR1_TSF_OFFSET
, IEEE80211_HEADER
);
337 rt2x00_set_field32(®
, TXCSR1_AUTORESPONDER
, 1);
338 rt2x00pci_register_write(rt2x00dev
, TXCSR1
, reg
);
340 rt2x00pci_register_read(rt2x00dev
, ARCSR2
, ®
);
341 rt2x00_set_field32(®
, ARCSR2_SIGNAL
, 0x00);
342 rt2x00_set_field32(®
, ARCSR2_SERVICE
, 0x04);
343 rt2x00_set_field32(®
, ARCSR2_LENGTH
, GET_DURATION(ACK_SIZE
, 10));
344 rt2x00pci_register_write(rt2x00dev
, ARCSR2
, reg
);
346 rt2x00pci_register_read(rt2x00dev
, ARCSR3
, ®
);
347 rt2x00_set_field32(®
, ARCSR3_SIGNAL
, 0x01 | preamble_mask
);
348 rt2x00_set_field32(®
, ARCSR3_SERVICE
, 0x04);
349 rt2x00_set_field32(®
, ARCSR2_LENGTH
, GET_DURATION(ACK_SIZE
, 20));
350 rt2x00pci_register_write(rt2x00dev
, ARCSR3
, reg
);
352 rt2x00pci_register_read(rt2x00dev
, ARCSR4
, ®
);
353 rt2x00_set_field32(®
, ARCSR4_SIGNAL
, 0x02 | preamble_mask
);
354 rt2x00_set_field32(®
, ARCSR4_SERVICE
, 0x04);
355 rt2x00_set_field32(®
, ARCSR2_LENGTH
, GET_DURATION(ACK_SIZE
, 55));
356 rt2x00pci_register_write(rt2x00dev
, ARCSR4
, reg
);
358 rt2x00pci_register_read(rt2x00dev
, ARCSR5
, ®
);
359 rt2x00_set_field32(®
, ARCSR5_SIGNAL
, 0x03 | preamble_mask
);
360 rt2x00_set_field32(®
, ARCSR5_SERVICE
, 0x84);
361 rt2x00_set_field32(®
, ARCSR2_LENGTH
, GET_DURATION(ACK_SIZE
, 110));
362 rt2x00pci_register_write(rt2x00dev
, ARCSR5
, reg
);
364 rt2x00pci_register_write(rt2x00dev
, ARCSR1
, erp
->basic_rates
);
366 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
367 rt2x00_set_field32(®
, CSR11_SLOT_TIME
, erp
->slot_time
);
368 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
370 rt2x00pci_register_read(rt2x00dev
, CSR12
, ®
);
371 rt2x00_set_field32(®
, CSR12_BEACON_INTERVAL
, erp
->beacon_int
* 16);
372 rt2x00_set_field32(®
, CSR12_CFP_MAX_DURATION
, erp
->beacon_int
* 16);
373 rt2x00pci_register_write(rt2x00dev
, CSR12
, reg
);
375 rt2x00pci_register_read(rt2x00dev
, CSR18
, ®
);
376 rt2x00_set_field32(®
, CSR18_SIFS
, erp
->sifs
);
377 rt2x00_set_field32(®
, CSR18_PIFS
, erp
->pifs
);
378 rt2x00pci_register_write(rt2x00dev
, CSR18
, reg
);
380 rt2x00pci_register_read(rt2x00dev
, CSR19
, ®
);
381 rt2x00_set_field32(®
, CSR19_DIFS
, erp
->difs
);
382 rt2x00_set_field32(®
, CSR19_EIFS
, erp
->eifs
);
383 rt2x00pci_register_write(rt2x00dev
, CSR19
, reg
);
386 static void rt2400pci_config_ant(struct rt2x00_dev
*rt2x00dev
,
387 struct antenna_setup
*ant
)
393 * We should never come here because rt2x00lib is supposed
394 * to catch this and send us the correct antenna explicitely.
396 BUG_ON(ant
->rx
== ANTENNA_SW_DIVERSITY
||
397 ant
->tx
== ANTENNA_SW_DIVERSITY
);
399 rt2400pci_bbp_read(rt2x00dev
, 4, &r4
);
400 rt2400pci_bbp_read(rt2x00dev
, 1, &r1
);
403 * Configure the TX antenna.
406 case ANTENNA_HW_DIVERSITY
:
407 rt2x00_set_field8(&r1
, BBP_R1_TX_ANTENNA
, 1);
410 rt2x00_set_field8(&r1
, BBP_R1_TX_ANTENNA
, 0);
414 rt2x00_set_field8(&r1
, BBP_R1_TX_ANTENNA
, 2);
419 * Configure the RX antenna.
422 case ANTENNA_HW_DIVERSITY
:
423 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 1);
426 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 0);
430 rt2x00_set_field8(&r4
, BBP_R4_RX_ANTENNA
, 2);
434 rt2400pci_bbp_write(rt2x00dev
, 4, r4
);
435 rt2400pci_bbp_write(rt2x00dev
, 1, r1
);
438 static void rt2400pci_config_channel(struct rt2x00_dev
*rt2x00dev
,
439 struct rf_channel
*rf
)
442 * Switch on tuning bits.
444 rt2x00_set_field32(&rf
->rf1
, RF1_TUNER
, 1);
445 rt2x00_set_field32(&rf
->rf3
, RF3_TUNER
, 1);
447 rt2400pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
448 rt2400pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
449 rt2400pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
452 * RF2420 chipset don't need any additional actions.
454 if (rt2x00_rf(rt2x00dev
, RF2420
))
458 * For the RT2421 chipsets we need to write an invalid
459 * reference clock rate to activate auto_tune.
460 * After that we set the value back to the correct channel.
462 rt2400pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
463 rt2400pci_rf_write(rt2x00dev
, 2, 0x000c2a32);
464 rt2400pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
468 rt2400pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
469 rt2400pci_rf_write(rt2x00dev
, 2, rf
->rf2
);
470 rt2400pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
475 * Switch off tuning bits.
477 rt2x00_set_field32(&rf
->rf1
, RF1_TUNER
, 0);
478 rt2x00_set_field32(&rf
->rf3
, RF3_TUNER
, 0);
480 rt2400pci_rf_write(rt2x00dev
, 1, rf
->rf1
);
481 rt2400pci_rf_write(rt2x00dev
, 3, rf
->rf3
);
484 * Clear false CRC during channel switch.
486 rt2x00pci_register_read(rt2x00dev
, CNT0
, &rf
->rf1
);
489 static void rt2400pci_config_txpower(struct rt2x00_dev
*rt2x00dev
, int txpower
)
491 rt2400pci_bbp_write(rt2x00dev
, 3, TXPOWER_TO_DEV(txpower
));
494 static void rt2400pci_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
495 struct rt2x00lib_conf
*libconf
)
499 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
500 rt2x00_set_field32(®
, CSR11_LONG_RETRY
,
501 libconf
->conf
->long_frame_max_tx_count
);
502 rt2x00_set_field32(®
, CSR11_SHORT_RETRY
,
503 libconf
->conf
->short_frame_max_tx_count
);
504 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
507 static void rt2400pci_config_ps(struct rt2x00_dev
*rt2x00dev
,
508 struct rt2x00lib_conf
*libconf
)
510 enum dev_state state
=
511 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
512 STATE_SLEEP
: STATE_AWAKE
;
515 if (state
== STATE_SLEEP
) {
516 rt2x00pci_register_read(rt2x00dev
, CSR20
, ®
);
517 rt2x00_set_field32(®
, CSR20_DELAY_AFTER_TBCN
,
518 (rt2x00dev
->beacon_int
- 20) * 16);
519 rt2x00_set_field32(®
, CSR20_TBCN_BEFORE_WAKEUP
,
520 libconf
->conf
->listen_interval
- 1);
522 /* We must first disable autowake before it can be enabled */
523 rt2x00_set_field32(®
, CSR20_AUTOWAKE
, 0);
524 rt2x00pci_register_write(rt2x00dev
, CSR20
, reg
);
526 rt2x00_set_field32(®
, CSR20_AUTOWAKE
, 1);
527 rt2x00pci_register_write(rt2x00dev
, CSR20
, reg
);
529 rt2x00pci_register_read(rt2x00dev
, CSR20
, ®
);
530 rt2x00_set_field32(®
, CSR20_AUTOWAKE
, 0);
531 rt2x00pci_register_write(rt2x00dev
, CSR20
, reg
);
534 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
537 static void rt2400pci_config(struct rt2x00_dev
*rt2x00dev
,
538 struct rt2x00lib_conf
*libconf
,
539 const unsigned int flags
)
541 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
542 rt2400pci_config_channel(rt2x00dev
, &libconf
->rf
);
543 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
544 rt2400pci_config_txpower(rt2x00dev
,
545 libconf
->conf
->power_level
);
546 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
547 rt2400pci_config_retry_limit(rt2x00dev
, libconf
);
548 if (flags
& IEEE80211_CONF_CHANGE_PS
)
549 rt2400pci_config_ps(rt2x00dev
, libconf
);
552 static void rt2400pci_config_cw(struct rt2x00_dev
*rt2x00dev
,
553 const int cw_min
, const int cw_max
)
557 rt2x00pci_register_read(rt2x00dev
, CSR11
, ®
);
558 rt2x00_set_field32(®
, CSR11_CWMIN
, cw_min
);
559 rt2x00_set_field32(®
, CSR11_CWMAX
, cw_max
);
560 rt2x00pci_register_write(rt2x00dev
, CSR11
, reg
);
566 static void rt2400pci_link_stats(struct rt2x00_dev
*rt2x00dev
,
567 struct link_qual
*qual
)
573 * Update FCS error count from register.
575 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
576 qual
->rx_failed
= rt2x00_get_field32(reg
, CNT0_FCS_ERROR
);
579 * Update False CCA count from register.
581 rt2400pci_bbp_read(rt2x00dev
, 39, &bbp
);
582 qual
->false_cca
= bbp
;
585 static inline void rt2400pci_set_vgc(struct rt2x00_dev
*rt2x00dev
,
586 struct link_qual
*qual
, u8 vgc_level
)
588 rt2400pci_bbp_write(rt2x00dev
, 13, vgc_level
);
589 qual
->vgc_level
= vgc_level
;
590 qual
->vgc_level_reg
= vgc_level
;
593 static void rt2400pci_reset_tuner(struct rt2x00_dev
*rt2x00dev
,
594 struct link_qual
*qual
)
596 rt2400pci_set_vgc(rt2x00dev
, qual
, 0x08);
599 static void rt2400pci_link_tuner(struct rt2x00_dev
*rt2x00dev
,
600 struct link_qual
*qual
, const u32 count
)
603 * The link tuner should not run longer then 60 seconds,
604 * and should run once every 2 seconds.
606 if (count
> 60 || !(count
& 1))
610 * Base r13 link tuning on the false cca count.
612 if ((qual
->false_cca
> 512) && (qual
->vgc_level
< 0x20))
613 rt2400pci_set_vgc(rt2x00dev
, qual
, ++qual
->vgc_level
);
614 else if ((qual
->false_cca
< 100) && (qual
->vgc_level
> 0x08))
615 rt2400pci_set_vgc(rt2x00dev
, qual
, --qual
->vgc_level
);
619 * Initialization functions.
621 static bool rt2400pci_get_entry_state(struct queue_entry
*entry
)
623 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
626 if (entry
->queue
->qid
== QID_RX
) {
627 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
629 return rt2x00_get_field32(word
, RXD_W0_OWNER_NIC
);
631 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
633 return (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
634 rt2x00_get_field32(word
, TXD_W0_VALID
));
638 static void rt2400pci_clear_entry(struct queue_entry
*entry
)
640 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
641 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
644 if (entry
->queue
->qid
== QID_RX
) {
645 rt2x00_desc_read(entry_priv
->desc
, 2, &word
);
646 rt2x00_set_field32(&word
, RXD_W2_BUFFER_LENGTH
, entry
->skb
->len
);
647 rt2x00_desc_write(entry_priv
->desc
, 2, word
);
649 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
650 rt2x00_set_field32(&word
, RXD_W1_BUFFER_ADDRESS
, skbdesc
->skb_dma
);
651 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
653 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
654 rt2x00_set_field32(&word
, RXD_W0_OWNER_NIC
, 1);
655 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
657 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
658 rt2x00_set_field32(&word
, TXD_W0_VALID
, 0);
659 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 0);
660 rt2x00_desc_write(entry_priv
->desc
, 0, word
);
664 static int rt2400pci_init_queues(struct rt2x00_dev
*rt2x00dev
)
666 struct queue_entry_priv_pci
*entry_priv
;
670 * Initialize registers.
672 rt2x00pci_register_read(rt2x00dev
, TXCSR2
, ®
);
673 rt2x00_set_field32(®
, TXCSR2_TXD_SIZE
, rt2x00dev
->tx
[0].desc_size
);
674 rt2x00_set_field32(®
, TXCSR2_NUM_TXD
, rt2x00dev
->tx
[1].limit
);
675 rt2x00_set_field32(®
, TXCSR2_NUM_ATIM
, rt2x00dev
->bcn
[1].limit
);
676 rt2x00_set_field32(®
, TXCSR2_NUM_PRIO
, rt2x00dev
->tx
[0].limit
);
677 rt2x00pci_register_write(rt2x00dev
, TXCSR2
, reg
);
679 entry_priv
= rt2x00dev
->tx
[1].entries
[0].priv_data
;
680 rt2x00pci_register_read(rt2x00dev
, TXCSR3
, ®
);
681 rt2x00_set_field32(®
, TXCSR3_TX_RING_REGISTER
,
682 entry_priv
->desc_dma
);
683 rt2x00pci_register_write(rt2x00dev
, TXCSR3
, reg
);
685 entry_priv
= rt2x00dev
->tx
[0].entries
[0].priv_data
;
686 rt2x00pci_register_read(rt2x00dev
, TXCSR5
, ®
);
687 rt2x00_set_field32(®
, TXCSR5_PRIO_RING_REGISTER
,
688 entry_priv
->desc_dma
);
689 rt2x00pci_register_write(rt2x00dev
, TXCSR5
, reg
);
691 entry_priv
= rt2x00dev
->bcn
[1].entries
[0].priv_data
;
692 rt2x00pci_register_read(rt2x00dev
, TXCSR4
, ®
);
693 rt2x00_set_field32(®
, TXCSR4_ATIM_RING_REGISTER
,
694 entry_priv
->desc_dma
);
695 rt2x00pci_register_write(rt2x00dev
, TXCSR4
, reg
);
697 entry_priv
= rt2x00dev
->bcn
[0].entries
[0].priv_data
;
698 rt2x00pci_register_read(rt2x00dev
, TXCSR6
, ®
);
699 rt2x00_set_field32(®
, TXCSR6_BEACON_RING_REGISTER
,
700 entry_priv
->desc_dma
);
701 rt2x00pci_register_write(rt2x00dev
, TXCSR6
, reg
);
703 rt2x00pci_register_read(rt2x00dev
, RXCSR1
, ®
);
704 rt2x00_set_field32(®
, RXCSR1_RXD_SIZE
, rt2x00dev
->rx
->desc_size
);
705 rt2x00_set_field32(®
, RXCSR1_NUM_RXD
, rt2x00dev
->rx
->limit
);
706 rt2x00pci_register_write(rt2x00dev
, RXCSR1
, reg
);
708 entry_priv
= rt2x00dev
->rx
->entries
[0].priv_data
;
709 rt2x00pci_register_read(rt2x00dev
, RXCSR2
, ®
);
710 rt2x00_set_field32(®
, RXCSR2_RX_RING_REGISTER
,
711 entry_priv
->desc_dma
);
712 rt2x00pci_register_write(rt2x00dev
, RXCSR2
, reg
);
717 static int rt2400pci_init_registers(struct rt2x00_dev
*rt2x00dev
)
721 rt2x00pci_register_write(rt2x00dev
, PSCSR0
, 0x00020002);
722 rt2x00pci_register_write(rt2x00dev
, PSCSR1
, 0x00000002);
723 rt2x00pci_register_write(rt2x00dev
, PSCSR2
, 0x00023f20);
724 rt2x00pci_register_write(rt2x00dev
, PSCSR3
, 0x00000002);
726 rt2x00pci_register_read(rt2x00dev
, TIMECSR
, ®
);
727 rt2x00_set_field32(®
, TIMECSR_US_COUNT
, 33);
728 rt2x00_set_field32(®
, TIMECSR_US_64_COUNT
, 63);
729 rt2x00_set_field32(®
, TIMECSR_BEACON_EXPECT
, 0);
730 rt2x00pci_register_write(rt2x00dev
, TIMECSR
, reg
);
732 rt2x00pci_register_read(rt2x00dev
, CSR9
, ®
);
733 rt2x00_set_field32(®
, CSR9_MAX_FRAME_UNIT
,
734 (rt2x00dev
->rx
->data_size
/ 128));
735 rt2x00pci_register_write(rt2x00dev
, CSR9
, reg
);
737 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
738 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 0);
739 rt2x00_set_field32(®
, CSR14_TSF_SYNC
, 0);
740 rt2x00_set_field32(®
, CSR14_TBCN
, 0);
741 rt2x00_set_field32(®
, CSR14_TCFP
, 0);
742 rt2x00_set_field32(®
, CSR14_TATIMW
, 0);
743 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 0);
744 rt2x00_set_field32(®
, CSR14_CFP_COUNT_PRELOAD
, 0);
745 rt2x00_set_field32(®
, CSR14_TBCM_PRELOAD
, 0);
746 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
748 rt2x00pci_register_write(rt2x00dev
, CNT3
, 0x3f080000);
750 rt2x00pci_register_read(rt2x00dev
, ARCSR0
, ®
);
751 rt2x00_set_field32(®
, ARCSR0_AR_BBP_DATA0
, 133);
752 rt2x00_set_field32(®
, ARCSR0_AR_BBP_ID0
, 134);
753 rt2x00_set_field32(®
, ARCSR0_AR_BBP_DATA1
, 136);
754 rt2x00_set_field32(®
, ARCSR0_AR_BBP_ID1
, 135);
755 rt2x00pci_register_write(rt2x00dev
, ARCSR0
, reg
);
757 rt2x00pci_register_read(rt2x00dev
, RXCSR3
, ®
);
758 rt2x00_set_field32(®
, RXCSR3_BBP_ID0
, 3); /* Tx power.*/
759 rt2x00_set_field32(®
, RXCSR3_BBP_ID0_VALID
, 1);
760 rt2x00_set_field32(®
, RXCSR3_BBP_ID1
, 32); /* Signal */
761 rt2x00_set_field32(®
, RXCSR3_BBP_ID1_VALID
, 1);
762 rt2x00_set_field32(®
, RXCSR3_BBP_ID2
, 36); /* Rssi */
763 rt2x00_set_field32(®
, RXCSR3_BBP_ID2_VALID
, 1);
764 rt2x00pci_register_write(rt2x00dev
, RXCSR3
, reg
);
766 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0x3f3b3100);
768 if (rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, STATE_AWAKE
))
771 rt2x00pci_register_write(rt2x00dev
, MACCSR0
, 0x00217223);
772 rt2x00pci_register_write(rt2x00dev
, MACCSR1
, 0x00235518);
774 rt2x00pci_register_read(rt2x00dev
, MACCSR2
, ®
);
775 rt2x00_set_field32(®
, MACCSR2_DELAY
, 64);
776 rt2x00pci_register_write(rt2x00dev
, MACCSR2
, reg
);
778 rt2x00pci_register_read(rt2x00dev
, RALINKCSR
, ®
);
779 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA0
, 17);
780 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID0
, 154);
781 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_DATA1
, 0);
782 rt2x00_set_field32(®
, RALINKCSR_AR_BBP_ID1
, 154);
783 rt2x00pci_register_write(rt2x00dev
, RALINKCSR
, reg
);
785 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
786 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 1);
787 rt2x00_set_field32(®
, CSR1_BBP_RESET
, 0);
788 rt2x00_set_field32(®
, CSR1_HOST_READY
, 0);
789 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
791 rt2x00pci_register_read(rt2x00dev
, CSR1
, ®
);
792 rt2x00_set_field32(®
, CSR1_SOFT_RESET
, 0);
793 rt2x00_set_field32(®
, CSR1_HOST_READY
, 1);
794 rt2x00pci_register_write(rt2x00dev
, CSR1
, reg
);
797 * We must clear the FCS and FIFO error count.
798 * These registers are cleared on read,
799 * so we may pass a useless variable to store the value.
801 rt2x00pci_register_read(rt2x00dev
, CNT0
, ®
);
802 rt2x00pci_register_read(rt2x00dev
, CNT4
, ®
);
807 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
812 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
813 rt2400pci_bbp_read(rt2x00dev
, 0, &value
);
814 if ((value
!= 0xff) && (value
!= 0x00))
816 udelay(REGISTER_BUSY_DELAY
);
819 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
823 static int rt2400pci_init_bbp(struct rt2x00_dev
*rt2x00dev
)
830 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev
)))
833 rt2400pci_bbp_write(rt2x00dev
, 1, 0x00);
834 rt2400pci_bbp_write(rt2x00dev
, 3, 0x27);
835 rt2400pci_bbp_write(rt2x00dev
, 4, 0x08);
836 rt2400pci_bbp_write(rt2x00dev
, 10, 0x0f);
837 rt2400pci_bbp_write(rt2x00dev
, 15, 0x72);
838 rt2400pci_bbp_write(rt2x00dev
, 16, 0x74);
839 rt2400pci_bbp_write(rt2x00dev
, 17, 0x20);
840 rt2400pci_bbp_write(rt2x00dev
, 18, 0x72);
841 rt2400pci_bbp_write(rt2x00dev
, 19, 0x0b);
842 rt2400pci_bbp_write(rt2x00dev
, 20, 0x00);
843 rt2400pci_bbp_write(rt2x00dev
, 28, 0x11);
844 rt2400pci_bbp_write(rt2x00dev
, 29, 0x04);
845 rt2400pci_bbp_write(rt2x00dev
, 30, 0x21);
846 rt2400pci_bbp_write(rt2x00dev
, 31, 0x00);
848 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
849 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
851 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
852 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
853 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
854 rt2400pci_bbp_write(rt2x00dev
, reg_id
, value
);
862 * Device state switch handlers.
864 static void rt2400pci_toggle_rx(struct rt2x00_dev
*rt2x00dev
,
865 enum dev_state state
)
869 rt2x00pci_register_read(rt2x00dev
, RXCSR0
, ®
);
870 rt2x00_set_field32(®
, RXCSR0_DISABLE_RX
,
871 (state
== STATE_RADIO_RX_OFF
) ||
872 (state
== STATE_RADIO_RX_OFF_LINK
));
873 rt2x00pci_register_write(rt2x00dev
, RXCSR0
, reg
);
876 static void rt2400pci_toggle_irq(struct rt2x00_dev
*rt2x00dev
,
877 enum dev_state state
)
879 int mask
= (state
== STATE_RADIO_IRQ_OFF
);
883 * When interrupts are being enabled, the interrupt registers
884 * should clear the register to assure a clean state.
886 if (state
== STATE_RADIO_IRQ_ON
) {
887 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
888 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
892 * Only toggle the interrupts bits we are going to use.
893 * Non-checked interrupt bits are disabled by default.
895 rt2x00pci_register_read(rt2x00dev
, CSR8
, ®
);
896 rt2x00_set_field32(®
, CSR8_TBCN_EXPIRE
, mask
);
897 rt2x00_set_field32(®
, CSR8_TXDONE_TXRING
, mask
);
898 rt2x00_set_field32(®
, CSR8_TXDONE_ATIMRING
, mask
);
899 rt2x00_set_field32(®
, CSR8_TXDONE_PRIORING
, mask
);
900 rt2x00_set_field32(®
, CSR8_RXDONE
, mask
);
901 rt2x00pci_register_write(rt2x00dev
, CSR8
, reg
);
904 static int rt2400pci_enable_radio(struct rt2x00_dev
*rt2x00dev
)
907 * Initialize all registers.
909 if (unlikely(rt2400pci_init_queues(rt2x00dev
) ||
910 rt2400pci_init_registers(rt2x00dev
) ||
911 rt2400pci_init_bbp(rt2x00dev
)))
917 static void rt2400pci_disable_radio(struct rt2x00_dev
*rt2x00dev
)
922 rt2x00pci_register_write(rt2x00dev
, PWRCSR0
, 0);
925 static int rt2400pci_set_state(struct rt2x00_dev
*rt2x00dev
,
926 enum dev_state state
)
934 put_to_sleep
= (state
!= STATE_AWAKE
);
936 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®
);
937 rt2x00_set_field32(®
, PWRCSR1_SET_STATE
, 1);
938 rt2x00_set_field32(®
, PWRCSR1_BBP_DESIRE_STATE
, state
);
939 rt2x00_set_field32(®
, PWRCSR1_RF_DESIRE_STATE
, state
);
940 rt2x00_set_field32(®
, PWRCSR1_PUT_TO_SLEEP
, put_to_sleep
);
941 rt2x00pci_register_write(rt2x00dev
, PWRCSR1
, reg
);
944 * Device is not guaranteed to be in the requested state yet.
945 * We must wait until the register indicates that the
946 * device has entered the correct state.
948 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
949 rt2x00pci_register_read(rt2x00dev
, PWRCSR1
, ®
);
950 bbp_state
= rt2x00_get_field32(reg
, PWRCSR1_BBP_CURR_STATE
);
951 rf_state
= rt2x00_get_field32(reg
, PWRCSR1_RF_CURR_STATE
);
952 if (bbp_state
== state
&& rf_state
== state
)
960 static int rt2400pci_set_device_state(struct rt2x00_dev
*rt2x00dev
,
961 enum dev_state state
)
967 retval
= rt2400pci_enable_radio(rt2x00dev
);
969 case STATE_RADIO_OFF
:
970 rt2400pci_disable_radio(rt2x00dev
);
972 case STATE_RADIO_RX_ON
:
973 case STATE_RADIO_RX_ON_LINK
:
974 case STATE_RADIO_RX_OFF
:
975 case STATE_RADIO_RX_OFF_LINK
:
976 rt2400pci_toggle_rx(rt2x00dev
, state
);
978 case STATE_RADIO_IRQ_ON
:
979 case STATE_RADIO_IRQ_OFF
:
980 rt2400pci_toggle_irq(rt2x00dev
, state
);
982 case STATE_DEEP_SLEEP
:
986 retval
= rt2400pci_set_state(rt2x00dev
, state
);
993 if (unlikely(retval
))
994 ERROR(rt2x00dev
, "Device failed to enter state %d (%d).\n",
1001 * TX descriptor initialization
1003 static void rt2400pci_write_tx_desc(struct rt2x00_dev
*rt2x00dev
,
1004 struct sk_buff
*skb
,
1005 struct txentry_desc
*txdesc
)
1007 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(skb
);
1008 struct queue_entry_priv_pci
*entry_priv
= skbdesc
->entry
->priv_data
;
1009 __le32
*txd
= entry_priv
->desc
;
1013 * Start writing the descriptor words.
1015 rt2x00_desc_read(txd
, 1, &word
);
1016 rt2x00_set_field32(&word
, TXD_W1_BUFFER_ADDRESS
, skbdesc
->skb_dma
);
1017 rt2x00_desc_write(txd
, 1, word
);
1019 rt2x00_desc_read(txd
, 2, &word
);
1020 rt2x00_set_field32(&word
, TXD_W2_BUFFER_LENGTH
, txdesc
->length
);
1021 rt2x00_set_field32(&word
, TXD_W2_DATABYTE_COUNT
, txdesc
->length
);
1022 rt2x00_desc_write(txd
, 2, word
);
1024 rt2x00_desc_read(txd
, 3, &word
);
1025 rt2x00_set_field32(&word
, TXD_W3_PLCP_SIGNAL
, txdesc
->signal
);
1026 rt2x00_set_field32(&word
, TXD_W3_PLCP_SIGNAL_REGNUM
, 5);
1027 rt2x00_set_field32(&word
, TXD_W3_PLCP_SIGNAL_BUSY
, 1);
1028 rt2x00_set_field32(&word
, TXD_W3_PLCP_SERVICE
, txdesc
->service
);
1029 rt2x00_set_field32(&word
, TXD_W3_PLCP_SERVICE_REGNUM
, 6);
1030 rt2x00_set_field32(&word
, TXD_W3_PLCP_SERVICE_BUSY
, 1);
1031 rt2x00_desc_write(txd
, 3, word
);
1033 rt2x00_desc_read(txd
, 4, &word
);
1034 rt2x00_set_field32(&word
, TXD_W4_PLCP_LENGTH_LOW
, txdesc
->length_low
);
1035 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_LOW_REGNUM
, 8);
1036 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_LOW_BUSY
, 1);
1037 rt2x00_set_field32(&word
, TXD_W4_PLCP_LENGTH_HIGH
, txdesc
->length_high
);
1038 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_HIGH_REGNUM
, 7);
1039 rt2x00_set_field32(&word
, TXD_W3_PLCP_LENGTH_HIGH_BUSY
, 1);
1040 rt2x00_desc_write(txd
, 4, word
);
1043 * Writing TXD word 0 must the last to prevent a race condition with
1044 * the device, whereby the device may take hold of the TXD before we
1045 * finished updating it.
1047 rt2x00_desc_read(txd
, 0, &word
);
1048 rt2x00_set_field32(&word
, TXD_W0_OWNER_NIC
, 1);
1049 rt2x00_set_field32(&word
, TXD_W0_VALID
, 1);
1050 rt2x00_set_field32(&word
, TXD_W0_MORE_FRAG
,
1051 test_bit(ENTRY_TXD_MORE_FRAG
, &txdesc
->flags
));
1052 rt2x00_set_field32(&word
, TXD_W0_ACK
,
1053 test_bit(ENTRY_TXD_ACK
, &txdesc
->flags
));
1054 rt2x00_set_field32(&word
, TXD_W0_TIMESTAMP
,
1055 test_bit(ENTRY_TXD_REQ_TIMESTAMP
, &txdesc
->flags
));
1056 rt2x00_set_field32(&word
, TXD_W0_RTS
,
1057 test_bit(ENTRY_TXD_RTS_FRAME
, &txdesc
->flags
));
1058 rt2x00_set_field32(&word
, TXD_W0_IFS
, txdesc
->ifs
);
1059 rt2x00_set_field32(&word
, TXD_W0_RETRY_MODE
,
1060 test_bit(ENTRY_TXD_RETRY_MODE
, &txdesc
->flags
));
1061 rt2x00_desc_write(txd
, 0, word
);
1064 * Register descriptor details in skb frame descriptor.
1066 skbdesc
->desc
= txd
;
1067 skbdesc
->desc_len
= TXD_DESC_SIZE
;
1071 * TX data initialization
1073 static void rt2400pci_write_beacon(struct queue_entry
*entry
,
1074 struct txentry_desc
*txdesc
)
1076 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1077 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1078 struct skb_frame_desc
*skbdesc
= get_skb_frame_desc(entry
->skb
);
1083 * Disable beaconing while we are reloading the beacon data,
1084 * otherwise we might be sending out invalid data.
1086 rt2x00pci_register_read(rt2x00dev
, CSR14
, ®
);
1087 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 0);
1088 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
1090 rt2x00queue_map_txskb(rt2x00dev
, entry
->skb
);
1092 rt2x00_desc_read(entry_priv
->desc
, 1, &word
);
1093 rt2x00_set_field32(&word
, TXD_W1_BUFFER_ADDRESS
, skbdesc
->skb_dma
);
1094 rt2x00_desc_write(entry_priv
->desc
, 1, word
);
1097 * Enable beaconing again.
1099 rt2x00_set_field32(®
, CSR14_TSF_COUNT
, 1);
1100 rt2x00_set_field32(®
, CSR14_TBCN
, 1);
1101 rt2x00_set_field32(®
, CSR14_BEACON_GEN
, 1);
1102 rt2x00pci_register_write(rt2x00dev
, CSR14
, reg
);
1105 static void rt2400pci_kick_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1106 const enum data_queue_qid queue
)
1110 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
1111 rt2x00_set_field32(®
, TXCSR0_KICK_PRIO
, (queue
== QID_AC_BE
));
1112 rt2x00_set_field32(®
, TXCSR0_KICK_TX
, (queue
== QID_AC_BK
));
1113 rt2x00_set_field32(®
, TXCSR0_KICK_ATIM
, (queue
== QID_ATIM
));
1114 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
1117 static void rt2400pci_kill_tx_queue(struct rt2x00_dev
*rt2x00dev
,
1118 const enum data_queue_qid qid
)
1122 if (qid
== QID_BEACON
) {
1123 rt2x00pci_register_write(rt2x00dev
, CSR14
, 0);
1125 rt2x00pci_register_read(rt2x00dev
, TXCSR0
, ®
);
1126 rt2x00_set_field32(®
, TXCSR0_ABORT
, 1);
1127 rt2x00pci_register_write(rt2x00dev
, TXCSR0
, reg
);
1132 * RX control handlers
1134 static void rt2400pci_fill_rxdone(struct queue_entry
*entry
,
1135 struct rxdone_entry_desc
*rxdesc
)
1137 struct rt2x00_dev
*rt2x00dev
= entry
->queue
->rt2x00dev
;
1138 struct queue_entry_priv_pci
*entry_priv
= entry
->priv_data
;
1147 rt2x00_desc_read(entry_priv
->desc
, 0, &word0
);
1148 rt2x00_desc_read(entry_priv
->desc
, 2, &word2
);
1149 rt2x00_desc_read(entry_priv
->desc
, 3, &word3
);
1150 rt2x00_desc_read(entry_priv
->desc
, 4, &word4
);
1152 if (rt2x00_get_field32(word0
, RXD_W0_CRC_ERROR
))
1153 rxdesc
->flags
|= RX_FLAG_FAILED_FCS_CRC
;
1154 if (rt2x00_get_field32(word0
, RXD_W0_PHYSICAL_ERROR
))
1155 rxdesc
->flags
|= RX_FLAG_FAILED_PLCP_CRC
;
1158 * We only get the lower 32bits from the timestamp,
1159 * to get the full 64bits we must complement it with
1160 * the timestamp from get_tsf().
1161 * Note that when a wraparound of the lower 32bits
1162 * has occurred between the frame arrival and the get_tsf()
1163 * call, we must decrease the higher 32bits with 1 to get
1166 tsf
= rt2x00dev
->ops
->hw
->get_tsf(rt2x00dev
->hw
);
1167 rx_low
= rt2x00_get_field32(word4
, RXD_W4_RX_END_TIME
);
1168 rx_high
= upper_32_bits(tsf
);
1170 if ((u32
)tsf
<= rx_low
)
1174 * Obtain the status about this packet.
1175 * The signal is the PLCP value, and needs to be stripped
1176 * of the preamble bit (0x08).
1178 rxdesc
->timestamp
= ((u64
)rx_high
<< 32) | rx_low
;
1179 rxdesc
->signal
= rt2x00_get_field32(word2
, RXD_W2_SIGNAL
) & ~0x08;
1180 rxdesc
->rssi
= rt2x00_get_field32(word2
, RXD_W3_RSSI
) -
1181 entry
->queue
->rt2x00dev
->rssi_offset
;
1182 rxdesc
->size
= rt2x00_get_field32(word0
, RXD_W0_DATABYTE_COUNT
);
1184 rxdesc
->dev_flags
|= RXDONE_SIGNAL_PLCP
;
1185 if (rt2x00_get_field32(word0
, RXD_W0_MY_BSS
))
1186 rxdesc
->dev_flags
|= RXDONE_MY_BSS
;
1190 * Interrupt functions.
1192 static void rt2400pci_txdone(struct rt2x00_dev
*rt2x00dev
,
1193 const enum data_queue_qid queue_idx
)
1195 struct data_queue
*queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
1196 struct queue_entry_priv_pci
*entry_priv
;
1197 struct queue_entry
*entry
;
1198 struct txdone_entry_desc txdesc
;
1201 while (!rt2x00queue_empty(queue
)) {
1202 entry
= rt2x00queue_get_entry(queue
, Q_INDEX_DONE
);
1203 entry_priv
= entry
->priv_data
;
1204 rt2x00_desc_read(entry_priv
->desc
, 0, &word
);
1206 if (rt2x00_get_field32(word
, TXD_W0_OWNER_NIC
) ||
1207 !rt2x00_get_field32(word
, TXD_W0_VALID
))
1211 * Obtain the status about this packet.
1214 switch (rt2x00_get_field32(word
, TXD_W0_RESULT
)) {
1215 case 0: /* Success */
1216 case 1: /* Success with retry */
1217 __set_bit(TXDONE_SUCCESS
, &txdesc
.flags
);
1219 case 2: /* Failure, excessive retries */
1220 __set_bit(TXDONE_EXCESSIVE_RETRY
, &txdesc
.flags
);
1221 /* Don't break, this is a failed frame! */
1222 default: /* Failure */
1223 __set_bit(TXDONE_FAILURE
, &txdesc
.flags
);
1225 txdesc
.retry
= rt2x00_get_field32(word
, TXD_W0_RETRY_COUNT
);
1227 rt2x00lib_txdone(entry
, &txdesc
);
1231 static irqreturn_t
rt2400pci_interrupt(int irq
, void *dev_instance
)
1233 struct rt2x00_dev
*rt2x00dev
= dev_instance
;
1237 * Get the interrupt sources & saved to local variable.
1238 * Write register value back to clear pending interrupts.
1240 rt2x00pci_register_read(rt2x00dev
, CSR7
, ®
);
1241 rt2x00pci_register_write(rt2x00dev
, CSR7
, reg
);
1246 if (!test_bit(DEVICE_STATE_ENABLED_RADIO
, &rt2x00dev
->flags
))
1250 * Handle interrupts, walk through all bits
1251 * and run the tasks, the bits are checked in order of
1256 * 1 - Beacon timer expired interrupt.
1258 if (rt2x00_get_field32(reg
, CSR7_TBCN_EXPIRE
))
1259 rt2x00lib_beacondone(rt2x00dev
);
1262 * 2 - Rx ring done interrupt.
1264 if (rt2x00_get_field32(reg
, CSR7_RXDONE
))
1265 rt2x00pci_rxdone(rt2x00dev
);
1268 * 3 - Atim ring transmit done interrupt.
1270 if (rt2x00_get_field32(reg
, CSR7_TXDONE_ATIMRING
))
1271 rt2400pci_txdone(rt2x00dev
, QID_ATIM
);
1274 * 4 - Priority ring transmit done interrupt.
1276 if (rt2x00_get_field32(reg
, CSR7_TXDONE_PRIORING
))
1277 rt2400pci_txdone(rt2x00dev
, QID_AC_BE
);
1280 * 5 - Tx ring transmit done interrupt.
1282 if (rt2x00_get_field32(reg
, CSR7_TXDONE_TXRING
))
1283 rt2400pci_txdone(rt2x00dev
, QID_AC_BK
);
1289 * Device probe functions.
1291 static int rt2400pci_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
1293 struct eeprom_93cx6 eeprom
;
1298 rt2x00pci_register_read(rt2x00dev
, CSR21
, ®
);
1300 eeprom
.data
= rt2x00dev
;
1301 eeprom
.register_read
= rt2400pci_eepromregister_read
;
1302 eeprom
.register_write
= rt2400pci_eepromregister_write
;
1303 eeprom
.width
= rt2x00_get_field32(reg
, CSR21_TYPE_93C46
) ?
1304 PCI_EEPROM_WIDTH_93C46
: PCI_EEPROM_WIDTH_93C66
;
1305 eeprom
.reg_data_in
= 0;
1306 eeprom
.reg_data_out
= 0;
1307 eeprom
.reg_data_clock
= 0;
1308 eeprom
.reg_chip_select
= 0;
1310 eeprom_93cx6_multiread(&eeprom
, EEPROM_BASE
, rt2x00dev
->eeprom
,
1311 EEPROM_SIZE
/ sizeof(u16
));
1314 * Start validation of the data that has been read.
1316 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
1317 if (!is_valid_ether_addr(mac
)) {
1318 random_ether_addr(mac
);
1319 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
1322 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
1323 if (word
== 0xffff) {
1324 ERROR(rt2x00dev
, "Invalid EEPROM data detected.\n");
1331 static int rt2400pci_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
1338 * Read EEPROM word for configuration.
1340 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1343 * Identify RF chipset.
1345 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
1346 rt2x00pci_register_read(rt2x00dev
, CSR0
, ®
);
1347 rt2x00_set_chip(rt2x00dev
, RT2460
, value
,
1348 rt2x00_get_field32(reg
, CSR0_REVISION
));
1350 if (!rt2x00_rf(rt2x00dev
, RF2420
) && !rt2x00_rf(rt2x00dev
, RF2421
)) {
1351 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
1356 * Identify default antenna configuration.
1358 rt2x00dev
->default_ant
.tx
=
1359 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TX_DEFAULT
);
1360 rt2x00dev
->default_ant
.rx
=
1361 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_DEFAULT
);
1364 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1365 * I am not 100% sure about this, but the legacy drivers do not
1366 * indicate antenna swapping in software is required when
1367 * diversity is enabled.
1369 if (rt2x00dev
->default_ant
.tx
== ANTENNA_SW_DIVERSITY
)
1370 rt2x00dev
->default_ant
.tx
= ANTENNA_HW_DIVERSITY
;
1371 if (rt2x00dev
->default_ant
.rx
== ANTENNA_SW_DIVERSITY
)
1372 rt2x00dev
->default_ant
.rx
= ANTENNA_HW_DIVERSITY
;
1375 * Store led mode, for correct led behaviour.
1377 #ifdef CONFIG_RT2X00_LIB_LEDS
1378 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_LED_MODE
);
1380 rt2400pci_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
1381 if (value
== LED_MODE_TXRX_ACTIVITY
||
1382 value
== LED_MODE_DEFAULT
||
1383 value
== LED_MODE_ASUS
)
1384 rt2400pci_init_led(rt2x00dev
, &rt2x00dev
->led_qual
,
1386 #endif /* CONFIG_RT2X00_LIB_LEDS */
1389 * Detect if this device has an hardware controlled radio.
1391 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_HARDWARE_RADIO
))
1392 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
1395 * Check if the BBP tuning should be enabled.
1397 if (!rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RX_AGCVGC_TUNING
))
1398 __set_bit(CONFIG_DISABLE_LINK_TUNING
, &rt2x00dev
->flags
);
1404 * RF value list for RF2420 & RF2421
1407 static const struct rf_channel rf_vals_b
[] = {
1408 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1409 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1410 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1411 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1412 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1413 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1414 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1415 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1416 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1417 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1418 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1419 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1420 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1421 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1424 static int rt2400pci_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
1426 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
1427 struct channel_info
*info
;
1432 * Initialize all hw fields.
1434 rt2x00dev
->hw
->flags
= IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
1435 IEEE80211_HW_SIGNAL_DBM
|
1436 IEEE80211_HW_SUPPORTS_PS
|
1437 IEEE80211_HW_PS_NULLFUNC_STACK
;
1439 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
1440 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
1441 rt2x00_eeprom_addr(rt2x00dev
,
1442 EEPROM_MAC_ADDR_0
));
1445 * Initialize hw_mode information.
1447 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
1448 spec
->supported_rates
= SUPPORT_RATE_CCK
;
1450 spec
->num_channels
= ARRAY_SIZE(rf_vals_b
);
1451 spec
->channels
= rf_vals_b
;
1454 * Create channel information array
1456 info
= kzalloc(spec
->num_channels
* sizeof(*info
), GFP_KERNEL
);
1460 spec
->channels_info
= info
;
1462 tx_power
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_START
);
1463 for (i
= 0; i
< 14; i
++)
1464 info
[i
].tx_power1
= TXPOWER_FROM_DEV(tx_power
[i
]);
1469 static int rt2400pci_probe_hw(struct rt2x00_dev
*rt2x00dev
)
1474 * Allocate eeprom data.
1476 retval
= rt2400pci_validate_eeprom(rt2x00dev
);
1480 retval
= rt2400pci_init_eeprom(rt2x00dev
);
1485 * Initialize hw specifications.
1487 retval
= rt2400pci_probe_hw_mode(rt2x00dev
);
1492 * This device requires the atim queue and DMA-mapped skbs.
1494 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE
, &rt2x00dev
->flags
);
1495 __set_bit(DRIVER_REQUIRE_DMA
, &rt2x00dev
->flags
);
1498 * Set the rssi offset.
1500 rt2x00dev
->rssi_offset
= DEFAULT_RSSI_OFFSET
;
1506 * IEEE80211 stack callback functions.
1508 static int rt2400pci_conf_tx(struct ieee80211_hw
*hw
, u16 queue
,
1509 const struct ieee80211_tx_queue_params
*params
)
1511 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1514 * We don't support variating cw_min and cw_max variables
1515 * per queue. So by default we only configure the TX queue,
1516 * and ignore all other configurations.
1521 if (rt2x00mac_conf_tx(hw
, queue
, params
))
1525 * Write configuration to register.
1527 rt2400pci_config_cw(rt2x00dev
,
1528 rt2x00dev
->tx
->cw_min
, rt2x00dev
->tx
->cw_max
);
1533 static u64
rt2400pci_get_tsf(struct ieee80211_hw
*hw
)
1535 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1539 rt2x00pci_register_read(rt2x00dev
, CSR17
, ®
);
1540 tsf
= (u64
) rt2x00_get_field32(reg
, CSR17_HIGH_TSFTIMER
) << 32;
1541 rt2x00pci_register_read(rt2x00dev
, CSR16
, ®
);
1542 tsf
|= rt2x00_get_field32(reg
, CSR16_LOW_TSFTIMER
);
1547 static int rt2400pci_tx_last_beacon(struct ieee80211_hw
*hw
)
1549 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
1552 rt2x00pci_register_read(rt2x00dev
, CSR15
, ®
);
1553 return rt2x00_get_field32(reg
, CSR15_BEACON_SENT
);
1556 static const struct ieee80211_ops rt2400pci_mac80211_ops
= {
1558 .start
= rt2x00mac_start
,
1559 .stop
= rt2x00mac_stop
,
1560 .add_interface
= rt2x00mac_add_interface
,
1561 .remove_interface
= rt2x00mac_remove_interface
,
1562 .config
= rt2x00mac_config
,
1563 .configure_filter
= rt2x00mac_configure_filter
,
1564 .set_tim
= rt2x00mac_set_tim
,
1565 .get_stats
= rt2x00mac_get_stats
,
1566 .bss_info_changed
= rt2x00mac_bss_info_changed
,
1567 .conf_tx
= rt2400pci_conf_tx
,
1568 .get_tsf
= rt2400pci_get_tsf
,
1569 .tx_last_beacon
= rt2400pci_tx_last_beacon
,
1570 .rfkill_poll
= rt2x00mac_rfkill_poll
,
1573 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops
= {
1574 .irq_handler
= rt2400pci_interrupt
,
1575 .probe_hw
= rt2400pci_probe_hw
,
1576 .initialize
= rt2x00pci_initialize
,
1577 .uninitialize
= rt2x00pci_uninitialize
,
1578 .get_entry_state
= rt2400pci_get_entry_state
,
1579 .clear_entry
= rt2400pci_clear_entry
,
1580 .set_device_state
= rt2400pci_set_device_state
,
1581 .rfkill_poll
= rt2400pci_rfkill_poll
,
1582 .link_stats
= rt2400pci_link_stats
,
1583 .reset_tuner
= rt2400pci_reset_tuner
,
1584 .link_tuner
= rt2400pci_link_tuner
,
1585 .write_tx_desc
= rt2400pci_write_tx_desc
,
1586 .write_tx_data
= rt2x00pci_write_tx_data
,
1587 .write_beacon
= rt2400pci_write_beacon
,
1588 .kick_tx_queue
= rt2400pci_kick_tx_queue
,
1589 .kill_tx_queue
= rt2400pci_kill_tx_queue
,
1590 .fill_rxdone
= rt2400pci_fill_rxdone
,
1591 .config_filter
= rt2400pci_config_filter
,
1592 .config_intf
= rt2400pci_config_intf
,
1593 .config_erp
= rt2400pci_config_erp
,
1594 .config_ant
= rt2400pci_config_ant
,
1595 .config
= rt2400pci_config
,
1598 static const struct data_queue_desc rt2400pci_queue_rx
= {
1599 .entry_num
= RX_ENTRIES
,
1600 .data_size
= DATA_FRAME_SIZE
,
1601 .desc_size
= RXD_DESC_SIZE
,
1602 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1605 static const struct data_queue_desc rt2400pci_queue_tx
= {
1606 .entry_num
= TX_ENTRIES
,
1607 .data_size
= DATA_FRAME_SIZE
,
1608 .desc_size
= TXD_DESC_SIZE
,
1609 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1612 static const struct data_queue_desc rt2400pci_queue_bcn
= {
1613 .entry_num
= BEACON_ENTRIES
,
1614 .data_size
= MGMT_FRAME_SIZE
,
1615 .desc_size
= TXD_DESC_SIZE
,
1616 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1619 static const struct data_queue_desc rt2400pci_queue_atim
= {
1620 .entry_num
= ATIM_ENTRIES
,
1621 .data_size
= DATA_FRAME_SIZE
,
1622 .desc_size
= TXD_DESC_SIZE
,
1623 .priv_size
= sizeof(struct queue_entry_priv_pci
),
1626 static const struct rt2x00_ops rt2400pci_ops
= {
1627 .name
= KBUILD_MODNAME
,
1630 .eeprom_size
= EEPROM_SIZE
,
1632 .tx_queues
= NUM_TX_QUEUES
,
1633 .extra_tx_headroom
= 0,
1634 .rx
= &rt2400pci_queue_rx
,
1635 .tx
= &rt2400pci_queue_tx
,
1636 .bcn
= &rt2400pci_queue_bcn
,
1637 .atim
= &rt2400pci_queue_atim
,
1638 .lib
= &rt2400pci_rt2x00_ops
,
1639 .hw
= &rt2400pci_mac80211_ops
,
1640 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1641 .debugfs
= &rt2400pci_rt2x00debug
,
1642 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1646 * RT2400pci module information.
1648 static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table
) = {
1649 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops
) },
1653 MODULE_AUTHOR(DRV_PROJECT
);
1654 MODULE_VERSION(DRV_VERSION
);
1655 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1656 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1657 MODULE_DEVICE_TABLE(pci
, rt2400pci_device_table
);
1658 MODULE_LICENSE("GPL");
1660 static struct pci_driver rt2400pci_driver
= {
1661 .name
= KBUILD_MODNAME
,
1662 .id_table
= rt2400pci_device_table
,
1663 .probe
= rt2x00pci_probe
,
1664 .remove
= __devexit_p(rt2x00pci_remove
),
1665 .suspend
= rt2x00pci_suspend
,
1666 .resume
= rt2x00pci_resume
,
1669 static int __init
rt2400pci_init(void)
1671 return pci_register_driver(&rt2400pci_driver
);
1674 static void __exit
rt2400pci_exit(void)
1676 pci_unregister_driver(&rt2400pci_driver
);
1679 module_init(rt2400pci_init
);
1680 module_exit(rt2400pci_exit
);