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KVM: X86: Delegate tsc-offset calculation to architecture code
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / typhoon.c
blob82653cb07857fa91ce46a9a5c79c6dee7057c942
1 /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
2 /*
3 Written 2002-2004 by David Dillow <dave@thedillows.org>
4 Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
5 Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This software is available on a public web site. It may enable
15 cryptographic capabilities of the 3Com hardware, and may be
16 exported from the United States under License Exception "TSU"
17 pursuant to 15 C.F.R. Section 740.13(e).
18
19 This work was funded by the National Library of Medicine under
20 the Department of Energy project number 0274DD06D1 and NLM project
21 number Y1-LM-2015-01.
22
23 This driver is designed for the 3Com 3CR990 Family of cards with the
24 3XP Processor. It has been tested on x86 and sparc64.
25
26 KNOWN ISSUES:
27 *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
28 issue. Hopefully 3Com will fix it.
29 *) Waiting for a command response takes 8ms due to non-preemptable
30 polling. Only significant for getting stats and creating
31 SAs, but an ugly wart never the less.
32
33 TODO:
34 *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
35 *) Add more support for ethtool (especially for NIC stats)
36 *) Allow disabling of RX checksum offloading
37 *) Fix MAC changing to work while the interface is up
38 (Need to put commands on the TX ring, which changes
39 the locking)
40 *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
41 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
42 */
43
44 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
45 * Setting to > 1518 effectively disables this feature.
46 */
47 static int rx_copybreak = 200;
48
49 /* Should we use MMIO or Port IO?
50 * 0: Port IO
51 * 1: MMIO
52 * 2: Try MMIO, fallback to Port IO
53 */
54 static unsigned int use_mmio = 2;
55
56 /* end user-configurable values */
57
58 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
59 */
60 static const int multicast_filter_limit = 32;
61
62 /* Operational parameters that are set at compile time. */
63
64 /* Keep the ring sizes a power of two for compile efficiency.
65 * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
66 * Making the Tx ring too large decreases the effectiveness of channel
67 * bonding and packet priority.
68 * There are no ill effects from too-large receive rings.
69 *
70 * We don't currently use the Hi Tx ring so, don't make it very big.
71 *
72 * Beware that if we start using the Hi Tx ring, we will need to change
73 * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
74 */
75 #define TXHI_ENTRIES 2
76 #define TXLO_ENTRIES 128
77 #define RX_ENTRIES 32
78 #define COMMAND_ENTRIES 16
79 #define RESPONSE_ENTRIES 32
80
81 #define COMMAND_RING_SIZE (COMMAND_ENTRIES * sizeof(struct cmd_desc))
82 #define RESPONSE_RING_SIZE (RESPONSE_ENTRIES * sizeof(struct resp_desc))
83
84 /* The 3XP will preload and remove 64 entries from the free buffer
85 * list, and we need one entry to keep the ring from wrapping, so
86 * to keep this a power of two, we use 128 entries.
87 */
88 #define RXFREE_ENTRIES 128
89 #define RXENT_ENTRIES (RXFREE_ENTRIES - 1)
90
91 /* Operational parameters that usually are not changed. */
92
93 /* Time in jiffies before concluding the transmitter is hung. */
94 #define TX_TIMEOUT (2*HZ)
95
96 #define PKT_BUF_SZ 1536
97 #define FIRMWARE_NAME "3com/typhoon.bin"
98
99 #define pr_fmt(fmt) KBUILD_MODNAME " " fmt
100
101 #include <linux/module.h>
102 #include <linux/kernel.h>
103 #include <linux/sched.h>
104 #include <linux/string.h>
105 #include <linux/timer.h>
106 #include <linux/errno.h>
107 #include <linux/ioport.h>
108 #include <linux/interrupt.h>
109 #include <linux/pci.h>
110 #include <linux/netdevice.h>
111 #include <linux/etherdevice.h>
112 #include <linux/skbuff.h>
113 #include <linux/mm.h>
114 #include <linux/init.h>
115 #include <linux/delay.h>
116 #include <linux/ethtool.h>
117 #include <linux/if_vlan.h>
118 #include <linux/crc32.h>
119 #include <linux/bitops.h>
120 #include <asm/processor.h>
121 #include <asm/io.h>
122 #include <asm/uaccess.h>
123 #include <linux/in6.h>
124 #include <linux/dma-mapping.h>
125 #include <linux/firmware.h>
126
127 #include "typhoon.h"
128
129 MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
130 MODULE_VERSION("1.0");
131 MODULE_LICENSE("GPL");
132 MODULE_FIRMWARE(FIRMWARE_NAME);
133 MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
134 MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
135 "the buffer given back to the NIC. Default "
136 "is 200.");
137 MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
138 "Default is to try MMIO and fallback to PIO.");
139 module_param(rx_copybreak, int, 0);
140 module_param(use_mmio, int, 0);
141
142 #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
143 #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
144 #undef NETIF_F_TSO
145 #endif
146
147 #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
148 #error TX ring too small!
149 #endif
150
151 struct typhoon_card_info {
152 const char *name;
153 const int capabilities;
154 };
155
156 #define TYPHOON_CRYPTO_NONE 0x00
157 #define TYPHOON_CRYPTO_DES 0x01
158 #define TYPHOON_CRYPTO_3DES 0x02
159 #define TYPHOON_CRYPTO_VARIABLE 0x04
160 #define TYPHOON_FIBER 0x08
161 #define TYPHOON_WAKEUP_NEEDS_RESET 0x10
162
163 enum typhoon_cards {
164 TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
165 TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
166 TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
167 TYPHOON_FXM,
168 };
169
170 /* directly indexed by enum typhoon_cards, above */
171 static struct typhoon_card_info typhoon_card_info[] __devinitdata = {
172 { "3Com Typhoon (3C990-TX)",
173 TYPHOON_CRYPTO_NONE},
174 { "3Com Typhoon (3CR990-TX-95)",
175 TYPHOON_CRYPTO_DES},
176 { "3Com Typhoon (3CR990-TX-97)",
177 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
178 { "3Com Typhoon (3C990SVR)",
179 TYPHOON_CRYPTO_NONE},
180 { "3Com Typhoon (3CR990SVR95)",
181 TYPHOON_CRYPTO_DES},
182 { "3Com Typhoon (3CR990SVR97)",
183 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
184 { "3Com Typhoon2 (3C990B-TX-M)",
185 TYPHOON_CRYPTO_VARIABLE},
186 { "3Com Typhoon2 (3C990BSVR)",
187 TYPHOON_CRYPTO_VARIABLE},
188 { "3Com Typhoon (3CR990-FX-95)",
189 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
190 { "3Com Typhoon (3CR990-FX-97)",
191 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
192 { "3Com Typhoon (3CR990-FX-95 Server)",
193 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
194 { "3Com Typhoon (3CR990-FX-97 Server)",
195 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
196 { "3Com Typhoon2 (3C990B-FX-97)",
197 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
198 };
199
200 /* Notes on the new subsystem numbering scheme:
201 * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
202 * bit 4 indicates if this card has secured firmware (we don't support it)
203 * bit 8 indicates if this is a (0) copper or (1) fiber card
204 * bits 12-16 indicate card type: (0) client and (1) server
205 */
206 static DEFINE_PCI_DEVICE_TABLE(typhoon_pci_tbl) = {
207 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
209 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
211 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
213 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
214 PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
215 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
216 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
217 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
218 PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
219 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
220 PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
221 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
222 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
223 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
224 PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
225 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
226 PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
227 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
229 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
231 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
233 { 0, }
234 };
235 MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
236
237 /* Define the shared memory area
238 * Align everything the 3XP will normally be using.
239 * We'll need to move/align txHi if we start using that ring.
240 */
241 #define __3xp_aligned ____cacheline_aligned
242 struct typhoon_shared {
243 struct typhoon_interface iface;
244 struct typhoon_indexes indexes __3xp_aligned;
245 struct tx_desc txLo[TXLO_ENTRIES] __3xp_aligned;
246 struct rx_desc rxLo[RX_ENTRIES] __3xp_aligned;
247 struct rx_desc rxHi[RX_ENTRIES] __3xp_aligned;
248 struct cmd_desc cmd[COMMAND_ENTRIES] __3xp_aligned;
249 struct resp_desc resp[RESPONSE_ENTRIES] __3xp_aligned;
250 struct rx_free rxBuff[RXFREE_ENTRIES] __3xp_aligned;
251 u32 zeroWord;
252 struct tx_desc txHi[TXHI_ENTRIES];
253 } __packed;
254
255 struct rxbuff_ent {
256 struct sk_buff *skb;
257 dma_addr_t dma_addr;
258 };
259
260 struct typhoon {
261 /* Tx cache line section */
262 struct transmit_ring txLoRing ____cacheline_aligned;
263 struct pci_dev * tx_pdev;
264 void __iomem *tx_ioaddr;
265 u32 txlo_dma_addr;
266
267 /* Irq/Rx cache line section */
268 void __iomem *ioaddr ____cacheline_aligned;
269 struct typhoon_indexes *indexes;
270 u8 awaiting_resp;
271 u8 duplex;
272 u8 speed;
273 u8 card_state;
274 struct basic_ring rxLoRing;
275 struct pci_dev * pdev;
276 struct net_device * dev;
277 struct napi_struct napi;
278 struct basic_ring rxHiRing;
279 struct basic_ring rxBuffRing;
280 struct rxbuff_ent rxbuffers[RXENT_ENTRIES];
281
282 /* general section */
283 spinlock_t command_lock ____cacheline_aligned;
284 struct basic_ring cmdRing;
285 struct basic_ring respRing;
286 struct net_device_stats stats;
287 struct net_device_stats stats_saved;
288 struct typhoon_shared * shared;
289 dma_addr_t shared_dma;
290 __le16 xcvr_select;
291 __le16 wol_events;
292 __le32 offload;
293
294 /* unused stuff (future use) */
295 int capabilities;
296 struct transmit_ring txHiRing;
297 };
298
299 enum completion_wait_values {
300 NoWait = 0, WaitNoSleep, WaitSleep,
301 };
302
303 /* These are the values for the typhoon.card_state variable.
304 * These determine where the statistics will come from in get_stats().
305 * The sleep image does not support the statistics we need.
306 */
307 enum state_values {
308 Sleeping = 0, Running,
309 };
310
311 /* PCI writes are not guaranteed to be posted in order, but outstanding writes
312 * cannot pass a read, so this forces current writes to post.
313 */
314 #define typhoon_post_pci_writes(x) \
315 do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
316
317 /* We'll wait up to six seconds for a reset, and half a second normally.
318 */
319 #define TYPHOON_UDELAY 50
320 #define TYPHOON_RESET_TIMEOUT_SLEEP (6 * HZ)
321 #define TYPHOON_RESET_TIMEOUT_NOSLEEP ((6 * 1000000) / TYPHOON_UDELAY)
322 #define TYPHOON_WAIT_TIMEOUT ((1000000 / 2) / TYPHOON_UDELAY)
323
324 #if defined(NETIF_F_TSO)
325 #define skb_tso_size(x) (skb_shinfo(x)->gso_size)
326 #define TSO_NUM_DESCRIPTORS 2
327 #define TSO_OFFLOAD_ON TYPHOON_OFFLOAD_TCP_SEGMENT
328 #else
329 #define NETIF_F_TSO 0
330 #define skb_tso_size(x) 0
331 #define TSO_NUM_DESCRIPTORS 0
332 #define TSO_OFFLOAD_ON 0
333 #endif
334
335 static inline void
336 typhoon_inc_index(u32 *index, const int count, const int num_entries)
337 {
338 /* Increment a ring index -- we can use this for all rings execept
339 * the Rx rings, as they use different size descriptors
340 * otherwise, everything is the same size as a cmd_desc
341 */
342 *index += count * sizeof(struct cmd_desc);
343 *index %= num_entries * sizeof(struct cmd_desc);
344 }
345
346 static inline void
347 typhoon_inc_cmd_index(u32 *index, const int count)
348 {
349 typhoon_inc_index(index, count, COMMAND_ENTRIES);
350 }
351
352 static inline void
353 typhoon_inc_resp_index(u32 *index, const int count)
354 {
355 typhoon_inc_index(index, count, RESPONSE_ENTRIES);
356 }
357
358 static inline void
359 typhoon_inc_rxfree_index(u32 *index, const int count)
360 {
361 typhoon_inc_index(index, count, RXFREE_ENTRIES);
362 }
363
364 static inline void
365 typhoon_inc_tx_index(u32 *index, const int count)
366 {
367 /* if we start using the Hi Tx ring, this needs updateing */
368 typhoon_inc_index(index, count, TXLO_ENTRIES);
369 }
370
371 static inline void
372 typhoon_inc_rx_index(u32 *index, const int count)
373 {
374 /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
375 *index += count * sizeof(struct rx_desc);
376 *index %= RX_ENTRIES * sizeof(struct rx_desc);
377 }
378
379 static int
380 typhoon_reset(void __iomem *ioaddr, int wait_type)
381 {
382 int i, err = 0;
383 int timeout;
384
385 if(wait_type == WaitNoSleep)
386 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
387 else
388 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
389
390 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
391 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
392
393 iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
394 typhoon_post_pci_writes(ioaddr);
395 udelay(1);
396 iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
397
398 if(wait_type != NoWait) {
399 for(i = 0; i < timeout; i++) {
400 if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
401 TYPHOON_STATUS_WAITING_FOR_HOST)
402 goto out;
403
404 if(wait_type == WaitSleep)
405 schedule_timeout_uninterruptible(1);
406 else
407 udelay(TYPHOON_UDELAY);
408 }
409
410 err = -ETIMEDOUT;
411 }
412
413 out:
414 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
415 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
416
417 /* The 3XP seems to need a little extra time to complete the load
418 * of the sleep image before we can reliably boot it. Failure to
419 * do this occasionally results in a hung adapter after boot in
420 * typhoon_init_one() while trying to read the MAC address or
421 * putting the card to sleep. 3Com's driver waits 5ms, but
422 * that seems to be overkill. However, if we can sleep, we might
423 * as well give it that much time. Otherwise, we'll give it 500us,
424 * which should be enough (I've see it work well at 100us, but still
425 * saw occasional problems.)
426 */
427 if(wait_type == WaitSleep)
428 msleep(5);
429 else
430 udelay(500);
431 return err;
432 }
433
434 static int
435 typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
436 {
437 int i, err = 0;
438
439 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
440 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
441 goto out;
442 udelay(TYPHOON_UDELAY);
443 }
444
445 err = -ETIMEDOUT;
446
447 out:
448 return err;
449 }
450
451 static inline void
452 typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
453 {
454 if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
455 netif_carrier_off(dev);
456 else
457 netif_carrier_on(dev);
458 }
459
460 static inline void
461 typhoon_hello(struct typhoon *tp)
462 {
463 struct basic_ring *ring = &tp->cmdRing;
464 struct cmd_desc *cmd;
465
466 /* We only get a hello request if we've not sent anything to the
467 * card in a long while. If the lock is held, then we're in the
468 * process of issuing a command, so we don't need to respond.
469 */
470 if(spin_trylock(&tp->command_lock)) {
471 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
472 typhoon_inc_cmd_index(&ring->lastWrite, 1);
473
474 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
475 wmb();
476 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
477 spin_unlock(&tp->command_lock);
478 }
479 }
480
481 static int
482 typhoon_process_response(struct typhoon *tp, int resp_size,
483 struct resp_desc *resp_save)
484 {
485 struct typhoon_indexes *indexes = tp->indexes;
486 struct resp_desc *resp;
487 u8 *base = tp->respRing.ringBase;
488 int count, len, wrap_len;
489 u32 cleared;
490 u32 ready;
491
492 cleared = le32_to_cpu(indexes->respCleared);
493 ready = le32_to_cpu(indexes->respReady);
494 while(cleared != ready) {
495 resp = (struct resp_desc *)(base + cleared);
496 count = resp->numDesc + 1;
497 if(resp_save && resp->seqNo) {
498 if(count > resp_size) {
499 resp_save->flags = TYPHOON_RESP_ERROR;
500 goto cleanup;
501 }
502
503 wrap_len = 0;
504 len = count * sizeof(*resp);
505 if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
506 wrap_len = cleared + len - RESPONSE_RING_SIZE;
507 len = RESPONSE_RING_SIZE - cleared;
508 }
509
510 memcpy(resp_save, resp, len);
511 if(unlikely(wrap_len)) {
512 resp_save += len / sizeof(*resp);
513 memcpy(resp_save, base, wrap_len);
514 }
515
516 resp_save = NULL;
517 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
518 typhoon_media_status(tp->dev, resp);
519 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
520 typhoon_hello(tp);
521 } else {
522 netdev_err(tp->dev,
523 "dumping unexpected response 0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
524 le16_to_cpu(resp->cmd),
525 resp->numDesc, resp->flags,
526 le16_to_cpu(resp->parm1),
527 le32_to_cpu(resp->parm2),
528 le32_to_cpu(resp->parm3));
529 }
530
531 cleanup:
532 typhoon_inc_resp_index(&cleared, count);
533 }
534
535 indexes->respCleared = cpu_to_le32(cleared);
536 wmb();
537 return resp_save == NULL;
538 }
539
540 static inline int
541 typhoon_num_free(int lastWrite, int lastRead, int ringSize)
542 {
543 /* this works for all descriptors but rx_desc, as they are a
544 * different size than the cmd_desc -- everyone else is the same
545 */
546 lastWrite /= sizeof(struct cmd_desc);
547 lastRead /= sizeof(struct cmd_desc);
548 return (ringSize + lastRead - lastWrite - 1) % ringSize;
549 }
550
551 static inline int
552 typhoon_num_free_cmd(struct typhoon *tp)
553 {
554 int lastWrite = tp->cmdRing.lastWrite;
555 int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
556
557 return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
558 }
559
560 static inline int
561 typhoon_num_free_resp(struct typhoon *tp)
562 {
563 int respReady = le32_to_cpu(tp->indexes->respReady);
564 int respCleared = le32_to_cpu(tp->indexes->respCleared);
565
566 return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
567 }
568
569 static inline int
570 typhoon_num_free_tx(struct transmit_ring *ring)
571 {
572 /* if we start using the Hi Tx ring, this needs updating */
573 return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
574 }
575
576 static int
577 typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
578 int num_resp, struct resp_desc *resp)
579 {
580 struct typhoon_indexes *indexes = tp->indexes;
581 struct basic_ring *ring = &tp->cmdRing;
582 struct resp_desc local_resp;
583 int i, err = 0;
584 int got_resp;
585 int freeCmd, freeResp;
586 int len, wrap_len;
587
588 spin_lock(&tp->command_lock);
589
590 freeCmd = typhoon_num_free_cmd(tp);
591 freeResp = typhoon_num_free_resp(tp);
592
593 if(freeCmd < num_cmd || freeResp < num_resp) {
594 netdev_err(tp->dev, "no descs for cmd, had (needed) %d (%d) cmd, %d (%d) resp\n",
595 freeCmd, num_cmd, freeResp, num_resp);
596 err = -ENOMEM;
597 goto out;
598 }
599
600 if(cmd->flags & TYPHOON_CMD_RESPOND) {
601 /* If we're expecting a response, but the caller hasn't given
602 * us a place to put it, we'll provide one.
603 */
604 tp->awaiting_resp = 1;
605 if(resp == NULL) {
606 resp = &local_resp;
607 num_resp = 1;
608 }
609 }
610
611 wrap_len = 0;
612 len = num_cmd * sizeof(*cmd);
613 if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
614 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
615 len = COMMAND_RING_SIZE - ring->lastWrite;
616 }
617
618 memcpy(ring->ringBase + ring->lastWrite, cmd, len);
619 if(unlikely(wrap_len)) {
620 struct cmd_desc *wrap_ptr = cmd;
621 wrap_ptr += len / sizeof(*cmd);
622 memcpy(ring->ringBase, wrap_ptr, wrap_len);
623 }
624
625 typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
626
627 /* "I feel a presence... another warrior is on the mesa."
628 */
629 wmb();
630 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
631 typhoon_post_pci_writes(tp->ioaddr);
632
633 if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
634 goto out;
635
636 /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
637 * preempt or do anything other than take interrupts. So, don't
638 * wait for a response unless you have to.
639 *
640 * I've thought about trying to sleep here, but we're called
641 * from many contexts that don't allow that. Also, given the way
642 * 3Com has implemented irq coalescing, we would likely timeout --
643 * this has been observed in real life!
644 *
645 * The big killer is we have to wait to get stats from the card,
646 * though we could go to a periodic refresh of those if we don't
647 * mind them getting somewhat stale. The rest of the waiting
648 * commands occur during open/close/suspend/resume, so they aren't
649 * time critical. Creating SAs in the future will also have to
650 * wait here.
651 */
652 got_resp = 0;
653 for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
654 if(indexes->respCleared != indexes->respReady)
655 got_resp = typhoon_process_response(tp, num_resp,
656 resp);
657 udelay(TYPHOON_UDELAY);
658 }
659
660 if(!got_resp) {
661 err = -ETIMEDOUT;
662 goto out;
663 }
664
665 /* Collect the error response even if we don't care about the
666 * rest of the response
667 */
668 if(resp->flags & TYPHOON_RESP_ERROR)
669 err = -EIO;
670
671 out:
672 if(tp->awaiting_resp) {
673 tp->awaiting_resp = 0;
674 smp_wmb();
675
676 /* Ugh. If a response was added to the ring between
677 * the call to typhoon_process_response() and the clearing
678 * of tp->awaiting_resp, we could have missed the interrupt
679 * and it could hang in the ring an indeterminate amount of
680 * time. So, check for it, and interrupt ourselves if this
681 * is the case.
682 */
683 if(indexes->respCleared != indexes->respReady)
684 iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
685 }
686
687 spin_unlock(&tp->command_lock);
688 return err;
689 }
690
691 static inline void
692 typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
693 u32 ring_dma)
694 {
695 struct tcpopt_desc *tcpd;
696 u32 tcpd_offset = ring_dma;
697
698 tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
699 tcpd_offset += txRing->lastWrite;
700 tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
701 typhoon_inc_tx_index(&txRing->lastWrite, 1);
702
703 tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
704 tcpd->numDesc = 1;
705 tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
706 tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
707 tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
708 tcpd->bytesTx = cpu_to_le32(skb->len);
709 tcpd->status = 0;
710 }
711
712 static netdev_tx_t
713 typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
714 {
715 struct typhoon *tp = netdev_priv(dev);
716 struct transmit_ring *txRing;
717 struct tx_desc *txd, *first_txd;
718 dma_addr_t skb_dma;
719 int numDesc;
720
721 /* we have two rings to choose from, but we only use txLo for now
722 * If we start using the Hi ring as well, we'll need to update
723 * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
724 * and TXHI_ENTRIES to match, as well as update the TSO code below
725 * to get the right DMA address
726 */
727 txRing = &tp->txLoRing;
728
729 /* We need one descriptor for each fragment of the sk_buff, plus the
730 * one for the ->data area of it.
731 *
732 * The docs say a maximum of 16 fragment descriptors per TCP option
733 * descriptor, then make a new packet descriptor and option descriptor
734 * for the next 16 fragments. The engineers say just an option
735 * descriptor is needed. I've tested up to 26 fragments with a single
736 * packet descriptor/option descriptor combo, so I use that for now.
737 *
738 * If problems develop with TSO, check this first.
739 */
740 numDesc = skb_shinfo(skb)->nr_frags + 1;
741 if (skb_is_gso(skb))
742 numDesc++;
743
744 /* When checking for free space in the ring, we need to also
745 * account for the initial Tx descriptor, and we always must leave
746 * at least one descriptor unused in the ring so that it doesn't
747 * wrap and look empty.
748 *
749 * The only time we should loop here is when we hit the race
750 * between marking the queue awake and updating the cleared index.
751 * Just loop and it will appear. This comes from the acenic driver.
752 */
753 while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
754 smp_rmb();
755
756 first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
757 typhoon_inc_tx_index(&txRing->lastWrite, 1);
758
759 first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
760 first_txd->numDesc = 0;
761 first_txd->len = 0;
762 first_txd->tx_addr = (u64)((unsigned long) skb);
763 first_txd->processFlags = 0;
764
765 if(skb->ip_summed == CHECKSUM_PARTIAL) {
766 /* The 3XP will figure out if this is UDP/TCP */
767 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
768 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
769 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
770 }
771
772 if(vlan_tx_tag_present(skb)) {
773 first_txd->processFlags |=
774 TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
775 first_txd->processFlags |=
776 cpu_to_le32(htons(vlan_tx_tag_get(skb)) <<
777 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
778 }
779
780 if (skb_is_gso(skb)) {
781 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
782 first_txd->numDesc++;
783
784 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
785 }
786
787 txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
788 typhoon_inc_tx_index(&txRing->lastWrite, 1);
789
790 /* No need to worry about padding packet -- the firmware pads
791 * it with zeros to ETH_ZLEN for us.
792 */
793 if(skb_shinfo(skb)->nr_frags == 0) {
794 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
795 PCI_DMA_TODEVICE);
796 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
797 txd->len = cpu_to_le16(skb->len);
798 txd->frag.addr = cpu_to_le32(skb_dma);
799 txd->frag.addrHi = 0;
800 first_txd->numDesc++;
801 } else {
802 int i, len;
803
804 len = skb_headlen(skb);
805 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
806 PCI_DMA_TODEVICE);
807 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
808 txd->len = cpu_to_le16(len);
809 txd->frag.addr = cpu_to_le32(skb_dma);
810 txd->frag.addrHi = 0;
811 first_txd->numDesc++;
812
813 for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
814 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
815 void *frag_addr;
816
817 txd = (struct tx_desc *) (txRing->ringBase +
818 txRing->lastWrite);
819 typhoon_inc_tx_index(&txRing->lastWrite, 1);
820
821 len = frag->size;
822 frag_addr = (void *) page_address(frag->page) +
823 frag->page_offset;
824 skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
825 PCI_DMA_TODEVICE);
826 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
827 txd->len = cpu_to_le16(len);
828 txd->frag.addr = cpu_to_le32(skb_dma);
829 txd->frag.addrHi = 0;
830 first_txd->numDesc++;
831 }
832 }
833
834 /* Kick the 3XP
835 */
836 wmb();
837 iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
838
839 /* If we don't have room to put the worst case packet on the
840 * queue, then we must stop the queue. We need 2 extra
841 * descriptors -- one to prevent ring wrap, and one for the
842 * Tx header.
843 */
844 numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
845
846 if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
847 netif_stop_queue(dev);
848
849 /* A Tx complete IRQ could have gotten between, making
850 * the ring free again. Only need to recheck here, since
851 * Tx is serialized.
852 */
853 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
854 netif_wake_queue(dev);
855 }
856
857 return NETDEV_TX_OK;
858 }
859
860 static void
861 typhoon_set_rx_mode(struct net_device *dev)
862 {
863 struct typhoon *tp = netdev_priv(dev);
864 struct cmd_desc xp_cmd;
865 u32 mc_filter[2];
866 __le16 filter;
867
868 filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
869 if(dev->flags & IFF_PROMISC) {
870 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
871 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
872 (dev->flags & IFF_ALLMULTI)) {
873 /* Too many to match, or accept all multicasts. */
874 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
875 } else if (!netdev_mc_empty(dev)) {
876 struct netdev_hw_addr *ha;
877
878 memset(mc_filter, 0, sizeof(mc_filter));
879 netdev_for_each_mc_addr(ha, dev) {
880 int bit = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
881 mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
882 }
883
884 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
885 TYPHOON_CMD_SET_MULTICAST_HASH);
886 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
887 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
888 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
889 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
890
891 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
892 }
893
894 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
895 xp_cmd.parm1 = filter;
896 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
897 }
898
899 static int
900 typhoon_do_get_stats(struct typhoon *tp)
901 {
902 struct net_device_stats *stats = &tp->stats;
903 struct net_device_stats *saved = &tp->stats_saved;
904 struct cmd_desc xp_cmd;
905 struct resp_desc xp_resp[7];
906 struct stats_resp *s = (struct stats_resp *) xp_resp;
907 int err;
908
909 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
910 err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
911 if(err < 0)
912 return err;
913
914 /* 3Com's Linux driver uses txMultipleCollisions as it's
915 * collisions value, but there is some other collision info as well...
916 *
917 * The extra status reported would be a good candidate for
918 * ethtool_ops->get_{strings,stats}()
919 */
920 stats->tx_packets = le32_to_cpu(s->txPackets) +
921 saved->tx_packets;
922 stats->tx_bytes = le64_to_cpu(s->txBytes) +
923 saved->tx_bytes;
924 stats->tx_errors = le32_to_cpu(s->txCarrierLost) +
925 saved->tx_errors;
926 stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost) +
927 saved->tx_carrier_errors;
928 stats->collisions = le32_to_cpu(s->txMultipleCollisions) +
929 saved->collisions;
930 stats->rx_packets = le32_to_cpu(s->rxPacketsGood) +
931 saved->rx_packets;
932 stats->rx_bytes = le64_to_cpu(s->rxBytesGood) +
933 saved->rx_bytes;
934 stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns) +
935 saved->rx_fifo_errors;
936 stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
937 le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors) +
938 saved->rx_errors;
939 stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors) +
940 saved->rx_crc_errors;
941 stats->rx_length_errors = le32_to_cpu(s->rxOversized) +
942 saved->rx_length_errors;
943 tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
944 SPEED_100 : SPEED_10;
945 tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
946 DUPLEX_FULL : DUPLEX_HALF;
947
948 return 0;
949 }
950
951 static struct net_device_stats *
952 typhoon_get_stats(struct net_device *dev)
953 {
954 struct typhoon *tp = netdev_priv(dev);
955 struct net_device_stats *stats = &tp->stats;
956 struct net_device_stats *saved = &tp->stats_saved;
957
958 smp_rmb();
959 if(tp->card_state == Sleeping)
960 return saved;
961
962 if(typhoon_do_get_stats(tp) < 0) {
963 netdev_err(dev, "error getting stats\n");
964 return saved;
965 }
966
967 return stats;
968 }
969
970 static int
971 typhoon_set_mac_address(struct net_device *dev, void *addr)
972 {
973 struct sockaddr *saddr = (struct sockaddr *) addr;
974
975 if(netif_running(dev))
976 return -EBUSY;
977
978 memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
979 return 0;
980 }
981
982 static void
983 typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
984 {
985 struct typhoon *tp = netdev_priv(dev);
986 struct pci_dev *pci_dev = tp->pdev;
987 struct cmd_desc xp_cmd;
988 struct resp_desc xp_resp[3];
989
990 smp_rmb();
991 if(tp->card_state == Sleeping) {
992 strcpy(info->fw_version, "Sleep image");
993 } else {
994 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
995 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
996 strcpy(info->fw_version, "Unknown runtime");
997 } else {
998 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
999 snprintf(info->fw_version, 32, "%02x.%03x.%03x",
1000 sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
1001 sleep_ver & 0xfff);
1002 }
1003 }
1004
1005 strcpy(info->driver, KBUILD_MODNAME);
1006 strcpy(info->bus_info, pci_name(pci_dev));
1007 }
1008
1009 static int
1010 typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1011 {
1012 struct typhoon *tp = netdev_priv(dev);
1013
1014 cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1015 SUPPORTED_Autoneg;
1016
1017 switch (tp->xcvr_select) {
1018 case TYPHOON_XCVR_10HALF:
1019 cmd->advertising = ADVERTISED_10baseT_Half;
1020 break;
1021 case TYPHOON_XCVR_10FULL:
1022 cmd->advertising = ADVERTISED_10baseT_Full;
1023 break;
1024 case TYPHOON_XCVR_100HALF:
1025 cmd->advertising = ADVERTISED_100baseT_Half;
1026 break;
1027 case TYPHOON_XCVR_100FULL:
1028 cmd->advertising = ADVERTISED_100baseT_Full;
1029 break;
1030 case TYPHOON_XCVR_AUTONEG:
1031 cmd->advertising = ADVERTISED_10baseT_Half |
1032 ADVERTISED_10baseT_Full |
1033 ADVERTISED_100baseT_Half |
1034 ADVERTISED_100baseT_Full |
1035 ADVERTISED_Autoneg;
1036 break;
1037 }
1038
1039 if(tp->capabilities & TYPHOON_FIBER) {
1040 cmd->supported |= SUPPORTED_FIBRE;
1041 cmd->advertising |= ADVERTISED_FIBRE;
1042 cmd->port = PORT_FIBRE;
1043 } else {
1044 cmd->supported |= SUPPORTED_10baseT_Half |
1045 SUPPORTED_10baseT_Full |
1046 SUPPORTED_TP;
1047 cmd->advertising |= ADVERTISED_TP;
1048 cmd->port = PORT_TP;
1049 }
1050
1051 /* need to get stats to make these link speed/duplex valid */
1052 typhoon_do_get_stats(tp);
1053 cmd->speed = tp->speed;
1054 cmd->duplex = tp->duplex;
1055 cmd->phy_address = 0;
1056 cmd->transceiver = XCVR_INTERNAL;
1057 if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1058 cmd->autoneg = AUTONEG_ENABLE;
1059 else
1060 cmd->autoneg = AUTONEG_DISABLE;
1061 cmd->maxtxpkt = 1;
1062 cmd->maxrxpkt = 1;
1063
1064 return 0;
1065 }
1066
1067 static int
1068 typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1069 {
1070 struct typhoon *tp = netdev_priv(dev);
1071 struct cmd_desc xp_cmd;
1072 __le16 xcvr;
1073 int err;
1074
1075 err = -EINVAL;
1076 if(cmd->autoneg == AUTONEG_ENABLE) {
1077 xcvr = TYPHOON_XCVR_AUTONEG;
1078 } else {
1079 if(cmd->duplex == DUPLEX_HALF) {
1080 if(cmd->speed == SPEED_10)
1081 xcvr = TYPHOON_XCVR_10HALF;
1082 else if(cmd->speed == SPEED_100)
1083 xcvr = TYPHOON_XCVR_100HALF;
1084 else
1085 goto out;
1086 } else if(cmd->duplex == DUPLEX_FULL) {
1087 if(cmd->speed == SPEED_10)
1088 xcvr = TYPHOON_XCVR_10FULL;
1089 else if(cmd->speed == SPEED_100)
1090 xcvr = TYPHOON_XCVR_100FULL;
1091 else
1092 goto out;
1093 } else
1094 goto out;
1095 }
1096
1097 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1098 xp_cmd.parm1 = xcvr;
1099 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1100 if(err < 0)
1101 goto out;
1102
1103 tp->xcvr_select = xcvr;
1104 if(cmd->autoneg == AUTONEG_ENABLE) {
1105 tp->speed = 0xff; /* invalid */
1106 tp->duplex = 0xff; /* invalid */
1107 } else {
1108 tp->speed = cmd->speed;
1109 tp->duplex = cmd->duplex;
1110 }
1111
1112 out:
1113 return err;
1114 }
1115
1116 static void
1117 typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1118 {
1119 struct typhoon *tp = netdev_priv(dev);
1120
1121 wol->supported = WAKE_PHY | WAKE_MAGIC;
1122 wol->wolopts = 0;
1123 if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1124 wol->wolopts |= WAKE_PHY;
1125 if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1126 wol->wolopts |= WAKE_MAGIC;
1127 memset(&wol->sopass, 0, sizeof(wol->sopass));
1128 }
1129
1130 static int
1131 typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1132 {
1133 struct typhoon *tp = netdev_priv(dev);
1134
1135 if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1136 return -EINVAL;
1137
1138 tp->wol_events = 0;
1139 if(wol->wolopts & WAKE_PHY)
1140 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1141 if(wol->wolopts & WAKE_MAGIC)
1142 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1143
1144 return 0;
1145 }
1146
1147 static u32
1148 typhoon_get_rx_csum(struct net_device *dev)
1149 {
1150 /* For now, we don't allow turning off RX checksums.
1151 */
1152 return 1;
1153 }
1154
1155 static int
1156 typhoon_set_flags(struct net_device *dev, u32 data)
1157 {
1158 /* There's no way to turn off the RX VLAN offloading and stripping
1159 * on the current 3XP firmware -- it does not respect the offload
1160 * settings -- so we only allow the user to toggle the TX processing.
1161 */
1162 if (!(data & ETH_FLAG_RXVLAN))
1163 return -EINVAL;
1164
1165 return ethtool_op_set_flags(dev, data,
1166 ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN);
1167 }
1168
1169 static void
1170 typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1171 {
1172 ering->rx_max_pending = RXENT_ENTRIES;
1173 ering->rx_mini_max_pending = 0;
1174 ering->rx_jumbo_max_pending = 0;
1175 ering->tx_max_pending = TXLO_ENTRIES - 1;
1176
1177 ering->rx_pending = RXENT_ENTRIES;
1178 ering->rx_mini_pending = 0;
1179 ering->rx_jumbo_pending = 0;
1180 ering->tx_pending = TXLO_ENTRIES - 1;
1181 }
1182
1183 static const struct ethtool_ops typhoon_ethtool_ops = {
1184 .get_settings = typhoon_get_settings,
1185 .set_settings = typhoon_set_settings,
1186 .get_drvinfo = typhoon_get_drvinfo,
1187 .get_wol = typhoon_get_wol,
1188 .set_wol = typhoon_set_wol,
1189 .get_link = ethtool_op_get_link,
1190 .get_rx_csum = typhoon_get_rx_csum,
1191 .set_tx_csum = ethtool_op_set_tx_csum,
1192 .set_sg = ethtool_op_set_sg,
1193 .set_tso = ethtool_op_set_tso,
1194 .get_ringparam = typhoon_get_ringparam,
1195 .set_flags = typhoon_set_flags,
1196 .get_flags = ethtool_op_get_flags,
1197 };
1198
1199 static int
1200 typhoon_wait_interrupt(void __iomem *ioaddr)
1201 {
1202 int i, err = 0;
1203
1204 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1205 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1206 TYPHOON_INTR_BOOTCMD)
1207 goto out;
1208 udelay(TYPHOON_UDELAY);
1209 }
1210
1211 err = -ETIMEDOUT;
1212
1213 out:
1214 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1215 return err;
1216 }
1217
1218 #define shared_offset(x) offsetof(struct typhoon_shared, x)
1219
1220 static void
1221 typhoon_init_interface(struct typhoon *tp)
1222 {
1223 struct typhoon_interface *iface = &tp->shared->iface;
1224 dma_addr_t shared_dma;
1225
1226 memset(tp->shared, 0, sizeof(struct typhoon_shared));
1227
1228 /* The *Hi members of iface are all init'd to zero by the memset().
1229 */
1230 shared_dma = tp->shared_dma + shared_offset(indexes);
1231 iface->ringIndex = cpu_to_le32(shared_dma);
1232
1233 shared_dma = tp->shared_dma + shared_offset(txLo);
1234 iface->txLoAddr = cpu_to_le32(shared_dma);
1235 iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1236
1237 shared_dma = tp->shared_dma + shared_offset(txHi);
1238 iface->txHiAddr = cpu_to_le32(shared_dma);
1239 iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1240
1241 shared_dma = tp->shared_dma + shared_offset(rxBuff);
1242 iface->rxBuffAddr = cpu_to_le32(shared_dma);
1243 iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1244 sizeof(struct rx_free));
1245
1246 shared_dma = tp->shared_dma + shared_offset(rxLo);
1247 iface->rxLoAddr = cpu_to_le32(shared_dma);
1248 iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1249
1250 shared_dma = tp->shared_dma + shared_offset(rxHi);
1251 iface->rxHiAddr = cpu_to_le32(shared_dma);
1252 iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1253
1254 shared_dma = tp->shared_dma + shared_offset(cmd);
1255 iface->cmdAddr = cpu_to_le32(shared_dma);
1256 iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1257
1258 shared_dma = tp->shared_dma + shared_offset(resp);
1259 iface->respAddr = cpu_to_le32(shared_dma);
1260 iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1261
1262 shared_dma = tp->shared_dma + shared_offset(zeroWord);
1263 iface->zeroAddr = cpu_to_le32(shared_dma);
1264
1265 tp->indexes = &tp->shared->indexes;
1266 tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1267 tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1268 tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1269 tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1270 tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1271 tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1272 tp->respRing.ringBase = (u8 *) tp->shared->resp;
1273
1274 tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1275 tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1276
1277 tp->txlo_dma_addr = le32_to_cpu(iface->txLoAddr);
1278 tp->card_state = Sleeping;
1279
1280 tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1281 tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1282 tp->offload |= TYPHOON_OFFLOAD_VLAN;
1283
1284 spin_lock_init(&tp->command_lock);
1285
1286 /* Force the writes to the shared memory area out before continuing. */
1287 wmb();
1288 }
1289
1290 static void
1291 typhoon_init_rings(struct typhoon *tp)
1292 {
1293 memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1294
1295 tp->txLoRing.lastWrite = 0;
1296 tp->txHiRing.lastWrite = 0;
1297 tp->rxLoRing.lastWrite = 0;
1298 tp->rxHiRing.lastWrite = 0;
1299 tp->rxBuffRing.lastWrite = 0;
1300 tp->cmdRing.lastWrite = 0;
1301 tp->respRing.lastWrite = 0;
1302
1303 tp->txLoRing.lastRead = 0;
1304 tp->txHiRing.lastRead = 0;
1305 }
1306
1307 static const struct firmware *typhoon_fw;
1308
1309 static int
1310 typhoon_request_firmware(struct typhoon *tp)
1311 {
1312 const struct typhoon_file_header *fHdr;
1313 const struct typhoon_section_header *sHdr;
1314 const u8 *image_data;
1315 u32 numSections;
1316 u32 section_len;
1317 u32 remaining;
1318 int err;
1319
1320 if (typhoon_fw)
1321 return 0;
1322
1323 err = request_firmware(&typhoon_fw, FIRMWARE_NAME, &tp->pdev->dev);
1324 if (err) {
1325 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
1326 FIRMWARE_NAME);
1327 return err;
1328 }
1329
1330 image_data = (u8 *) typhoon_fw->data;
1331 remaining = typhoon_fw->size;
1332 if (remaining < sizeof(struct typhoon_file_header))
1333 goto invalid_fw;
1334
1335 fHdr = (struct typhoon_file_header *) image_data;
1336 if (memcmp(fHdr->tag, "TYPHOON", 8))
1337 goto invalid_fw;
1338
1339 numSections = le32_to_cpu(fHdr->numSections);
1340 image_data += sizeof(struct typhoon_file_header);
1341 remaining -= sizeof(struct typhoon_file_header);
1342
1343 while (numSections--) {
1344 if (remaining < sizeof(struct typhoon_section_header))
1345 goto invalid_fw;
1346
1347 sHdr = (struct typhoon_section_header *) image_data;
1348 image_data += sizeof(struct typhoon_section_header);
1349 section_len = le32_to_cpu(sHdr->len);
1350
1351 if (remaining < section_len)
1352 goto invalid_fw;
1353
1354 image_data += section_len;
1355 remaining -= section_len;
1356 }
1357
1358 return 0;
1359
1360 invalid_fw:
1361 netdev_err(tp->dev, "Invalid firmware image\n");
1362 release_firmware(typhoon_fw);
1363 typhoon_fw = NULL;
1364 return -EINVAL;
1365 }
1366
1367 static int
1368 typhoon_download_firmware(struct typhoon *tp)
1369 {
1370 void __iomem *ioaddr = tp->ioaddr;
1371 struct pci_dev *pdev = tp->pdev;
1372 const struct typhoon_file_header *fHdr;
1373 const struct typhoon_section_header *sHdr;
1374 const u8 *image_data;
1375 void *dpage;
1376 dma_addr_t dpage_dma;
1377 __sum16 csum;
1378 u32 irqEnabled;
1379 u32 irqMasked;
1380 u32 numSections;
1381 u32 section_len;
1382 u32 len;
1383 u32 load_addr;
1384 u32 hmac;
1385 int i;
1386 int err;
1387
1388 image_data = (u8 *) typhoon_fw->data;
1389 fHdr = (struct typhoon_file_header *) image_data;
1390
1391 /* Cannot just map the firmware image using pci_map_single() as
1392 * the firmware is vmalloc()'d and may not be physically contiguous,
1393 * so we allocate some consistent memory to copy the sections into.
1394 */
1395 err = -ENOMEM;
1396 dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1397 if(!dpage) {
1398 netdev_err(tp->dev, "no DMA mem for firmware\n");
1399 goto err_out;
1400 }
1401
1402 irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1403 iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1404 ioaddr + TYPHOON_REG_INTR_ENABLE);
1405 irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1406 iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1407 ioaddr + TYPHOON_REG_INTR_MASK);
1408
1409 err = -ETIMEDOUT;
1410 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1411 netdev_err(tp->dev, "card ready timeout\n");
1412 goto err_out_irq;
1413 }
1414
1415 numSections = le32_to_cpu(fHdr->numSections);
1416 load_addr = le32_to_cpu(fHdr->startAddr);
1417
1418 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1419 iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1420 hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1421 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1422 hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1423 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1424 hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1425 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1426 hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1427 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1428 hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1429 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1430 typhoon_post_pci_writes(ioaddr);
1431 iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1432
1433 image_data += sizeof(struct typhoon_file_header);
1434
1435 /* The ioread32() in typhoon_wait_interrupt() will force the
1436 * last write to the command register to post, so
1437 * we don't need a typhoon_post_pci_writes() after it.
1438 */
1439 for(i = 0; i < numSections; i++) {
1440 sHdr = (struct typhoon_section_header *) image_data;
1441 image_data += sizeof(struct typhoon_section_header);
1442 load_addr = le32_to_cpu(sHdr->startAddr);
1443 section_len = le32_to_cpu(sHdr->len);
1444
1445 while(section_len) {
1446 len = min_t(u32, section_len, PAGE_SIZE);
1447
1448 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1449 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1450 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1451 netdev_err(tp->dev, "segment ready timeout\n");
1452 goto err_out_irq;
1453 }
1454
1455 /* Do an pseudo IPv4 checksum on the data -- first
1456 * need to convert each u16 to cpu order before
1457 * summing. Fortunately, due to the properties of
1458 * the checksum, we can do this once, at the end.
1459 */
1460 csum = csum_fold(csum_partial_copy_nocheck(image_data,
1461 dpage, len,
1462 0));
1463
1464 iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1465 iowrite32(le16_to_cpu((__force __le16)csum),
1466 ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1467 iowrite32(load_addr,
1468 ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1469 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1470 iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1471 typhoon_post_pci_writes(ioaddr);
1472 iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1473 ioaddr + TYPHOON_REG_COMMAND);
1474
1475 image_data += len;
1476 load_addr += len;
1477 section_len -= len;
1478 }
1479 }
1480
1481 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1482 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1483 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1484 netdev_err(tp->dev, "final segment ready timeout\n");
1485 goto err_out_irq;
1486 }
1487
1488 iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1489
1490 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1491 netdev_err(tp->dev, "boot ready timeout, status 0x%0x\n",
1492 ioread32(ioaddr + TYPHOON_REG_STATUS));
1493 goto err_out_irq;
1494 }
1495
1496 err = 0;
1497
1498 err_out_irq:
1499 iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1500 iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1501
1502 pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1503
1504 err_out:
1505 return err;
1506 }
1507
1508 static int
1509 typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1510 {
1511 void __iomem *ioaddr = tp->ioaddr;
1512
1513 if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1514 netdev_err(tp->dev, "boot ready timeout\n");
1515 goto out_timeout;
1516 }
1517
1518 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1519 iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1520 typhoon_post_pci_writes(ioaddr);
1521 iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1522 ioaddr + TYPHOON_REG_COMMAND);
1523
1524 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1525 netdev_err(tp->dev, "boot finish timeout (status 0x%x)\n",
1526 ioread32(ioaddr + TYPHOON_REG_STATUS));
1527 goto out_timeout;
1528 }
1529
1530 /* Clear the Transmit and Command ready registers
1531 */
1532 iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1533 iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1534 iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1535 typhoon_post_pci_writes(ioaddr);
1536 iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1537
1538 return 0;
1539
1540 out_timeout:
1541 return -ETIMEDOUT;
1542 }
1543
1544 static u32
1545 typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1546 volatile __le32 * index)
1547 {
1548 u32 lastRead = txRing->lastRead;
1549 struct tx_desc *tx;
1550 dma_addr_t skb_dma;
1551 int dma_len;
1552 int type;
1553
1554 while(lastRead != le32_to_cpu(*index)) {
1555 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1556 type = tx->flags & TYPHOON_TYPE_MASK;
1557
1558 if(type == TYPHOON_TX_DESC) {
1559 /* This tx_desc describes a packet.
1560 */
1561 unsigned long ptr = tx->tx_addr;
1562 struct sk_buff *skb = (struct sk_buff *) ptr;
1563 dev_kfree_skb_irq(skb);
1564 } else if(type == TYPHOON_FRAG_DESC) {
1565 /* This tx_desc describes a memory mapping. Free it.
1566 */
1567 skb_dma = (dma_addr_t) le32_to_cpu(tx->frag.addr);
1568 dma_len = le16_to_cpu(tx->len);
1569 pci_unmap_single(tp->pdev, skb_dma, dma_len,
1570 PCI_DMA_TODEVICE);
1571 }
1572
1573 tx->flags = 0;
1574 typhoon_inc_tx_index(&lastRead, 1);
1575 }
1576
1577 return lastRead;
1578 }
1579
1580 static void
1581 typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1582 volatile __le32 * index)
1583 {
1584 u32 lastRead;
1585 int numDesc = MAX_SKB_FRAGS + 1;
1586
1587 /* This will need changing if we start to use the Hi Tx ring. */
1588 lastRead = typhoon_clean_tx(tp, txRing, index);
1589 if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1590 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1591 netif_wake_queue(tp->dev);
1592
1593 txRing->lastRead = lastRead;
1594 smp_wmb();
1595 }
1596
1597 static void
1598 typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1599 {
1600 struct typhoon_indexes *indexes = tp->indexes;
1601 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1602 struct basic_ring *ring = &tp->rxBuffRing;
1603 struct rx_free *r;
1604
1605 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1606 le32_to_cpu(indexes->rxBuffCleared)) {
1607 /* no room in ring, just drop the skb
1608 */
1609 dev_kfree_skb_any(rxb->skb);
1610 rxb->skb = NULL;
1611 return;
1612 }
1613
1614 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1615 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1616 r->virtAddr = idx;
1617 r->physAddr = cpu_to_le32(rxb->dma_addr);
1618
1619 /* Tell the card about it */
1620 wmb();
1621 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1622 }
1623
1624 static int
1625 typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1626 {
1627 struct typhoon_indexes *indexes = tp->indexes;
1628 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1629 struct basic_ring *ring = &tp->rxBuffRing;
1630 struct rx_free *r;
1631 struct sk_buff *skb;
1632 dma_addr_t dma_addr;
1633
1634 rxb->skb = NULL;
1635
1636 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1637 le32_to_cpu(indexes->rxBuffCleared))
1638 return -ENOMEM;
1639
1640 skb = dev_alloc_skb(PKT_BUF_SZ);
1641 if(!skb)
1642 return -ENOMEM;
1643
1644 #if 0
1645 /* Please, 3com, fix the firmware to allow DMA to a unaligned
1646 * address! Pretty please?
1647 */
1648 skb_reserve(skb, 2);
1649 #endif
1650
1651 skb->dev = tp->dev;
1652 dma_addr = pci_map_single(tp->pdev, skb->data,
1653 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1654
1655 /* Since no card does 64 bit DAC, the high bits will never
1656 * change from zero.
1657 */
1658 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1659 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1660 r->virtAddr = idx;
1661 r->physAddr = cpu_to_le32(dma_addr);
1662 rxb->skb = skb;
1663 rxb->dma_addr = dma_addr;
1664
1665 /* Tell the card about it */
1666 wmb();
1667 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1668 return 0;
1669 }
1670
1671 static int
1672 typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready,
1673 volatile __le32 * cleared, int budget)
1674 {
1675 struct rx_desc *rx;
1676 struct sk_buff *skb, *new_skb;
1677 struct rxbuff_ent *rxb;
1678 dma_addr_t dma_addr;
1679 u32 local_ready;
1680 u32 rxaddr;
1681 int pkt_len;
1682 u32 idx;
1683 __le32 csum_bits;
1684 int received;
1685
1686 received = 0;
1687 local_ready = le32_to_cpu(*ready);
1688 rxaddr = le32_to_cpu(*cleared);
1689 while(rxaddr != local_ready && budget > 0) {
1690 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1691 idx = rx->addr;
1692 rxb = &tp->rxbuffers[idx];
1693 skb = rxb->skb;
1694 dma_addr = rxb->dma_addr;
1695
1696 typhoon_inc_rx_index(&rxaddr, 1);
1697
1698 if(rx->flags & TYPHOON_RX_ERROR) {
1699 typhoon_recycle_rx_skb(tp, idx);
1700 continue;
1701 }
1702
1703 pkt_len = le16_to_cpu(rx->frameLen);
1704
1705 if(pkt_len < rx_copybreak &&
1706 (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1707 skb_reserve(new_skb, 2);
1708 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1709 PKT_BUF_SZ,
1710 PCI_DMA_FROMDEVICE);
1711 skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1712 pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1713 PKT_BUF_SZ,
1714 PCI_DMA_FROMDEVICE);
1715 skb_put(new_skb, pkt_len);
1716 typhoon_recycle_rx_skb(tp, idx);
1717 } else {
1718 new_skb = skb;
1719 skb_put(new_skb, pkt_len);
1720 pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1721 PCI_DMA_FROMDEVICE);
1722 typhoon_alloc_rx_skb(tp, idx);
1723 }
1724 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1725 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1726 TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1727 if(csum_bits ==
1728 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD) ||
1729 csum_bits ==
1730 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1731 new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1732 } else
1733 skb_checksum_none_assert(new_skb);
1734
1735 if (rx->rxStatus & TYPHOON_RX_VLAN)
1736 __vlan_hwaccel_put_tag(new_skb,
1737 ntohl(rx->vlanTag) & 0xffff);
1738 netif_receive_skb(new_skb);
1739
1740 received++;
1741 budget--;
1742 }
1743 *cleared = cpu_to_le32(rxaddr);
1744
1745 return received;
1746 }
1747
1748 static void
1749 typhoon_fill_free_ring(struct typhoon *tp)
1750 {
1751 u32 i;
1752
1753 for(i = 0; i < RXENT_ENTRIES; i++) {
1754 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1755 if(rxb->skb)
1756 continue;
1757 if(typhoon_alloc_rx_skb(tp, i) < 0)
1758 break;
1759 }
1760 }
1761
1762 static int
1763 typhoon_poll(struct napi_struct *napi, int budget)
1764 {
1765 struct typhoon *tp = container_of(napi, struct typhoon, napi);
1766 struct typhoon_indexes *indexes = tp->indexes;
1767 int work_done;
1768
1769 rmb();
1770 if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1771 typhoon_process_response(tp, 0, NULL);
1772
1773 if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1774 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1775
1776 work_done = 0;
1777
1778 if(indexes->rxHiCleared != indexes->rxHiReady) {
1779 work_done += typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1780 &indexes->rxHiCleared, budget);
1781 }
1782
1783 if(indexes->rxLoCleared != indexes->rxLoReady) {
1784 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1785 &indexes->rxLoCleared, budget - work_done);
1786 }
1787
1788 if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1789 /* rxBuff ring is empty, try to fill it. */
1790 typhoon_fill_free_ring(tp);
1791 }
1792
1793 if (work_done < budget) {
1794 napi_complete(napi);
1795 iowrite32(TYPHOON_INTR_NONE,
1796 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1797 typhoon_post_pci_writes(tp->ioaddr);
1798 }
1799
1800 return work_done;
1801 }
1802
1803 static irqreturn_t
1804 typhoon_interrupt(int irq, void *dev_instance)
1805 {
1806 struct net_device *dev = dev_instance;
1807 struct typhoon *tp = netdev_priv(dev);
1808 void __iomem *ioaddr = tp->ioaddr;
1809 u32 intr_status;
1810
1811 intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1812 if(!(intr_status & TYPHOON_INTR_HOST_INT))
1813 return IRQ_NONE;
1814
1815 iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1816
1817 if (napi_schedule_prep(&tp->napi)) {
1818 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1819 typhoon_post_pci_writes(ioaddr);
1820 __napi_schedule(&tp->napi);
1821 } else {
1822 netdev_err(dev, "Error, poll already scheduled\n");
1823 }
1824 return IRQ_HANDLED;
1825 }
1826
1827 static void
1828 typhoon_free_rx_rings(struct typhoon *tp)
1829 {
1830 u32 i;
1831
1832 for(i = 0; i < RXENT_ENTRIES; i++) {
1833 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1834 if(rxb->skb) {
1835 pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1836 PCI_DMA_FROMDEVICE);
1837 dev_kfree_skb(rxb->skb);
1838 rxb->skb = NULL;
1839 }
1840 }
1841 }
1842
1843 static int
1844 typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events)
1845 {
1846 struct pci_dev *pdev = tp->pdev;
1847 void __iomem *ioaddr = tp->ioaddr;
1848 struct cmd_desc xp_cmd;
1849 int err;
1850
1851 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1852 xp_cmd.parm1 = events;
1853 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1854 if(err < 0) {
1855 netdev_err(tp->dev, "typhoon_sleep(): wake events cmd err %d\n",
1856 err);
1857 return err;
1858 }
1859
1860 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1861 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1862 if(err < 0) {
1863 netdev_err(tp->dev, "typhoon_sleep(): sleep cmd err %d\n", err);
1864 return err;
1865 }
1866
1867 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1868 return -ETIMEDOUT;
1869
1870 /* Since we cannot monitor the status of the link while sleeping,
1871 * tell the world it went away.
1872 */
1873 netif_carrier_off(tp->dev);
1874
1875 pci_enable_wake(tp->pdev, state, 1);
1876 pci_disable_device(pdev);
1877 return pci_set_power_state(pdev, state);
1878 }
1879
1880 static int
1881 typhoon_wakeup(struct typhoon *tp, int wait_type)
1882 {
1883 struct pci_dev *pdev = tp->pdev;
1884 void __iomem *ioaddr = tp->ioaddr;
1885
1886 pci_set_power_state(pdev, PCI_D0);
1887 pci_restore_state(pdev);
1888
1889 /* Post 2.x.x versions of the Sleep Image require a reset before
1890 * we can download the Runtime Image. But let's not make users of
1891 * the old firmware pay for the reset.
1892 */
1893 iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1894 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1895 (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1896 return typhoon_reset(ioaddr, wait_type);
1897
1898 return 0;
1899 }
1900
1901 static int
1902 typhoon_start_runtime(struct typhoon *tp)
1903 {
1904 struct net_device *dev = tp->dev;
1905 void __iomem *ioaddr = tp->ioaddr;
1906 struct cmd_desc xp_cmd;
1907 int err;
1908
1909 typhoon_init_rings(tp);
1910 typhoon_fill_free_ring(tp);
1911
1912 err = typhoon_download_firmware(tp);
1913 if(err < 0) {
1914 netdev_err(tp->dev, "cannot load runtime on 3XP\n");
1915 goto error_out;
1916 }
1917
1918 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1919 netdev_err(tp->dev, "cannot boot 3XP\n");
1920 err = -EIO;
1921 goto error_out;
1922 }
1923
1924 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1925 xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1926 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1927 if(err < 0)
1928 goto error_out;
1929
1930 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1931 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
1932 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
1933 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1934 if(err < 0)
1935 goto error_out;
1936
1937 /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1938 * us some more information on how to control it.
1939 */
1940 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1941 xp_cmd.parm1 = 0;
1942 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1943 if(err < 0)
1944 goto error_out;
1945
1946 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1947 xp_cmd.parm1 = tp->xcvr_select;
1948 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1949 if(err < 0)
1950 goto error_out;
1951
1952 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1953 xp_cmd.parm1 = cpu_to_le16(ETH_P_8021Q);
1954 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1955 if(err < 0)
1956 goto error_out;
1957
1958 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1959 xp_cmd.parm2 = tp->offload;
1960 xp_cmd.parm3 = tp->offload;
1961 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1962 if(err < 0)
1963 goto error_out;
1964
1965 typhoon_set_rx_mode(dev);
1966
1967 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1968 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1969 if(err < 0)
1970 goto error_out;
1971
1972 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1973 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1974 if(err < 0)
1975 goto error_out;
1976
1977 tp->card_state = Running;
1978 smp_wmb();
1979
1980 iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1981 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
1982 typhoon_post_pci_writes(ioaddr);
1983
1984 return 0;
1985
1986 error_out:
1987 typhoon_reset(ioaddr, WaitNoSleep);
1988 typhoon_free_rx_rings(tp);
1989 typhoon_init_rings(tp);
1990 return err;
1991 }
1992
1993 static int
1994 typhoon_stop_runtime(struct typhoon *tp, int wait_type)
1995 {
1996 struct typhoon_indexes *indexes = tp->indexes;
1997 struct transmit_ring *txLo = &tp->txLoRing;
1998 void __iomem *ioaddr = tp->ioaddr;
1999 struct cmd_desc xp_cmd;
2000 int i;
2001
2002 /* Disable interrupts early, since we can't schedule a poll
2003 * when called with !netif_running(). This will be posted
2004 * when we force the posting of the command.
2005 */
2006 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2007
2008 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
2009 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2010
2011 /* Wait 1/2 sec for any outstanding transmits to occur
2012 * We'll cleanup after the reset if this times out.
2013 */
2014 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
2015 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
2016 break;
2017 udelay(TYPHOON_UDELAY);
2018 }
2019
2020 if(i == TYPHOON_WAIT_TIMEOUT)
2021 netdev_err(tp->dev, "halt timed out waiting for Tx to complete\n");
2022
2023 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
2024 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2025
2026 /* save the statistics so when we bring the interface up again,
2027 * the values reported to userspace are correct.
2028 */
2029 tp->card_state = Sleeping;
2030 smp_wmb();
2031 typhoon_do_get_stats(tp);
2032 memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2033
2034 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2035 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2036
2037 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2038 netdev_err(tp->dev, "timed out waiting for 3XP to halt\n");
2039
2040 if(typhoon_reset(ioaddr, wait_type) < 0) {
2041 netdev_err(tp->dev, "unable to reset 3XP\n");
2042 return -ETIMEDOUT;
2043 }
2044
2045 /* cleanup any outstanding Tx packets */
2046 if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2047 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2048 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2049 }
2050
2051 return 0;
2052 }
2053
2054 static void
2055 typhoon_tx_timeout(struct net_device *dev)
2056 {
2057 struct typhoon *tp = netdev_priv(dev);
2058
2059 if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2060 netdev_warn(dev, "could not reset in tx timeout\n");
2061 goto truly_dead;
2062 }
2063
2064 /* If we ever start using the Hi ring, it will need cleaning too */
2065 typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2066 typhoon_free_rx_rings(tp);
2067
2068 if(typhoon_start_runtime(tp) < 0) {
2069 netdev_err(dev, "could not start runtime in tx timeout\n");
2070 goto truly_dead;
2071 }
2072
2073 netif_wake_queue(dev);
2074 return;
2075
2076 truly_dead:
2077 /* Reset the hardware, and turn off carrier to avoid more timeouts */
2078 typhoon_reset(tp->ioaddr, NoWait);
2079 netif_carrier_off(dev);
2080 }
2081
2082 static int
2083 typhoon_open(struct net_device *dev)
2084 {
2085 struct typhoon *tp = netdev_priv(dev);
2086 int err;
2087
2088 err = typhoon_request_firmware(tp);
2089 if (err)
2090 goto out;
2091
2092 err = typhoon_wakeup(tp, WaitSleep);
2093 if(err < 0) {
2094 netdev_err(dev, "unable to wakeup device\n");
2095 goto out_sleep;
2096 }
2097
2098 err = request_irq(dev->irq, typhoon_interrupt, IRQF_SHARED,
2099 dev->name, dev);
2100 if(err < 0)
2101 goto out_sleep;
2102
2103 napi_enable(&tp->napi);
2104
2105 err = typhoon_start_runtime(tp);
2106 if(err < 0) {
2107 napi_disable(&tp->napi);
2108 goto out_irq;
2109 }
2110
2111 netif_start_queue(dev);
2112 return 0;
2113
2114 out_irq:
2115 free_irq(dev->irq, dev);
2116
2117 out_sleep:
2118 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2119 netdev_err(dev, "unable to reboot into sleep img\n");
2120 typhoon_reset(tp->ioaddr, NoWait);
2121 goto out;
2122 }
2123
2124 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2125 netdev_err(dev, "unable to go back to sleep\n");
2126
2127 out:
2128 return err;
2129 }
2130
2131 static int
2132 typhoon_close(struct net_device *dev)
2133 {
2134 struct typhoon *tp = netdev_priv(dev);
2135
2136 netif_stop_queue(dev);
2137 napi_disable(&tp->napi);
2138
2139 if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2140 netdev_err(dev, "unable to stop runtime\n");
2141
2142 /* Make sure there is no irq handler running on a different CPU. */
2143 free_irq(dev->irq, dev);
2144
2145 typhoon_free_rx_rings(tp);
2146 typhoon_init_rings(tp);
2147
2148 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2149 netdev_err(dev, "unable to boot sleep image\n");
2150
2151 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2152 netdev_err(dev, "unable to put card to sleep\n");
2153
2154 return 0;
2155 }
2156
2157 #ifdef CONFIG_PM
2158 static int
2159 typhoon_resume(struct pci_dev *pdev)
2160 {
2161 struct net_device *dev = pci_get_drvdata(pdev);
2162 struct typhoon *tp = netdev_priv(dev);
2163
2164 /* If we're down, resume when we are upped.
2165 */
2166 if(!netif_running(dev))
2167 return 0;
2168
2169 if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2170 netdev_err(dev, "critical: could not wake up in resume\n");
2171 goto reset;
2172 }
2173
2174 if(typhoon_start_runtime(tp) < 0) {
2175 netdev_err(dev, "critical: could not start runtime in resume\n");
2176 goto reset;
2177 }
2178
2179 netif_device_attach(dev);
2180 return 0;
2181
2182 reset:
2183 typhoon_reset(tp->ioaddr, NoWait);
2184 return -EBUSY;
2185 }
2186
2187 static int
2188 typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2189 {
2190 struct net_device *dev = pci_get_drvdata(pdev);
2191 struct typhoon *tp = netdev_priv(dev);
2192 struct cmd_desc xp_cmd;
2193
2194 /* If we're down, we're already suspended.
2195 */
2196 if(!netif_running(dev))
2197 return 0;
2198
2199 /* TYPHOON_OFFLOAD_VLAN is always on now, so this doesn't work */
2200 if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
2201 netdev_warn(dev, "cannot do WAKE_MAGIC with VLAN offloading\n");
2202
2203 netif_device_detach(dev);
2204
2205 if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2206 netdev_err(dev, "unable to stop runtime\n");
2207 goto need_resume;
2208 }
2209
2210 typhoon_free_rx_rings(tp);
2211 typhoon_init_rings(tp);
2212
2213 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2214 netdev_err(dev, "unable to boot sleep image\n");
2215 goto need_resume;
2216 }
2217
2218 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2219 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
2220 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
2221 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2222 netdev_err(dev, "unable to set mac address in suspend\n");
2223 goto need_resume;
2224 }
2225
2226 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2227 xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2228 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2229 netdev_err(dev, "unable to set rx filter in suspend\n");
2230 goto need_resume;
2231 }
2232
2233 if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2234 netdev_err(dev, "unable to put card to sleep\n");
2235 goto need_resume;
2236 }
2237
2238 return 0;
2239
2240 need_resume:
2241 typhoon_resume(pdev);
2242 return -EBUSY;
2243 }
2244 #endif
2245
2246 static int __devinit
2247 typhoon_test_mmio(struct pci_dev *pdev)
2248 {
2249 void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2250 int mode = 0;
2251 u32 val;
2252
2253 if(!ioaddr)
2254 goto out;
2255
2256 if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2257 TYPHOON_STATUS_WAITING_FOR_HOST)
2258 goto out_unmap;
2259
2260 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2261 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2262 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2263
2264 /* Ok, see if we can change our interrupt status register by
2265 * sending ourselves an interrupt. If so, then MMIO works.
2266 * The 50usec delay is arbitrary -- it could probably be smaller.
2267 */
2268 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2269 if((val & TYPHOON_INTR_SELF) == 0) {
2270 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2271 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2272 udelay(50);
2273 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2274 if(val & TYPHOON_INTR_SELF)
2275 mode = 1;
2276 }
2277
2278 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2279 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2280 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2281 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2282
2283 out_unmap:
2284 pci_iounmap(pdev, ioaddr);
2285
2286 out:
2287 if(!mode)
2288 pr_info("%s: falling back to port IO\n", pci_name(pdev));
2289 return mode;
2290 }
2291
2292 static const struct net_device_ops typhoon_netdev_ops = {
2293 .ndo_open = typhoon_open,
2294 .ndo_stop = typhoon_close,
2295 .ndo_start_xmit = typhoon_start_tx,
2296 .ndo_set_multicast_list = typhoon_set_rx_mode,
2297 .ndo_tx_timeout = typhoon_tx_timeout,
2298 .ndo_get_stats = typhoon_get_stats,
2299 .ndo_validate_addr = eth_validate_addr,
2300 .ndo_set_mac_address = typhoon_set_mac_address,
2301 .ndo_change_mtu = eth_change_mtu,
2302 };
2303
2304 static int __devinit
2305 typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2306 {
2307 struct net_device *dev;
2308 struct typhoon *tp;
2309 int card_id = (int) ent->driver_data;
2310 void __iomem *ioaddr;
2311 void *shared;
2312 dma_addr_t shared_dma;
2313 struct cmd_desc xp_cmd;
2314 struct resp_desc xp_resp[3];
2315 int err = 0;
2316 const char *err_msg;
2317
2318 dev = alloc_etherdev(sizeof(*tp));
2319 if(dev == NULL) {
2320 err_msg = "unable to alloc new net device";
2321 err = -ENOMEM;
2322 goto error_out;
2323 }
2324 SET_NETDEV_DEV(dev, &pdev->dev);
2325
2326 err = pci_enable_device(pdev);
2327 if(err < 0) {
2328 err_msg = "unable to enable device";
2329 goto error_out_dev;
2330 }
2331
2332 err = pci_set_mwi(pdev);
2333 if(err < 0) {
2334 err_msg = "unable to set MWI";
2335 goto error_out_disable;
2336 }
2337
2338 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2339 if(err < 0) {
2340 err_msg = "No usable DMA configuration";
2341 goto error_out_mwi;
2342 }
2343
2344 /* sanity checks on IO and MMIO BARs
2345 */
2346 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2347 err_msg = "region #1 not a PCI IO resource, aborting";
2348 err = -ENODEV;
2349 goto error_out_mwi;
2350 }
2351 if(pci_resource_len(pdev, 0) < 128) {
2352 err_msg = "Invalid PCI IO region size, aborting";
2353 err = -ENODEV;
2354 goto error_out_mwi;
2355 }
2356 if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2357 err_msg = "region #1 not a PCI MMIO resource, aborting";
2358 err = -ENODEV;
2359 goto error_out_mwi;
2360 }
2361 if(pci_resource_len(pdev, 1) < 128) {
2362 err_msg = "Invalid PCI MMIO region size, aborting";
2363 err = -ENODEV;
2364 goto error_out_mwi;
2365 }
2366
2367 err = pci_request_regions(pdev, KBUILD_MODNAME);
2368 if(err < 0) {
2369 err_msg = "could not request regions";
2370 goto error_out_mwi;
2371 }
2372
2373 /* map our registers
2374 */
2375 if(use_mmio != 0 && use_mmio != 1)
2376 use_mmio = typhoon_test_mmio(pdev);
2377
2378 ioaddr = pci_iomap(pdev, use_mmio, 128);
2379 if (!ioaddr) {
2380 err_msg = "cannot remap registers, aborting";
2381 err = -EIO;
2382 goto error_out_regions;
2383 }
2384
2385 /* allocate pci dma space for rx and tx descriptor rings
2386 */
2387 shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2388 &shared_dma);
2389 if(!shared) {
2390 err_msg = "could not allocate DMA memory";
2391 err = -ENOMEM;
2392 goto error_out_remap;
2393 }
2394
2395 dev->irq = pdev->irq;
2396 tp = netdev_priv(dev);
2397 tp->shared = (struct typhoon_shared *) shared;
2398 tp->shared_dma = shared_dma;
2399 tp->pdev = pdev;
2400 tp->tx_pdev = pdev;
2401 tp->ioaddr = ioaddr;
2402 tp->tx_ioaddr = ioaddr;
2403 tp->dev = dev;
2404
2405 /* Init sequence:
2406 * 1) Reset the adapter to clear any bad juju
2407 * 2) Reload the sleep image
2408 * 3) Boot the sleep image
2409 * 4) Get the hardware address.
2410 * 5) Put the card to sleep.
2411 */
2412 if (typhoon_reset(ioaddr, WaitSleep) < 0) {
2413 err_msg = "could not reset 3XP";
2414 err = -EIO;
2415 goto error_out_dma;
2416 }
2417
2418 /* Now that we've reset the 3XP and are sure it's not going to
2419 * write all over memory, enable bus mastering, and save our
2420 * state for resuming after a suspend.
2421 */
2422 pci_set_master(pdev);
2423 pci_save_state(pdev);
2424
2425 typhoon_init_interface(tp);
2426 typhoon_init_rings(tp);
2427
2428 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2429 err_msg = "cannot boot 3XP sleep image";
2430 err = -EIO;
2431 goto error_out_reset;
2432 }
2433
2434 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2435 if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2436 err_msg = "cannot read MAC address";
2437 err = -EIO;
2438 goto error_out_reset;
2439 }
2440
2441 *(__be16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2442 *(__be32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2443
2444 if(!is_valid_ether_addr(dev->dev_addr)) {
2445 err_msg = "Could not obtain valid ethernet address, aborting";
2446 goto error_out_reset;
2447 }
2448
2449 /* Read the Sleep Image version last, so the response is valid
2450 * later when we print out the version reported.
2451 */
2452 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2453 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2454 err_msg = "Could not get Sleep Image version";
2455 goto error_out_reset;
2456 }
2457
2458 tp->capabilities = typhoon_card_info[card_id].capabilities;
2459 tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2460
2461 /* Typhoon 1.0 Sleep Images return one response descriptor to the
2462 * READ_VERSIONS command. Those versions are OK after waking up
2463 * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2464 * seem to need a little extra help to get started. Since we don't
2465 * know how to nudge it along, just kick it.
2466 */
2467 if(xp_resp[0].numDesc != 0)
2468 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2469
2470 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
2471 err_msg = "cannot put adapter to sleep";
2472 err = -EIO;
2473 goto error_out_reset;
2474 }
2475
2476 /* The chip-specific entries in the device structure. */
2477 dev->netdev_ops = &typhoon_netdev_ops;
2478 netif_napi_add(dev, &tp->napi, typhoon_poll, 16);
2479 dev->watchdog_timeo = TX_TIMEOUT;
2480
2481 SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2482
2483 /* We can handle scatter gather, up to 16 entries, and
2484 * we can do IP checksumming (only version 4, doh...)
2485 */
2486 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2487 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2488 dev->features |= NETIF_F_TSO;
2489
2490 if(register_netdev(dev) < 0) {
2491 err_msg = "unable to register netdev";
2492 goto error_out_reset;
2493 }
2494
2495 pci_set_drvdata(pdev, dev);
2496
2497 netdev_info(dev, "%s at %s 0x%llx, %pM\n",
2498 typhoon_card_info[card_id].name,
2499 use_mmio ? "MMIO" : "IO",
2500 (unsigned long long)pci_resource_start(pdev, use_mmio),
2501 dev->dev_addr);
2502
2503 /* xp_resp still contains the response to the READ_VERSIONS command.
2504 * For debugging, let the user know what version he has.
2505 */
2506 if(xp_resp[0].numDesc == 0) {
2507 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2508 * of version is Month/Day of build.
2509 */
2510 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2511 netdev_info(dev, "Typhoon 1.0 Sleep Image built %02u/%02u/2000\n",
2512 monthday >> 8, monthday & 0xff);
2513 } else if(xp_resp[0].numDesc == 2) {
2514 /* This is the Typhoon 1.1+ type Sleep Image
2515 */
2516 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2517 u8 *ver_string = (u8 *) &xp_resp[1];
2518 ver_string[25] = 0;
2519 netdev_info(dev, "Typhoon 1.1+ Sleep Image version %02x.%03x.%03x %s\n",
2520 sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
2521 sleep_ver & 0xfff, ver_string);
2522 } else {
2523 netdev_warn(dev, "Unknown Sleep Image version (%u:%04x)\n",
2524 xp_resp[0].numDesc, le32_to_cpu(xp_resp[0].parm2));
2525 }
2526
2527 return 0;
2528
2529 error_out_reset:
2530 typhoon_reset(ioaddr, NoWait);
2531
2532 error_out_dma:
2533 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2534 shared, shared_dma);
2535 error_out_remap:
2536 pci_iounmap(pdev, ioaddr);
2537 error_out_regions:
2538 pci_release_regions(pdev);
2539 error_out_mwi:
2540 pci_clear_mwi(pdev);
2541 error_out_disable:
2542 pci_disable_device(pdev);
2543 error_out_dev:
2544 free_netdev(dev);
2545 error_out:
2546 pr_err("%s: %s\n", pci_name(pdev), err_msg);
2547 return err;
2548 }
2549
2550 static void __devexit
2551 typhoon_remove_one(struct pci_dev *pdev)
2552 {
2553 struct net_device *dev = pci_get_drvdata(pdev);
2554 struct typhoon *tp = netdev_priv(dev);
2555
2556 unregister_netdev(dev);
2557 pci_set_power_state(pdev, PCI_D0);
2558 pci_restore_state(pdev);
2559 typhoon_reset(tp->ioaddr, NoWait);
2560 pci_iounmap(pdev, tp->ioaddr);
2561 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2562 tp->shared, tp->shared_dma);
2563 pci_release_regions(pdev);
2564 pci_clear_mwi(pdev);
2565 pci_disable_device(pdev);
2566 pci_set_drvdata(pdev, NULL);
2567 free_netdev(dev);
2568 }
2569
2570 static struct pci_driver typhoon_driver = {
2571 .name = KBUILD_MODNAME,
2572 .id_table = typhoon_pci_tbl,
2573 .probe = typhoon_init_one,
2574 .remove = __devexit_p(typhoon_remove_one),
2575 #ifdef CONFIG_PM
2576 .suspend = typhoon_suspend,
2577 .resume = typhoon_resume,
2578 #endif
2579 };
2580
2581 static int __init
2582 typhoon_init(void)
2583 {
2584 return pci_register_driver(&typhoon_driver);
2585 }
2586
2587 static void __exit
2588 typhoon_cleanup(void)
2589 {
2590 if (typhoon_fw)
2591 release_firmware(typhoon_fw);
2592 pci_unregister_driver(&typhoon_driver);
2593 }
2594
2595 module_init(typhoon_init);
2596 module_exit(typhoon_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree