2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
8 #include <linux/delay.h>
11 #define MASK(n) ((1ULL<<(n))-1)
12 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
13 ((addr >> 25) & 0x3ff))
14 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
15 ((addr >> 25) & 0x3ff))
16 #define MS_WIN(addr) (addr & 0x0ffc0000)
17 #define QLA82XX_PCI_MN_2M (0)
18 #define QLA82XX_PCI_MS_2M (0x80000)
19 #define QLA82XX_PCI_OCM0_2M (0xc0000)
20 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
21 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
22 #define BLOCK_PROTECT_BITS 0x0F
24 /* CRB window related */
25 #define CRB_BLK(off) ((off >> 20) & 0x3f)
26 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
27 #define CRB_WINDOW_2M (0x130060)
28 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
29 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
31 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
32 #define CRB_INDIRECT_2M (0x1e0000UL)
34 #define MAX_CRB_XFORM 60
35 static unsigned long crb_addr_xform
[MAX_CRB_XFORM
];
36 int qla82xx_crb_table_initialized
;
38 #define qla82xx_crb_addr_transform(name) \
39 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
40 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
42 static void qla82xx_crb_addr_transform_setup(void)
44 qla82xx_crb_addr_transform(XDMA
);
45 qla82xx_crb_addr_transform(TIMR
);
46 qla82xx_crb_addr_transform(SRE
);
47 qla82xx_crb_addr_transform(SQN3
);
48 qla82xx_crb_addr_transform(SQN2
);
49 qla82xx_crb_addr_transform(SQN1
);
50 qla82xx_crb_addr_transform(SQN0
);
51 qla82xx_crb_addr_transform(SQS3
);
52 qla82xx_crb_addr_transform(SQS2
);
53 qla82xx_crb_addr_transform(SQS1
);
54 qla82xx_crb_addr_transform(SQS0
);
55 qla82xx_crb_addr_transform(RPMX7
);
56 qla82xx_crb_addr_transform(RPMX6
);
57 qla82xx_crb_addr_transform(RPMX5
);
58 qla82xx_crb_addr_transform(RPMX4
);
59 qla82xx_crb_addr_transform(RPMX3
);
60 qla82xx_crb_addr_transform(RPMX2
);
61 qla82xx_crb_addr_transform(RPMX1
);
62 qla82xx_crb_addr_transform(RPMX0
);
63 qla82xx_crb_addr_transform(ROMUSB
);
64 qla82xx_crb_addr_transform(SN
);
65 qla82xx_crb_addr_transform(QMN
);
66 qla82xx_crb_addr_transform(QMS
);
67 qla82xx_crb_addr_transform(PGNI
);
68 qla82xx_crb_addr_transform(PGND
);
69 qla82xx_crb_addr_transform(PGN3
);
70 qla82xx_crb_addr_transform(PGN2
);
71 qla82xx_crb_addr_transform(PGN1
);
72 qla82xx_crb_addr_transform(PGN0
);
73 qla82xx_crb_addr_transform(PGSI
);
74 qla82xx_crb_addr_transform(PGSD
);
75 qla82xx_crb_addr_transform(PGS3
);
76 qla82xx_crb_addr_transform(PGS2
);
77 qla82xx_crb_addr_transform(PGS1
);
78 qla82xx_crb_addr_transform(PGS0
);
79 qla82xx_crb_addr_transform(PS
);
80 qla82xx_crb_addr_transform(PH
);
81 qla82xx_crb_addr_transform(NIU
);
82 qla82xx_crb_addr_transform(I2Q
);
83 qla82xx_crb_addr_transform(EG
);
84 qla82xx_crb_addr_transform(MN
);
85 qla82xx_crb_addr_transform(MS
);
86 qla82xx_crb_addr_transform(CAS2
);
87 qla82xx_crb_addr_transform(CAS1
);
88 qla82xx_crb_addr_transform(CAS0
);
89 qla82xx_crb_addr_transform(CAM
);
90 qla82xx_crb_addr_transform(C2C1
);
91 qla82xx_crb_addr_transform(C2C0
);
92 qla82xx_crb_addr_transform(SMB
);
93 qla82xx_crb_addr_transform(OCM0
);
95 * Used only in P3 just define it for P2 also.
97 qla82xx_crb_addr_transform(I2C0
);
99 qla82xx_crb_table_initialized
= 1;
102 struct crb_128M_2M_block_map crb_128M_2M_map
[64] = {
104 {{{1, 0x0100000, 0x0102000, 0x120000},
105 {1, 0x0110000, 0x0120000, 0x130000},
106 {1, 0x0120000, 0x0122000, 0x124000},
107 {1, 0x0130000, 0x0132000, 0x126000},
108 {1, 0x0140000, 0x0142000, 0x128000},
109 {1, 0x0150000, 0x0152000, 0x12a000},
110 {1, 0x0160000, 0x0170000, 0x110000},
111 {1, 0x0170000, 0x0172000, 0x12e000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {1, 0x01e0000, 0x01e0800, 0x122000},
119 {0, 0x0000000, 0x0000000, 0x000000} } } ,
120 {{{1, 0x0200000, 0x0210000, 0x180000} } },
122 {{{1, 0x0400000, 0x0401000, 0x169000} } },
123 {{{1, 0x0500000, 0x0510000, 0x140000} } },
124 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
125 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
126 {{{1, 0x0800000, 0x0802000, 0x170000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {1, 0x08f0000, 0x08f2000, 0x172000} } },
142 {{{1, 0x0900000, 0x0902000, 0x174000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {1, 0x09f0000, 0x09f2000, 0x176000} } },
158 {{{0, 0x0a00000, 0x0a02000, 0x178000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
174 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
190 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
191 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
192 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
193 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
194 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
195 {{{1, 0x1100000, 0x1101000, 0x160000} } },
196 {{{1, 0x1200000, 0x1201000, 0x161000} } },
197 {{{1, 0x1300000, 0x1301000, 0x162000} } },
198 {{{1, 0x1400000, 0x1401000, 0x163000} } },
199 {{{1, 0x1500000, 0x1501000, 0x165000} } },
200 {{{1, 0x1600000, 0x1601000, 0x166000} } },
207 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
208 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
209 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
211 {{{1, 0x2100000, 0x2102000, 0x120000},
212 {1, 0x2110000, 0x2120000, 0x130000},
213 {1, 0x2120000, 0x2122000, 0x124000},
214 {1, 0x2130000, 0x2132000, 0x126000},
215 {1, 0x2140000, 0x2142000, 0x128000},
216 {1, 0x2150000, 0x2152000, 0x12a000},
217 {1, 0x2160000, 0x2170000, 0x110000},
218 {1, 0x2170000, 0x2172000, 0x12e000},
219 {0, 0x0000000, 0x0000000, 0x000000},
220 {0, 0x0000000, 0x0000000, 0x000000},
221 {0, 0x0000000, 0x0000000, 0x000000},
222 {0, 0x0000000, 0x0000000, 0x000000},
223 {0, 0x0000000, 0x0000000, 0x000000},
224 {0, 0x0000000, 0x0000000, 0x000000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000} } },
227 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
233 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
234 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
235 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
236 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
237 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
238 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
239 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
240 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
241 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
242 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
243 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
244 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
246 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
247 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
248 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
249 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
250 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
251 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
254 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
255 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
256 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
260 * top 12 bits of crb internal address (hub, agent)
262 unsigned qla82xx_crb_hub_agt
[64] = {
264 QLA82XX_HW_CRB_HUB_AGT_ADR_PS
,
265 QLA82XX_HW_CRB_HUB_AGT_ADR_MN
,
266 QLA82XX_HW_CRB_HUB_AGT_ADR_MS
,
268 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE
,
269 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU
,
270 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN
,
271 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0
,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1
,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2
,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3
,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q
,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR
,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB
,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4
,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA
,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0
,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1
,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2
,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3
,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND
,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI
,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0
,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1
,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2
,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3
,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI
,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_SN
,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_EG
,
296 QLA82XX_HW_CRB_HUB_AGT_ADR_PS
,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM
,
303 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR
,
305 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1
,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2
,
307 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3
,
308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4
,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5
,
310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6
,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7
,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA
,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q
,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB
,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0
,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8
,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9
,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0
,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB
,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0
,
323 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1
,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC
,
330 char *qdev_state
[] = {
342 * In: 'off' is offset from CRB space in 128M pci map
343 * Out: 'off' is 2M pci map addr
344 * side effect: lock crb window
347 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data
*ha
, ulong
*off
)
351 ha
->crb_win
= CRB_HI(*off
);
353 (void *)(CRB_WINDOW_2M
+ ha
->nx_pcibase
));
355 /* Read back value to make sure write has gone through before trying
358 win_read
= RD_REG_DWORD((void *)(CRB_WINDOW_2M
+ ha
->nx_pcibase
));
359 if (win_read
!= ha
->crb_win
) {
360 DEBUG2(qla_printk(KERN_INFO
, ha
,
361 "%s: Written crbwin (0x%x) != Read crbwin (0x%x), "
362 "off=0x%lx\n", __func__
, ha
->crb_win
, win_read
, *off
));
364 *off
= (*off
& MASK(16)) + CRB_INDIRECT_2M
+ ha
->nx_pcibase
;
367 static inline unsigned long
368 qla82xx_pci_set_crbwindow(struct qla_hw_data
*ha
, u64 off
)
370 /* See if we are currently pointing to the region we want to use next */
371 if ((off
>= QLA82XX_CRB_PCIX_HOST
) && (off
< QLA82XX_CRB_DDR_NET
)) {
372 /* No need to change window. PCIX and PCIEregs are in both
373 * regs are in both windows.
378 if ((off
>= QLA82XX_CRB_PCIX_HOST
) && (off
< QLA82XX_CRB_PCIX_HOST2
)) {
379 /* We are in first CRB window */
380 if (ha
->curr_window
!= 0)
385 if ((off
> QLA82XX_CRB_PCIX_HOST2
) && (off
< QLA82XX_CRB_MAX
)) {
386 /* We are in second CRB window */
387 off
= off
- QLA82XX_CRB_PCIX_HOST2
+ QLA82XX_CRB_PCIX_HOST
;
389 if (ha
->curr_window
!= 1)
392 /* We are in the QM or direct access
393 * register region - do nothing
395 if ((off
>= QLA82XX_PCI_DIRECT_CRB
) &&
396 (off
< QLA82XX_PCI_CAMQM_MAX
))
399 /* strange address given */
400 qla_printk(KERN_WARNING
, ha
,
401 "%s: Warning: unm_nic_pci_set_crbwindow called with"
402 " an unknown address(%llx)\n", QLA2XXX_DRIVER_NAME
, off
);
407 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data
*ha
, ulong
*off
)
409 struct crb_128M_2M_sub_block_map
*m
;
411 if (*off
>= QLA82XX_CRB_MAX
)
414 if (*off
>= QLA82XX_PCI_CAMQM
&& (*off
< QLA82XX_PCI_CAMQM_2M_END
)) {
415 *off
= (*off
- QLA82XX_PCI_CAMQM
) +
416 QLA82XX_PCI_CAMQM_2M_BASE
+ ha
->nx_pcibase
;
420 if (*off
< QLA82XX_PCI_CRBSPACE
)
423 *off
-= QLA82XX_PCI_CRBSPACE
;
426 m
= &crb_128M_2M_map
[CRB_BLK(*off
)].sub_block
[CRB_SUBBLK(*off
)];
428 if (m
->valid
&& (m
->start_128M
<= *off
) && (m
->end_128M
> *off
)) {
429 *off
= *off
+ m
->start_2M
- m
->start_128M
+ ha
->nx_pcibase
;
432 /* Not in direct map, use crb window */
436 #define CRB_WIN_LOCK_TIMEOUT 100000000
437 static int qla82xx_crb_win_lock(struct qla_hw_data
*ha
)
439 int done
= 0, timeout
= 0;
442 /* acquire semaphore3 from PCI HW block */
443 done
= qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK
));
446 if (timeout
>= CRB_WIN_LOCK_TIMEOUT
)
450 qla82xx_wr_32(ha
, QLA82XX_CRB_WIN_LOCK_ID
, ha
->portnum
);
455 qla82xx_wr_32(struct qla_hw_data
*ha
, ulong off
, u32 data
)
457 unsigned long flags
= 0;
460 rv
= qla82xx_pci_get_crb_addr_2M(ha
, &off
);
465 write_lock_irqsave(&ha
->hw_lock
, flags
);
466 qla82xx_crb_win_lock(ha
);
467 qla82xx_pci_set_crbwindow_2M(ha
, &off
);
470 writel(data
, (void __iomem
*)off
);
473 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK
));
474 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
480 qla82xx_rd_32(struct qla_hw_data
*ha
, ulong off
)
482 unsigned long flags
= 0;
486 rv
= qla82xx_pci_get_crb_addr_2M(ha
, &off
);
491 write_lock_irqsave(&ha
->hw_lock
, flags
);
492 qla82xx_crb_win_lock(ha
);
493 qla82xx_pci_set_crbwindow_2M(ha
, &off
);
495 data
= RD_REG_DWORD((void __iomem
*)off
);
498 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK
));
499 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
504 #define IDC_LOCK_TIMEOUT 100000000
505 int qla82xx_idc_lock(struct qla_hw_data
*ha
)
508 int done
= 0, timeout
= 0;
511 /* acquire semaphore5 from PCI HW block */
512 done
= qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK
));
515 if (timeout
>= IDC_LOCK_TIMEOUT
)
524 for (i
= 0; i
< 20; i
++)
532 void qla82xx_idc_unlock(struct qla_hw_data
*ha
)
534 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK
));
537 /* PCI Windowing for DDR regions. */
538 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
539 (((addr) <= (high)) && ((addr) >= (low)))
541 * check memory access boundary.
542 * used by test agent. support ddr access only for now
545 qla82xx_pci_mem_bound_check(struct qla_hw_data
*ha
,
546 unsigned long long addr
, int size
)
548 if (!QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_DDR_NET
,
549 QLA82XX_ADDR_DDR_NET_MAX
) ||
550 !QLA82XX_ADDR_IN_RANGE(addr
+ size
- 1, QLA82XX_ADDR_DDR_NET
,
551 QLA82XX_ADDR_DDR_NET_MAX
) ||
552 ((size
!= 1) && (size
!= 2) && (size
!= 4) && (size
!= 8)))
558 int qla82xx_pci_set_window_warning_count
;
561 qla82xx_pci_set_window(struct qla_hw_data
*ha
, unsigned long long addr
)
566 if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_DDR_NET
,
567 QLA82XX_ADDR_DDR_NET_MAX
)) {
568 /* DDR network side */
569 window
= MN_WIN(addr
);
570 ha
->ddr_mn_window
= window
;
572 ha
->mn_win_crb
| QLA82XX_PCI_CRBSPACE
, window
);
573 win_read
= qla82xx_rd_32(ha
,
574 ha
->mn_win_crb
| QLA82XX_PCI_CRBSPACE
);
575 if ((win_read
<< 17) != window
) {
576 qla_printk(KERN_WARNING
, ha
,
577 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
578 __func__
, window
, win_read
);
580 addr
= GET_MEM_OFFS_2M(addr
) + QLA82XX_PCI_DDR_NET
;
581 } else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_OCM0
,
582 QLA82XX_ADDR_OCM0_MAX
)) {
584 if ((addr
& 0x00ff800) == 0xff800) {
585 qla_printk(KERN_WARNING
, ha
,
586 "%s: QM access not handled.\n", __func__
);
589 window
= OCM_WIN(addr
);
590 ha
->ddr_mn_window
= window
;
592 ha
->mn_win_crb
| QLA82XX_PCI_CRBSPACE
, window
);
593 win_read
= qla82xx_rd_32(ha
,
594 ha
->mn_win_crb
| QLA82XX_PCI_CRBSPACE
);
595 temp1
= ((window
& 0x1FF) << 7) |
596 ((window
& 0x0FFFE0000) >> 17);
597 if (win_read
!= temp1
) {
598 qla_printk(KERN_WARNING
, ha
,
599 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x)\n",
600 __func__
, temp1
, win_read
);
602 addr
= GET_MEM_OFFS_2M(addr
) + QLA82XX_PCI_OCM0_2M
;
604 } else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_QDR_NET
,
605 QLA82XX_P3_ADDR_QDR_NET_MAX
)) {
606 /* QDR network side */
607 window
= MS_WIN(addr
);
608 ha
->qdr_sn_window
= window
;
610 ha
->ms_win_crb
| QLA82XX_PCI_CRBSPACE
, window
);
611 win_read
= qla82xx_rd_32(ha
,
612 ha
->ms_win_crb
| QLA82XX_PCI_CRBSPACE
);
613 if (win_read
!= window
) {
614 qla_printk(KERN_WARNING
, ha
,
615 "%s: Written MSwin (0x%x) != Read MSwin (0x%x)\n",
616 __func__
, window
, win_read
);
618 addr
= GET_MEM_OFFS_2M(addr
) + QLA82XX_PCI_QDR_NET
;
621 * peg gdb frequently accesses memory that doesn't exist,
622 * this limits the chit chat so debugging isn't slowed down.
624 if ((qla82xx_pci_set_window_warning_count
++ < 8) ||
625 (qla82xx_pci_set_window_warning_count
%64 == 0)) {
626 qla_printk(KERN_WARNING
, ha
,
627 "%s: Warning:%s Unknown address range!\n", __func__
,
628 QLA2XXX_DRIVER_NAME
);
635 /* check if address is in the same windows as the previous access */
636 static int qla82xx_pci_is_same_window(struct qla_hw_data
*ha
,
637 unsigned long long addr
)
640 unsigned long long qdr_max
;
642 qdr_max
= QLA82XX_P3_ADDR_QDR_NET_MAX
;
644 /* DDR network side */
645 if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_DDR_NET
,
646 QLA82XX_ADDR_DDR_NET_MAX
))
648 else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_OCM0
,
649 QLA82XX_ADDR_OCM0_MAX
))
651 else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_OCM1
,
652 QLA82XX_ADDR_OCM1_MAX
))
654 else if (QLA82XX_ADDR_IN_RANGE(addr
, QLA82XX_ADDR_QDR_NET
, qdr_max
)) {
655 /* QDR network side */
656 window
= ((addr
- QLA82XX_ADDR_QDR_NET
) >> 22) & 0x3f;
657 if (ha
->qdr_sn_window
== window
)
663 static int qla82xx_pci_mem_read_direct(struct qla_hw_data
*ha
,
664 u64 off
, void *data
, int size
)
670 uint8_t *mem_ptr
= NULL
;
671 unsigned long mem_base
;
672 unsigned long mem_page
;
674 write_lock_irqsave(&ha
->hw_lock
, flags
);
677 * If attempting to access unknown address or straddle hw windows,
680 start
= qla82xx_pci_set_window(ha
, off
);
681 if ((start
== -1UL) ||
682 (qla82xx_pci_is_same_window(ha
, off
+ size
- 1) == 0)) {
683 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
684 qla_printk(KERN_ERR
, ha
,
685 "%s out of bound pci memory access. "
686 "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME
, off
);
690 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
691 mem_base
= pci_resource_start(ha
->pdev
, 0);
692 mem_page
= start
& PAGE_MASK
;
693 /* Map two pages whenever user tries to access addresses in two
696 if (mem_page
!= ((start
+ size
- 1) & PAGE_MASK
))
697 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
* 2);
699 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
);
700 if (mem_ptr
== 0UL) {
705 addr
+= start
& (PAGE_SIZE
- 1);
706 write_lock_irqsave(&ha
->hw_lock
, flags
);
710 *(u8
*)data
= readb(addr
);
713 *(u16
*)data
= readw(addr
);
716 *(u32
*)data
= readl(addr
);
719 *(u64
*)data
= readq(addr
);
725 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
733 qla82xx_pci_mem_write_direct(struct qla_hw_data
*ha
,
734 u64 off
, void *data
, int size
)
740 uint8_t *mem_ptr
= NULL
;
741 unsigned long mem_base
;
742 unsigned long mem_page
;
744 write_lock_irqsave(&ha
->hw_lock
, flags
);
747 * If attempting to access unknown address or straddle hw windows,
750 start
= qla82xx_pci_set_window(ha
, off
);
751 if ((start
== -1UL) ||
752 (qla82xx_pci_is_same_window(ha
, off
+ size
- 1) == 0)) {
753 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
754 qla_printk(KERN_ERR
, ha
,
755 "%s out of bound pci memory access. "
756 "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME
, off
);
760 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
761 mem_base
= pci_resource_start(ha
->pdev
, 0);
762 mem_page
= start
& PAGE_MASK
;
763 /* Map two pages whenever user tries to access addresses in two
766 if (mem_page
!= ((start
+ size
- 1) & PAGE_MASK
))
767 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
*2);
769 mem_ptr
= ioremap(mem_base
+ mem_page
, PAGE_SIZE
);
774 addr
+= start
& (PAGE_SIZE
- 1);
775 write_lock_irqsave(&ha
->hw_lock
, flags
);
779 writeb(*(u8
*)data
, addr
);
782 writew(*(u16
*)data
, addr
);
785 writel(*(u32
*)data
, addr
);
788 writeq(*(u64
*)data
, addr
);
794 write_unlock_irqrestore(&ha
->hw_lock
, flags
);
800 #define MTU_FUDGE_FACTOR 100
802 qla82xx_decode_crb_addr(unsigned long addr
)
805 unsigned long base_addr
, offset
, pci_base
;
807 if (!qla82xx_crb_table_initialized
)
808 qla82xx_crb_addr_transform_setup();
810 pci_base
= ADDR_ERROR
;
811 base_addr
= addr
& 0xfff00000;
812 offset
= addr
& 0x000fffff;
814 for (i
= 0; i
< MAX_CRB_XFORM
; i
++) {
815 if (crb_addr_xform
[i
] == base_addr
) {
820 if (pci_base
== ADDR_ERROR
)
822 return pci_base
+ offset
;
825 static long rom_max_timeout
= 100;
826 static long qla82xx_rom_lock_timeout
= 100;
829 qla82xx_rom_lock(struct qla_hw_data
*ha
)
831 int done
= 0, timeout
= 0;
834 /* acquire semaphore2 from PCI HW block */
835 done
= qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK
));
838 if (timeout
>= qla82xx_rom_lock_timeout
)
842 qla82xx_wr_32(ha
, QLA82XX_ROM_LOCK_ID
, ROM_LOCK_DRIVER
);
847 qla82xx_wait_rom_busy(struct qla_hw_data
*ha
)
853 done
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_GLB_STATUS
);
856 if (timeout
>= rom_max_timeout
) {
857 DEBUG(qla_printk(KERN_INFO
, ha
,
858 "%s: Timeout reached waiting for rom busy",
859 QLA2XXX_DRIVER_NAME
));
867 qla82xx_wait_rom_done(struct qla_hw_data
*ha
)
873 done
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_GLB_STATUS
);
876 if (timeout
>= rom_max_timeout
) {
877 DEBUG(qla_printk(KERN_INFO
, ha
,
878 "%s: Timeout reached waiting for rom done",
879 QLA2XXX_DRIVER_NAME
));
887 qla82xx_do_rom_fast_read(struct qla_hw_data
*ha
, int addr
, int *valp
)
889 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ADDRESS
, addr
);
890 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT
, 0);
891 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 3);
892 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, 0xb);
893 qla82xx_wait_rom_busy(ha
);
894 if (qla82xx_wait_rom_done(ha
)) {
895 qla_printk(KERN_WARNING
, ha
,
896 "%s: Error waiting for rom done\n",
897 QLA2XXX_DRIVER_NAME
);
900 /* Reset abyte_cnt and dummy_byte_cnt */
901 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT
, 0);
904 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 0);
905 *valp
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_ROM_RDATA
);
910 qla82xx_rom_fast_read(struct qla_hw_data
*ha
, int addr
, int *valp
)
914 while ((qla82xx_rom_lock(ha
) != 0) && (loops
< 50000)) {
919 if (loops
>= 50000) {
920 qla_printk(KERN_INFO
, ha
,
921 "%s: qla82xx_rom_lock failed\n",
922 QLA2XXX_DRIVER_NAME
);
925 ret
= qla82xx_do_rom_fast_read(ha
, addr
, valp
);
926 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK
));
931 qla82xx_read_status_reg(struct qla_hw_data
*ha
, uint32_t *val
)
933 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_RDSR
);
934 qla82xx_wait_rom_busy(ha
);
935 if (qla82xx_wait_rom_done(ha
)) {
936 qla_printk(KERN_WARNING
, ha
,
937 "Error waiting for rom done\n");
940 *val
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_ROM_RDATA
);
945 qla82xx_flash_wait_write_finish(struct qla_hw_data
*ha
)
952 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 0);
953 while ((done
!= 0) && (ret
== 0)) {
954 ret
= qla82xx_read_status_reg(ha
, &val
);
959 if (timeout
>= 50000) {
960 qla_printk(KERN_WARNING
, ha
,
961 "Timeout reached waiting for write finish");
969 qla82xx_flash_set_write_enable(struct qla_hw_data
*ha
)
972 qla82xx_wait_rom_busy(ha
);
973 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 0);
974 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_WREN
);
975 qla82xx_wait_rom_busy(ha
);
976 if (qla82xx_wait_rom_done(ha
))
978 if (qla82xx_read_status_reg(ha
, &val
) != 0)
986 qla82xx_write_status_reg(struct qla_hw_data
*ha
, uint32_t val
)
988 if (qla82xx_flash_set_write_enable(ha
))
990 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_WDATA
, val
);
991 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, 0x1);
992 if (qla82xx_wait_rom_done(ha
)) {
993 qla_printk(KERN_WARNING
, ha
,
994 "Error waiting for rom done\n");
997 return qla82xx_flash_wait_write_finish(ha
);
1001 qla82xx_write_disable_flash(struct qla_hw_data
*ha
)
1003 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_WRDI
);
1004 if (qla82xx_wait_rom_done(ha
)) {
1005 qla_printk(KERN_WARNING
, ha
,
1006 "Error waiting for rom done\n");
1013 ql82xx_rom_lock_d(struct qla_hw_data
*ha
)
1016 while ((qla82xx_rom_lock(ha
) != 0) && (loops
< 50000)) {
1021 if (loops
>= 50000) {
1022 qla_printk(KERN_WARNING
, ha
, "ROM lock failed\n");
1029 qla82xx_write_flash_dword(struct qla_hw_data
*ha
, uint32_t flashaddr
,
1034 ret
= ql82xx_rom_lock_d(ha
);
1036 qla_printk(KERN_WARNING
, ha
, "ROM Lock failed\n");
1040 if (qla82xx_flash_set_write_enable(ha
))
1043 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_WDATA
, data
);
1044 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ADDRESS
, flashaddr
);
1045 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 3);
1046 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_PP
);
1047 qla82xx_wait_rom_busy(ha
);
1048 if (qla82xx_wait_rom_done(ha
)) {
1049 qla_printk(KERN_WARNING
, ha
,
1050 "Error waiting for rom done\n");
1055 ret
= qla82xx_flash_wait_write_finish(ha
);
1058 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK
));
1062 /* This routine does CRB initialize sequence
1063 * to put the ISP into operational state
1066 qla82xx_pinit_from_rom(scsi_qla_host_t
*vha
)
1070 struct crb_addr_pair
*buf
;
1073 struct qla_hw_data
*ha
= vha
->hw
;
1075 struct crb_addr_pair
{
1080 /* Halt all the indiviual PEGs and other blocks of the ISP */
1081 qla82xx_rom_lock(ha
);
1082 if (test_bit(ABORT_ISP_ACTIVE
, &vha
->dpc_flags
))
1083 /* don't reset CAM block on reset */
1084 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0xfeffffff);
1086 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0xffffffff);
1087 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK
));
1089 /* Read the signature value from the flash.
1090 * Offset 0: Contain signature (0xcafecafe)
1091 * Offset 4: Offset and number of addr/value pairs
1092 * that present in CRB initialize sequence
1094 if (qla82xx_rom_fast_read(ha
, 0, &n
) != 0 || n
!= 0xcafecafeUL
||
1095 qla82xx_rom_fast_read(ha
, 4, &n
) != 0) {
1096 qla_printk(KERN_WARNING
, ha
,
1097 "[ERROR] Reading crb_init area: n: %08x\n", n
);
1101 /* Offset in flash = lower 16 bits
1102 * Number of enteries = upper 16 bits
1104 offset
= n
& 0xffffU
;
1105 n
= (n
>> 16) & 0xffffU
;
1107 /* number of addr/value pair should not exceed 1024 enteries */
1109 qla_printk(KERN_WARNING
, ha
,
1110 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1111 QLA2XXX_DRIVER_NAME
, __func__
, n
);
1115 qla_printk(KERN_INFO
, ha
,
1116 "%s: %d CRB init values found in ROM.\n", QLA2XXX_DRIVER_NAME
, n
);
1118 buf
= kmalloc(n
* sizeof(struct crb_addr_pair
), GFP_KERNEL
);
1120 qla_printk(KERN_WARNING
, ha
,
1121 "%s: [ERROR] Unable to malloc memory.\n",
1122 QLA2XXX_DRIVER_NAME
);
1126 for (i
= 0; i
< n
; i
++) {
1127 if (qla82xx_rom_fast_read(ha
, 8*i
+ 4*offset
, &val
) != 0 ||
1128 qla82xx_rom_fast_read(ha
, 8*i
+ 4*offset
+ 4, &addr
) != 0) {
1137 for (i
= 0; i
< n
; i
++) {
1138 /* Translate internal CRB initialization
1139 * address to PCI bus address
1141 off
= qla82xx_decode_crb_addr((unsigned long)buf
[i
].addr
) +
1142 QLA82XX_PCI_CRBSPACE
;
1143 /* Not all CRB addr/value pair to be written,
1144 * some of them are skipped
1147 /* skipping cold reboot MAGIC */
1148 if (off
== QLA82XX_CAM_RAM(0x1fc))
1151 /* do not reset PCI */
1152 if (off
== (ROMUSB_GLB
+ 0xbc))
1155 /* skip core clock, so that firmware can increase the clock */
1156 if (off
== (ROMUSB_GLB
+ 0xc8))
1159 /* skip the function enable register */
1160 if (off
== QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION
))
1163 if (off
== QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2
))
1166 if ((off
& 0x0ff00000) == QLA82XX_CRB_SMB
)
1169 if ((off
& 0x0ff00000) == QLA82XX_CRB_DDR_NET
)
1172 if (off
== ADDR_ERROR
) {
1173 qla_printk(KERN_WARNING
, ha
,
1174 "%s: [ERROR] Unknown addr: 0x%08lx\n",
1175 QLA2XXX_DRIVER_NAME
, buf
[i
].addr
);
1179 qla82xx_wr_32(ha
, off
, buf
[i
].data
);
1181 /* ISP requires much bigger delay to settle down,
1182 * else crb_window returns 0xffffffff
1184 if (off
== QLA82XX_ROMUSB_GLB_SW_RESET
)
1187 /* ISP requires millisec delay between
1188 * successive CRB register updation
1195 /* Resetting the data and instruction cache */
1196 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_D
+0xec, 0x1e);
1197 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_D
+0x4c, 8);
1198 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_I
+0x4c, 8);
1200 /* Clear all protocol processing engines */
1201 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+0x8, 0);
1202 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+0xc, 0);
1203 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_1
+0x8, 0);
1204 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_1
+0xc, 0);
1205 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_2
+0x8, 0);
1206 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_2
+0xc, 0);
1207 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_3
+0x8, 0);
1208 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_3
+0xc, 0);
1213 qla82xx_check_for_bad_spd(struct qla_hw_data
*ha
)
1216 val
= qla82xx_rd_32(ha
, BOOT_LOADER_DIMM_STATUS
);
1217 val
&= QLA82XX_BOOT_LOADER_MN_ISSUE
;
1218 if (val
& QLA82XX_PEG_TUNE_MN_SPD_ZEROED
) {
1219 qla_printk(KERN_INFO
, ha
,
1220 "Memory DIMM SPD not programmed. "
1221 " Assumed valid.\n");
1224 qla_printk(KERN_INFO
, ha
,
1225 "Memory DIMM type incorrect.Info:%08X.\n", val
);
1232 qla82xx_pci_mem_write_2M(struct qla_hw_data
*ha
,
1233 u64 off
, void *data
, int size
)
1235 int i
, j
, ret
= 0, loop
, sz
[2], off0
;
1236 int scale
, shift_amount
, startword
;
1238 uint64_t off8
, mem_crb
, tmpw
, word
[2] = {0, 0};
1241 * If not MN, go check for MS or invalid.
1243 if (off
>= QLA82XX_ADDR_QDR_NET
&& off
<= QLA82XX_P3_ADDR_QDR_NET_MAX
)
1244 mem_crb
= QLA82XX_CRB_QDR_NET
;
1246 mem_crb
= QLA82XX_CRB_DDR_NET
;
1247 if (qla82xx_pci_mem_bound_check(ha
, off
, size
) == 0)
1248 return qla82xx_pci_mem_write_direct(ha
,
1253 sz
[0] = (size
< (8 - off0
)) ? size
: (8 - off0
);
1254 sz
[1] = size
- sz
[0];
1256 off8
= off
& 0xfffffff0;
1257 loop
= (((off
& 0xf) + size
- 1) >> 4) + 1;
1260 startword
= (off
& 0xf)/8;
1262 for (i
= 0; i
< loop
; i
++) {
1263 if (qla82xx_pci_mem_read_2M(ha
, off8
+
1264 (i
<< shift_amount
), &word
[i
* scale
], 8))
1270 tmpw
= *((uint8_t *)data
);
1273 tmpw
= *((uint16_t *)data
);
1276 tmpw
= *((uint32_t *)data
);
1280 tmpw
= *((uint64_t *)data
);
1285 word
[startword
] = tmpw
;
1288 ~((~(~0ULL << (sz
[0] * 8))) << (off0
* 8));
1289 word
[startword
] |= tmpw
<< (off0
* 8);
1292 word
[startword
+1] &= ~(~0ULL << (sz
[1] * 8));
1293 word
[startword
+1] |= tmpw
>> (sz
[0] * 8);
1297 * don't lock here - write_wx gets the lock if each time
1298 * write_lock_irqsave(&adapter->adapter_lock, flags);
1299 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1301 for (i
= 0; i
< loop
; i
++) {
1302 temp
= off8
+ (i
<< shift_amount
);
1303 qla82xx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_ADDR_LO
, temp
);
1305 qla82xx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_ADDR_HI
, temp
);
1306 temp
= word
[i
* scale
] & 0xffffffff;
1307 qla82xx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_WRDATA_LO
, temp
);
1308 temp
= (word
[i
* scale
] >> 32) & 0xffffffff;
1309 qla82xx_wr_32(ha
, mem_crb
+MIU_TEST_AGT_WRDATA_HI
, temp
);
1310 temp
= word
[i
*scale
+ 1] & 0xffffffff;
1311 qla82xx_wr_32(ha
, mem_crb
+
1312 MIU_TEST_AGT_WRDATA_UPPER_LO
, temp
);
1313 temp
= (word
[i
*scale
+ 1] >> 32) & 0xffffffff;
1314 qla82xx_wr_32(ha
, mem_crb
+
1315 MIU_TEST_AGT_WRDATA_UPPER_HI
, temp
);
1317 temp
= MIU_TA_CTL_ENABLE
| MIU_TA_CTL_WRITE
;
1318 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1319 temp
= MIU_TA_CTL_START
| MIU_TA_CTL_ENABLE
| MIU_TA_CTL_WRITE
;
1320 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1322 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1323 temp
= qla82xx_rd_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
);
1324 if ((temp
& MIU_TA_CTL_BUSY
) == 0)
1328 if (j
>= MAX_CTL_CHECK
) {
1329 if (printk_ratelimit())
1330 dev_err(&ha
->pdev
->dev
,
1331 "failed to write through agent\n");
1341 qla82xx_fw_load_from_flash(struct qla_hw_data
*ha
)
1345 long flashaddr
= ha
->flt_region_bootload
<< 2;
1346 long memaddr
= BOOTLD_START
;
1349 size
= (IMAGE_START
- BOOTLD_START
) / 8;
1351 for (i
= 0; i
< size
; i
++) {
1352 if ((qla82xx_rom_fast_read(ha
, flashaddr
, (int *)&low
)) ||
1353 (qla82xx_rom_fast_read(ha
, flashaddr
+ 4, (int *)&high
))) {
1356 data
= ((u64
)high
<< 32) | low
;
1357 qla82xx_pci_mem_write_2M(ha
, memaddr
, &data
, 8);
1361 if (i
% 0x1000 == 0)
1365 read_lock(&ha
->hw_lock
);
1366 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+ 0x18, 0x1020);
1367 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0x80001e);
1368 read_unlock(&ha
->hw_lock
);
1373 qla82xx_pci_mem_read_2M(struct qla_hw_data
*ha
,
1374 u64 off
, void *data
, int size
)
1376 int i
, j
= 0, k
, start
, end
, loop
, sz
[2], off0
[2];
1379 uint64_t off8
, val
, mem_crb
, word
[2] = {0, 0};
1382 * If not MN, go check for MS or invalid.
1385 if (off
>= QLA82XX_ADDR_QDR_NET
&& off
<= QLA82XX_P3_ADDR_QDR_NET_MAX
)
1386 mem_crb
= QLA82XX_CRB_QDR_NET
;
1388 mem_crb
= QLA82XX_CRB_DDR_NET
;
1389 if (qla82xx_pci_mem_bound_check(ha
, off
, size
) == 0)
1390 return qla82xx_pci_mem_read_direct(ha
,
1394 off8
= off
& 0xfffffff0;
1395 off0
[0] = off
& 0xf;
1396 sz
[0] = (size
< (16 - off0
[0])) ? size
: (16 - off0
[0]);
1398 loop
= ((off0
[0] + size
- 1) >> shift_amount
) + 1;
1400 sz
[1] = size
- sz
[0];
1403 * don't lock here - write_wx gets the lock if each time
1404 * write_lock_irqsave(&adapter->adapter_lock, flags);
1405 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1408 for (i
= 0; i
< loop
; i
++) {
1409 temp
= off8
+ (i
<< shift_amount
);
1410 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_ADDR_LO
, temp
);
1412 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_ADDR_HI
, temp
);
1413 temp
= MIU_TA_CTL_ENABLE
;
1414 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1415 temp
= MIU_TA_CTL_START
| MIU_TA_CTL_ENABLE
;
1416 qla82xx_wr_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
, temp
);
1418 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1419 temp
= qla82xx_rd_32(ha
, mem_crb
+ MIU_TEST_AGT_CTRL
);
1420 if ((temp
& MIU_TA_CTL_BUSY
) == 0)
1424 if (j
>= MAX_CTL_CHECK
) {
1425 if (printk_ratelimit())
1426 dev_err(&ha
->pdev
->dev
,
1427 "failed to read through agent\n");
1431 start
= off0
[i
] >> 2;
1432 end
= (off0
[i
] + sz
[i
] - 1) >> 2;
1433 for (k
= start
; k
<= end
; k
++) {
1434 temp
= qla82xx_rd_32(ha
,
1435 mem_crb
+ MIU_TEST_AGT_RDDATA(k
));
1436 word
[i
] |= ((uint64_t)temp
<< (32 * (k
& 1)));
1441 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1442 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1445 if (j
>= MAX_CTL_CHECK
)
1448 if ((off0
[0] & 7) == 0) {
1451 val
= ((word
[0] >> (off0
[0] * 8)) & (~(~0ULL << (sz
[0] * 8)))) |
1452 ((word
[1] & (~(~0ULL << (sz
[1] * 8)))) << (sz
[0] * 8));
1457 *(uint8_t *)data
= val
;
1460 *(uint16_t *)data
= val
;
1463 *(uint32_t *)data
= val
;
1466 *(uint64_t *)data
= val
;
1473 static struct qla82xx_uri_table_desc
*
1474 qla82xx_get_table_desc(const u8
*unirom
, int section
)
1477 struct qla82xx_uri_table_desc
*directory
=
1478 (struct qla82xx_uri_table_desc
*)&unirom
[0];
1481 __le32 entries
= cpu_to_le32(directory
->num_entries
);
1483 for (i
= 0; i
< entries
; i
++) {
1484 offset
= cpu_to_le32(directory
->findex
) +
1485 (i
* cpu_to_le32(directory
->entry_size
));
1486 tab_type
= cpu_to_le32(*((u32
*)&unirom
[offset
] + 8));
1488 if (tab_type
== section
)
1489 return (struct qla82xx_uri_table_desc
*)&unirom
[offset
];
1495 static struct qla82xx_uri_data_desc
*
1496 qla82xx_get_data_desc(struct qla_hw_data
*ha
,
1497 u32 section
, u32 idx_offset
)
1499 const u8
*unirom
= ha
->hablob
->fw
->data
;
1500 int idx
= cpu_to_le32(*((int *)&unirom
[ha
->file_prd_off
] + idx_offset
));
1501 struct qla82xx_uri_table_desc
*tab_desc
= NULL
;
1504 tab_desc
= qla82xx_get_table_desc(unirom
, section
);
1508 offset
= cpu_to_le32(tab_desc
->findex
) +
1509 (cpu_to_le32(tab_desc
->entry_size
) * idx
);
1511 return (struct qla82xx_uri_data_desc
*)&unirom
[offset
];
1515 qla82xx_get_bootld_offset(struct qla_hw_data
*ha
)
1517 u32 offset
= BOOTLD_START
;
1518 struct qla82xx_uri_data_desc
*uri_desc
= NULL
;
1520 if (ha
->fw_type
== QLA82XX_UNIFIED_ROMIMAGE
) {
1521 uri_desc
= qla82xx_get_data_desc(ha
,
1522 QLA82XX_URI_DIR_SECT_BOOTLD
, QLA82XX_URI_BOOTLD_IDX_OFF
);
1524 offset
= cpu_to_le32(uri_desc
->findex
);
1527 return (u8
*)&ha
->hablob
->fw
->data
[offset
];
1531 qla82xx_get_fw_size(struct qla_hw_data
*ha
)
1533 struct qla82xx_uri_data_desc
*uri_desc
= NULL
;
1535 if (ha
->fw_type
== QLA82XX_UNIFIED_ROMIMAGE
) {
1536 uri_desc
= qla82xx_get_data_desc(ha
, QLA82XX_URI_DIR_SECT_FW
,
1537 QLA82XX_URI_FIRMWARE_IDX_OFF
);
1539 return cpu_to_le32(uri_desc
->size
);
1542 return cpu_to_le32(*(u32
*)&ha
->hablob
->fw
->data
[FW_SIZE_OFFSET
]);
1546 qla82xx_get_fw_offs(struct qla_hw_data
*ha
)
1548 u32 offset
= IMAGE_START
;
1549 struct qla82xx_uri_data_desc
*uri_desc
= NULL
;
1551 if (ha
->fw_type
== QLA82XX_UNIFIED_ROMIMAGE
) {
1552 uri_desc
= qla82xx_get_data_desc(ha
, QLA82XX_URI_DIR_SECT_FW
,
1553 QLA82XX_URI_FIRMWARE_IDX_OFF
);
1555 offset
= cpu_to_le32(uri_desc
->findex
);
1558 return (u8
*)&ha
->hablob
->fw
->data
[offset
];
1561 /* PCI related functions */
1563 qla82xx_pci_info_str(struct scsi_qla_host
*vha
, char *str
)
1566 struct qla_hw_data
*ha
= vha
->hw
;
1570 pcie_reg
= pci_find_capability(ha
->pdev
, PCI_CAP_ID_EXP
);
1571 pci_read_config_word(ha
->pdev
, pcie_reg
+ PCI_EXP_LNKSTA
, &lnk
);
1572 ha
->link_width
= (lnk
>> 4) & 0x3f;
1574 strcpy(str
, "PCIe (");
1575 strcat(str
, "2.5Gb/s ");
1576 snprintf(lwstr
, sizeof(lwstr
), "x%d)", ha
->link_width
);
1581 int qla82xx_pci_region_offset(struct pci_dev
*pdev
, int region
)
1583 unsigned long val
= 0;
1591 pci_read_config_dword(pdev
, QLA82XX_PCI_REG_MSIX_TBL
, &control
);
1592 val
= control
+ QLA82XX_MSIX_TBL_SPACE
;
1600 qla82xx_iospace_config(struct qla_hw_data
*ha
)
1604 if (pci_request_regions(ha
->pdev
, QLA2XXX_DRIVER_NAME
)) {
1605 qla_printk(KERN_WARNING
, ha
,
1606 "Failed to reserve selected regions (%s)\n",
1607 pci_name(ha
->pdev
));
1608 goto iospace_error_exit
;
1611 /* Use MMIO operations for all accesses. */
1612 if (!(pci_resource_flags(ha
->pdev
, 0) & IORESOURCE_MEM
)) {
1613 qla_printk(KERN_ERR
, ha
,
1614 "region #0 not an MMIO resource (%s), aborting\n",
1615 pci_name(ha
->pdev
));
1616 goto iospace_error_exit
;
1619 len
= pci_resource_len(ha
->pdev
, 0);
1621 (unsigned long)ioremap(pci_resource_start(ha
->pdev
, 0), len
);
1622 if (!ha
->nx_pcibase
) {
1623 qla_printk(KERN_ERR
, ha
,
1624 "cannot remap pcibase MMIO (%s), aborting\n",
1625 pci_name(ha
->pdev
));
1626 pci_release_regions(ha
->pdev
);
1627 goto iospace_error_exit
;
1630 /* Mapping of IO base pointer */
1631 ha
->iobase
= (device_reg_t __iomem
*)((uint8_t *)ha
->nx_pcibase
+
1632 0xbc000 + (ha
->pdev
->devfn
<< 11));
1636 (unsigned long)ioremap((pci_resource_start(ha
->pdev
, 4) +
1637 (ha
->pdev
->devfn
<< 12)), 4);
1638 if (!ha
->nxdb_wr_ptr
) {
1639 qla_printk(KERN_ERR
, ha
,
1640 "cannot remap MMIO (%s), aborting\n",
1641 pci_name(ha
->pdev
));
1642 pci_release_regions(ha
->pdev
);
1643 goto iospace_error_exit
;
1646 /* Mapping of IO base pointer,
1647 * door bell read and write pointer
1649 ha
->nxdb_rd_ptr
= (uint8_t *) ha
->nx_pcibase
+ (512 * 1024) +
1650 (ha
->pdev
->devfn
* 8);
1652 ha
->nxdb_wr_ptr
= (ha
->pdev
->devfn
== 6 ?
1653 QLA82XX_CAMRAM_DB1
:
1654 QLA82XX_CAMRAM_DB2
);
1657 ha
->max_req_queues
= ha
->max_rsp_queues
= 1;
1658 ha
->msix_count
= ha
->max_rsp_queues
+ 1;
1665 /* GS related functions */
1667 /* Initialization related functions */
1670 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1673 * Returns 0 on success.
1676 qla82xx_pci_config(scsi_qla_host_t
*vha
)
1678 struct qla_hw_data
*ha
= vha
->hw
;
1681 pci_set_master(ha
->pdev
);
1682 ret
= pci_set_mwi(ha
->pdev
);
1683 ha
->chip_revision
= ha
->pdev
->revision
;
1688 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1691 * Returns 0 on success.
1694 qla82xx_reset_chip(scsi_qla_host_t
*vha
)
1696 struct qla_hw_data
*ha
= vha
->hw
;
1697 ha
->isp_ops
->disable_intrs(ha
);
1700 void qla82xx_config_rings(struct scsi_qla_host
*vha
)
1702 struct qla_hw_data
*ha
= vha
->hw
;
1703 struct device_reg_82xx __iomem
*reg
= &ha
->iobase
->isp82
;
1704 struct init_cb_81xx
*icb
;
1705 struct req_que
*req
= ha
->req_q_map
[0];
1706 struct rsp_que
*rsp
= ha
->rsp_q_map
[0];
1708 /* Setup ring parameters in initialization control block. */
1709 icb
= (struct init_cb_81xx
*)ha
->init_cb
;
1710 icb
->request_q_outpointer
= __constant_cpu_to_le16(0);
1711 icb
->response_q_inpointer
= __constant_cpu_to_le16(0);
1712 icb
->request_q_length
= cpu_to_le16(req
->length
);
1713 icb
->response_q_length
= cpu_to_le16(rsp
->length
);
1714 icb
->request_q_address
[0] = cpu_to_le32(LSD(req
->dma
));
1715 icb
->request_q_address
[1] = cpu_to_le32(MSD(req
->dma
));
1716 icb
->response_q_address
[0] = cpu_to_le32(LSD(rsp
->dma
));
1717 icb
->response_q_address
[1] = cpu_to_le32(MSD(rsp
->dma
));
1719 WRT_REG_DWORD((unsigned long __iomem
*)®
->req_q_out
[0], 0);
1720 WRT_REG_DWORD((unsigned long __iomem
*)®
->rsp_q_in
[0], 0);
1721 WRT_REG_DWORD((unsigned long __iomem
*)®
->rsp_q_out
[0], 0);
1724 void qla82xx_reset_adapter(struct scsi_qla_host
*vha
)
1726 struct qla_hw_data
*ha
= vha
->hw
;
1727 vha
->flags
.online
= 0;
1728 qla2x00_try_to_stop_firmware(vha
);
1729 ha
->isp_ops
->disable_intrs(ha
);
1733 qla82xx_fw_load_from_blob(struct qla_hw_data
*ha
)
1736 u32 i
, flashaddr
, size
;
1739 size
= (IMAGE_START
- BOOTLD_START
) / 8;
1741 ptr64
= (u64
*)qla82xx_get_bootld_offset(ha
);
1742 flashaddr
= BOOTLD_START
;
1744 for (i
= 0; i
< size
; i
++) {
1745 data
= cpu_to_le64(ptr64
[i
]);
1746 if (qla82xx_pci_mem_write_2M(ha
, flashaddr
, &data
, 8))
1751 flashaddr
= FLASH_ADDR_START
;
1752 size
= (__force u32
)qla82xx_get_fw_size(ha
) / 8;
1753 ptr64
= (u64
*)qla82xx_get_fw_offs(ha
);
1755 for (i
= 0; i
< size
; i
++) {
1756 data
= cpu_to_le64(ptr64
[i
]);
1758 if (qla82xx_pci_mem_write_2M(ha
, flashaddr
, &data
, 8))
1764 /* Write a magic value to CAMRAM register
1765 * at a specified offset to indicate
1766 * that all data is written and
1767 * ready for firmware to initialize.
1769 qla82xx_wr_32(ha
, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC
);
1771 read_lock(&ha
->hw_lock
);
1772 qla82xx_wr_32(ha
, QLA82XX_CRB_PEG_NET_0
+ 0x18, 0x1020);
1773 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, 0x80001e);
1774 read_unlock(&ha
->hw_lock
);
1779 qla82xx_set_product_offset(struct qla_hw_data
*ha
)
1781 struct qla82xx_uri_table_desc
*ptab_desc
= NULL
;
1782 const uint8_t *unirom
= ha
->hablob
->fw
->data
;
1785 __le32 flags
, file_chiprev
, offset
;
1786 uint8_t chiprev
= ha
->chip_revision
;
1787 /* Hardcoding mn_present flag for P3P */
1791 ptab_desc
= qla82xx_get_table_desc(unirom
,
1792 QLA82XX_URI_DIR_SECT_PRODUCT_TBL
);
1796 entries
= cpu_to_le32(ptab_desc
->num_entries
);
1798 for (i
= 0; i
< entries
; i
++) {
1799 offset
= cpu_to_le32(ptab_desc
->findex
) +
1800 (i
* cpu_to_le32(ptab_desc
->entry_size
));
1801 flags
= cpu_to_le32(*((int *)&unirom
[offset
] +
1802 QLA82XX_URI_FLAGS_OFF
));
1803 file_chiprev
= cpu_to_le32(*((int *)&unirom
[offset
] +
1804 QLA82XX_URI_CHIP_REV_OFF
));
1806 flagbit
= mn_present
? 1 : 2;
1808 if ((chiprev
== file_chiprev
) && ((1ULL << flagbit
) & flags
)) {
1809 ha
->file_prd_off
= offset
;
1817 qla82xx_validate_firmware_blob(scsi_qla_host_t
*vha
, uint8_t fw_type
)
1821 struct qla_hw_data
*ha
= vha
->hw
;
1822 const struct firmware
*fw
= ha
->hablob
->fw
;
1824 ha
->fw_type
= fw_type
;
1826 if (fw_type
== QLA82XX_UNIFIED_ROMIMAGE
) {
1827 if (qla82xx_set_product_offset(ha
))
1830 min_size
= QLA82XX_URI_FW_MIN_SIZE
;
1832 val
= cpu_to_le32(*(u32
*)&fw
->data
[QLA82XX_FW_MAGIC_OFFSET
]);
1833 if ((__force u32
)val
!= QLA82XX_BDINFO_MAGIC
)
1836 min_size
= QLA82XX_FW_MIN_SIZE
;
1839 if (fw
->size
< min_size
)
1845 qla82xx_check_cmdpeg_state(struct qla_hw_data
*ha
)
1851 read_lock(&ha
->hw_lock
);
1852 val
= qla82xx_rd_32(ha
, CRB_CMDPEG_STATE
);
1853 read_unlock(&ha
->hw_lock
);
1856 case PHAN_INITIALIZE_COMPLETE
:
1857 case PHAN_INITIALIZE_ACK
:
1859 case PHAN_INITIALIZE_FAILED
:
1864 qla_printk(KERN_WARNING
, ha
,
1865 "CRB_CMDPEG_STATE: 0x%x and retries: 0x%x\n",
1870 } while (--retries
);
1872 qla_printk(KERN_INFO
, ha
,
1873 "Cmd Peg initialization failed: 0x%x.\n", val
);
1875 qla82xx_check_for_bad_spd(ha
);
1876 val
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE
);
1877 read_lock(&ha
->hw_lock
);
1878 qla82xx_wr_32(ha
, CRB_CMDPEG_STATE
, PHAN_INITIALIZE_FAILED
);
1879 read_unlock(&ha
->hw_lock
);
1880 return QLA_FUNCTION_FAILED
;
1884 qla82xx_check_rcvpeg_state(struct qla_hw_data
*ha
)
1890 read_lock(&ha
->hw_lock
);
1891 val
= qla82xx_rd_32(ha
, CRB_RCVPEG_STATE
);
1892 read_unlock(&ha
->hw_lock
);
1895 case PHAN_INITIALIZE_COMPLETE
:
1896 case PHAN_INITIALIZE_ACK
:
1898 case PHAN_INITIALIZE_FAILED
:
1904 qla_printk(KERN_WARNING
, ha
,
1905 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x\n",
1910 } while (--retries
);
1912 qla_printk(KERN_INFO
, ha
,
1913 "Rcv Peg initialization failed: 0x%x.\n", val
);
1914 read_lock(&ha
->hw_lock
);
1915 qla82xx_wr_32(ha
, CRB_RCVPEG_STATE
, PHAN_INITIALIZE_FAILED
);
1916 read_unlock(&ha
->hw_lock
);
1917 return QLA_FUNCTION_FAILED
;
1920 /* ISR related functions */
1921 uint32_t qla82xx_isr_int_target_mask_enable
[8] = {
1922 ISR_INT_TARGET_MASK
, ISR_INT_TARGET_MASK_F1
,
1923 ISR_INT_TARGET_MASK_F2
, ISR_INT_TARGET_MASK_F3
,
1924 ISR_INT_TARGET_MASK_F4
, ISR_INT_TARGET_MASK_F5
,
1925 ISR_INT_TARGET_MASK_F7
, ISR_INT_TARGET_MASK_F7
1928 uint32_t qla82xx_isr_int_target_status
[8] = {
1929 ISR_INT_TARGET_STATUS
, ISR_INT_TARGET_STATUS_F1
,
1930 ISR_INT_TARGET_STATUS_F2
, ISR_INT_TARGET_STATUS_F3
,
1931 ISR_INT_TARGET_STATUS_F4
, ISR_INT_TARGET_STATUS_F5
,
1932 ISR_INT_TARGET_STATUS_F7
, ISR_INT_TARGET_STATUS_F7
1935 static struct qla82xx_legacy_intr_set legacy_intr
[] = \
1936 QLA82XX_LEGACY_INTR_CONFIG
;
1939 * qla82xx_mbx_completion() - Process mailbox command completions.
1940 * @ha: SCSI driver HA context
1941 * @mb0: Mailbox0 register
1944 qla82xx_mbx_completion(scsi_qla_host_t
*vha
, uint16_t mb0
)
1947 uint16_t __iomem
*wptr
;
1948 struct qla_hw_data
*ha
= vha
->hw
;
1949 struct device_reg_82xx __iomem
*reg
= &ha
->iobase
->isp82
;
1950 wptr
= (uint16_t __iomem
*)®
->mailbox_out
[1];
1952 /* Load return mailbox registers. */
1953 ha
->flags
.mbox_int
= 1;
1954 ha
->mailbox_out
[0] = mb0
;
1956 for (cnt
= 1; cnt
< ha
->mbx_count
; cnt
++) {
1957 ha
->mailbox_out
[cnt
] = RD_REG_WORD(wptr
);
1962 DEBUG3_11(printk(KERN_INFO
"%s(%ld): "
1963 "Got mailbox completion. cmd=%x.\n",
1964 __func__
, vha
->host_no
, ha
->mcp
->mb
[0]));
1966 qla_printk(KERN_INFO
, ha
,
1967 "%s(%ld): MBX pointer ERROR!\n",
1968 __func__
, vha
->host_no
);
1973 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
1975 * @dev_id: SCSI driver HA context
1978 * Called by system whenever the host adapter generates an interrupt.
1980 * Returns handled flag.
1983 qla82xx_intr_handler(int irq
, void *dev_id
)
1985 scsi_qla_host_t
*vha
;
1986 struct qla_hw_data
*ha
;
1987 struct rsp_que
*rsp
;
1988 struct device_reg_82xx __iomem
*reg
;
1989 int status
= 0, status1
= 0;
1990 unsigned long flags
;
1995 rsp
= (struct rsp_que
*) dev_id
;
1998 "%s(): NULL response queue pointer\n", __func__
);
2003 if (!ha
->flags
.msi_enabled
) {
2004 status
= qla82xx_rd_32(ha
, ISR_INT_VECTOR
);
2005 if (!(status
& ha
->nx_legacy_intr
.int_vec_bit
))
2008 status1
= qla82xx_rd_32(ha
, ISR_INT_STATE_REG
);
2009 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1
))
2013 /* clear the interrupt */
2014 qla82xx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_status_reg
, 0xffffffff);
2016 /* read twice to ensure write is flushed */
2017 qla82xx_rd_32(ha
, ISR_INT_VECTOR
);
2018 qla82xx_rd_32(ha
, ISR_INT_VECTOR
);
2020 reg
= &ha
->iobase
->isp82
;
2022 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
2023 vha
= pci_get_drvdata(ha
->pdev
);
2024 for (iter
= 1; iter
--; ) {
2026 if (RD_REG_DWORD(®
->host_int
)) {
2027 stat
= RD_REG_DWORD(®
->host_status
);
2029 switch (stat
& 0xff) {
2034 qla82xx_mbx_completion(vha
, MSW(stat
));
2035 status
|= MBX_INTERRUPT
;
2039 mb
[1] = RD_REG_WORD(®
->mailbox_out
[1]);
2040 mb
[2] = RD_REG_WORD(®
->mailbox_out
[2]);
2041 mb
[3] = RD_REG_WORD(®
->mailbox_out
[3]);
2042 qla2x00_async_event(vha
, rsp
, mb
);
2045 qla24xx_process_response_queue(vha
, rsp
);
2048 DEBUG2(printk("scsi(%ld): "
2049 " Unrecognized interrupt type (%d).\n",
2050 vha
->host_no
, stat
& 0xff));
2054 WRT_REG_DWORD(®
->host_int
, 0);
2056 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2057 if (!ha
->flags
.msi_enabled
)
2058 qla82xx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_mask_reg
, 0xfbff);
2060 #ifdef QL_DEBUG_LEVEL_17
2061 if (!irq
&& ha
->flags
.eeh_busy
)
2062 qla_printk(KERN_WARNING
, ha
,
2063 "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n",
2064 status
, ha
->mbx_cmd_flags
, ha
->flags
.mbox_int
, stat
);
2067 if (test_bit(MBX_INTR_WAIT
, &ha
->mbx_cmd_flags
) &&
2068 (status
& MBX_INTERRUPT
) && ha
->flags
.mbox_int
) {
2069 set_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
2070 complete(&ha
->mbx_intr_comp
);
2076 qla82xx_msix_default(int irq
, void *dev_id
)
2078 scsi_qla_host_t
*vha
;
2079 struct qla_hw_data
*ha
;
2080 struct rsp_que
*rsp
;
2081 struct device_reg_82xx __iomem
*reg
;
2083 unsigned long flags
;
2087 rsp
= (struct rsp_que
*) dev_id
;
2090 "%s(): NULL response queue pointer\n", __func__
);
2095 reg
= &ha
->iobase
->isp82
;
2097 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
2098 vha
= pci_get_drvdata(ha
->pdev
);
2100 if (RD_REG_DWORD(®
->host_int
)) {
2101 stat
= RD_REG_DWORD(®
->host_status
);
2103 switch (stat
& 0xff) {
2108 qla82xx_mbx_completion(vha
, MSW(stat
));
2109 status
|= MBX_INTERRUPT
;
2113 mb
[1] = RD_REG_WORD(®
->mailbox_out
[1]);
2114 mb
[2] = RD_REG_WORD(®
->mailbox_out
[2]);
2115 mb
[3] = RD_REG_WORD(®
->mailbox_out
[3]);
2116 qla2x00_async_event(vha
, rsp
, mb
);
2119 qla24xx_process_response_queue(vha
, rsp
);
2122 DEBUG2(printk("scsi(%ld): "
2123 " Unrecognized interrupt type (%d).\n",
2124 vha
->host_no
, stat
& 0xff));
2128 WRT_REG_DWORD(®
->host_int
, 0);
2131 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2133 #ifdef QL_DEBUG_LEVEL_17
2134 if (!irq
&& ha
->flags
.eeh_busy
)
2135 qla_printk(KERN_WARNING
, ha
,
2136 "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n",
2137 status
, ha
->mbx_cmd_flags
, ha
->flags
.mbox_int
, stat
);
2140 if (test_bit(MBX_INTR_WAIT
, &ha
->mbx_cmd_flags
) &&
2141 (status
& MBX_INTERRUPT
) && ha
->flags
.mbox_int
) {
2142 set_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
2143 complete(&ha
->mbx_intr_comp
);
2149 qla82xx_msix_rsp_q(int irq
, void *dev_id
)
2151 scsi_qla_host_t
*vha
;
2152 struct qla_hw_data
*ha
;
2153 struct rsp_que
*rsp
;
2154 struct device_reg_82xx __iomem
*reg
;
2156 rsp
= (struct rsp_que
*) dev_id
;
2159 "%s(): NULL response queue pointer\n", __func__
);
2164 reg
= &ha
->iobase
->isp82
;
2165 spin_lock_irq(&ha
->hardware_lock
);
2166 vha
= pci_get_drvdata(ha
->pdev
);
2167 qla24xx_process_response_queue(vha
, rsp
);
2168 WRT_REG_DWORD(®
->host_int
, 0);
2169 spin_unlock_irq(&ha
->hardware_lock
);
2174 qla82xx_poll(int irq
, void *dev_id
)
2176 scsi_qla_host_t
*vha
;
2177 struct qla_hw_data
*ha
;
2178 struct rsp_que
*rsp
;
2179 struct device_reg_82xx __iomem
*reg
;
2183 unsigned long flags
;
2185 rsp
= (struct rsp_que
*) dev_id
;
2188 "%s(): NULL response queue pointer\n", __func__
);
2193 reg
= &ha
->iobase
->isp82
;
2194 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
2195 vha
= pci_get_drvdata(ha
->pdev
);
2197 if (RD_REG_DWORD(®
->host_int
)) {
2198 stat
= RD_REG_DWORD(®
->host_status
);
2199 switch (stat
& 0xff) {
2204 qla82xx_mbx_completion(vha
, MSW(stat
));
2205 status
|= MBX_INTERRUPT
;
2209 mb
[1] = RD_REG_WORD(®
->mailbox_out
[1]);
2210 mb
[2] = RD_REG_WORD(®
->mailbox_out
[2]);
2211 mb
[3] = RD_REG_WORD(®
->mailbox_out
[3]);
2212 qla2x00_async_event(vha
, rsp
, mb
);
2215 qla24xx_process_response_queue(vha
, rsp
);
2218 DEBUG2(printk("scsi(%ld): Unrecognized interrupt type "
2220 vha
->host_no
, stat
& 0xff));
2224 WRT_REG_DWORD(®
->host_int
, 0);
2225 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2229 qla82xx_enable_intrs(struct qla_hw_data
*ha
)
2231 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2232 qla82xx_mbx_intr_enable(vha
);
2233 spin_lock_irq(&ha
->hardware_lock
);
2234 qla82xx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_mask_reg
, 0xfbff);
2235 spin_unlock_irq(&ha
->hardware_lock
);
2236 ha
->interrupts_on
= 1;
2240 qla82xx_disable_intrs(struct qla_hw_data
*ha
)
2242 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2243 qla82xx_mbx_intr_disable(vha
);
2244 spin_lock_irq(&ha
->hardware_lock
);
2245 qla82xx_wr_32(ha
, ha
->nx_legacy_intr
.tgt_mask_reg
, 0x0400);
2246 spin_unlock_irq(&ha
->hardware_lock
);
2247 ha
->interrupts_on
= 0;
2250 void qla82xx_init_flags(struct qla_hw_data
*ha
)
2252 struct qla82xx_legacy_intr_set
*nx_legacy_intr
;
2254 /* ISP 8021 initializations */
2255 rwlock_init(&ha
->hw_lock
);
2256 ha
->qdr_sn_window
= -1;
2257 ha
->ddr_mn_window
= -1;
2258 ha
->curr_window
= 255;
2259 ha
->portnum
= PCI_FUNC(ha
->pdev
->devfn
);
2260 nx_legacy_intr
= &legacy_intr
[ha
->portnum
];
2261 ha
->nx_legacy_intr
.int_vec_bit
= nx_legacy_intr
->int_vec_bit
;
2262 ha
->nx_legacy_intr
.tgt_status_reg
= nx_legacy_intr
->tgt_status_reg
;
2263 ha
->nx_legacy_intr
.tgt_mask_reg
= nx_legacy_intr
->tgt_mask_reg
;
2264 ha
->nx_legacy_intr
.pci_int_reg
= nx_legacy_intr
->pci_int_reg
;
2268 qla82xx_set_drv_active(scsi_qla_host_t
*vha
)
2270 uint32_t drv_active
;
2271 struct qla_hw_data
*ha
= vha
->hw
;
2273 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
2275 /* If reset value is all FF's, initialize DRV_ACTIVE */
2276 if (drv_active
== 0xffffffff) {
2277 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_ACTIVE
,
2278 QLA82XX_DRV_NOT_ACTIVE
);
2279 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
2281 drv_active
|= (QLA82XX_DRV_ACTIVE
<< (ha
->portnum
* 4));
2282 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_ACTIVE
, drv_active
);
2286 qla82xx_clear_drv_active(struct qla_hw_data
*ha
)
2288 uint32_t drv_active
;
2290 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
2291 drv_active
&= ~(QLA82XX_DRV_ACTIVE
<< (ha
->portnum
* 4));
2292 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_ACTIVE
, drv_active
);
2296 qla82xx_need_reset(struct qla_hw_data
*ha
)
2301 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2302 rval
= drv_state
& (QLA82XX_DRVST_RST_RDY
<< (ha
->portnum
* 4));
2307 qla82xx_set_rst_ready(struct qla_hw_data
*ha
)
2310 scsi_qla_host_t
*vha
= pci_get_drvdata(ha
->pdev
);
2312 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2314 /* If reset value is all FF's, initialize DRV_STATE */
2315 if (drv_state
== 0xffffffff) {
2316 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, QLA82XX_DRVST_NOT_RDY
);
2317 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2319 drv_state
|= (QLA82XX_DRVST_RST_RDY
<< (ha
->portnum
* 4));
2320 qla_printk(KERN_INFO
, ha
,
2321 "%s(%ld):drv_state = 0x%x\n",
2322 __func__
, vha
->host_no
, drv_state
);
2323 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, drv_state
);
2327 qla82xx_clear_rst_ready(struct qla_hw_data
*ha
)
2331 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2332 drv_state
&= ~(QLA82XX_DRVST_RST_RDY
<< (ha
->portnum
* 4));
2333 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, drv_state
);
2337 qla82xx_set_qsnt_ready(struct qla_hw_data
*ha
)
2339 uint32_t qsnt_state
;
2341 qsnt_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
2342 qsnt_state
|= (QLA82XX_DRVST_QSNT_RDY
<< (ha
->portnum
* 4));
2343 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_STATE
, qsnt_state
);
2347 qla82xx_load_fw(scsi_qla_host_t
*vha
)
2350 struct fw_blob
*blob
;
2351 struct qla_hw_data
*ha
= vha
->hw
;
2353 if (qla82xx_pinit_from_rom(vha
) != QLA_SUCCESS
) {
2354 qla_printk(KERN_ERR
, ha
,
2355 "%s: Error during CRB Initialization\n", __func__
);
2356 return QLA_FUNCTION_FAILED
;
2360 /* Bring QM and CAMRAM out of reset */
2361 rst
= qla82xx_rd_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
);
2362 rst
&= ~((1 << 28) | (1 << 24));
2363 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_GLB_SW_RESET
, rst
);
2367 * 1) Operational firmware residing in flash.
2368 * 2) Firmware via request-firmware interface (.bin file).
2370 if (ql2xfwloadbin
== 2)
2373 qla_printk(KERN_INFO
, ha
,
2374 "Attempting to load firmware from flash\n");
2376 if (qla82xx_fw_load_from_flash(ha
) == QLA_SUCCESS
) {
2377 qla_printk(KERN_ERR
, ha
,
2378 "Firmware loaded successfully from flash\n");
2382 qla_printk(KERN_INFO
, ha
,
2383 "Attempting to load firmware from blob\n");
2385 /* Load firmware blob. */
2386 blob
= ha
->hablob
= qla2x00_request_firmware(vha
);
2388 qla_printk(KERN_ERR
, ha
,
2389 "Firmware image not present.\n");
2390 goto fw_load_failed
;
2393 /* Validating firmware blob */
2394 if (qla82xx_validate_firmware_blob(vha
,
2395 QLA82XX_FLASH_ROMIMAGE
)) {
2396 /* Fallback to URI format */
2397 if (qla82xx_validate_firmware_blob(vha
,
2398 QLA82XX_UNIFIED_ROMIMAGE
)) {
2399 qla_printk(KERN_ERR
, ha
,
2400 "No valid firmware image found!!!");
2401 return QLA_FUNCTION_FAILED
;
2405 if (qla82xx_fw_load_from_blob(ha
) == QLA_SUCCESS
) {
2406 qla_printk(KERN_ERR
, ha
,
2407 "%s: Firmware loaded successfully "
2408 " from binary blob\n", __func__
);
2411 qla_printk(KERN_ERR
, ha
,
2412 "Firmware load failed from binary blob\n");
2415 goto fw_load_failed
;
2420 return QLA_FUNCTION_FAILED
;
2424 qla82xx_start_firmware(scsi_qla_host_t
*vha
)
2428 struct qla_hw_data
*ha
= vha
->hw
;
2430 /* scrub dma mask expansion register */
2431 qla82xx_wr_32(ha
, CRB_DMA_SHIFT
, QLA82XX_DMA_SHIFT_VALUE
);
2433 /* Put both the PEG CMD and RCV PEG to default state
2434 * of 0 before resetting the hardware
2436 qla82xx_wr_32(ha
, CRB_CMDPEG_STATE
, 0);
2437 qla82xx_wr_32(ha
, CRB_RCVPEG_STATE
, 0);
2439 /* Overwrite stale initialization register values */
2440 qla82xx_wr_32(ha
, QLA82XX_PEG_HALT_STATUS1
, 0);
2441 qla82xx_wr_32(ha
, QLA82XX_PEG_HALT_STATUS2
, 0);
2443 if (qla82xx_load_fw(vha
) != QLA_SUCCESS
) {
2444 qla_printk(KERN_INFO
, ha
,
2445 "%s: Error trying to start fw!\n", __func__
);
2446 return QLA_FUNCTION_FAILED
;
2449 /* Handshake with the card before we register the devices. */
2450 if (qla82xx_check_cmdpeg_state(ha
) != QLA_SUCCESS
) {
2451 qla_printk(KERN_INFO
, ha
,
2452 "%s: Error during card handshake!\n", __func__
);
2453 return QLA_FUNCTION_FAILED
;
2456 /* Negotiated Link width */
2457 pcie_cap
= pci_find_capability(ha
->pdev
, PCI_CAP_ID_EXP
);
2458 pci_read_config_word(ha
->pdev
, pcie_cap
+ PCI_EXP_LNKSTA
, &lnk
);
2459 ha
->link_width
= (lnk
>> 4) & 0x3f;
2461 /* Synchronize with Receive peg */
2462 return qla82xx_check_rcvpeg_state(ha
);
2466 qla2xx_build_scsi_type_6_iocbs(srb_t
*sp
, struct cmd_type_6
*cmd_pkt
,
2469 uint32_t *cur_dsd
= NULL
;
2470 scsi_qla_host_t
*vha
;
2471 struct qla_hw_data
*ha
;
2472 struct scsi_cmnd
*cmd
;
2473 struct scatterlist
*cur_seg
;
2477 uint8_t first_iocb
= 1;
2478 uint32_t dsd_list_len
;
2479 struct dsd_dma
*dsd_ptr
;
2480 struct ct6_dsd
*ctx
;
2484 /* Update entry type to indicate Command Type 3 IOCB */
2485 *((uint32_t *)(&cmd_pkt
->entry_type
)) =
2486 __constant_cpu_to_le32(COMMAND_TYPE_6
);
2488 /* No data transfer */
2489 if (!scsi_bufflen(cmd
) || cmd
->sc_data_direction
== DMA_NONE
) {
2490 cmd_pkt
->byte_count
= __constant_cpu_to_le32(0);
2494 vha
= sp
->fcport
->vha
;
2497 /* Set transfer direction */
2498 if (cmd
->sc_data_direction
== DMA_TO_DEVICE
) {
2499 cmd_pkt
->control_flags
=
2500 __constant_cpu_to_le16(CF_WRITE_DATA
);
2501 ha
->qla_stats
.output_bytes
+= scsi_bufflen(cmd
);
2502 } else if (cmd
->sc_data_direction
== DMA_FROM_DEVICE
) {
2503 cmd_pkt
->control_flags
=
2504 __constant_cpu_to_le16(CF_READ_DATA
);
2505 ha
->qla_stats
.input_bytes
+= scsi_bufflen(cmd
);
2508 cur_seg
= scsi_sglist(cmd
);
2512 avail_dsds
= (tot_dsds
> QLA_DSDS_PER_IOCB
) ?
2513 QLA_DSDS_PER_IOCB
: tot_dsds
;
2514 tot_dsds
-= avail_dsds
;
2515 dsd_list_len
= (avail_dsds
+ 1) * QLA_DSD_SIZE
;
2517 dsd_ptr
= list_first_entry(&ha
->gbl_dsd_list
,
2518 struct dsd_dma
, list
);
2519 next_dsd
= dsd_ptr
->dsd_addr
;
2520 list_del(&dsd_ptr
->list
);
2521 ha
->gbl_dsd_avail
--;
2522 list_add_tail(&dsd_ptr
->list
, &ctx
->dsd_list
);
2524 ha
->gbl_dsd_inuse
++;
2528 dsd_seg
= (uint32_t *)&cmd_pkt
->fcp_data_dseg_address
;
2529 *dsd_seg
++ = cpu_to_le32(LSD(dsd_ptr
->dsd_list_dma
));
2530 *dsd_seg
++ = cpu_to_le32(MSD(dsd_ptr
->dsd_list_dma
));
2531 *dsd_seg
++ = dsd_list_len
;
2533 *cur_dsd
++ = cpu_to_le32(LSD(dsd_ptr
->dsd_list_dma
));
2534 *cur_dsd
++ = cpu_to_le32(MSD(dsd_ptr
->dsd_list_dma
));
2535 *cur_dsd
++ = dsd_list_len
;
2537 cur_dsd
= (uint32_t *)next_dsd
;
2538 while (avail_dsds
) {
2541 sle_dma
= sg_dma_address(cur_seg
);
2542 *cur_dsd
++ = cpu_to_le32(LSD(sle_dma
));
2543 *cur_dsd
++ = cpu_to_le32(MSD(sle_dma
));
2544 *cur_dsd
++ = cpu_to_le32(sg_dma_len(cur_seg
));
2550 /* Null termination */
2554 cmd_pkt
->control_flags
|= CF_DATA_SEG_DESCR_ENABLE
;
2559 * qla82xx_calc_dsd_lists() - Determine number of DSD list required
2560 * for Command Type 6.
2562 * @dsds: number of data segment decriptors needed
2564 * Returns the number of dsd list needed to store @dsds.
2567 qla82xx_calc_dsd_lists(uint16_t dsds
)
2569 uint16_t dsd_lists
= 0;
2571 dsd_lists
= (dsds
/QLA_DSDS_PER_IOCB
);
2572 if (dsds
% QLA_DSDS_PER_IOCB
)
2578 * qla82xx_start_scsi() - Send a SCSI command to the ISP
2579 * @sp: command to send to the ISP
2581 * Returns non-zero if a failure occured, else zero.
2584 qla82xx_start_scsi(srb_t
*sp
)
2587 unsigned long flags
;
2588 struct scsi_cmnd
*cmd
;
2595 struct device_reg_82xx __iomem
*reg
;
2598 uint8_t additional_cdb_len
;
2599 struct ct6_dsd
*ctx
;
2600 struct scsi_qla_host
*vha
= sp
->fcport
->vha
;
2601 struct qla_hw_data
*ha
= vha
->hw
;
2602 struct req_que
*req
= NULL
;
2603 struct rsp_que
*rsp
= NULL
;
2605 /* Setup device pointers. */
2607 reg
= &ha
->iobase
->isp82
;
2610 rsp
= ha
->rsp_q_map
[0];
2612 /* So we know we haven't pci_map'ed anything yet */
2615 dbval
= 0x04 | (ha
->portnum
<< 5);
2617 /* Send marker if required */
2618 if (vha
->marker_needed
!= 0) {
2619 if (qla2x00_marker(vha
, req
,
2620 rsp
, 0, 0, MK_SYNC_ALL
) != QLA_SUCCESS
)
2621 return QLA_FUNCTION_FAILED
;
2622 vha
->marker_needed
= 0;
2625 /* Acquire ring specific lock */
2626 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
2628 /* Check for room in outstanding command list. */
2629 handle
= req
->current_outstanding_cmd
;
2630 for (index
= 1; index
< MAX_OUTSTANDING_COMMANDS
; index
++) {
2632 if (handle
== MAX_OUTSTANDING_COMMANDS
)
2634 if (!req
->outstanding_cmds
[handle
])
2637 if (index
== MAX_OUTSTANDING_COMMANDS
)
2640 /* Map the sg table so we have an accurate count of sg entries needed */
2641 if (scsi_sg_count(cmd
)) {
2642 nseg
= dma_map_sg(&ha
->pdev
->dev
, scsi_sglist(cmd
),
2643 scsi_sg_count(cmd
), cmd
->sc_data_direction
);
2644 if (unlikely(!nseg
))
2651 if (tot_dsds
> ql2xshiftctondsd
) {
2652 struct cmd_type_6
*cmd_pkt
;
2653 uint16_t more_dsd_lists
= 0;
2654 struct dsd_dma
*dsd_ptr
;
2657 more_dsd_lists
= qla82xx_calc_dsd_lists(tot_dsds
);
2658 if ((more_dsd_lists
+ ha
->gbl_dsd_inuse
) >= NUM_DSD_CHAIN
)
2661 if (more_dsd_lists
<= ha
->gbl_dsd_avail
)
2662 goto sufficient_dsds
;
2664 more_dsd_lists
-= ha
->gbl_dsd_avail
;
2666 for (i
= 0; i
< more_dsd_lists
; i
++) {
2667 dsd_ptr
= kzalloc(sizeof(struct dsd_dma
), GFP_ATOMIC
);
2671 dsd_ptr
->dsd_addr
= dma_pool_alloc(ha
->dl_dma_pool
,
2672 GFP_ATOMIC
, &dsd_ptr
->dsd_list_dma
);
2673 if (!dsd_ptr
->dsd_addr
) {
2677 list_add_tail(&dsd_ptr
->list
, &ha
->gbl_dsd_list
);
2678 ha
->gbl_dsd_avail
++;
2684 if (req
->cnt
< (req_cnt
+ 2)) {
2685 cnt
= (uint16_t)RD_REG_DWORD_RELAXED(
2686 ®
->req_q_out
[0]);
2687 if (req
->ring_index
< cnt
)
2688 req
->cnt
= cnt
- req
->ring_index
;
2690 req
->cnt
= req
->length
-
2691 (req
->ring_index
- cnt
);
2694 if (req
->cnt
< (req_cnt
+ 2))
2697 ctx
= sp
->ctx
= mempool_alloc(ha
->ctx_mempool
, GFP_ATOMIC
);
2699 DEBUG(printk(KERN_INFO
2700 "%s(%ld): failed to allocate"
2701 " ctx.\n", __func__
, vha
->host_no
));
2704 memset(ctx
, 0, sizeof(struct ct6_dsd
));
2705 ctx
->fcp_cmnd
= dma_pool_alloc(ha
->fcp_cmnd_dma_pool
,
2706 GFP_ATOMIC
, &ctx
->fcp_cmnd_dma
);
2707 if (!ctx
->fcp_cmnd
) {
2708 DEBUG2_3(printk("%s(%ld): failed to allocate"
2709 " fcp_cmnd.\n", __func__
, vha
->host_no
));
2710 goto queuing_error_fcp_cmnd
;
2713 /* Initialize the DSD list and dma handle */
2714 INIT_LIST_HEAD(&ctx
->dsd_list
);
2715 ctx
->dsd_use_cnt
= 0;
2717 if (cmd
->cmd_len
> 16) {
2718 additional_cdb_len
= cmd
->cmd_len
- 16;
2719 if ((cmd
->cmd_len
% 4) != 0) {
2720 /* SCSI command bigger than 16 bytes must be
2723 goto queuing_error_fcp_cmnd
;
2725 ctx
->fcp_cmnd_len
= 12 + cmd
->cmd_len
+ 4;
2727 additional_cdb_len
= 0;
2728 ctx
->fcp_cmnd_len
= 12 + 16 + 4;
2731 cmd_pkt
= (struct cmd_type_6
*)req
->ring_ptr
;
2732 cmd_pkt
->handle
= MAKE_HANDLE(req
->id
, handle
);
2734 /* Zero out remaining portion of packet. */
2735 /* tagged queuing modifier -- default is TSK_SIMPLE (0). */
2736 clr_ptr
= (uint32_t *)cmd_pkt
+ 2;
2737 memset(clr_ptr
, 0, REQUEST_ENTRY_SIZE
- 8);
2738 cmd_pkt
->dseg_count
= cpu_to_le16(tot_dsds
);
2740 /* Set NPORT-ID and LUN number*/
2741 cmd_pkt
->nport_handle
= cpu_to_le16(sp
->fcport
->loop_id
);
2742 cmd_pkt
->port_id
[0] = sp
->fcport
->d_id
.b
.al_pa
;
2743 cmd_pkt
->port_id
[1] = sp
->fcport
->d_id
.b
.area
;
2744 cmd_pkt
->port_id
[2] = sp
->fcport
->d_id
.b
.domain
;
2745 cmd_pkt
->vp_index
= sp
->fcport
->vp_idx
;
2747 /* Build IOCB segments */
2748 if (qla2xx_build_scsi_type_6_iocbs(sp
, cmd_pkt
, tot_dsds
))
2749 goto queuing_error_fcp_cmnd
;
2751 int_to_scsilun(sp
->cmd
->device
->lun
, &cmd_pkt
->lun
);
2752 host_to_fcp_swap((uint8_t *)&cmd_pkt
->lun
, sizeof(cmd_pkt
->lun
));
2754 /* build FCP_CMND IU */
2755 memset(ctx
->fcp_cmnd
, 0, sizeof(struct fcp_cmnd
));
2756 int_to_scsilun(sp
->cmd
->device
->lun
, &ctx
->fcp_cmnd
->lun
);
2757 ctx
->fcp_cmnd
->additional_cdb_len
= additional_cdb_len
;
2759 if (cmd
->sc_data_direction
== DMA_TO_DEVICE
)
2760 ctx
->fcp_cmnd
->additional_cdb_len
|= 1;
2761 else if (cmd
->sc_data_direction
== DMA_FROM_DEVICE
)
2762 ctx
->fcp_cmnd
->additional_cdb_len
|= 2;
2764 memcpy(ctx
->fcp_cmnd
->cdb
, cmd
->cmnd
, cmd
->cmd_len
);
2766 fcp_dl
= (uint32_t *)(ctx
->fcp_cmnd
->cdb
+ 16 +
2767 additional_cdb_len
);
2768 *fcp_dl
= htonl((uint32_t)scsi_bufflen(cmd
));
2770 cmd_pkt
->fcp_cmnd_dseg_len
= cpu_to_le16(ctx
->fcp_cmnd_len
);
2771 cmd_pkt
->fcp_cmnd_dseg_address
[0] =
2772 cpu_to_le32(LSD(ctx
->fcp_cmnd_dma
));
2773 cmd_pkt
->fcp_cmnd_dseg_address
[1] =
2774 cpu_to_le32(MSD(ctx
->fcp_cmnd_dma
));
2776 sp
->flags
|= SRB_FCP_CMND_DMA_VALID
;
2777 cmd_pkt
->byte_count
= cpu_to_le32((uint32_t)scsi_bufflen(cmd
));
2778 /* Set total data segment count. */
2779 cmd_pkt
->entry_count
= (uint8_t)req_cnt
;
2780 /* Specify response queue number where
2781 * completion should happen
2783 cmd_pkt
->entry_status
= (uint8_t) rsp
->id
;
2785 struct cmd_type_7
*cmd_pkt
;
2786 req_cnt
= qla24xx_calc_iocbs(tot_dsds
);
2787 if (req
->cnt
< (req_cnt
+ 2)) {
2788 cnt
= (uint16_t)RD_REG_DWORD_RELAXED(
2789 ®
->req_q_out
[0]);
2790 if (req
->ring_index
< cnt
)
2791 req
->cnt
= cnt
- req
->ring_index
;
2793 req
->cnt
= req
->length
-
2794 (req
->ring_index
- cnt
);
2796 if (req
->cnt
< (req_cnt
+ 2))
2799 cmd_pkt
= (struct cmd_type_7
*)req
->ring_ptr
;
2800 cmd_pkt
->handle
= MAKE_HANDLE(req
->id
, handle
);
2802 /* Zero out remaining portion of packet. */
2803 /* tagged queuing modifier -- default is TSK_SIMPLE (0).*/
2804 clr_ptr
= (uint32_t *)cmd_pkt
+ 2;
2805 memset(clr_ptr
, 0, REQUEST_ENTRY_SIZE
- 8);
2806 cmd_pkt
->dseg_count
= cpu_to_le16(tot_dsds
);
2808 /* Set NPORT-ID and LUN number*/
2809 cmd_pkt
->nport_handle
= cpu_to_le16(sp
->fcport
->loop_id
);
2810 cmd_pkt
->port_id
[0] = sp
->fcport
->d_id
.b
.al_pa
;
2811 cmd_pkt
->port_id
[1] = sp
->fcport
->d_id
.b
.area
;
2812 cmd_pkt
->port_id
[2] = sp
->fcport
->d_id
.b
.domain
;
2813 cmd_pkt
->vp_index
= sp
->fcport
->vp_idx
;
2815 int_to_scsilun(sp
->cmd
->device
->lun
, &cmd_pkt
->lun
);
2816 host_to_fcp_swap((uint8_t *)&cmd_pkt
->lun
,
2817 sizeof(cmd_pkt
->lun
));
2819 /* Load SCSI command packet. */
2820 memcpy(cmd_pkt
->fcp_cdb
, cmd
->cmnd
, cmd
->cmd_len
);
2821 host_to_fcp_swap(cmd_pkt
->fcp_cdb
, sizeof(cmd_pkt
->fcp_cdb
));
2823 cmd_pkt
->byte_count
= cpu_to_le32((uint32_t)scsi_bufflen(cmd
));
2825 /* Build IOCB segments */
2826 qla24xx_build_scsi_iocbs(sp
, cmd_pkt
, tot_dsds
);
2828 /* Set total data segment count. */
2829 cmd_pkt
->entry_count
= (uint8_t)req_cnt
;
2830 /* Specify response queue number where
2831 * completion should happen.
2833 cmd_pkt
->entry_status
= (uint8_t) rsp
->id
;
2836 /* Build command packet. */
2837 req
->current_outstanding_cmd
= handle
;
2838 req
->outstanding_cmds
[handle
] = sp
;
2839 sp
->handle
= handle
;
2840 sp
->cmd
->host_scribble
= (unsigned char *)(unsigned long)handle
;
2841 req
->cnt
-= req_cnt
;
2844 /* Adjust ring index. */
2846 if (req
->ring_index
== req
->length
) {
2847 req
->ring_index
= 0;
2848 req
->ring_ptr
= req
->ring
;
2852 sp
->flags
|= SRB_DMA_VALID
;
2854 /* Set chip new ring index. */
2855 /* write, read and verify logic */
2856 dbval
= dbval
| (req
->id
<< 8) | (req
->ring_index
<< 16);
2858 qla82xx_wr_32(ha
, ha
->nxdb_wr_ptr
, dbval
);
2861 (unsigned long __iomem
*)ha
->nxdb_wr_ptr
,
2864 while (RD_REG_DWORD(ha
->nxdb_rd_ptr
) != dbval
) {
2866 (unsigned long __iomem
*)ha
->nxdb_wr_ptr
,
2872 /* Manage unprocessed RIO/ZIO commands in response queue. */
2873 if (vha
->flags
.process_response_queue
&&
2874 rsp
->ring_ptr
->signature
!= RESPONSE_PROCESSED
)
2875 qla24xx_process_response_queue(vha
, rsp
);
2877 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2880 queuing_error_fcp_cmnd
:
2881 dma_pool_free(ha
->fcp_cmnd_dma_pool
, ctx
->fcp_cmnd
, ctx
->fcp_cmnd_dma
);
2884 scsi_dma_unmap(cmd
);
2887 mempool_free(sp
->ctx
, ha
->ctx_mempool
);
2890 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2892 return QLA_FUNCTION_FAILED
;
2896 qla82xx_read_flash_data(scsi_qla_host_t
*vha
, uint32_t *dwptr
, uint32_t faddr
,
2901 struct qla_hw_data
*ha
= vha
->hw
;
2903 /* Dword reads to flash. */
2904 for (i
= 0; i
< length
/4; i
++, faddr
+= 4) {
2905 if (qla82xx_rom_fast_read(ha
, faddr
, &val
)) {
2906 qla_printk(KERN_WARNING
, ha
,
2907 "Do ROM fast read failed\n");
2910 dwptr
[i
] = __constant_cpu_to_le32(val
);
2917 qla82xx_unprotect_flash(struct qla_hw_data
*ha
)
2922 ret
= ql82xx_rom_lock_d(ha
);
2924 qla_printk(KERN_WARNING
, ha
, "ROM Lock failed\n");
2928 ret
= qla82xx_read_status_reg(ha
, &val
);
2930 goto done_unprotect
;
2932 val
&= ~(BLOCK_PROTECT_BITS
<< 2);
2933 ret
= qla82xx_write_status_reg(ha
, val
);
2935 val
|= (BLOCK_PROTECT_BITS
<< 2);
2936 qla82xx_write_status_reg(ha
, val
);
2939 if (qla82xx_write_disable_flash(ha
) != 0)
2940 qla_printk(KERN_WARNING
, ha
, "Write disable failed\n");
2943 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK
));
2948 qla82xx_protect_flash(struct qla_hw_data
*ha
)
2953 ret
= ql82xx_rom_lock_d(ha
);
2955 qla_printk(KERN_WARNING
, ha
, "ROM Lock failed\n");
2959 ret
= qla82xx_read_status_reg(ha
, &val
);
2963 val
|= (BLOCK_PROTECT_BITS
<< 2);
2964 /* LOCK all sectors */
2965 ret
= qla82xx_write_status_reg(ha
, val
);
2967 qla_printk(KERN_WARNING
, ha
, "Write status register failed\n");
2969 if (qla82xx_write_disable_flash(ha
) != 0)
2970 qla_printk(KERN_WARNING
, ha
, "Write disable failed\n");
2972 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK
));
2977 qla82xx_erase_sector(struct qla_hw_data
*ha
, int addr
)
2981 ret
= ql82xx_rom_lock_d(ha
);
2983 qla_printk(KERN_WARNING
, ha
, "ROM Lock failed\n");
2987 qla82xx_flash_set_write_enable(ha
);
2988 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ADDRESS
, addr
);
2989 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_ABYTE_CNT
, 3);
2990 qla82xx_wr_32(ha
, QLA82XX_ROMUSB_ROM_INSTR_OPCODE
, M25P_INSTR_SE
);
2992 if (qla82xx_wait_rom_done(ha
)) {
2993 qla_printk(KERN_WARNING
, ha
,
2994 "Error waiting for rom done\n");
2998 ret
= qla82xx_flash_wait_write_finish(ha
);
3000 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK
));
3005 * Address and length are byte address
3008 qla82xx_read_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
3009 uint32_t offset
, uint32_t length
)
3011 scsi_block_requests(vha
->host
);
3012 qla82xx_read_flash_data(vha
, (uint32_t *)buf
, offset
, length
);
3013 scsi_unblock_requests(vha
->host
);
3018 qla82xx_write_flash_data(struct scsi_qla_host
*vha
, uint32_t *dwptr
,
3019 uint32_t faddr
, uint32_t dwords
)
3023 uint32_t sec_mask
, rest_addr
;
3024 dma_addr_t optrom_dma
;
3025 void *optrom
= NULL
;
3027 struct qla_hw_data
*ha
= vha
->hw
;
3031 /* Prepare burst-capable write on supported ISPs. */
3032 if (page_mode
&& !(faddr
& 0xfff) &&
3033 dwords
> OPTROM_BURST_DWORDS
) {
3034 optrom
= dma_alloc_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
3035 &optrom_dma
, GFP_KERNEL
);
3037 qla_printk(KERN_DEBUG
, ha
,
3038 "Unable to allocate memory for optrom "
3039 "burst write (%x KB).\n",
3040 OPTROM_BURST_SIZE
/ 1024);
3044 rest_addr
= ha
->fdt_block_size
- 1;
3045 sec_mask
= ~rest_addr
;
3047 ret
= qla82xx_unprotect_flash(ha
);
3049 qla_printk(KERN_WARNING
, ha
,
3050 "Unable to unprotect flash for update.\n");
3054 for (liter
= 0; liter
< dwords
; liter
++, faddr
+= 4, dwptr
++) {
3055 /* Are we at the beginning of a sector? */
3056 if ((faddr
& rest_addr
) == 0) {
3058 ret
= qla82xx_erase_sector(ha
, faddr
);
3060 DEBUG9(qla_printk(KERN_ERR
, ha
,
3061 "Unable to erase sector: "
3062 "address=%x.\n", faddr
));
3067 /* Go with burst-write. */
3068 if (optrom
&& (liter
+ OPTROM_BURST_DWORDS
) <= dwords
) {
3069 /* Copy data to DMA'ble buffer. */
3070 memcpy(optrom
, dwptr
, OPTROM_BURST_SIZE
);
3072 ret
= qla2x00_load_ram(vha
, optrom_dma
,
3073 (ha
->flash_data_off
| faddr
),
3074 OPTROM_BURST_DWORDS
);
3075 if (ret
!= QLA_SUCCESS
) {
3076 qla_printk(KERN_WARNING
, ha
,
3077 "Unable to burst-write optrom segment "
3078 "(%x/%x/%llx).\n", ret
,
3079 (ha
->flash_data_off
| faddr
),
3080 (unsigned long long)optrom_dma
);
3081 qla_printk(KERN_WARNING
, ha
,
3082 "Reverting to slow-write.\n");
3084 dma_free_coherent(&ha
->pdev
->dev
,
3085 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
3088 liter
+= OPTROM_BURST_DWORDS
- 1;
3089 faddr
+= OPTROM_BURST_DWORDS
- 1;
3090 dwptr
+= OPTROM_BURST_DWORDS
- 1;
3095 ret
= qla82xx_write_flash_dword(ha
, faddr
,
3096 cpu_to_le32(*dwptr
));
3098 DEBUG9(printk(KERN_DEBUG
"%s(%ld) Unable to program"
3099 "flash address=%x data=%x.\n", __func__
,
3100 ha
->host_no
, faddr
, *dwptr
));
3105 ret
= qla82xx_protect_flash(ha
);
3107 qla_printk(KERN_WARNING
, ha
,
3108 "Unable to protect flash after update.\n");
3111 dma_free_coherent(&ha
->pdev
->dev
,
3112 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
3117 qla82xx_write_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
3118 uint32_t offset
, uint32_t length
)
3123 scsi_block_requests(vha
->host
);
3124 rval
= qla82xx_write_flash_data(vha
, (uint32_t *)buf
, offset
,
3126 scsi_unblock_requests(vha
->host
);
3128 /* Convert return ISP82xx to generic */
3130 rval
= QLA_FUNCTION_FAILED
;
3137 qla82xx_start_iocbs(srb_t
*sp
)
3139 struct qla_hw_data
*ha
= sp
->fcport
->vha
->hw
;
3140 struct req_que
*req
= ha
->req_q_map
[0];
3141 struct device_reg_82xx __iomem
*reg
;
3144 /* Adjust ring index. */
3146 if (req
->ring_index
== req
->length
) {
3147 req
->ring_index
= 0;
3148 req
->ring_ptr
= req
->ring
;
3152 reg
= &ha
->iobase
->isp82
;
3153 dbval
= 0x04 | (ha
->portnum
<< 5);
3155 dbval
= dbval
| (req
->id
<< 8) | (req
->ring_index
<< 16);
3157 qla82xx_wr_32(ha
, ha
->nxdb_wr_ptr
, dbval
);
3159 WRT_REG_DWORD((unsigned long __iomem
*)ha
->nxdb_wr_ptr
, dbval
);
3161 while (RD_REG_DWORD(ha
->nxdb_rd_ptr
) != dbval
) {
3162 WRT_REG_DWORD((unsigned long __iomem
*)ha
->nxdb_wr_ptr
,
3169 void qla82xx_rom_lock_recovery(struct qla_hw_data
*ha
)
3171 if (qla82xx_rom_lock(ha
))
3172 /* Someone else is holding the lock. */
3173 qla_printk(KERN_INFO
, ha
, "Resetting rom_lock\n");
3176 * Either we got the lock, or someone
3177 * else died while holding it.
3178 * In either case, unlock.
3180 qla82xx_rd_32(ha
, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK
));
3184 * qla82xx_device_bootstrap
3185 * Initialize device, set DEV_READY, start fw
3188 * IDC lock must be held upon entry
3195 qla82xx_device_bootstrap(scsi_qla_host_t
*vha
)
3197 int rval
= QLA_SUCCESS
;
3199 uint32_t old_count
, count
;
3200 struct qla_hw_data
*ha
= vha
->hw
;
3201 int need_reset
= 0, peg_stuck
= 1;
3203 need_reset
= qla82xx_need_reset(ha
);
3205 old_count
= qla82xx_rd_32(ha
, QLA82XX_PEG_ALIVE_COUNTER
);
3207 for (i
= 0; i
< 10; i
++) {
3208 timeout
= msleep_interruptible(200);
3210 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
,
3211 QLA82XX_DEV_FAILED
);
3212 return QLA_FUNCTION_FAILED
;
3215 count
= qla82xx_rd_32(ha
, QLA82XX_PEG_ALIVE_COUNTER
);
3216 if (count
!= old_count
)
3221 /* We are trying to perform a recovery here. */
3223 qla82xx_rom_lock_recovery(ha
);
3224 goto dev_initialize
;
3226 /* Start of day for this ha context. */
3228 /* Either we are the first or recovery in progress. */
3229 qla82xx_rom_lock_recovery(ha
);
3230 goto dev_initialize
;
3232 /* Firmware already running. */
3239 /* set to DEV_INITIALIZING */
3240 qla_printk(KERN_INFO
, ha
, "HW State: INITIALIZING\n");
3241 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA82XX_DEV_INITIALIZING
);
3243 /* Driver that sets device state to initializating sets IDC version */
3244 qla82xx_wr_32(ha
, QLA82XX_CRB_DRV_IDC_VERSION
, QLA82XX_IDC_VERSION
);
3246 qla82xx_idc_unlock(ha
);
3247 rval
= qla82xx_start_firmware(vha
);
3248 qla82xx_idc_lock(ha
);
3250 if (rval
!= QLA_SUCCESS
) {
3251 qla_printk(KERN_INFO
, ha
, "HW State: FAILED\n");
3252 qla82xx_clear_drv_active(ha
);
3253 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA82XX_DEV_FAILED
);
3258 qla_printk(KERN_INFO
, ha
, "HW State: READY\n");
3259 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA82XX_DEV_READY
);
3265 qla82xx_dev_failed_handler(scsi_qla_host_t
*vha
)
3267 struct qla_hw_data
*ha
= vha
->hw
;
3269 /* Disable the board */
3270 qla_printk(KERN_INFO
, ha
, "Disabling the board\n");
3272 qla82xx_idc_lock(ha
);
3273 qla82xx_clear_drv_active(ha
);
3274 qla82xx_idc_unlock(ha
);
3276 /* Set DEV_FAILED flag to disable timer */
3277 vha
->device_flags
|= DFLG_DEV_FAILED
;
3278 qla2x00_abort_all_cmds(vha
, DID_NO_CONNECT
<< 16);
3279 qla2x00_mark_all_devices_lost(vha
, 0);
3280 vha
->flags
.online
= 0;
3281 vha
->flags
.init_done
= 0;
3285 * qla82xx_need_reset_handler
3286 * Code to start reset sequence
3289 * IDC lock must be held upon entry
3296 qla82xx_need_reset_handler(scsi_qla_host_t
*vha
)
3298 uint32_t dev_state
, drv_state
, drv_active
;
3299 unsigned long reset_timeout
;
3300 struct qla_hw_data
*ha
= vha
->hw
;
3301 struct req_que
*req
= ha
->req_q_map
[0];
3303 if (vha
->flags
.online
) {
3304 qla82xx_idc_unlock(ha
);
3305 qla2x00_abort_isp_cleanup(vha
);
3306 ha
->isp_ops
->get_flash_version(vha
, req
->ring
);
3307 ha
->isp_ops
->nvram_config(vha
);
3308 qla82xx_idc_lock(ha
);
3311 qla82xx_set_rst_ready(ha
);
3313 /* wait for 10 seconds for reset ack from all functions */
3314 reset_timeout
= jiffies
+ (ha
->nx_reset_timeout
* HZ
);
3316 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
3317 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
3319 while (drv_state
!= drv_active
) {
3320 if (time_after_eq(jiffies
, reset_timeout
)) {
3321 qla_printk(KERN_INFO
, ha
,
3322 "%s: RESET TIMEOUT!\n", QLA2XXX_DRIVER_NAME
);
3325 qla82xx_idc_unlock(ha
);
3327 qla82xx_idc_lock(ha
);
3328 drv_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_STATE
);
3329 drv_active
= qla82xx_rd_32(ha
, QLA82XX_CRB_DRV_ACTIVE
);
3332 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3333 qla_printk(KERN_INFO
, ha
, "3:Device state is 0x%x = %s\n", dev_state
,
3334 dev_state
< MAX_STATES
? qdev_state
[dev_state
] : "Unknown");
3336 /* Force to DEV_COLD unless someone else is starting a reset */
3337 if (dev_state
!= QLA82XX_DEV_INITIALIZING
) {
3338 qla_printk(KERN_INFO
, ha
, "HW State: COLD/RE-INIT\n");
3339 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
, QLA82XX_DEV_COLD
);
3344 qla82xx_check_fw_alive(scsi_qla_host_t
*vha
)
3346 uint32_t fw_heartbeat_counter
, halt_status
;
3347 struct qla_hw_data
*ha
= vha
->hw
;
3349 fw_heartbeat_counter
= qla82xx_rd_32(ha
, QLA82XX_PEG_ALIVE_COUNTER
);
3350 /* all 0xff, assume AER/EEH in progress, ignore */
3351 if (fw_heartbeat_counter
== 0xffffffff)
3353 if (vha
->fw_heartbeat_counter
== fw_heartbeat_counter
) {
3354 vha
->seconds_since_last_heartbeat
++;
3355 /* FW not alive after 2 seconds */
3356 if (vha
->seconds_since_last_heartbeat
== 2) {
3357 vha
->seconds_since_last_heartbeat
= 0;
3358 halt_status
= qla82xx_rd_32(ha
,
3359 QLA82XX_PEG_HALT_STATUS1
);
3360 if (halt_status
& HALT_STATUS_UNRECOVERABLE
) {
3361 set_bit(ISP_UNRECOVERABLE
, &vha
->dpc_flags
);
3363 qla_printk(KERN_INFO
, ha
,
3364 "scsi(%ld): %s - detect abort needed\n",
3365 vha
->host_no
, __func__
);
3366 set_bit(ISP_ABORT_NEEDED
, &vha
->dpc_flags
);
3368 qla2xxx_wake_dpc(vha
);
3369 ha
->flags
.fw_hung
= 1;
3370 if (ha
->flags
.mbox_busy
) {
3371 ha
->flags
.mbox_int
= 1;
3372 DEBUG2(qla_printk(KERN_ERR
, ha
,
3373 "Due to fw hung, doing premature "
3374 "completion of mbx command\n"));
3375 if (test_bit(MBX_INTR_WAIT
,
3376 &ha
->mbx_cmd_flags
))
3377 complete(&ha
->mbx_intr_comp
);
3381 vha
->seconds_since_last_heartbeat
= 0;
3382 vha
->fw_heartbeat_counter
= fw_heartbeat_counter
;
3386 * qla82xx_device_state_handler
3387 * Main state handler
3390 * IDC lock must be held upon entry
3397 qla82xx_device_state_handler(scsi_qla_host_t
*vha
)
3400 int rval
= QLA_SUCCESS
;
3401 unsigned long dev_init_timeout
;
3402 struct qla_hw_data
*ha
= vha
->hw
;
3404 qla82xx_idc_lock(ha
);
3405 if (!vha
->flags
.init_done
)
3406 qla82xx_set_drv_active(vha
);
3408 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3409 qla_printk(KERN_INFO
, ha
, "1:Device state is 0x%x = %s\n", dev_state
,
3410 dev_state
< MAX_STATES
? qdev_state
[dev_state
] : "Unknown");
3412 /* wait for 30 seconds for device to go ready */
3413 dev_init_timeout
= jiffies
+ (ha
->nx_dev_init_timeout
* HZ
);
3417 if (time_after_eq(jiffies
, dev_init_timeout
)) {
3418 DEBUG(qla_printk(KERN_INFO
, ha
,
3419 "%s: device init failed!\n",
3420 QLA2XXX_DRIVER_NAME
));
3421 rval
= QLA_FUNCTION_FAILED
;
3424 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3425 qla_printk(KERN_INFO
, ha
,
3426 "2:Device state is 0x%x = %s\n", dev_state
,
3427 dev_state
< MAX_STATES
?
3428 qdev_state
[dev_state
] : "Unknown");
3430 switch (dev_state
) {
3431 case QLA82XX_DEV_READY
:
3433 case QLA82XX_DEV_COLD
:
3434 rval
= qla82xx_device_bootstrap(vha
);
3436 case QLA82XX_DEV_INITIALIZING
:
3437 qla82xx_idc_unlock(ha
);
3439 qla82xx_idc_lock(ha
);
3441 case QLA82XX_DEV_NEED_RESET
:
3442 if (!ql2xdontresethba
)
3443 qla82xx_need_reset_handler(vha
);
3445 case QLA82XX_DEV_NEED_QUIESCENT
:
3446 qla82xx_set_qsnt_ready(ha
);
3447 case QLA82XX_DEV_QUIESCENT
:
3448 qla82xx_idc_unlock(ha
);
3450 qla82xx_idc_lock(ha
);
3452 case QLA82XX_DEV_FAILED
:
3453 qla82xx_dev_failed_handler(vha
);
3454 rval
= QLA_FUNCTION_FAILED
;
3457 qla82xx_idc_unlock(ha
);
3459 qla82xx_idc_lock(ha
);
3463 qla82xx_idc_unlock(ha
);
3467 void qla82xx_watchdog(scsi_qla_host_t
*vha
)
3470 struct qla_hw_data
*ha
= vha
->hw
;
3472 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3474 /* don't poll if reset is going on */
3475 if (!(test_bit(ISP_ABORT_NEEDED
, &vha
->dpc_flags
) ||
3476 test_bit(ABORT_ISP_ACTIVE
, &vha
->dpc_flags
) ||
3477 test_bit(ISP_ABORT_RETRY
, &vha
->dpc_flags
))) {
3478 if (dev_state
== QLA82XX_DEV_NEED_RESET
) {
3479 qla_printk(KERN_WARNING
, ha
,
3480 "%s(): Adapter reset needed!\n", __func__
);
3481 set_bit(ISP_ABORT_NEEDED
, &vha
->dpc_flags
);
3482 qla2xxx_wake_dpc(vha
);
3483 ha
->flags
.fw_hung
= 1;
3484 if (ha
->flags
.mbox_busy
) {
3485 ha
->flags
.mbox_int
= 1;
3486 DEBUG2(qla_printk(KERN_ERR
, ha
,
3487 "Need reset, doing premature "
3488 "completion of mbx command\n"));
3489 if (test_bit(MBX_INTR_WAIT
,
3490 &ha
->mbx_cmd_flags
))
3491 complete(&ha
->mbx_intr_comp
);
3494 qla82xx_check_fw_alive(vha
);
3499 int qla82xx_load_risc(scsi_qla_host_t
*vha
, uint32_t *srisc_addr
)
3502 rval
= qla82xx_device_state_handler(vha
);
3508 * Resets ISP and aborts all outstanding commands.
3511 * ha = adapter block pointer.
3517 qla82xx_abort_isp(scsi_qla_host_t
*vha
)
3520 struct qla_hw_data
*ha
= vha
->hw
;
3523 if (vha
->device_flags
& DFLG_DEV_FAILED
) {
3524 qla_printk(KERN_WARNING
, ha
,
3525 "%s(%ld): Device in failed state, "
3526 "Exiting.\n", __func__
, vha
->host_no
);
3530 qla82xx_idc_lock(ha
);
3531 dev_state
= qla82xx_rd_32(ha
, QLA82XX_CRB_DEV_STATE
);
3532 if (dev_state
== QLA82XX_DEV_READY
) {
3533 qla_printk(KERN_INFO
, ha
, "HW State: NEED RESET\n");
3534 qla82xx_wr_32(ha
, QLA82XX_CRB_DEV_STATE
,
3535 QLA82XX_DEV_NEED_RESET
);
3537 qla_printk(KERN_INFO
, ha
, "HW State: %s\n",
3538 dev_state
< MAX_STATES
?
3539 qdev_state
[dev_state
] : "Unknown");
3540 qla82xx_idc_unlock(ha
);
3542 rval
= qla82xx_device_state_handler(vha
);
3544 qla82xx_idc_lock(ha
);
3545 qla82xx_clear_rst_ready(ha
);
3546 qla82xx_idc_unlock(ha
);
3548 if (rval
== QLA_SUCCESS
) {
3549 ha
->flags
.fw_hung
= 0;
3550 qla82xx_restart_isp(vha
);
3554 vha
->flags
.online
= 1;
3555 if (test_bit(ISP_ABORT_RETRY
, &vha
->dpc_flags
)) {
3556 if (ha
->isp_abort_cnt
== 0) {
3557 qla_printk(KERN_WARNING
, ha
,
3558 "ISP error recovery failed - "
3559 "board disabled\n");
3561 * The next call disables the board
3564 ha
->isp_ops
->reset_adapter(vha
);
3565 vha
->flags
.online
= 0;
3566 clear_bit(ISP_ABORT_RETRY
,
3569 } else { /* schedule another ISP abort */
3570 ha
->isp_abort_cnt
--;
3571 DEBUG(qla_printk(KERN_INFO
, ha
,
3572 "qla%ld: ISP abort - retry remaining %d\n",
3573 vha
->host_no
, ha
->isp_abort_cnt
));
3574 rval
= QLA_FUNCTION_FAILED
;
3577 ha
->isp_abort_cnt
= MAX_RETRIES_OF_ISP_ABORT
;
3578 DEBUG(qla_printk(KERN_INFO
, ha
,
3579 "(%ld): ISP error recovery - retrying (%d) "
3580 "more times\n", vha
->host_no
, ha
->isp_abort_cnt
));
3581 set_bit(ISP_ABORT_RETRY
, &vha
->dpc_flags
);
3582 rval
= QLA_FUNCTION_FAILED
;
3589 * qla82xx_fcoe_ctx_reset
3590 * Perform a quick reset and aborts all outstanding commands.
3591 * This will only perform an FCoE context reset and avoids a full blown
3595 * ha = adapter block pointer.
3596 * is_reset_path = flag for identifying the reset path.
3601 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t
*vha
)
3603 int rval
= QLA_FUNCTION_FAILED
;
3605 if (vha
->flags
.online
) {
3606 /* Abort all outstanding commands, so as to be requeued later */
3607 qla2x00_abort_isp_cleanup(vha
);
3610 /* Stop currently executing firmware.
3611 * This will destroy existing FCoE context at the F/W end.
3613 qla2x00_try_to_stop_firmware(vha
);
3615 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3616 rval
= qla82xx_restart_isp(vha
);
3622 * qla2x00_wait_for_fcoe_ctx_reset
3623 * Wait till the FCoE context is reset.
3626 * Does context switching here.
3627 * Release SPIN_LOCK (if any) before calling this routine.
3630 * Success (fcoe_ctx reset is done) : 0
3631 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3633 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t
*vha
)
3635 int status
= QLA_FUNCTION_FAILED
;
3636 unsigned long wait_reset
;
3638 wait_reset
= jiffies
+ (MAX_LOOP_TIMEOUT
* HZ
);
3639 while ((test_bit(FCOE_CTX_RESET_NEEDED
, &vha
->dpc_flags
) ||
3640 test_bit(ABORT_ISP_ACTIVE
, &vha
->dpc_flags
))
3641 && time_before(jiffies
, wait_reset
)) {
3643 set_current_state(TASK_UNINTERRUPTIBLE
);
3644 schedule_timeout(HZ
);
3646 if (!test_bit(FCOE_CTX_RESET_NEEDED
, &vha
->dpc_flags
) &&
3647 !test_bit(ABORT_ISP_ACTIVE
, &vha
->dpc_flags
)) {
3648 status
= QLA_SUCCESS
;
3652 DEBUG2(printk(KERN_INFO
3653 "%s status=%d\n", __func__
, status
));