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drm/i915: Retire any pending operations on the old scanout when switching
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
blobbee24b1a58e86b5dc1d1c038f8f1a653848bec97
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static inline u32 /* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device *dev)
347 {
348 if (IS_GEN5(dev)) {
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
351 } else
352 return 27;
353 }
354
355 static const intel_limit_t intel_limits_i8xx_dvo = {
356 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
357 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
358 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
359 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
360 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
361 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
362 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
363 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
364 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
366 .find_pll = intel_find_best_PLL,
367 };
368
369 static const intel_limit_t intel_limits_i8xx_lvds = {
370 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
371 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
372 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
373 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
374 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
375 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
376 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
377 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
378 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
380 .find_pll = intel_find_best_PLL,
381 };
382
383 static const intel_limit_t intel_limits_i9xx_sdvo = {
384 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
385 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
386 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
387 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
388 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
389 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
390 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
391 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
392 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
394 .find_pll = intel_find_best_PLL,
395 };
396
397 static const intel_limit_t intel_limits_i9xx_lvds = {
398 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
399 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
400 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
401 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
402 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
403 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
404 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
405 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
408 */
409 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
411 .find_pll = intel_find_best_PLL,
412 };
413
414 /* below parameter and function is for G4X Chipset Family*/
415 static const intel_limit_t intel_limits_g4x_sdvo = {
416 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
419 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
420 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
421 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
422 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
423 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
424 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
425 .p2_slow = G4X_P2_SDVO_SLOW,
426 .p2_fast = G4X_P2_SDVO_FAST
427 },
428 .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_hdmi = {
432 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
433 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
434 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
435 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
436 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
437 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
438 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
439 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
440 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
442 .p2_fast = G4X_P2_HDMI_DAC_FAST
443 },
444 .find_pll = intel_g4x_find_best_PLL,
445 };
446
447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
448 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450 .vco = { .min = G4X_VCO_MIN,
451 .max = G4X_VCO_MAX },
452 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
467 },
468 .find_pll = intel_g4x_find_best_PLL,
469 };
470
471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
472 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474 .vco = { .min = G4X_VCO_MIN,
475 .max = G4X_VCO_MAX },
476 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
491 },
492 .find_pll = intel_g4x_find_best_PLL,
493 };
494
495 static const intel_limit_t intel_limits_g4x_display_port = {
496 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497 .max = G4X_DOT_DISPLAY_PORT_MAX },
498 .vco = { .min = G4X_VCO_MIN,
499 .max = G4X_VCO_MAX},
500 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
501 .max = G4X_N_DISPLAY_PORT_MAX },
502 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
503 .max = G4X_M_DISPLAY_PORT_MAX },
504 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
505 .max = G4X_M1_DISPLAY_PORT_MAX },
506 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507 .max = G4X_M2_DISPLAY_PORT_MAX },
508 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
509 .max = G4X_P_DISPLAY_PORT_MAX },
510 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511 .max = G4X_P1_DISPLAY_PORT_MAX},
512 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515 .find_pll = intel_find_pll_g4x_dp,
516 };
517
518 static const intel_limit_t intel_limits_pineview_sdvo = {
519 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
520 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
521 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
522 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
523 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
524 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
525 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
526 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
527 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
529 .find_pll = intel_find_best_PLL,
530 };
531
532 static const intel_limit_t intel_limits_pineview_lvds = {
533 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
534 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
535 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
536 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
537 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
538 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
539 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
540 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
541 /* Pineview only supports single-channel mode. */
542 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
544 .find_pll = intel_find_best_PLL,
545 };
546
547 static const intel_limit_t intel_limits_ironlake_dac = {
548 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
549 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
550 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
551 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
552 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
553 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
554 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
555 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
556 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
557 .p2_slow = IRONLAKE_DAC_P2_SLOW,
558 .p2_fast = IRONLAKE_DAC_P2_FAST },
559 .find_pll = intel_g4x_find_best_PLL,
560 };
561
562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
563 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
564 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
565 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
566 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
567 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
568 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
569 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
570 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
571 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
572 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574 .find_pll = intel_g4x_find_best_PLL,
575 };
576
577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
579 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
580 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
581 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
582 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
583 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
584 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
585 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
586 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589 .find_pll = intel_g4x_find_best_PLL,
590 };
591
592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
594 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
595 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
598 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
599 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604 .find_pll = intel_g4x_find_best_PLL,
605 };
606
607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
610 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
613 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
614 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
619 .find_pll = intel_g4x_find_best_PLL,
620 };
621
622 static const intel_limit_t intel_limits_ironlake_display_port = {
623 .dot = { .min = IRONLAKE_DOT_MIN,
624 .max = IRONLAKE_DOT_MAX },
625 .vco = { .min = IRONLAKE_VCO_MIN,
626 .max = IRONLAKE_VCO_MAX},
627 .n = { .min = IRONLAKE_DP_N_MIN,
628 .max = IRONLAKE_DP_N_MAX },
629 .m = { .min = IRONLAKE_DP_M_MIN,
630 .max = IRONLAKE_DP_M_MAX },
631 .m1 = { .min = IRONLAKE_M1_MIN,
632 .max = IRONLAKE_M1_MAX },
633 .m2 = { .min = IRONLAKE_M2_MIN,
634 .max = IRONLAKE_M2_MAX },
635 .p = { .min = IRONLAKE_DP_P_MIN,
636 .max = IRONLAKE_DP_P_MAX },
637 .p1 = { .min = IRONLAKE_DP_P1_MIN,
638 .max = IRONLAKE_DP_P1_MAX},
639 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640 .p2_slow = IRONLAKE_DP_P2_SLOW,
641 .p2_fast = IRONLAKE_DP_P2_FAST },
642 .find_pll = intel_find_pll_ironlake_dp,
643 };
644
645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
646 {
647 struct drm_device *dev = crtc->dev;
648 struct drm_i915_private *dev_priv = dev->dev_private;
649 const intel_limit_t *limit;
650 int refclk = 120;
651
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
654 refclk = 100;
655
656 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
657 LVDS_CLKB_POWER_UP) {
658 /* LVDS dual channel */
659 if (refclk == 100)
660 limit = &intel_limits_ironlake_dual_lvds_100m;
661 else
662 limit = &intel_limits_ironlake_dual_lvds;
663 } else {
664 if (refclk == 100)
665 limit = &intel_limits_ironlake_single_lvds_100m;
666 else
667 limit = &intel_limits_ironlake_single_lvds;
668 }
669 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
670 HAS_eDP)
671 limit = &intel_limits_ironlake_display_port;
672 else
673 limit = &intel_limits_ironlake_dac;
674
675 return limit;
676 }
677
678 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
679 {
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 const intel_limit_t *limit;
683
684 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
685 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
686 LVDS_CLKB_POWER_UP)
687 /* LVDS with dual channel */
688 limit = &intel_limits_g4x_dual_channel_lvds;
689 else
690 /* LVDS with dual channel */
691 limit = &intel_limits_g4x_single_channel_lvds;
692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
693 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
694 limit = &intel_limits_g4x_hdmi;
695 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
696 limit = &intel_limits_g4x_sdvo;
697 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
698 limit = &intel_limits_g4x_display_port;
699 } else /* The option is for other outputs */
700 limit = &intel_limits_i9xx_sdvo;
701
702 return limit;
703 }
704
705 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
706 {
707 struct drm_device *dev = crtc->dev;
708 const intel_limit_t *limit;
709
710 if (HAS_PCH_SPLIT(dev))
711 limit = intel_ironlake_limit(crtc);
712 else if (IS_G4X(dev)) {
713 limit = intel_g4x_limit(crtc);
714 } else if (IS_PINEVIEW(dev)) {
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
716 limit = &intel_limits_pineview_lvds;
717 else
718 limit = &intel_limits_pineview_sdvo;
719 } else if (!IS_GEN2(dev)) {
720 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
721 limit = &intel_limits_i9xx_lvds;
722 else
723 limit = &intel_limits_i9xx_sdvo;
724 } else {
725 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
726 limit = &intel_limits_i8xx_lvds;
727 else
728 limit = &intel_limits_i8xx_dvo;
729 }
730 return limit;
731 }
732
733 /* m1 is reserved as 0 in Pineview, n is a ring counter */
734 static void pineview_clock(int refclk, intel_clock_t *clock)
735 {
736 clock->m = clock->m2 + 2;
737 clock->p = clock->p1 * clock->p2;
738 clock->vco = refclk * clock->m / clock->n;
739 clock->dot = clock->vco / clock->p;
740 }
741
742 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
743 {
744 if (IS_PINEVIEW(dev)) {
745 pineview_clock(refclk, clock);
746 return;
747 }
748 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
749 clock->p = clock->p1 * clock->p2;
750 clock->vco = refclk * clock->m / (clock->n + 2);
751 clock->dot = clock->vco / clock->p;
752 }
753
754 /**
755 * Returns whether any output on the specified pipe is of the specified type
756 */
757 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
758 {
759 struct drm_device *dev = crtc->dev;
760 struct drm_mode_config *mode_config = &dev->mode_config;
761 struct intel_encoder *encoder;
762
763 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
764 if (encoder->base.crtc == crtc && encoder->type == type)
765 return true;
766
767 return false;
768 }
769
770 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
771 /**
772 * Returns whether the given set of divisors are valid for a given refclk with
773 * the given connectors.
774 */
775
776 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
777 {
778 const intel_limit_t *limit = intel_limit (crtc);
779 struct drm_device *dev = crtc->dev;
780
781 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
782 INTELPllInvalid ("p1 out of range\n");
783 if (clock->p < limit->p.min || limit->p.max < clock->p)
784 INTELPllInvalid ("p out of range\n");
785 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
786 INTELPllInvalid ("m2 out of range\n");
787 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
788 INTELPllInvalid ("m1 out of range\n");
789 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
790 INTELPllInvalid ("m1 <= m2\n");
791 if (clock->m < limit->m.min || limit->m.max < clock->m)
792 INTELPllInvalid ("m out of range\n");
793 if (clock->n < limit->n.min || limit->n.max < clock->n)
794 INTELPllInvalid ("n out of range\n");
795 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
796 INTELPllInvalid ("vco out of range\n");
797 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
798 * connector, etc., rather than just a single range.
799 */
800 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
801 INTELPllInvalid ("dot out of range\n");
802
803 return true;
804 }
805
806 static bool
807 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
808 int target, int refclk, intel_clock_t *best_clock)
809
810 {
811 struct drm_device *dev = crtc->dev;
812 struct drm_i915_private *dev_priv = dev->dev_private;
813 intel_clock_t clock;
814 int err = target;
815
816 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
817 (I915_READ(LVDS)) != 0) {
818 /*
819 * For LVDS, if the panel is on, just rely on its current
820 * settings for dual-channel. We haven't figured out how to
821 * reliably set up different single/dual channel state, if we
822 * even can.
823 */
824 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
825 LVDS_CLKB_POWER_UP)
826 clock.p2 = limit->p2.p2_fast;
827 else
828 clock.p2 = limit->p2.p2_slow;
829 } else {
830 if (target < limit->p2.dot_limit)
831 clock.p2 = limit->p2.p2_slow;
832 else
833 clock.p2 = limit->p2.p2_fast;
834 }
835
836 memset (best_clock, 0, sizeof (*best_clock));
837
838 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
839 clock.m1++) {
840 for (clock.m2 = limit->m2.min;
841 clock.m2 <= limit->m2.max; clock.m2++) {
842 /* m1 is always 0 in Pineview */
843 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
844 break;
845 for (clock.n = limit->n.min;
846 clock.n <= limit->n.max; clock.n++) {
847 for (clock.p1 = limit->p1.min;
848 clock.p1 <= limit->p1.max; clock.p1++) {
849 int this_err;
850
851 intel_clock(dev, refclk, &clock);
852
853 if (!intel_PLL_is_valid(crtc, &clock))
854 continue;
855
856 this_err = abs(clock.dot - target);
857 if (this_err < err) {
858 *best_clock = clock;
859 err = this_err;
860 }
861 }
862 }
863 }
864 }
865
866 return (err != target);
867 }
868
869 static bool
870 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *best_clock)
872 {
873 struct drm_device *dev = crtc->dev;
874 struct drm_i915_private *dev_priv = dev->dev_private;
875 intel_clock_t clock;
876 int max_n;
877 bool found;
878 /* approximately equals target * 0.00585 */
879 int err_most = (target >> 8) + (target >> 9);
880 found = false;
881
882 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
883 int lvds_reg;
884
885 if (HAS_PCH_SPLIT(dev))
886 lvds_reg = PCH_LVDS;
887 else
888 lvds_reg = LVDS;
889 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
890 LVDS_CLKB_POWER_UP)
891 clock.p2 = limit->p2.p2_fast;
892 else
893 clock.p2 = limit->p2.p2_slow;
894 } else {
895 if (target < limit->p2.dot_limit)
896 clock.p2 = limit->p2.p2_slow;
897 else
898 clock.p2 = limit->p2.p2_fast;
899 }
900
901 memset(best_clock, 0, sizeof(*best_clock));
902 max_n = limit->n.max;
903 /* based on hardware requirement, prefer smaller n to precision */
904 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
905 /* based on hardware requirement, prefere larger m1,m2 */
906 for (clock.m1 = limit->m1.max;
907 clock.m1 >= limit->m1.min; clock.m1--) {
908 for (clock.m2 = limit->m2.max;
909 clock.m2 >= limit->m2.min; clock.m2--) {
910 for (clock.p1 = limit->p1.max;
911 clock.p1 >= limit->p1.min; clock.p1--) {
912 int this_err;
913
914 intel_clock(dev, refclk, &clock);
915 if (!intel_PLL_is_valid(crtc, &clock))
916 continue;
917 this_err = abs(clock.dot - target) ;
918 if (this_err < err_most) {
919 *best_clock = clock;
920 err_most = this_err;
921 max_n = clock.n;
922 found = true;
923 }
924 }
925 }
926 }
927 }
928 return found;
929 }
930
931 static bool
932 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
933 int target, int refclk, intel_clock_t *best_clock)
934 {
935 struct drm_device *dev = crtc->dev;
936 intel_clock_t clock;
937
938 if (target < 200000) {
939 clock.n = 1;
940 clock.p1 = 2;
941 clock.p2 = 10;
942 clock.m1 = 12;
943 clock.m2 = 9;
944 } else {
945 clock.n = 2;
946 clock.p1 = 1;
947 clock.p2 = 10;
948 clock.m1 = 14;
949 clock.m2 = 8;
950 }
951 intel_clock(dev, refclk, &clock);
952 memcpy(best_clock, &clock, sizeof(intel_clock_t));
953 return true;
954 }
955
956 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
957 static bool
958 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
959 int target, int refclk, intel_clock_t *best_clock)
960 {
961 intel_clock_t clock;
962 if (target < 200000) {
963 clock.p1 = 2;
964 clock.p2 = 10;
965 clock.n = 2;
966 clock.m1 = 23;
967 clock.m2 = 8;
968 } else {
969 clock.p1 = 1;
970 clock.p2 = 10;
971 clock.n = 1;
972 clock.m1 = 14;
973 clock.m2 = 2;
974 }
975 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
976 clock.p = (clock.p1 * clock.p2);
977 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
978 clock.vco = 0;
979 memcpy(best_clock, &clock, sizeof(intel_clock_t));
980 return true;
981 }
982
983 /**
984 * intel_wait_for_vblank - wait for vblank on a given pipe
985 * @dev: drm device
986 * @pipe: pipe to wait for
987 *
988 * Wait for vblank to occur on a given pipe. Needed for various bits of
989 * mode setting code.
990 */
991 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
992 {
993 struct drm_i915_private *dev_priv = dev->dev_private;
994 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
995
996 /* Clear existing vblank status. Note this will clear any other
997 * sticky status fields as well.
998 *
999 * This races with i915_driver_irq_handler() with the result
1000 * that either function could miss a vblank event. Here it is not
1001 * fatal, as we will either wait upon the next vblank interrupt or
1002 * timeout. Generally speaking intel_wait_for_vblank() is only
1003 * called during modeset at which time the GPU should be idle and
1004 * should *not* be performing page flips and thus not waiting on
1005 * vblanks...
1006 * Currently, the result of us stealing a vblank from the irq
1007 * handler is that a single frame will be skipped during swapbuffers.
1008 */
1009 I915_WRITE(pipestat_reg,
1010 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1011
1012 /* Wait for vblank interrupt bit to set */
1013 if (wait_for(I915_READ(pipestat_reg) &
1014 PIPE_VBLANK_INTERRUPT_STATUS,
1015 50))
1016 DRM_DEBUG_KMS("vblank wait timed out\n");
1017 }
1018
1019 /*
1020 * intel_wait_for_pipe_off - wait for pipe to turn off
1021 * @dev: drm device
1022 * @pipe: pipe to wait for
1023 *
1024 * After disabling a pipe, we can't wait for vblank in the usual way,
1025 * spinning on the vblank interrupt status bit, since we won't actually
1026 * see an interrupt when the pipe is disabled.
1027 *
1028 * On Gen4 and above:
1029 * wait for the pipe register state bit to turn off
1030 *
1031 * Otherwise:
1032 * wait for the display line value to settle (it usually
1033 * ends up stopping at the start of the next frame).
1034 *
1035 */
1036 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1037 {
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039
1040 if (INTEL_INFO(dev)->gen >= 4) {
1041 int reg = PIPECONF(pipe);
1042
1043 /* Wait for the Pipe State to go off */
1044 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1045 100))
1046 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047 } else {
1048 u32 last_line;
1049 int reg = PIPEDSL(pipe);
1050 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1051
1052 /* Wait for the display line to settle */
1053 do {
1054 last_line = I915_READ(reg) & DSL_LINEMASK;
1055 mdelay(5);
1056 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1057 time_after(timeout, jiffies));
1058 if (time_after(jiffies, timeout))
1059 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1060 }
1061 }
1062
1063 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1064 {
1065 struct drm_device *dev = crtc->dev;
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067 struct drm_framebuffer *fb = crtc->fb;
1068 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1069 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071 int plane, i;
1072 u32 fbc_ctl, fbc_ctl2;
1073
1074 if (fb->pitch == dev_priv->cfb_pitch &&
1075 obj_priv->fence_reg == dev_priv->cfb_fence &&
1076 intel_crtc->plane == dev_priv->cfb_plane &&
1077 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1078 return;
1079
1080 i8xx_disable_fbc(dev);
1081
1082 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1083
1084 if (fb->pitch < dev_priv->cfb_pitch)
1085 dev_priv->cfb_pitch = fb->pitch;
1086
1087 /* FBC_CTL wants 64B units */
1088 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089 dev_priv->cfb_fence = obj_priv->fence_reg;
1090 dev_priv->cfb_plane = intel_crtc->plane;
1091 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1092
1093 /* Clear old tags */
1094 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1095 I915_WRITE(FBC_TAG + (i * 4), 0);
1096
1097 /* Set it up... */
1098 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1099 if (obj_priv->tiling_mode != I915_TILING_NONE)
1100 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1101 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1102 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1103
1104 /* enable it... */
1105 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1106 if (IS_I945GM(dev))
1107 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1108 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1109 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1110 if (obj_priv->tiling_mode != I915_TILING_NONE)
1111 fbc_ctl |= dev_priv->cfb_fence;
1112 I915_WRITE(FBC_CONTROL, fbc_ctl);
1113
1114 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1115 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1116 }
1117
1118 void i8xx_disable_fbc(struct drm_device *dev)
1119 {
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1121 u32 fbc_ctl;
1122
1123 /* Disable compression */
1124 fbc_ctl = I915_READ(FBC_CONTROL);
1125 if ((fbc_ctl & FBC_CTL_EN) == 0)
1126 return;
1127
1128 fbc_ctl &= ~FBC_CTL_EN;
1129 I915_WRITE(FBC_CONTROL, fbc_ctl);
1130
1131 /* Wait for compressing bit to clear */
1132 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1133 DRM_DEBUG_KMS("FBC idle timed out\n");
1134 return;
1135 }
1136
1137 DRM_DEBUG_KMS("disabled FBC\n");
1138 }
1139
1140 static bool i8xx_fbc_enabled(struct drm_device *dev)
1141 {
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143
1144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1145 }
1146
1147 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1148 {
1149 struct drm_device *dev = crtc->dev;
1150 struct drm_i915_private *dev_priv = dev->dev_private;
1151 struct drm_framebuffer *fb = crtc->fb;
1152 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1153 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1155 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1156 unsigned long stall_watermark = 200;
1157 u32 dpfc_ctl;
1158
1159 dpfc_ctl = I915_READ(DPFC_CONTROL);
1160 if (dpfc_ctl & DPFC_CTL_EN) {
1161 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1162 dev_priv->cfb_fence == obj_priv->fence_reg &&
1163 dev_priv->cfb_plane == intel_crtc->plane &&
1164 dev_priv->cfb_y == crtc->y)
1165 return;
1166
1167 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1168 POSTING_READ(DPFC_CONTROL);
1169 intel_wait_for_vblank(dev, intel_crtc->pipe);
1170 }
1171
1172 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1173 dev_priv->cfb_fence = obj_priv->fence_reg;
1174 dev_priv->cfb_plane = intel_crtc->plane;
1175 dev_priv->cfb_y = crtc->y;
1176
1177 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1178 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1179 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1180 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1181 } else {
1182 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1183 }
1184
1185 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1186 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1187 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1188 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1189
1190 /* enable it... */
1191 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1192
1193 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1194 }
1195
1196 void g4x_disable_fbc(struct drm_device *dev)
1197 {
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 u32 dpfc_ctl;
1200
1201 /* Disable compression */
1202 dpfc_ctl = I915_READ(DPFC_CONTROL);
1203 if (dpfc_ctl & DPFC_CTL_EN) {
1204 dpfc_ctl &= ~DPFC_CTL_EN;
1205 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1206
1207 DRM_DEBUG_KMS("disabled FBC\n");
1208 }
1209 }
1210
1211 static bool g4x_fbc_enabled(struct drm_device *dev)
1212 {
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1216 }
1217
1218 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1219 {
1220 struct drm_device *dev = crtc->dev;
1221 struct drm_i915_private *dev_priv = dev->dev_private;
1222 struct drm_framebuffer *fb = crtc->fb;
1223 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1224 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1226 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1227 unsigned long stall_watermark = 200;
1228 u32 dpfc_ctl;
1229
1230 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1231 if (dpfc_ctl & DPFC_CTL_EN) {
1232 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1233 dev_priv->cfb_fence == obj_priv->fence_reg &&
1234 dev_priv->cfb_plane == intel_crtc->plane &&
1235 dev_priv->cfb_offset == obj_priv->gtt_offset &&
1236 dev_priv->cfb_y == crtc->y)
1237 return;
1238
1239 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1240 POSTING_READ(ILK_DPFC_CONTROL);
1241 intel_wait_for_vblank(dev, intel_crtc->pipe);
1242 }
1243
1244 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1245 dev_priv->cfb_fence = obj_priv->fence_reg;
1246 dev_priv->cfb_plane = intel_crtc->plane;
1247 dev_priv->cfb_offset = obj_priv->gtt_offset;
1248 dev_priv->cfb_y = crtc->y;
1249
1250 dpfc_ctl &= DPFC_RESERVED;
1251 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1252 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1253 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1254 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1255 } else {
1256 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1257 }
1258
1259 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1260 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1261 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1262 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1263 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1264 /* enable it... */
1265 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1266
1267 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1268 }
1269
1270 void ironlake_disable_fbc(struct drm_device *dev)
1271 {
1272 struct drm_i915_private *dev_priv = dev->dev_private;
1273 u32 dpfc_ctl;
1274
1275 /* Disable compression */
1276 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1277 if (dpfc_ctl & DPFC_CTL_EN) {
1278 dpfc_ctl &= ~DPFC_CTL_EN;
1279 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1280
1281 DRM_DEBUG_KMS("disabled FBC\n");
1282 }
1283 }
1284
1285 static bool ironlake_fbc_enabled(struct drm_device *dev)
1286 {
1287 struct drm_i915_private *dev_priv = dev->dev_private;
1288
1289 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1290 }
1291
1292 bool intel_fbc_enabled(struct drm_device *dev)
1293 {
1294 struct drm_i915_private *dev_priv = dev->dev_private;
1295
1296 if (!dev_priv->display.fbc_enabled)
1297 return false;
1298
1299 return dev_priv->display.fbc_enabled(dev);
1300 }
1301
1302 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1303 {
1304 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1305
1306 if (!dev_priv->display.enable_fbc)
1307 return;
1308
1309 dev_priv->display.enable_fbc(crtc, interval);
1310 }
1311
1312 void intel_disable_fbc(struct drm_device *dev)
1313 {
1314 struct drm_i915_private *dev_priv = dev->dev_private;
1315
1316 if (!dev_priv->display.disable_fbc)
1317 return;
1318
1319 dev_priv->display.disable_fbc(dev);
1320 }
1321
1322 /**
1323 * intel_update_fbc - enable/disable FBC as needed
1324 * @dev: the drm_device
1325 *
1326 * Set up the framebuffer compression hardware at mode set time. We
1327 * enable it if possible:
1328 * - plane A only (on pre-965)
1329 * - no pixel mulitply/line duplication
1330 * - no alpha buffer discard
1331 * - no dual wide
1332 * - framebuffer <= 2048 in width, 1536 in height
1333 *
1334 * We can't assume that any compression will take place (worst case),
1335 * so the compressed buffer has to be the same size as the uncompressed
1336 * one. It also must reside (along with the line length buffer) in
1337 * stolen memory.
1338 *
1339 * We need to enable/disable FBC on a global basis.
1340 */
1341 static void intel_update_fbc(struct drm_device *dev)
1342 {
1343 struct drm_i915_private *dev_priv = dev->dev_private;
1344 struct drm_crtc *crtc = NULL, *tmp_crtc;
1345 struct intel_crtc *intel_crtc;
1346 struct drm_framebuffer *fb;
1347 struct intel_framebuffer *intel_fb;
1348 struct drm_i915_gem_object *obj_priv;
1349
1350 DRM_DEBUG_KMS("\n");
1351
1352 if (!i915_powersave)
1353 return;
1354
1355 if (!I915_HAS_FBC(dev))
1356 return;
1357
1358 /*
1359 * If FBC is already on, we just have to verify that we can
1360 * keep it that way...
1361 * Need to disable if:
1362 * - more than one pipe is active
1363 * - changing FBC params (stride, fence, mode)
1364 * - new fb is too large to fit in compressed buffer
1365 * - going to an unsupported config (interlace, pixel multiply, etc.)
1366 */
1367 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1368 if (tmp_crtc->enabled) {
1369 if (crtc) {
1370 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1371 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1372 goto out_disable;
1373 }
1374 crtc = tmp_crtc;
1375 }
1376 }
1377
1378 if (!crtc || crtc->fb == NULL) {
1379 DRM_DEBUG_KMS("no output, disabling\n");
1380 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1381 goto out_disable;
1382 }
1383
1384 intel_crtc = to_intel_crtc(crtc);
1385 fb = crtc->fb;
1386 intel_fb = to_intel_framebuffer(fb);
1387 obj_priv = to_intel_bo(intel_fb->obj);
1388
1389 if (intel_fb->obj->size > dev_priv->cfb_size) {
1390 DRM_DEBUG_KMS("framebuffer too large, disabling "
1391 "compression\n");
1392 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1393 goto out_disable;
1394 }
1395 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1396 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1397 DRM_DEBUG_KMS("mode incompatible with compression, "
1398 "disabling\n");
1399 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1400 goto out_disable;
1401 }
1402 if ((crtc->mode.hdisplay > 2048) ||
1403 (crtc->mode.vdisplay > 1536)) {
1404 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1405 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1406 goto out_disable;
1407 }
1408 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1409 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1410 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1411 goto out_disable;
1412 }
1413 if (obj_priv->tiling_mode != I915_TILING_X) {
1414 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1415 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1416 goto out_disable;
1417 }
1418
1419 /* If the kernel debugger is active, always disable compression */
1420 if (in_dbg_master())
1421 goto out_disable;
1422
1423 intel_enable_fbc(crtc, 500);
1424 return;
1425
1426 out_disable:
1427 /* Multiple disables should be harmless */
1428 if (intel_fbc_enabled(dev)) {
1429 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1430 intel_disable_fbc(dev);
1431 }
1432 }
1433
1434 int
1435 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1436 struct drm_gem_object *obj,
1437 bool pipelined)
1438 {
1439 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1440 u32 alignment;
1441 int ret;
1442
1443 switch (obj_priv->tiling_mode) {
1444 case I915_TILING_NONE:
1445 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1446 alignment = 128 * 1024;
1447 else if (INTEL_INFO(dev)->gen >= 4)
1448 alignment = 4 * 1024;
1449 else
1450 alignment = 64 * 1024;
1451 break;
1452 case I915_TILING_X:
1453 /* pin() will align the object as required by fence */
1454 alignment = 0;
1455 break;
1456 case I915_TILING_Y:
1457 /* FIXME: Is this true? */
1458 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1459 return -EINVAL;
1460 default:
1461 BUG();
1462 }
1463
1464 ret = i915_gem_object_pin(obj, alignment);
1465 if (ret)
1466 return ret;
1467
1468 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1469 if (ret)
1470 goto err_unpin;
1471
1472 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1473 * fence, whereas 965+ only requires a fence if using
1474 * framebuffer compression. For simplicity, we always install
1475 * a fence as the cost is not that onerous.
1476 */
1477 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1478 obj_priv->tiling_mode != I915_TILING_NONE) {
1479 ret = i915_gem_object_get_fence_reg(obj, false);
1480 if (ret)
1481 goto err_unpin;
1482 }
1483
1484 return 0;
1485
1486 err_unpin:
1487 i915_gem_object_unpin(obj);
1488 return ret;
1489 }
1490
1491 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1492 static int
1493 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1494 int x, int y, enum mode_set_atomic state)
1495 {
1496 struct drm_device *dev = crtc->dev;
1497 struct drm_i915_private *dev_priv = dev->dev_private;
1498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1499 struct intel_framebuffer *intel_fb;
1500 struct drm_i915_gem_object *obj_priv;
1501 struct drm_gem_object *obj;
1502 int plane = intel_crtc->plane;
1503 unsigned long Start, Offset;
1504 u32 dspcntr;
1505 u32 reg;
1506
1507 switch (plane) {
1508 case 0:
1509 case 1:
1510 break;
1511 default:
1512 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1513 return -EINVAL;
1514 }
1515
1516 intel_fb = to_intel_framebuffer(fb);
1517 obj = intel_fb->obj;
1518 obj_priv = to_intel_bo(obj);
1519
1520 reg = DSPCNTR(plane);
1521 dspcntr = I915_READ(reg);
1522 /* Mask out pixel format bits in case we change it */
1523 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1524 switch (fb->bits_per_pixel) {
1525 case 8:
1526 dspcntr |= DISPPLANE_8BPP;
1527 break;
1528 case 16:
1529 if (fb->depth == 15)
1530 dspcntr |= DISPPLANE_15_16BPP;
1531 else
1532 dspcntr |= DISPPLANE_16BPP;
1533 break;
1534 case 24:
1535 case 32:
1536 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1537 break;
1538 default:
1539 DRM_ERROR("Unknown color depth\n");
1540 return -EINVAL;
1541 }
1542 if (INTEL_INFO(dev)->gen >= 4) {
1543 if (obj_priv->tiling_mode != I915_TILING_NONE)
1544 dspcntr |= DISPPLANE_TILED;
1545 else
1546 dspcntr &= ~DISPPLANE_TILED;
1547 }
1548
1549 if (HAS_PCH_SPLIT(dev))
1550 /* must disable */
1551 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1552
1553 I915_WRITE(reg, dspcntr);
1554
1555 Start = obj_priv->gtt_offset;
1556 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1557
1558 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1559 Start, Offset, x, y, fb->pitch);
1560 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1561 if (INTEL_INFO(dev)->gen >= 4) {
1562 I915_WRITE(DSPSURF(plane), Start);
1563 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1564 I915_WRITE(DSPADDR(plane), Offset);
1565 } else
1566 I915_WRITE(DSPADDR(plane), Start + Offset);
1567 POSTING_READ(reg);
1568
1569 intel_update_fbc(dev);
1570 intel_increase_pllclock(crtc);
1571
1572 return 0;
1573 }
1574
1575 static int
1576 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1577 struct drm_framebuffer *old_fb)
1578 {
1579 struct drm_device *dev = crtc->dev;
1580 struct drm_i915_master_private *master_priv;
1581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1582 int ret;
1583
1584 /* no fb bound */
1585 if (!crtc->fb) {
1586 DRM_DEBUG_KMS("No FB bound\n");
1587 return 0;
1588 }
1589
1590 switch (intel_crtc->plane) {
1591 case 0:
1592 case 1:
1593 break;
1594 default:
1595 return -EINVAL;
1596 }
1597
1598 mutex_lock(&dev->struct_mutex);
1599 ret = intel_pin_and_fence_fb_obj(dev,
1600 to_intel_framebuffer(crtc->fb)->obj,
1601 false);
1602 if (ret != 0) {
1603 mutex_unlock(&dev->struct_mutex);
1604 return ret;
1605 }
1606
1607 if (old_fb) {
1608 struct drm_i915_private *dev_priv = dev->dev_private;
1609 struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1610 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1611
1612 wait_event(dev_priv->pending_flip_queue,
1613 atomic_read(&obj_priv->pending_flip) == 0);
1614
1615 /* Big Hammer, we also need to ensure that any pending
1616 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1617 * current scanout is retired before unpinning the old
1618 * framebuffer.
1619 */
1620 ret = i915_gem_object_flush_gpu(obj_priv, false);
1621 if (ret) {
1622 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1623 mutex_unlock(&dev->struct_mutex);
1624 return ret;
1625 }
1626 }
1627
1628 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1629 LEAVE_ATOMIC_MODE_SET);
1630 if (ret) {
1631 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1632 mutex_unlock(&dev->struct_mutex);
1633 return ret;
1634 }
1635
1636 if (old_fb)
1637 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1638
1639 mutex_unlock(&dev->struct_mutex);
1640
1641 if (!dev->primary->master)
1642 return 0;
1643
1644 master_priv = dev->primary->master->driver_priv;
1645 if (!master_priv->sarea_priv)
1646 return 0;
1647
1648 if (intel_crtc->pipe) {
1649 master_priv->sarea_priv->pipeB_x = x;
1650 master_priv->sarea_priv->pipeB_y = y;
1651 } else {
1652 master_priv->sarea_priv->pipeA_x = x;
1653 master_priv->sarea_priv->pipeA_y = y;
1654 }
1655
1656 return 0;
1657 }
1658
1659 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1660 {
1661 struct drm_device *dev = crtc->dev;
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663 u32 dpa_ctl;
1664
1665 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1666 dpa_ctl = I915_READ(DP_A);
1667 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1668
1669 if (clock < 200000) {
1670 u32 temp;
1671 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1672 /* workaround for 160Mhz:
1673 1) program 0x4600c bits 15:0 = 0x8124
1674 2) program 0x46010 bit 0 = 1
1675 3) program 0x46034 bit 24 = 1
1676 4) program 0x64000 bit 14 = 1
1677 */
1678 temp = I915_READ(0x4600c);
1679 temp &= 0xffff0000;
1680 I915_WRITE(0x4600c, temp | 0x8124);
1681
1682 temp = I915_READ(0x46010);
1683 I915_WRITE(0x46010, temp | 1);
1684
1685 temp = I915_READ(0x46034);
1686 I915_WRITE(0x46034, temp | (1 << 24));
1687 } else {
1688 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1689 }
1690 I915_WRITE(DP_A, dpa_ctl);
1691
1692 POSTING_READ(DP_A);
1693 udelay(500);
1694 }
1695
1696 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1697 {
1698 struct drm_device *dev = crtc->dev;
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1701 int pipe = intel_crtc->pipe;
1702 u32 reg, temp;
1703
1704 /* enable normal train */
1705 reg = FDI_TX_CTL(pipe);
1706 temp = I915_READ(reg);
1707 temp &= ~FDI_LINK_TRAIN_NONE;
1708 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1709 I915_WRITE(reg, temp);
1710
1711 reg = FDI_RX_CTL(pipe);
1712 temp = I915_READ(reg);
1713 if (HAS_PCH_CPT(dev)) {
1714 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1715 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1716 } else {
1717 temp &= ~FDI_LINK_TRAIN_NONE;
1718 temp |= FDI_LINK_TRAIN_NONE;
1719 }
1720 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1721
1722 /* wait one idle pattern time */
1723 POSTING_READ(reg);
1724 udelay(1000);
1725 }
1726
1727 /* The FDI link training functions for ILK/Ibexpeak. */
1728 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1729 {
1730 struct drm_device *dev = crtc->dev;
1731 struct drm_i915_private *dev_priv = dev->dev_private;
1732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1733 int pipe = intel_crtc->pipe;
1734 u32 reg, temp, tries;
1735
1736 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1737 for train result */
1738 reg = FDI_RX_IMR(pipe);
1739 temp = I915_READ(reg);
1740 temp &= ~FDI_RX_SYMBOL_LOCK;
1741 temp &= ~FDI_RX_BIT_LOCK;
1742 I915_WRITE(reg, temp);
1743 I915_READ(reg);
1744 udelay(150);
1745
1746 /* enable CPU FDI TX and PCH FDI RX */
1747 reg = FDI_TX_CTL(pipe);
1748 temp = I915_READ(reg);
1749 temp &= ~(7 << 19);
1750 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1751 temp &= ~FDI_LINK_TRAIN_NONE;
1752 temp |= FDI_LINK_TRAIN_PATTERN_1;
1753 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1754
1755 reg = FDI_RX_CTL(pipe);
1756 temp = I915_READ(reg);
1757 temp &= ~FDI_LINK_TRAIN_NONE;
1758 temp |= FDI_LINK_TRAIN_PATTERN_1;
1759 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1760
1761 POSTING_READ(reg);
1762 udelay(150);
1763
1764 /* Ironlake workaround, enable clock pointer after FDI enable*/
1765 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1766
1767 reg = FDI_RX_IIR(pipe);
1768 for (tries = 0; tries < 5; tries++) {
1769 temp = I915_READ(reg);
1770 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1771
1772 if ((temp & FDI_RX_BIT_LOCK)) {
1773 DRM_DEBUG_KMS("FDI train 1 done.\n");
1774 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1775 break;
1776 }
1777 }
1778 if (tries == 5)
1779 DRM_ERROR("FDI train 1 fail!\n");
1780
1781 /* Train 2 */
1782 reg = FDI_TX_CTL(pipe);
1783 temp = I915_READ(reg);
1784 temp &= ~FDI_LINK_TRAIN_NONE;
1785 temp |= FDI_LINK_TRAIN_PATTERN_2;
1786 I915_WRITE(reg, temp);
1787
1788 reg = FDI_RX_CTL(pipe);
1789 temp = I915_READ(reg);
1790 temp &= ~FDI_LINK_TRAIN_NONE;
1791 temp |= FDI_LINK_TRAIN_PATTERN_2;
1792 I915_WRITE(reg, temp);
1793
1794 POSTING_READ(reg);
1795 udelay(150);
1796
1797 reg = FDI_RX_IIR(pipe);
1798 for (tries = 0; tries < 5; tries++) {
1799 temp = I915_READ(reg);
1800 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1801
1802 if (temp & FDI_RX_SYMBOL_LOCK) {
1803 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1804 DRM_DEBUG_KMS("FDI train 2 done.\n");
1805 break;
1806 }
1807 }
1808 if (tries == 5)
1809 DRM_ERROR("FDI train 2 fail!\n");
1810
1811 DRM_DEBUG_KMS("FDI train done\n");
1812
1813 }
1814
1815 static const int const snb_b_fdi_train_param [] = {
1816 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1817 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1818 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1819 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1820 };
1821
1822 /* The FDI link training functions for SNB/Cougarpoint. */
1823 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1824 {
1825 struct drm_device *dev = crtc->dev;
1826 struct drm_i915_private *dev_priv = dev->dev_private;
1827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1828 int pipe = intel_crtc->pipe;
1829 u32 reg, temp, i;
1830
1831 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1832 for train result */
1833 reg = FDI_RX_IMR(pipe);
1834 temp = I915_READ(reg);
1835 temp &= ~FDI_RX_SYMBOL_LOCK;
1836 temp &= ~FDI_RX_BIT_LOCK;
1837 I915_WRITE(reg, temp);
1838
1839 POSTING_READ(reg);
1840 udelay(150);
1841
1842 /* enable CPU FDI TX and PCH FDI RX */
1843 reg = FDI_TX_CTL(pipe);
1844 temp = I915_READ(reg);
1845 temp &= ~(7 << 19);
1846 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1847 temp &= ~FDI_LINK_TRAIN_NONE;
1848 temp |= FDI_LINK_TRAIN_PATTERN_1;
1849 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1850 /* SNB-B */
1851 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1852 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1853
1854 reg = FDI_RX_CTL(pipe);
1855 temp = I915_READ(reg);
1856 if (HAS_PCH_CPT(dev)) {
1857 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1858 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1859 } else {
1860 temp &= ~FDI_LINK_TRAIN_NONE;
1861 temp |= FDI_LINK_TRAIN_PATTERN_1;
1862 }
1863 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1864
1865 POSTING_READ(reg);
1866 udelay(150);
1867
1868 for (i = 0; i < 4; i++ ) {
1869 reg = FDI_TX_CTL(pipe);
1870 temp = I915_READ(reg);
1871 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1872 temp |= snb_b_fdi_train_param[i];
1873 I915_WRITE(reg, temp);
1874
1875 POSTING_READ(reg);
1876 udelay(500);
1877
1878 reg = FDI_RX_IIR(pipe);
1879 temp = I915_READ(reg);
1880 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1881
1882 if (temp & FDI_RX_BIT_LOCK) {
1883 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1884 DRM_DEBUG_KMS("FDI train 1 done.\n");
1885 break;
1886 }
1887 }
1888 if (i == 4)
1889 DRM_ERROR("FDI train 1 fail!\n");
1890
1891 /* Train 2 */
1892 reg = FDI_TX_CTL(pipe);
1893 temp = I915_READ(reg);
1894 temp &= ~FDI_LINK_TRAIN_NONE;
1895 temp |= FDI_LINK_TRAIN_PATTERN_2;
1896 if (IS_GEN6(dev)) {
1897 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1898 /* SNB-B */
1899 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1900 }
1901 I915_WRITE(reg, temp);
1902
1903 reg = FDI_RX_CTL(pipe);
1904 temp = I915_READ(reg);
1905 if (HAS_PCH_CPT(dev)) {
1906 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1907 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1908 } else {
1909 temp &= ~FDI_LINK_TRAIN_NONE;
1910 temp |= FDI_LINK_TRAIN_PATTERN_2;
1911 }
1912 I915_WRITE(reg, temp);
1913
1914 POSTING_READ(reg);
1915 udelay(150);
1916
1917 for (i = 0; i < 4; i++ ) {
1918 reg = FDI_TX_CTL(pipe);
1919 temp = I915_READ(reg);
1920 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1921 temp |= snb_b_fdi_train_param[i];
1922 I915_WRITE(reg, temp);
1923
1924 POSTING_READ(reg);
1925 udelay(500);
1926
1927 reg = FDI_RX_IIR(pipe);
1928 temp = I915_READ(reg);
1929 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1930
1931 if (temp & FDI_RX_SYMBOL_LOCK) {
1932 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1933 DRM_DEBUG_KMS("FDI train 2 done.\n");
1934 break;
1935 }
1936 }
1937 if (i == 4)
1938 DRM_ERROR("FDI train 2 fail!\n");
1939
1940 DRM_DEBUG_KMS("FDI train done.\n");
1941 }
1942
1943 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1944 {
1945 struct drm_device *dev = crtc->dev;
1946 struct drm_i915_private *dev_priv = dev->dev_private;
1947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1948 int pipe = intel_crtc->pipe;
1949 u32 reg, temp;
1950
1951 /* Write the TU size bits so error detection works */
1952 I915_WRITE(FDI_RX_TUSIZE1(pipe),
1953 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1954
1955 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1956 reg = FDI_RX_CTL(pipe);
1957 temp = I915_READ(reg);
1958 temp &= ~((0x7 << 19) | (0x7 << 16));
1959 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1960 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1961 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1962
1963 POSTING_READ(reg);
1964 udelay(200);
1965
1966 /* Switch from Rawclk to PCDclk */
1967 temp = I915_READ(reg);
1968 I915_WRITE(reg, temp | FDI_PCDCLK);
1969
1970 POSTING_READ(reg);
1971 udelay(200);
1972
1973 /* Enable CPU FDI TX PLL, always on for Ironlake */
1974 reg = FDI_TX_CTL(pipe);
1975 temp = I915_READ(reg);
1976 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1977 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1978
1979 POSTING_READ(reg);
1980 udelay(100);
1981 }
1982 }
1983
1984 static void intel_flush_display_plane(struct drm_device *dev,
1985 int plane)
1986 {
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 u32 reg = DSPADDR(plane);
1989 I915_WRITE(reg, I915_READ(reg));
1990 }
1991
1992 /*
1993 * When we disable a pipe, we need to clear any pending scanline wait events
1994 * to avoid hanging the ring, which we assume we are waiting on.
1995 */
1996 static void intel_clear_scanline_wait(struct drm_device *dev)
1997 {
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 u32 tmp;
2000
2001 if (IS_GEN2(dev))
2002 /* Can't break the hang on i8xx */
2003 return;
2004
2005 tmp = I915_READ(PRB0_CTL);
2006 if (tmp & RING_WAIT) {
2007 I915_WRITE(PRB0_CTL, tmp);
2008 POSTING_READ(PRB0_CTL);
2009 }
2010 }
2011
2012 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2013 {
2014 struct drm_i915_gem_object *obj_priv;
2015 struct drm_i915_private *dev_priv;
2016
2017 if (crtc->fb == NULL)
2018 return;
2019
2020 obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
2021 dev_priv = crtc->dev->dev_private;
2022 wait_event(dev_priv->pending_flip_queue,
2023 atomic_read(&obj_priv->pending_flip) == 0);
2024 }
2025
2026 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2027 {
2028 struct drm_device *dev = crtc->dev;
2029 struct drm_i915_private *dev_priv = dev->dev_private;
2030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2031 int pipe = intel_crtc->pipe;
2032 int plane = intel_crtc->plane;
2033 u32 reg, temp;
2034
2035 if (intel_crtc->active)
2036 return;
2037
2038 intel_crtc->active = true;
2039 intel_update_watermarks(dev);
2040
2041 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2042 temp = I915_READ(PCH_LVDS);
2043 if ((temp & LVDS_PORT_EN) == 0)
2044 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2045 }
2046
2047 ironlake_fdi_enable(crtc);
2048
2049 /* Enable panel fitting for LVDS */
2050 if (dev_priv->pch_pf_size &&
2051 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2052 /* Force use of hard-coded filter coefficients
2053 * as some pre-programmed values are broken,
2054 * e.g. x201.
2055 */
2056 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2057 PF_ENABLE | PF_FILTER_MED_3x3);
2058 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2059 dev_priv->pch_pf_pos);
2060 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2061 dev_priv->pch_pf_size);
2062 }
2063
2064 /* Enable CPU pipe */
2065 reg = PIPECONF(pipe);
2066 temp = I915_READ(reg);
2067 if ((temp & PIPECONF_ENABLE) == 0) {
2068 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2069 POSTING_READ(reg);
2070 intel_wait_for_vblank(dev, intel_crtc->pipe);
2071 }
2072
2073 /* configure and enable CPU plane */
2074 reg = DSPCNTR(plane);
2075 temp = I915_READ(reg);
2076 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2077 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2078 intel_flush_display_plane(dev, plane);
2079 }
2080
2081 /* For PCH output, training FDI link */
2082 if (IS_GEN6(dev))
2083 gen6_fdi_link_train(crtc);
2084 else
2085 ironlake_fdi_link_train(crtc);
2086
2087 /* enable PCH DPLL */
2088 reg = PCH_DPLL(pipe);
2089 temp = I915_READ(reg);
2090 if ((temp & DPLL_VCO_ENABLE) == 0) {
2091 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2092 POSTING_READ(reg);
2093 udelay(200);
2094 }
2095
2096 if (HAS_PCH_CPT(dev)) {
2097 /* Be sure PCH DPLL SEL is set */
2098 temp = I915_READ(PCH_DPLL_SEL);
2099 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2100 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2101 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2102 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2103 I915_WRITE(PCH_DPLL_SEL, temp);
2104 }
2105
2106 /* set transcoder timing */
2107 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2108 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2109 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2110
2111 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2112 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2113 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2114
2115 intel_fdi_normal_train(crtc);
2116
2117 /* For PCH DP, enable TRANS_DP_CTL */
2118 if (HAS_PCH_CPT(dev) &&
2119 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2120 reg = TRANS_DP_CTL(pipe);
2121 temp = I915_READ(reg);
2122 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2123 TRANS_DP_SYNC_MASK);
2124 temp |= (TRANS_DP_OUTPUT_ENABLE |
2125 TRANS_DP_ENH_FRAMING);
2126
2127 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2128 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2129 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2130 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2131
2132 switch (intel_trans_dp_port_sel(crtc)) {
2133 case PCH_DP_B:
2134 temp |= TRANS_DP_PORT_SEL_B;
2135 break;
2136 case PCH_DP_C:
2137 temp |= TRANS_DP_PORT_SEL_C;
2138 break;
2139 case PCH_DP_D:
2140 temp |= TRANS_DP_PORT_SEL_D;
2141 break;
2142 default:
2143 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2144 temp |= TRANS_DP_PORT_SEL_B;
2145 break;
2146 }
2147
2148 I915_WRITE(reg, temp);
2149 }
2150
2151 /* enable PCH transcoder */
2152 reg = TRANSCONF(pipe);
2153 temp = I915_READ(reg);
2154 /*
2155 * make the BPC in transcoder be consistent with
2156 * that in pipeconf reg.
2157 */
2158 temp &= ~PIPE_BPC_MASK;
2159 temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2160 I915_WRITE(reg, temp | TRANS_ENABLE);
2161 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2162 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2163
2164 intel_crtc_load_lut(crtc);
2165 intel_update_fbc(dev);
2166 intel_crtc_update_cursor(crtc, true);
2167 }
2168
2169 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2170 {
2171 struct drm_device *dev = crtc->dev;
2172 struct drm_i915_private *dev_priv = dev->dev_private;
2173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2174 int pipe = intel_crtc->pipe;
2175 int plane = intel_crtc->plane;
2176 u32 reg, temp;
2177
2178 if (!intel_crtc->active)
2179 return;
2180
2181 intel_crtc_wait_for_pending_flips(crtc);
2182 drm_vblank_off(dev, pipe);
2183 intel_crtc_update_cursor(crtc, false);
2184
2185 /* Disable display plane */
2186 reg = DSPCNTR(plane);
2187 temp = I915_READ(reg);
2188 if (temp & DISPLAY_PLANE_ENABLE) {
2189 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2190 intel_flush_display_plane(dev, plane);
2191 }
2192
2193 if (dev_priv->cfb_plane == plane &&
2194 dev_priv->display.disable_fbc)
2195 dev_priv->display.disable_fbc(dev);
2196
2197 /* disable cpu pipe, disable after all planes disabled */
2198 reg = PIPECONF(pipe);
2199 temp = I915_READ(reg);
2200 if (temp & PIPECONF_ENABLE) {
2201 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2202 POSTING_READ(reg);
2203 /* wait for cpu pipe off, pipe state */
2204 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2205 }
2206
2207 /* Disable PF */
2208 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2209 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2210
2211 /* disable CPU FDI tx and PCH FDI rx */
2212 reg = FDI_TX_CTL(pipe);
2213 temp = I915_READ(reg);
2214 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2215 POSTING_READ(reg);
2216
2217 reg = FDI_RX_CTL(pipe);
2218 temp = I915_READ(reg);
2219 temp &= ~(0x7 << 16);
2220 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2221 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2222
2223 POSTING_READ(reg);
2224 udelay(100);
2225
2226 /* Ironlake workaround, disable clock pointer after downing FDI */
2227 if (HAS_PCH_IBX(dev))
2228 I915_WRITE(FDI_RX_CHICKEN(pipe),
2229 I915_READ(FDI_RX_CHICKEN(pipe) &
2230 ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2231
2232 /* still set train pattern 1 */
2233 reg = FDI_TX_CTL(pipe);
2234 temp = I915_READ(reg);
2235 temp &= ~FDI_LINK_TRAIN_NONE;
2236 temp |= FDI_LINK_TRAIN_PATTERN_1;
2237 I915_WRITE(reg, temp);
2238
2239 reg = FDI_RX_CTL(pipe);
2240 temp = I915_READ(reg);
2241 if (HAS_PCH_CPT(dev)) {
2242 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2243 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2244 } else {
2245 temp &= ~FDI_LINK_TRAIN_NONE;
2246 temp |= FDI_LINK_TRAIN_PATTERN_1;
2247 }
2248 /* BPC in FDI rx is consistent with that in PIPECONF */
2249 temp &= ~(0x07 << 16);
2250 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2251 I915_WRITE(reg, temp);
2252
2253 POSTING_READ(reg);
2254 udelay(100);
2255
2256 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2257 temp = I915_READ(PCH_LVDS);
2258 if (temp & LVDS_PORT_EN) {
2259 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2260 POSTING_READ(PCH_LVDS);
2261 udelay(100);
2262 }
2263 }
2264
2265 /* disable PCH transcoder */
2266 reg = TRANSCONF(plane);
2267 temp = I915_READ(reg);
2268 if (temp & TRANS_ENABLE) {
2269 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2270 /* wait for PCH transcoder off, transcoder state */
2271 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2272 DRM_ERROR("failed to disable transcoder\n");
2273 }
2274
2275 if (HAS_PCH_CPT(dev)) {
2276 /* disable TRANS_DP_CTL */
2277 reg = TRANS_DP_CTL(pipe);
2278 temp = I915_READ(reg);
2279 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2280 I915_WRITE(reg, temp);
2281
2282 /* disable DPLL_SEL */
2283 temp = I915_READ(PCH_DPLL_SEL);
2284 if (pipe == 0)
2285 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2286 else
2287 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2288 I915_WRITE(PCH_DPLL_SEL, temp);
2289 }
2290
2291 /* disable PCH DPLL */
2292 reg = PCH_DPLL(pipe);
2293 temp = I915_READ(reg);
2294 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2295
2296 /* Switch from PCDclk to Rawclk */
2297 reg = FDI_RX_CTL(pipe);
2298 temp = I915_READ(reg);
2299 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2300
2301 /* Disable CPU FDI TX PLL */
2302 reg = FDI_TX_CTL(pipe);
2303 temp = I915_READ(reg);
2304 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2305
2306 POSTING_READ(reg);
2307 udelay(100);
2308
2309 reg = FDI_RX_CTL(pipe);
2310 temp = I915_READ(reg);
2311 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2312
2313 /* Wait for the clocks to turn off. */
2314 POSTING_READ(reg);
2315 udelay(100);
2316
2317 intel_crtc->active = false;
2318 intel_update_watermarks(dev);
2319 intel_update_fbc(dev);
2320 intel_clear_scanline_wait(dev);
2321 }
2322
2323 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2324 {
2325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2326 int pipe = intel_crtc->pipe;
2327 int plane = intel_crtc->plane;
2328
2329 /* XXX: When our outputs are all unaware of DPMS modes other than off
2330 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2331 */
2332 switch (mode) {
2333 case DRM_MODE_DPMS_ON:
2334 case DRM_MODE_DPMS_STANDBY:
2335 case DRM_MODE_DPMS_SUSPEND:
2336 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2337 ironlake_crtc_enable(crtc);
2338 break;
2339
2340 case DRM_MODE_DPMS_OFF:
2341 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2342 ironlake_crtc_disable(crtc);
2343 break;
2344 }
2345 }
2346
2347 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2348 {
2349 if (!enable && intel_crtc->overlay) {
2350 struct drm_device *dev = intel_crtc->base.dev;
2351
2352 mutex_lock(&dev->struct_mutex);
2353 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2354 mutex_unlock(&dev->struct_mutex);
2355 }
2356
2357 /* Let userspace switch the overlay on again. In most cases userspace
2358 * has to recompute where to put it anyway.
2359 */
2360 }
2361
2362 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2363 {
2364 struct drm_device *dev = crtc->dev;
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2367 int pipe = intel_crtc->pipe;
2368 int plane = intel_crtc->plane;
2369 u32 reg, temp;
2370
2371 if (intel_crtc->active)
2372 return;
2373
2374 intel_crtc->active = true;
2375 intel_update_watermarks(dev);
2376
2377 /* Enable the DPLL */
2378 reg = DPLL(pipe);
2379 temp = I915_READ(reg);
2380 if ((temp & DPLL_VCO_ENABLE) == 0) {
2381 I915_WRITE(reg, temp);
2382
2383 /* Wait for the clocks to stabilize. */
2384 POSTING_READ(reg);
2385 udelay(150);
2386
2387 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2388
2389 /* Wait for the clocks to stabilize. */
2390 POSTING_READ(reg);
2391 udelay(150);
2392
2393 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2394
2395 /* Wait for the clocks to stabilize. */
2396 POSTING_READ(reg);
2397 udelay(150);
2398 }
2399
2400 /* Enable the pipe */
2401 reg = PIPECONF(pipe);
2402 temp = I915_READ(reg);
2403 if ((temp & PIPECONF_ENABLE) == 0)
2404 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2405
2406 /* Enable the plane */
2407 reg = DSPCNTR(plane);
2408 temp = I915_READ(reg);
2409 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2410 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2411 intel_flush_display_plane(dev, plane);
2412 }
2413
2414 intel_crtc_load_lut(crtc);
2415 intel_update_fbc(dev);
2416
2417 /* Give the overlay scaler a chance to enable if it's on this pipe */
2418 intel_crtc_dpms_overlay(intel_crtc, true);
2419 intel_crtc_update_cursor(crtc, true);
2420 }
2421
2422 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2423 {
2424 struct drm_device *dev = crtc->dev;
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2427 int pipe = intel_crtc->pipe;
2428 int plane = intel_crtc->plane;
2429 u32 reg, temp;
2430
2431 if (!intel_crtc->active)
2432 return;
2433
2434 /* Give the overlay scaler a chance to disable if it's on this pipe */
2435 intel_crtc_wait_for_pending_flips(crtc);
2436 drm_vblank_off(dev, pipe);
2437 intel_crtc_dpms_overlay(intel_crtc, false);
2438 intel_crtc_update_cursor(crtc, false);
2439
2440 if (dev_priv->cfb_plane == plane &&
2441 dev_priv->display.disable_fbc)
2442 dev_priv->display.disable_fbc(dev);
2443
2444 /* Disable display plane */
2445 reg = DSPCNTR(plane);
2446 temp = I915_READ(reg);
2447 if (temp & DISPLAY_PLANE_ENABLE) {
2448 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2449 /* Flush the plane changes */
2450 intel_flush_display_plane(dev, plane);
2451
2452 /* Wait for vblank for the disable to take effect */
2453 if (IS_GEN2(dev))
2454 intel_wait_for_vblank(dev, pipe);
2455 }
2456
2457 /* Don't disable pipe A or pipe A PLLs if needed */
2458 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2459 goto done;
2460
2461 /* Next, disable display pipes */
2462 reg = PIPECONF(pipe);
2463 temp = I915_READ(reg);
2464 if (temp & PIPECONF_ENABLE) {
2465 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2466
2467 /* Wait for the pipe to turn off */
2468 POSTING_READ(reg);
2469 intel_wait_for_pipe_off(dev, pipe);
2470 }
2471
2472 reg = DPLL(pipe);
2473 temp = I915_READ(reg);
2474 if (temp & DPLL_VCO_ENABLE) {
2475 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2476
2477 /* Wait for the clocks to turn off. */
2478 POSTING_READ(reg);
2479 udelay(150);
2480 }
2481
2482 done:
2483 intel_crtc->active = false;
2484 intel_update_fbc(dev);
2485 intel_update_watermarks(dev);
2486 intel_clear_scanline_wait(dev);
2487 }
2488
2489 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2490 {
2491 /* XXX: When our outputs are all unaware of DPMS modes other than off
2492 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2493 */
2494 switch (mode) {
2495 case DRM_MODE_DPMS_ON:
2496 case DRM_MODE_DPMS_STANDBY:
2497 case DRM_MODE_DPMS_SUSPEND:
2498 i9xx_crtc_enable(crtc);
2499 break;
2500 case DRM_MODE_DPMS_OFF:
2501 i9xx_crtc_disable(crtc);
2502 break;
2503 }
2504 }
2505
2506 /**
2507 * Sets the power management mode of the pipe and plane.
2508 */
2509 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2510 {
2511 struct drm_device *dev = crtc->dev;
2512 struct drm_i915_private *dev_priv = dev->dev_private;
2513 struct drm_i915_master_private *master_priv;
2514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2515 int pipe = intel_crtc->pipe;
2516 bool enabled;
2517
2518 if (intel_crtc->dpms_mode == mode)
2519 return;
2520
2521 intel_crtc->dpms_mode = mode;
2522
2523 dev_priv->display.dpms(crtc, mode);
2524
2525 if (!dev->primary->master)
2526 return;
2527
2528 master_priv = dev->primary->master->driver_priv;
2529 if (!master_priv->sarea_priv)
2530 return;
2531
2532 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2533
2534 switch (pipe) {
2535 case 0:
2536 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2537 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2538 break;
2539 case 1:
2540 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2541 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2542 break;
2543 default:
2544 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2545 break;
2546 }
2547 }
2548
2549 static void intel_crtc_disable(struct drm_crtc *crtc)
2550 {
2551 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2552 struct drm_device *dev = crtc->dev;
2553
2554 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2555
2556 if (crtc->fb) {
2557 mutex_lock(&dev->struct_mutex);
2558 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2559 mutex_unlock(&dev->struct_mutex);
2560 }
2561 }
2562
2563 /* Prepare for a mode set.
2564 *
2565 * Note we could be a lot smarter here. We need to figure out which outputs
2566 * will be enabled, which disabled (in short, how the config will changes)
2567 * and perform the minimum necessary steps to accomplish that, e.g. updating
2568 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2569 * panel fitting is in the proper state, etc.
2570 */
2571 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2572 {
2573 i9xx_crtc_disable(crtc);
2574 }
2575
2576 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2577 {
2578 i9xx_crtc_enable(crtc);
2579 }
2580
2581 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2582 {
2583 ironlake_crtc_disable(crtc);
2584 }
2585
2586 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2587 {
2588 ironlake_crtc_enable(crtc);
2589 }
2590
2591 void intel_encoder_prepare (struct drm_encoder *encoder)
2592 {
2593 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2594 /* lvds has its own version of prepare see intel_lvds_prepare */
2595 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2596 }
2597
2598 void intel_encoder_commit (struct drm_encoder *encoder)
2599 {
2600 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2601 /* lvds has its own version of commit see intel_lvds_commit */
2602 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2603 }
2604
2605 void intel_encoder_destroy(struct drm_encoder *encoder)
2606 {
2607 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2608
2609 drm_encoder_cleanup(encoder);
2610 kfree(intel_encoder);
2611 }
2612
2613 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2614 struct drm_display_mode *mode,
2615 struct drm_display_mode *adjusted_mode)
2616 {
2617 struct drm_device *dev = crtc->dev;
2618
2619 if (HAS_PCH_SPLIT(dev)) {
2620 /* FDI link clock is fixed at 2.7G */
2621 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2622 return false;
2623 }
2624
2625 /* XXX some encoders set the crtcinfo, others don't.
2626 * Obviously we need some form of conflict resolution here...
2627 */
2628 if (adjusted_mode->crtc_htotal == 0)
2629 drm_mode_set_crtcinfo(adjusted_mode, 0);
2630
2631 return true;
2632 }
2633
2634 static int i945_get_display_clock_speed(struct drm_device *dev)
2635 {
2636 return 400000;
2637 }
2638
2639 static int i915_get_display_clock_speed(struct drm_device *dev)
2640 {
2641 return 333000;
2642 }
2643
2644 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2645 {
2646 return 200000;
2647 }
2648
2649 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2650 {
2651 u16 gcfgc = 0;
2652
2653 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2654
2655 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2656 return 133000;
2657 else {
2658 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2659 case GC_DISPLAY_CLOCK_333_MHZ:
2660 return 333000;
2661 default:
2662 case GC_DISPLAY_CLOCK_190_200_MHZ:
2663 return 190000;
2664 }
2665 }
2666 }
2667
2668 static int i865_get_display_clock_speed(struct drm_device *dev)
2669 {
2670 return 266000;
2671 }
2672
2673 static int i855_get_display_clock_speed(struct drm_device *dev)
2674 {
2675 u16 hpllcc = 0;
2676 /* Assume that the hardware is in the high speed state. This
2677 * should be the default.
2678 */
2679 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2680 case GC_CLOCK_133_200:
2681 case GC_CLOCK_100_200:
2682 return 200000;
2683 case GC_CLOCK_166_250:
2684 return 250000;
2685 case GC_CLOCK_100_133:
2686 return 133000;
2687 }
2688
2689 /* Shouldn't happen */
2690 return 0;
2691 }
2692
2693 static int i830_get_display_clock_speed(struct drm_device *dev)
2694 {
2695 return 133000;
2696 }
2697
2698 struct fdi_m_n {
2699 u32 tu;
2700 u32 gmch_m;
2701 u32 gmch_n;
2702 u32 link_m;
2703 u32 link_n;
2704 };
2705
2706 static void
2707 fdi_reduce_ratio(u32 *num, u32 *den)
2708 {
2709 while (*num > 0xffffff || *den > 0xffffff) {
2710 *num >>= 1;
2711 *den >>= 1;
2712 }
2713 }
2714
2715 #define DATA_N 0x800000
2716 #define LINK_N 0x80000
2717
2718 static void
2719 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2720 int link_clock, struct fdi_m_n *m_n)
2721 {
2722 u64 temp;
2723
2724 m_n->tu = 64; /* default size */
2725
2726 temp = (u64) DATA_N * pixel_clock;
2727 temp = div_u64(temp, link_clock);
2728 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2729 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2730 m_n->gmch_n = DATA_N;
2731 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2732
2733 temp = (u64) LINK_N * pixel_clock;
2734 m_n->link_m = div_u64(temp, link_clock);
2735 m_n->link_n = LINK_N;
2736 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2737 }
2738
2739
2740 struct intel_watermark_params {
2741 unsigned long fifo_size;
2742 unsigned long max_wm;
2743 unsigned long default_wm;
2744 unsigned long guard_size;
2745 unsigned long cacheline_size;
2746 };
2747
2748 /* Pineview has different values for various configs */
2749 static struct intel_watermark_params pineview_display_wm = {
2750 PINEVIEW_DISPLAY_FIFO,
2751 PINEVIEW_MAX_WM,
2752 PINEVIEW_DFT_WM,
2753 PINEVIEW_GUARD_WM,
2754 PINEVIEW_FIFO_LINE_SIZE
2755 };
2756 static struct intel_watermark_params pineview_display_hplloff_wm = {
2757 PINEVIEW_DISPLAY_FIFO,
2758 PINEVIEW_MAX_WM,
2759 PINEVIEW_DFT_HPLLOFF_WM,
2760 PINEVIEW_GUARD_WM,
2761 PINEVIEW_FIFO_LINE_SIZE
2762 };
2763 static struct intel_watermark_params pineview_cursor_wm = {
2764 PINEVIEW_CURSOR_FIFO,
2765 PINEVIEW_CURSOR_MAX_WM,
2766 PINEVIEW_CURSOR_DFT_WM,
2767 PINEVIEW_CURSOR_GUARD_WM,
2768 PINEVIEW_FIFO_LINE_SIZE,
2769 };
2770 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2771 PINEVIEW_CURSOR_FIFO,
2772 PINEVIEW_CURSOR_MAX_WM,
2773 PINEVIEW_CURSOR_DFT_WM,
2774 PINEVIEW_CURSOR_GUARD_WM,
2775 PINEVIEW_FIFO_LINE_SIZE
2776 };
2777 static struct intel_watermark_params g4x_wm_info = {
2778 G4X_FIFO_SIZE,
2779 G4X_MAX_WM,
2780 G4X_MAX_WM,
2781 2,
2782 G4X_FIFO_LINE_SIZE,
2783 };
2784 static struct intel_watermark_params g4x_cursor_wm_info = {
2785 I965_CURSOR_FIFO,
2786 I965_CURSOR_MAX_WM,
2787 I965_CURSOR_DFT_WM,
2788 2,
2789 G4X_FIFO_LINE_SIZE,
2790 };
2791 static struct intel_watermark_params i965_cursor_wm_info = {
2792 I965_CURSOR_FIFO,
2793 I965_CURSOR_MAX_WM,
2794 I965_CURSOR_DFT_WM,
2795 2,
2796 I915_FIFO_LINE_SIZE,
2797 };
2798 static struct intel_watermark_params i945_wm_info = {
2799 I945_FIFO_SIZE,
2800 I915_MAX_WM,
2801 1,
2802 2,
2803 I915_FIFO_LINE_SIZE
2804 };
2805 static struct intel_watermark_params i915_wm_info = {
2806 I915_FIFO_SIZE,
2807 I915_MAX_WM,
2808 1,
2809 2,
2810 I915_FIFO_LINE_SIZE
2811 };
2812 static struct intel_watermark_params i855_wm_info = {
2813 I855GM_FIFO_SIZE,
2814 I915_MAX_WM,
2815 1,
2816 2,
2817 I830_FIFO_LINE_SIZE
2818 };
2819 static struct intel_watermark_params i830_wm_info = {
2820 I830_FIFO_SIZE,
2821 I915_MAX_WM,
2822 1,
2823 2,
2824 I830_FIFO_LINE_SIZE
2825 };
2826
2827 static struct intel_watermark_params ironlake_display_wm_info = {
2828 ILK_DISPLAY_FIFO,
2829 ILK_DISPLAY_MAXWM,
2830 ILK_DISPLAY_DFTWM,
2831 2,
2832 ILK_FIFO_LINE_SIZE
2833 };
2834
2835 static struct intel_watermark_params ironlake_cursor_wm_info = {
2836 ILK_CURSOR_FIFO,
2837 ILK_CURSOR_MAXWM,
2838 ILK_CURSOR_DFTWM,
2839 2,
2840 ILK_FIFO_LINE_SIZE
2841 };
2842
2843 static struct intel_watermark_params ironlake_display_srwm_info = {
2844 ILK_DISPLAY_SR_FIFO,
2845 ILK_DISPLAY_MAX_SRWM,
2846 ILK_DISPLAY_DFT_SRWM,
2847 2,
2848 ILK_FIFO_LINE_SIZE
2849 };
2850
2851 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2852 ILK_CURSOR_SR_FIFO,
2853 ILK_CURSOR_MAX_SRWM,
2854 ILK_CURSOR_DFT_SRWM,
2855 2,
2856 ILK_FIFO_LINE_SIZE
2857 };
2858
2859 /**
2860 * intel_calculate_wm - calculate watermark level
2861 * @clock_in_khz: pixel clock
2862 * @wm: chip FIFO params
2863 * @pixel_size: display pixel size
2864 * @latency_ns: memory latency for the platform
2865 *
2866 * Calculate the watermark level (the level at which the display plane will
2867 * start fetching from memory again). Each chip has a different display
2868 * FIFO size and allocation, so the caller needs to figure that out and pass
2869 * in the correct intel_watermark_params structure.
2870 *
2871 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2872 * on the pixel size. When it reaches the watermark level, it'll start
2873 * fetching FIFO line sized based chunks from memory until the FIFO fills
2874 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2875 * will occur, and a display engine hang could result.
2876 */
2877 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2878 struct intel_watermark_params *wm,
2879 int pixel_size,
2880 unsigned long latency_ns)
2881 {
2882 long entries_required, wm_size;
2883
2884 /*
2885 * Note: we need to make sure we don't overflow for various clock &
2886 * latency values.
2887 * clocks go from a few thousand to several hundred thousand.
2888 * latency is usually a few thousand
2889 */
2890 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2891 1000;
2892 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2893
2894 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2895
2896 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2897
2898 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2899
2900 /* Don't promote wm_size to unsigned... */
2901 if (wm_size > (long)wm->max_wm)
2902 wm_size = wm->max_wm;
2903 if (wm_size <= 0)
2904 wm_size = wm->default_wm;
2905 return wm_size;
2906 }
2907
2908 struct cxsr_latency {
2909 int is_desktop;
2910 int is_ddr3;
2911 unsigned long fsb_freq;
2912 unsigned long mem_freq;
2913 unsigned long display_sr;
2914 unsigned long display_hpll_disable;
2915 unsigned long cursor_sr;
2916 unsigned long cursor_hpll_disable;
2917 };
2918
2919 static const struct cxsr_latency cxsr_latency_table[] = {
2920 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2921 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2922 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2923 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2924 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2925
2926 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2927 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2928 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2929 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2930 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2931
2932 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2933 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2934 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2935 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2936 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2937
2938 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2939 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2940 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2941 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2942 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2943
2944 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2945 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2946 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2947 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2948 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2949
2950 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2951 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2952 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2953 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2954 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2955 };
2956
2957 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2958 int is_ddr3,
2959 int fsb,
2960 int mem)
2961 {
2962 const struct cxsr_latency *latency;
2963 int i;
2964
2965 if (fsb == 0 || mem == 0)
2966 return NULL;
2967
2968 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2969 latency = &cxsr_latency_table[i];
2970 if (is_desktop == latency->is_desktop &&
2971 is_ddr3 == latency->is_ddr3 &&
2972 fsb == latency->fsb_freq && mem == latency->mem_freq)
2973 return latency;
2974 }
2975
2976 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2977
2978 return NULL;
2979 }
2980
2981 static void pineview_disable_cxsr(struct drm_device *dev)
2982 {
2983 struct drm_i915_private *dev_priv = dev->dev_private;
2984
2985 /* deactivate cxsr */
2986 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2987 }
2988
2989 /*
2990 * Latency for FIFO fetches is dependent on several factors:
2991 * - memory configuration (speed, channels)
2992 * - chipset
2993 * - current MCH state
2994 * It can be fairly high in some situations, so here we assume a fairly
2995 * pessimal value. It's a tradeoff between extra memory fetches (if we
2996 * set this value too high, the FIFO will fetch frequently to stay full)
2997 * and power consumption (set it too low to save power and we might see
2998 * FIFO underruns and display "flicker").
2999 *
3000 * A value of 5us seems to be a good balance; safe for very low end
3001 * platforms but not overly aggressive on lower latency configs.
3002 */
3003 static const int latency_ns = 5000;
3004
3005 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3006 {
3007 struct drm_i915_private *dev_priv = dev->dev_private;
3008 uint32_t dsparb = I915_READ(DSPARB);
3009 int size;
3010
3011 size = dsparb & 0x7f;
3012 if (plane)
3013 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3014
3015 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3016 plane ? "B" : "A", size);
3017
3018 return size;
3019 }
3020
3021 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3022 {
3023 struct drm_i915_private *dev_priv = dev->dev_private;
3024 uint32_t dsparb = I915_READ(DSPARB);
3025 int size;
3026
3027 size = dsparb & 0x1ff;
3028 if (plane)
3029 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3030 size >>= 1; /* Convert to cachelines */
3031
3032 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3033 plane ? "B" : "A", size);
3034
3035 return size;
3036 }
3037
3038 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3039 {
3040 struct drm_i915_private *dev_priv = dev->dev_private;
3041 uint32_t dsparb = I915_READ(DSPARB);
3042 int size;
3043
3044 size = dsparb & 0x7f;
3045 size >>= 2; /* Convert to cachelines */
3046
3047 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3048 plane ? "B" : "A",
3049 size);
3050
3051 return size;
3052 }
3053
3054 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3055 {
3056 struct drm_i915_private *dev_priv = dev->dev_private;
3057 uint32_t dsparb = I915_READ(DSPARB);
3058 int size;
3059
3060 size = dsparb & 0x7f;
3061 size >>= 1; /* Convert to cachelines */
3062
3063 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3064 plane ? "B" : "A", size);
3065
3066 return size;
3067 }
3068
3069 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3070 int planeb_clock, int sr_hdisplay, int unused,
3071 int pixel_size)
3072 {
3073 struct drm_i915_private *dev_priv = dev->dev_private;
3074 const struct cxsr_latency *latency;
3075 u32 reg;
3076 unsigned long wm;
3077 int sr_clock;
3078
3079 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3080 dev_priv->fsb_freq, dev_priv->mem_freq);
3081 if (!latency) {
3082 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3083 pineview_disable_cxsr(dev);
3084 return;
3085 }
3086
3087 if (!planea_clock || !planeb_clock) {
3088 sr_clock = planea_clock ? planea_clock : planeb_clock;
3089
3090 /* Display SR */
3091 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3092 pixel_size, latency->display_sr);
3093 reg = I915_READ(DSPFW1);
3094 reg &= ~DSPFW_SR_MASK;
3095 reg |= wm << DSPFW_SR_SHIFT;
3096 I915_WRITE(DSPFW1, reg);
3097 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3098
3099 /* cursor SR */
3100 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3101 pixel_size, latency->cursor_sr);
3102 reg = I915_READ(DSPFW3);
3103 reg &= ~DSPFW_CURSOR_SR_MASK;
3104 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3105 I915_WRITE(DSPFW3, reg);
3106
3107 /* Display HPLL off SR */
3108 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3109 pixel_size, latency->display_hpll_disable);
3110 reg = I915_READ(DSPFW3);
3111 reg &= ~DSPFW_HPLL_SR_MASK;
3112 reg |= wm & DSPFW_HPLL_SR_MASK;
3113 I915_WRITE(DSPFW3, reg);
3114
3115 /* cursor HPLL off SR */
3116 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3117 pixel_size, latency->cursor_hpll_disable);
3118 reg = I915_READ(DSPFW3);
3119 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3120 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3121 I915_WRITE(DSPFW3, reg);
3122 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3123
3124 /* activate cxsr */
3125 I915_WRITE(DSPFW3,
3126 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3127 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3128 } else {
3129 pineview_disable_cxsr(dev);
3130 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3131 }
3132 }
3133
3134 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3135 int planeb_clock, int sr_hdisplay, int sr_htotal,
3136 int pixel_size)
3137 {
3138 struct drm_i915_private *dev_priv = dev->dev_private;
3139 int total_size, cacheline_size;
3140 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3141 struct intel_watermark_params planea_params, planeb_params;
3142 unsigned long line_time_us;
3143 int sr_clock, sr_entries = 0, entries_required;
3144
3145 /* Create copies of the base settings for each pipe */
3146 planea_params = planeb_params = g4x_wm_info;
3147
3148 /* Grab a couple of global values before we overwrite them */
3149 total_size = planea_params.fifo_size;
3150 cacheline_size = planea_params.cacheline_size;
3151
3152 /*
3153 * Note: we need to make sure we don't overflow for various clock &
3154 * latency values.
3155 * clocks go from a few thousand to several hundred thousand.
3156 * latency is usually a few thousand
3157 */
3158 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3159 1000;
3160 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3161 planea_wm = entries_required + planea_params.guard_size;
3162
3163 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3164 1000;
3165 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3166 planeb_wm = entries_required + planeb_params.guard_size;
3167
3168 cursora_wm = cursorb_wm = 16;
3169 cursor_sr = 32;
3170
3171 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3172
3173 /* Calc sr entries for one plane configs */
3174 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3175 /* self-refresh has much higher latency */
3176 static const int sr_latency_ns = 12000;
3177
3178 sr_clock = planea_clock ? planea_clock : planeb_clock;
3179 line_time_us = ((sr_htotal * 1000) / sr_clock);
3180
3181 /* Use ns/us then divide to preserve precision */
3182 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3183 pixel_size * sr_hdisplay;
3184 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3185
3186 entries_required = (((sr_latency_ns / line_time_us) +
3187 1000) / 1000) * pixel_size * 64;
3188 entries_required = DIV_ROUND_UP(entries_required,
3189 g4x_cursor_wm_info.cacheline_size);
3190 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3191
3192 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3193 cursor_sr = g4x_cursor_wm_info.max_wm;
3194 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3195 "cursor %d\n", sr_entries, cursor_sr);
3196
3197 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3198 } else {
3199 /* Turn off self refresh if both pipes are enabled */
3200 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3201 & ~FW_BLC_SELF_EN);
3202 }
3203
3204 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3205 planea_wm, planeb_wm, sr_entries);
3206
3207 planea_wm &= 0x3f;
3208 planeb_wm &= 0x3f;
3209
3210 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3211 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3212 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3213 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3214 (cursora_wm << DSPFW_CURSORA_SHIFT));
3215 /* HPLL off in SR has some issues on G4x... disable it */
3216 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3217 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3218 }
3219
3220 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3221 int planeb_clock, int sr_hdisplay, int sr_htotal,
3222 int pixel_size)
3223 {
3224 struct drm_i915_private *dev_priv = dev->dev_private;
3225 unsigned long line_time_us;
3226 int sr_clock, sr_entries, srwm = 1;
3227 int cursor_sr = 16;
3228
3229 /* Calc sr entries for one plane configs */
3230 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3231 /* self-refresh has much higher latency */
3232 static const int sr_latency_ns = 12000;
3233
3234 sr_clock = planea_clock ? planea_clock : planeb_clock;
3235 line_time_us = ((sr_htotal * 1000) / sr_clock);
3236
3237 /* Use ns/us then divide to preserve precision */
3238 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3239 pixel_size * sr_hdisplay;
3240 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3241 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3242 srwm = I965_FIFO_SIZE - sr_entries;
3243 if (srwm < 0)
3244 srwm = 1;
3245 srwm &= 0x1ff;
3246
3247 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3248 pixel_size * 64;
3249 sr_entries = DIV_ROUND_UP(sr_entries,
3250 i965_cursor_wm_info.cacheline_size);
3251 cursor_sr = i965_cursor_wm_info.fifo_size -
3252 (sr_entries + i965_cursor_wm_info.guard_size);
3253
3254 if (cursor_sr > i965_cursor_wm_info.max_wm)
3255 cursor_sr = i965_cursor_wm_info.max_wm;
3256
3257 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3258 "cursor %d\n", srwm, cursor_sr);
3259
3260 if (IS_CRESTLINE(dev))
3261 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3262 } else {
3263 /* Turn off self refresh if both pipes are enabled */
3264 if (IS_CRESTLINE(dev))
3265 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3266 & ~FW_BLC_SELF_EN);
3267 }
3268
3269 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3270 srwm);
3271
3272 /* 965 has limitations... */
3273 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3274 (8 << 0));
3275 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3276 /* update cursor SR watermark */
3277 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3278 }
3279
3280 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3281 int planeb_clock, int sr_hdisplay, int sr_htotal,
3282 int pixel_size)
3283 {
3284 struct drm_i915_private *dev_priv = dev->dev_private;
3285 uint32_t fwater_lo;
3286 uint32_t fwater_hi;
3287 int total_size, cacheline_size, cwm, srwm = 1;
3288 int planea_wm, planeb_wm;
3289 struct intel_watermark_params planea_params, planeb_params;
3290 unsigned long line_time_us;
3291 int sr_clock, sr_entries = 0;
3292
3293 /* Create copies of the base settings for each pipe */
3294 if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3295 planea_params = planeb_params = i945_wm_info;
3296 else if (!IS_GEN2(dev))
3297 planea_params = planeb_params = i915_wm_info;
3298 else
3299 planea_params = planeb_params = i855_wm_info;
3300
3301 /* Grab a couple of global values before we overwrite them */
3302 total_size = planea_params.fifo_size;
3303 cacheline_size = planea_params.cacheline_size;
3304
3305 /* Update per-plane FIFO sizes */
3306 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3307 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3308
3309 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3310 pixel_size, latency_ns);
3311 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3312 pixel_size, latency_ns);
3313 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3314
3315 /*
3316 * Overlay gets an aggressive default since video jitter is bad.
3317 */
3318 cwm = 2;
3319
3320 /* Calc sr entries for one plane configs */
3321 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3322 (!planea_clock || !planeb_clock)) {
3323 /* self-refresh has much higher latency */
3324 static const int sr_latency_ns = 6000;
3325
3326 sr_clock = planea_clock ? planea_clock : planeb_clock;
3327 line_time_us = ((sr_htotal * 1000) / sr_clock);
3328
3329 /* Use ns/us then divide to preserve precision */
3330 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3331 pixel_size * sr_hdisplay;
3332 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3333 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3334 srwm = total_size - sr_entries;
3335 if (srwm < 0)
3336 srwm = 1;
3337
3338 if (IS_I945G(dev) || IS_I945GM(dev))
3339 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3340 else if (IS_I915GM(dev)) {
3341 /* 915M has a smaller SRWM field */
3342 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3343 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3344 }
3345 } else {
3346 /* Turn off self refresh if both pipes are enabled */
3347 if (IS_I945G(dev) || IS_I945GM(dev)) {
3348 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3349 & ~FW_BLC_SELF_EN);
3350 } else if (IS_I915GM(dev)) {
3351 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3352 }
3353 }
3354
3355 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3356 planea_wm, planeb_wm, cwm, srwm);
3357
3358 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3359 fwater_hi = (cwm & 0x1f);
3360
3361 /* Set request length to 8 cachelines per fetch */
3362 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3363 fwater_hi = fwater_hi | (1 << 8);
3364
3365 I915_WRITE(FW_BLC, fwater_lo);
3366 I915_WRITE(FW_BLC2, fwater_hi);
3367 }
3368
3369 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3370 int unused2, int unused3, int pixel_size)
3371 {
3372 struct drm_i915_private *dev_priv = dev->dev_private;
3373 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3374 int planea_wm;
3375
3376 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3377
3378 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3379 pixel_size, latency_ns);
3380 fwater_lo |= (3<<8) | planea_wm;
3381
3382 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3383
3384 I915_WRITE(FW_BLC, fwater_lo);
3385 }
3386
3387 #define ILK_LP0_PLANE_LATENCY 700
3388 #define ILK_LP0_CURSOR_LATENCY 1300
3389
3390 static bool ironlake_compute_wm0(struct drm_device *dev,
3391 int pipe,
3392 int *plane_wm,
3393 int *cursor_wm)
3394 {
3395 struct drm_crtc *crtc;
3396 int htotal, hdisplay, clock, pixel_size = 0;
3397 int line_time_us, line_count, entries;
3398
3399 crtc = intel_get_crtc_for_pipe(dev, pipe);
3400 if (crtc->fb == NULL || !crtc->enabled)
3401 return false;
3402
3403 htotal = crtc->mode.htotal;
3404 hdisplay = crtc->mode.hdisplay;
3405 clock = crtc->mode.clock;
3406 pixel_size = crtc->fb->bits_per_pixel / 8;
3407
3408 /* Use the small buffer method to calculate plane watermark */
3409 entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3410 entries = DIV_ROUND_UP(entries,
3411 ironlake_display_wm_info.cacheline_size);
3412 *plane_wm = entries + ironlake_display_wm_info.guard_size;
3413 if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3414 *plane_wm = ironlake_display_wm_info.max_wm;
3415
3416 /* Use the large buffer method to calculate cursor watermark */
3417 line_time_us = ((htotal * 1000) / clock);
3418 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3419 entries = line_count * 64 * pixel_size;
3420 entries = DIV_ROUND_UP(entries,
3421 ironlake_cursor_wm_info.cacheline_size);
3422 *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3423 if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3424 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3425
3426 return true;
3427 }
3428
3429 static void ironlake_update_wm(struct drm_device *dev,
3430 int planea_clock, int planeb_clock,
3431 int sr_hdisplay, int sr_htotal,
3432 int pixel_size)
3433 {
3434 struct drm_i915_private *dev_priv = dev->dev_private;
3435 int plane_wm, cursor_wm, enabled;
3436 int tmp;
3437
3438 enabled = 0;
3439 if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3440 I915_WRITE(WM0_PIPEA_ILK,
3441 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3442 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3443 " plane %d, " "cursor: %d\n",
3444 plane_wm, cursor_wm);
3445 enabled++;
3446 }
3447
3448 if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3449 I915_WRITE(WM0_PIPEB_ILK,
3450 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3451 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3452 " plane %d, cursor: %d\n",
3453 plane_wm, cursor_wm);
3454 enabled++;
3455 }
3456
3457 /*
3458 * Calculate and update the self-refresh watermark only when one
3459 * display plane is used.
3460 */
3461 tmp = 0;
3462 if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3463 unsigned long line_time_us;
3464 int small, large, plane_fbc;
3465 int sr_clock, entries;
3466 int line_count, line_size;
3467 /* Read the self-refresh latency. The unit is 0.5us */
3468 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3469
3470 sr_clock = planea_clock ? planea_clock : planeb_clock;
3471 line_time_us = (sr_htotal * 1000) / sr_clock;
3472
3473 /* Use ns/us then divide to preserve precision */
3474 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3475 / 1000;
3476 line_size = sr_hdisplay * pixel_size;
3477
3478 /* Use the minimum of the small and large buffer method for primary */
3479 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3480 large = line_count * line_size;
3481
3482 entries = DIV_ROUND_UP(min(small, large),
3483 ironlake_display_srwm_info.cacheline_size);
3484
3485 plane_fbc = entries * 64;
3486 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3487
3488 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3489 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3490 plane_wm = ironlake_display_srwm_info.max_wm;
3491
3492 /* calculate the self-refresh watermark for display cursor */
3493 entries = line_count * pixel_size * 64;
3494 entries = DIV_ROUND_UP(entries,
3495 ironlake_cursor_srwm_info.cacheline_size);
3496
3497 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3498 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3499 cursor_wm = ironlake_cursor_srwm_info.max_wm;
3500
3501 /* configure watermark and enable self-refresh */
3502 tmp = (WM1_LP_SR_EN |
3503 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3504 (plane_fbc << WM1_LP_FBC_SHIFT) |
3505 (plane_wm << WM1_LP_SR_SHIFT) |
3506 cursor_wm);
3507 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3508 " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3509 }
3510 I915_WRITE(WM1_LP_ILK, tmp);
3511 /* XXX setup WM2 and WM3 */
3512 }
3513
3514 /**
3515 * intel_update_watermarks - update FIFO watermark values based on current modes
3516 *
3517 * Calculate watermark values for the various WM regs based on current mode
3518 * and plane configuration.
3519 *
3520 * There are several cases to deal with here:
3521 * - normal (i.e. non-self-refresh)
3522 * - self-refresh (SR) mode
3523 * - lines are large relative to FIFO size (buffer can hold up to 2)
3524 * - lines are small relative to FIFO size (buffer can hold more than 2
3525 * lines), so need to account for TLB latency
3526 *
3527 * The normal calculation is:
3528 * watermark = dotclock * bytes per pixel * latency
3529 * where latency is platform & configuration dependent (we assume pessimal
3530 * values here).
3531 *
3532 * The SR calculation is:
3533 * watermark = (trunc(latency/line time)+1) * surface width *
3534 * bytes per pixel
3535 * where
3536 * line time = htotal / dotclock
3537 * surface width = hdisplay for normal plane and 64 for cursor
3538 * and latency is assumed to be high, as above.
3539 *
3540 * The final value programmed to the register should always be rounded up,
3541 * and include an extra 2 entries to account for clock crossings.
3542 *
3543 * We don't use the sprite, so we can ignore that. And on Crestline we have
3544 * to set the non-SR watermarks to 8.
3545 */
3546 static void intel_update_watermarks(struct drm_device *dev)
3547 {
3548 struct drm_i915_private *dev_priv = dev->dev_private;
3549 struct drm_crtc *crtc;
3550 int sr_hdisplay = 0;
3551 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3552 int enabled = 0, pixel_size = 0;
3553 int sr_htotal = 0;
3554
3555 if (!dev_priv->display.update_wm)
3556 return;
3557
3558 /* Get the clock config from both planes */
3559 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3561 if (intel_crtc->active) {
3562 enabled++;
3563 if (intel_crtc->plane == 0) {
3564 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3565 intel_crtc->pipe, crtc->mode.clock);
3566 planea_clock = crtc->mode.clock;
3567 } else {
3568 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3569 intel_crtc->pipe, crtc->mode.clock);
3570 planeb_clock = crtc->mode.clock;
3571 }
3572 sr_hdisplay = crtc->mode.hdisplay;
3573 sr_clock = crtc->mode.clock;
3574 sr_htotal = crtc->mode.htotal;
3575 if (crtc->fb)
3576 pixel_size = crtc->fb->bits_per_pixel / 8;
3577 else
3578 pixel_size = 4; /* by default */
3579 }
3580 }
3581
3582 if (enabled <= 0)
3583 return;
3584
3585 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3586 sr_hdisplay, sr_htotal, pixel_size);
3587 }
3588
3589 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3590 struct drm_display_mode *mode,
3591 struct drm_display_mode *adjusted_mode,
3592 int x, int y,
3593 struct drm_framebuffer *old_fb)
3594 {
3595 struct drm_device *dev = crtc->dev;
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3598 int pipe = intel_crtc->pipe;
3599 int plane = intel_crtc->plane;
3600 u32 fp_reg, dpll_reg;
3601 int refclk, num_connectors = 0;
3602 intel_clock_t clock, reduced_clock;
3603 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3604 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3605 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3606 struct intel_encoder *has_edp_encoder = NULL;
3607 struct drm_mode_config *mode_config = &dev->mode_config;
3608 struct intel_encoder *encoder;
3609 const intel_limit_t *limit;
3610 int ret;
3611 struct fdi_m_n m_n = {0};
3612 u32 reg, temp;
3613 int target_clock;
3614
3615 drm_vblank_pre_modeset(dev, pipe);
3616
3617 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3618 if (encoder->base.crtc != crtc)
3619 continue;
3620
3621 switch (encoder->type) {
3622 case INTEL_OUTPUT_LVDS:
3623 is_lvds = true;
3624 break;
3625 case INTEL_OUTPUT_SDVO:
3626 case INTEL_OUTPUT_HDMI:
3627 is_sdvo = true;
3628 if (encoder->needs_tv_clock)
3629 is_tv = true;
3630 break;
3631 case INTEL_OUTPUT_DVO:
3632 is_dvo = true;
3633 break;
3634 case INTEL_OUTPUT_TVOUT:
3635 is_tv = true;
3636 break;
3637 case INTEL_OUTPUT_ANALOG:
3638 is_crt = true;
3639 break;
3640 case INTEL_OUTPUT_DISPLAYPORT:
3641 is_dp = true;
3642 break;
3643 case INTEL_OUTPUT_EDP:
3644 has_edp_encoder = encoder;
3645 break;
3646 }
3647
3648 num_connectors++;
3649 }
3650
3651 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3652 refclk = dev_priv->lvds_ssc_freq * 1000;
3653 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3654 refclk / 1000);
3655 } else if (!IS_GEN2(dev)) {
3656 refclk = 96000;
3657 if (HAS_PCH_SPLIT(dev) &&
3658 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3659 refclk = 120000; /* 120Mhz refclk */
3660 } else {
3661 refclk = 48000;
3662 }
3663
3664 /*
3665 * Returns a set of divisors for the desired target clock with the given
3666 * refclk, or FALSE. The returned values represent the clock equation:
3667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3668 */
3669 limit = intel_limit(crtc);
3670 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3671 if (!ok) {
3672 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3673 drm_vblank_post_modeset(dev, pipe);
3674 return -EINVAL;
3675 }
3676
3677 /* Ensure that the cursor is valid for the new mode before changing... */
3678 intel_crtc_update_cursor(crtc, true);
3679
3680 if (is_lvds && dev_priv->lvds_downclock_avail) {
3681 has_reduced_clock = limit->find_pll(limit, crtc,
3682 dev_priv->lvds_downclock,
3683 refclk,
3684 &reduced_clock);
3685 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3686 /*
3687 * If the different P is found, it means that we can't
3688 * switch the display clock by using the FP0/FP1.
3689 * In such case we will disable the LVDS downclock
3690 * feature.
3691 */
3692 DRM_DEBUG_KMS("Different P is found for "
3693 "LVDS clock/downclock\n");
3694 has_reduced_clock = 0;
3695 }
3696 }
3697 /* SDVO TV has fixed PLL values depend on its clock range,
3698 this mirrors vbios setting. */
3699 if (is_sdvo && is_tv) {
3700 if (adjusted_mode->clock >= 100000
3701 && adjusted_mode->clock < 140500) {
3702 clock.p1 = 2;
3703 clock.p2 = 10;
3704 clock.n = 3;
3705 clock.m1 = 16;
3706 clock.m2 = 8;
3707 } else if (adjusted_mode->clock >= 140500
3708 && adjusted_mode->clock <= 200000) {
3709 clock.p1 = 1;
3710 clock.p2 = 10;
3711 clock.n = 6;
3712 clock.m1 = 12;
3713 clock.m2 = 8;
3714 }
3715 }
3716
3717 /* FDI link */
3718 if (HAS_PCH_SPLIT(dev)) {
3719 int lane = 0, link_bw, bpp;
3720 /* CPU eDP doesn't require FDI link, so just set DP M/N
3721 according to current link config */
3722 if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) {
3723 target_clock = mode->clock;
3724 intel_edp_link_config(has_edp_encoder,
3725 &lane, &link_bw);
3726 } else {
3727 /* [e]DP over FDI requires target mode clock
3728 instead of link clock */
3729 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3730 target_clock = mode->clock;
3731 else
3732 target_clock = adjusted_mode->clock;
3733
3734 /* FDI is a binary signal running at ~2.7GHz, encoding
3735 * each output octet as 10 bits. The actual frequency
3736 * is stored as a divider into a 100MHz clock, and the
3737 * mode pixel clock is stored in units of 1KHz.
3738 * Hence the bw of each lane in terms of the mode signal
3739 * is:
3740 */
3741 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3742 }
3743
3744 /* determine panel color depth */
3745 temp = I915_READ(PIPECONF(pipe));
3746 temp &= ~PIPE_BPC_MASK;
3747 if (is_lvds) {
3748 /* the BPC will be 6 if it is 18-bit LVDS panel */
3749 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3750 temp |= PIPE_8BPC;
3751 else
3752 temp |= PIPE_6BPC;
3753 } else if (has_edp_encoder) {
3754 switch (dev_priv->edp.bpp/3) {
3755 case 8:
3756 temp |= PIPE_8BPC;
3757 break;
3758 case 10:
3759 temp |= PIPE_10BPC;
3760 break;
3761 case 6:
3762 temp |= PIPE_6BPC;
3763 break;
3764 case 12:
3765 temp |= PIPE_12BPC;
3766 break;
3767 }
3768 } else
3769 temp |= PIPE_8BPC;
3770 I915_WRITE(PIPECONF(pipe), temp);
3771
3772 switch (temp & PIPE_BPC_MASK) {
3773 case PIPE_8BPC:
3774 bpp = 24;
3775 break;
3776 case PIPE_10BPC:
3777 bpp = 30;
3778 break;
3779 case PIPE_6BPC:
3780 bpp = 18;
3781 break;
3782 case PIPE_12BPC:
3783 bpp = 36;
3784 break;
3785 default:
3786 DRM_ERROR("unknown pipe bpc value\n");
3787 bpp = 24;
3788 }
3789
3790 if (!lane) {
3791 /*
3792 * Account for spread spectrum to avoid
3793 * oversubscribing the link. Max center spread
3794 * is 2.5%; use 5% for safety's sake.
3795 */
3796 u32 bps = target_clock * bpp * 21 / 20;
3797 lane = bps / (link_bw * 8) + 1;
3798 }
3799
3800 intel_crtc->fdi_lanes = lane;
3801
3802 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3803 }
3804
3805 /* Ironlake: try to setup display ref clock before DPLL
3806 * enabling. This is only under driver's control after
3807 * PCH B stepping, previous chipset stepping should be
3808 * ignoring this setting.
3809 */
3810 if (HAS_PCH_SPLIT(dev)) {
3811 temp = I915_READ(PCH_DREF_CONTROL);
3812 /* Always enable nonspread source */
3813 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3814 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3815 temp &= ~DREF_SSC_SOURCE_MASK;
3816 temp |= DREF_SSC_SOURCE_ENABLE;
3817 I915_WRITE(PCH_DREF_CONTROL, temp);
3818
3819 POSTING_READ(PCH_DREF_CONTROL);
3820 udelay(200);
3821
3822 if (has_edp_encoder) {
3823 if (dev_priv->lvds_use_ssc) {
3824 temp |= DREF_SSC1_ENABLE;
3825 I915_WRITE(PCH_DREF_CONTROL, temp);
3826
3827 POSTING_READ(PCH_DREF_CONTROL);
3828 udelay(200);
3829 }
3830 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3831
3832 /* Enable CPU source on CPU attached eDP */
3833 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3834 if (dev_priv->lvds_use_ssc)
3835 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3836 else
3837 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3838 } else {
3839 /* Enable SSC on PCH eDP if needed */
3840 if (dev_priv->lvds_use_ssc) {
3841 DRM_ERROR("enabling SSC on PCH\n");
3842 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
3843 }
3844 }
3845 I915_WRITE(PCH_DREF_CONTROL, temp);
3846 POSTING_READ(PCH_DREF_CONTROL);
3847 udelay(200);
3848 }
3849 }
3850
3851 if (IS_PINEVIEW(dev)) {
3852 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3853 if (has_reduced_clock)
3854 fp2 = (1 << reduced_clock.n) << 16 |
3855 reduced_clock.m1 << 8 | reduced_clock.m2;
3856 } else {
3857 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3858 if (has_reduced_clock)
3859 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3860 reduced_clock.m2;
3861 }
3862
3863 dpll = 0;
3864 if (!HAS_PCH_SPLIT(dev))
3865 dpll = DPLL_VGA_MODE_DIS;
3866
3867 if (!IS_GEN2(dev)) {
3868 if (is_lvds)
3869 dpll |= DPLLB_MODE_LVDS;
3870 else
3871 dpll |= DPLLB_MODE_DAC_SERIAL;
3872 if (is_sdvo) {
3873 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3874 if (pixel_multiplier > 1) {
3875 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3876 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3877 else if (HAS_PCH_SPLIT(dev))
3878 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3879 }
3880 dpll |= DPLL_DVO_HIGH_SPEED;
3881 }
3882 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3883 dpll |= DPLL_DVO_HIGH_SPEED;
3884
3885 /* compute bitmask from p1 value */
3886 if (IS_PINEVIEW(dev))
3887 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3888 else {
3889 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3890 /* also FPA1 */
3891 if (HAS_PCH_SPLIT(dev))
3892 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3893 if (IS_G4X(dev) && has_reduced_clock)
3894 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3895 }
3896 switch (clock.p2) {
3897 case 5:
3898 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3899 break;
3900 case 7:
3901 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3902 break;
3903 case 10:
3904 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3905 break;
3906 case 14:
3907 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3908 break;
3909 }
3910 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
3911 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3912 } else {
3913 if (is_lvds) {
3914 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3915 } else {
3916 if (clock.p1 == 2)
3917 dpll |= PLL_P1_DIVIDE_BY_TWO;
3918 else
3919 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3920 if (clock.p2 == 4)
3921 dpll |= PLL_P2_DIVIDE_BY_4;
3922 }
3923 }
3924
3925 if (is_sdvo && is_tv)
3926 dpll |= PLL_REF_INPUT_TVCLKINBC;
3927 else if (is_tv)
3928 /* XXX: just matching BIOS for now */
3929 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3930 dpll |= 3;
3931 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3932 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3933 else
3934 dpll |= PLL_REF_INPUT_DREFCLK;
3935
3936 /* setup pipeconf */
3937 pipeconf = I915_READ(PIPECONF(pipe));
3938
3939 /* Set up the display plane register */
3940 dspcntr = DISPPLANE_GAMMA_ENABLE;
3941
3942 /* Ironlake's plane is forced to pipe, bit 24 is to
3943 enable color space conversion */
3944 if (!HAS_PCH_SPLIT(dev)) {
3945 if (pipe == 0)
3946 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3947 else
3948 dspcntr |= DISPPLANE_SEL_PIPE_B;
3949 }
3950
3951 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3952 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3953 * core speed.
3954 *
3955 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3956 * pipe == 0 check?
3957 */
3958 if (mode->clock >
3959 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3960 pipeconf |= PIPECONF_DOUBLE_WIDE;
3961 else
3962 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3963 }
3964
3965 dspcntr |= DISPLAY_PLANE_ENABLE;
3966 pipeconf |= PIPECONF_ENABLE;
3967 dpll |= DPLL_VCO_ENABLE;
3968
3969 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3970 drm_mode_debug_printmodeline(mode);
3971
3972 /* assign to Ironlake registers */
3973 if (HAS_PCH_SPLIT(dev)) {
3974 fp_reg = PCH_FP0(pipe);
3975 dpll_reg = PCH_DPLL(pipe);
3976 } else {
3977 fp_reg = FP0(pipe);
3978 dpll_reg = DPLL(pipe);
3979 }
3980
3981 /* PCH eDP needs FDI, but CPU eDP does not */
3982 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3983 I915_WRITE(fp_reg, fp);
3984 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3985
3986 POSTING_READ(dpll_reg);
3987 udelay(150);
3988 }
3989
3990 /* enable transcoder DPLL */
3991 if (HAS_PCH_CPT(dev)) {
3992 temp = I915_READ(PCH_DPLL_SEL);
3993 if (pipe == 0)
3994 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3995 else
3996 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3997 I915_WRITE(PCH_DPLL_SEL, temp);
3998
3999 POSTING_READ(PCH_DPLL_SEL);
4000 udelay(150);
4001 }
4002
4003 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4004 * This is an exception to the general rule that mode_set doesn't turn
4005 * things on.
4006 */
4007 if (is_lvds) {
4008 reg = LVDS;
4009 if (HAS_PCH_SPLIT(dev))
4010 reg = PCH_LVDS;
4011
4012 temp = I915_READ(reg);
4013 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4014 if (pipe == 1) {
4015 if (HAS_PCH_CPT(dev))
4016 temp |= PORT_TRANS_B_SEL_CPT;
4017 else
4018 temp |= LVDS_PIPEB_SELECT;
4019 } else {
4020 if (HAS_PCH_CPT(dev))
4021 temp &= ~PORT_TRANS_SEL_MASK;
4022 else
4023 temp &= ~LVDS_PIPEB_SELECT;
4024 }
4025 /* set the corresponsding LVDS_BORDER bit */
4026 temp |= dev_priv->lvds_border_bits;
4027 /* Set the B0-B3 data pairs corresponding to whether we're going to
4028 * set the DPLLs for dual-channel mode or not.
4029 */
4030 if (clock.p2 == 7)
4031 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4032 else
4033 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4034
4035 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4036 * appropriately here, but we need to look more thoroughly into how
4037 * panels behave in the two modes.
4038 */
4039 /* set the dithering flag on non-PCH LVDS as needed */
4040 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4041 if (dev_priv->lvds_dither)
4042 temp |= LVDS_ENABLE_DITHER;
4043 else
4044 temp &= ~LVDS_ENABLE_DITHER;
4045 }
4046 I915_WRITE(reg, temp);
4047 }
4048
4049 /* set the dithering flag and clear for anything other than a panel. */
4050 if (HAS_PCH_SPLIT(dev)) {
4051 pipeconf &= ~PIPECONF_DITHER_EN;
4052 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4053 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4054 pipeconf |= PIPECONF_DITHER_EN;
4055 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4056 }
4057 }
4058
4059 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4060 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4061 } else if (HAS_PCH_SPLIT(dev)) {
4062 /* For non-DP output, clear any trans DP clock recovery setting.*/
4063 if (pipe == 0) {
4064 I915_WRITE(TRANSA_DATA_M1, 0);
4065 I915_WRITE(TRANSA_DATA_N1, 0);
4066 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4067 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4068 } else {
4069 I915_WRITE(TRANSB_DATA_M1, 0);
4070 I915_WRITE(TRANSB_DATA_N1, 0);
4071 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4072 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4073 }
4074 }
4075
4076 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4077 I915_WRITE(fp_reg, fp);
4078 I915_WRITE(dpll_reg, dpll);
4079
4080 /* Wait for the clocks to stabilize. */
4081 POSTING_READ(dpll_reg);
4082 udelay(150);
4083
4084 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4085 temp = 0;
4086 if (is_sdvo) {
4087 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4088 if (temp > 1)
4089 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4090 else
4091 temp = 0;
4092 }
4093 I915_WRITE(DPLL_MD(pipe), temp);
4094 } else {
4095 /* write it again -- the BIOS does, after all */
4096 I915_WRITE(dpll_reg, dpll);
4097 }
4098
4099 /* Wait for the clocks to stabilize. */
4100 POSTING_READ(dpll_reg);
4101 udelay(150);
4102 }
4103
4104 intel_crtc->lowfreq_avail = false;
4105 if (is_lvds && has_reduced_clock && i915_powersave) {
4106 I915_WRITE(fp_reg + 4, fp2);
4107 intel_crtc->lowfreq_avail = true;
4108 if (HAS_PIPE_CXSR(dev)) {
4109 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4110 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4111 }
4112 } else {
4113 I915_WRITE(fp_reg + 4, fp);
4114 if (HAS_PIPE_CXSR(dev)) {
4115 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4116 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4117 }
4118 }
4119
4120 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4121 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4122 /* the chip adds 2 halflines automatically */
4123 adjusted_mode->crtc_vdisplay -= 1;
4124 adjusted_mode->crtc_vtotal -= 1;
4125 adjusted_mode->crtc_vblank_start -= 1;
4126 adjusted_mode->crtc_vblank_end -= 1;
4127 adjusted_mode->crtc_vsync_end -= 1;
4128 adjusted_mode->crtc_vsync_start -= 1;
4129 } else
4130 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4131
4132 I915_WRITE(HTOTAL(pipe),
4133 (adjusted_mode->crtc_hdisplay - 1) |
4134 ((adjusted_mode->crtc_htotal - 1) << 16));
4135 I915_WRITE(HBLANK(pipe),
4136 (adjusted_mode->crtc_hblank_start - 1) |
4137 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4138 I915_WRITE(HSYNC(pipe),
4139 (adjusted_mode->crtc_hsync_start - 1) |
4140 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4141
4142 I915_WRITE(VTOTAL(pipe),
4143 (adjusted_mode->crtc_vdisplay - 1) |
4144 ((adjusted_mode->crtc_vtotal - 1) << 16));
4145 I915_WRITE(VBLANK(pipe),
4146 (adjusted_mode->crtc_vblank_start - 1) |
4147 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4148 I915_WRITE(VSYNC(pipe),
4149 (adjusted_mode->crtc_vsync_start - 1) |
4150 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4151
4152 /* pipesrc and dspsize control the size that is scaled from,
4153 * which should always be the user's requested size.
4154 */
4155 if (!HAS_PCH_SPLIT(dev)) {
4156 I915_WRITE(DSPSIZE(plane),
4157 ((mode->vdisplay - 1) << 16) |
4158 (mode->hdisplay - 1));
4159 I915_WRITE(DSPPOS(plane), 0);
4160 }
4161 I915_WRITE(PIPESRC(pipe),
4162 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4163
4164 if (HAS_PCH_SPLIT(dev)) {
4165 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4166 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4167 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4168 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4169
4170 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4171 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4172 }
4173 }
4174
4175 I915_WRITE(PIPECONF(pipe), pipeconf);
4176 POSTING_READ(PIPECONF(pipe));
4177
4178 intel_wait_for_vblank(dev, pipe);
4179
4180 if (IS_GEN5(dev)) {
4181 /* enable address swizzle for tiling buffer */
4182 temp = I915_READ(DISP_ARB_CTL);
4183 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4184 }
4185
4186 I915_WRITE(DSPCNTR(plane), dspcntr);
4187
4188 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4189
4190 intel_update_watermarks(dev);
4191
4192 drm_vblank_post_modeset(dev, pipe);
4193
4194 return ret;
4195 }
4196
4197 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4198 void intel_crtc_load_lut(struct drm_crtc *crtc)
4199 {
4200 struct drm_device *dev = crtc->dev;
4201 struct drm_i915_private *dev_priv = dev->dev_private;
4202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4203 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4204 int i;
4205
4206 /* The clocks have to be on to load the palette. */
4207 if (!crtc->enabled)
4208 return;
4209
4210 /* use legacy palette for Ironlake */
4211 if (HAS_PCH_SPLIT(dev))
4212 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4213 LGC_PALETTE_B;
4214
4215 for (i = 0; i < 256; i++) {
4216 I915_WRITE(palreg + 4 * i,
4217 (intel_crtc->lut_r[i] << 16) |
4218 (intel_crtc->lut_g[i] << 8) |
4219 intel_crtc->lut_b[i]);
4220 }
4221 }
4222
4223 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4224 {
4225 struct drm_device *dev = crtc->dev;
4226 struct drm_i915_private *dev_priv = dev->dev_private;
4227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4228 bool visible = base != 0;
4229 u32 cntl;
4230
4231 if (intel_crtc->cursor_visible == visible)
4232 return;
4233
4234 cntl = I915_READ(CURACNTR);
4235 if (visible) {
4236 /* On these chipsets we can only modify the base whilst
4237 * the cursor is disabled.
4238 */
4239 I915_WRITE(CURABASE, base);
4240
4241 cntl &= ~(CURSOR_FORMAT_MASK);
4242 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4243 cntl |= CURSOR_ENABLE |
4244 CURSOR_GAMMA_ENABLE |
4245 CURSOR_FORMAT_ARGB;
4246 } else
4247 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4248 I915_WRITE(CURACNTR, cntl);
4249
4250 intel_crtc->cursor_visible = visible;
4251 }
4252
4253 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4254 {
4255 struct drm_device *dev = crtc->dev;
4256 struct drm_i915_private *dev_priv = dev->dev_private;
4257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4258 int pipe = intel_crtc->pipe;
4259 bool visible = base != 0;
4260
4261 if (intel_crtc->cursor_visible != visible) {
4262 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4263 if (base) {
4264 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4265 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4266 cntl |= pipe << 28; /* Connect to correct pipe */
4267 } else {
4268 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4269 cntl |= CURSOR_MODE_DISABLE;
4270 }
4271 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4272
4273 intel_crtc->cursor_visible = visible;
4274 }
4275 /* and commit changes on next vblank */
4276 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4277 }
4278
4279 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4280 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4281 bool on)
4282 {
4283 struct drm_device *dev = crtc->dev;
4284 struct drm_i915_private *dev_priv = dev->dev_private;
4285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4286 int pipe = intel_crtc->pipe;
4287 int x = intel_crtc->cursor_x;
4288 int y = intel_crtc->cursor_y;
4289 u32 base, pos;
4290 bool visible;
4291
4292 pos = 0;
4293
4294 if (on && crtc->enabled && crtc->fb) {
4295 base = intel_crtc->cursor_addr;
4296 if (x > (int) crtc->fb->width)
4297 base = 0;
4298
4299 if (y > (int) crtc->fb->height)
4300 base = 0;
4301 } else
4302 base = 0;
4303
4304 if (x < 0) {
4305 if (x + intel_crtc->cursor_width < 0)
4306 base = 0;
4307
4308 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4309 x = -x;
4310 }
4311 pos |= x << CURSOR_X_SHIFT;
4312
4313 if (y < 0) {
4314 if (y + intel_crtc->cursor_height < 0)
4315 base = 0;
4316
4317 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4318 y = -y;
4319 }
4320 pos |= y << CURSOR_Y_SHIFT;
4321
4322 visible = base != 0;
4323 if (!visible && !intel_crtc->cursor_visible)
4324 return;
4325
4326 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4327 if (IS_845G(dev) || IS_I865G(dev))
4328 i845_update_cursor(crtc, base);
4329 else
4330 i9xx_update_cursor(crtc, base);
4331
4332 if (visible)
4333 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4334 }
4335
4336 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4337 struct drm_file *file_priv,
4338 uint32_t handle,
4339 uint32_t width, uint32_t height)
4340 {
4341 struct drm_device *dev = crtc->dev;
4342 struct drm_i915_private *dev_priv = dev->dev_private;
4343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4344 struct drm_gem_object *bo;
4345 struct drm_i915_gem_object *obj_priv;
4346 uint32_t addr;
4347 int ret;
4348
4349 DRM_DEBUG_KMS("\n");
4350
4351 /* if we want to turn off the cursor ignore width and height */
4352 if (!handle) {
4353 DRM_DEBUG_KMS("cursor off\n");
4354 addr = 0;
4355 bo = NULL;
4356 mutex_lock(&dev->struct_mutex);
4357 goto finish;
4358 }
4359
4360 /* Currently we only support 64x64 cursors */
4361 if (width != 64 || height != 64) {
4362 DRM_ERROR("we currently only support 64x64 cursors\n");
4363 return -EINVAL;
4364 }
4365
4366 bo = drm_gem_object_lookup(dev, file_priv, handle);
4367 if (!bo)
4368 return -ENOENT;
4369
4370 obj_priv = to_intel_bo(bo);
4371
4372 if (bo->size < width * height * 4) {
4373 DRM_ERROR("buffer is to small\n");
4374 ret = -ENOMEM;
4375 goto fail;
4376 }
4377
4378 /* we only need to pin inside GTT if cursor is non-phy */
4379 mutex_lock(&dev->struct_mutex);
4380 if (!dev_priv->info->cursor_needs_physical) {
4381 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4382 if (ret) {
4383 DRM_ERROR("failed to pin cursor bo\n");
4384 goto fail_locked;
4385 }
4386
4387 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4388 if (ret) {
4389 DRM_ERROR("failed to move cursor bo into the GTT\n");
4390 goto fail_unpin;
4391 }
4392
4393 addr = obj_priv->gtt_offset;
4394 } else {
4395 int align = IS_I830(dev) ? 16 * 1024 : 256;
4396 ret = i915_gem_attach_phys_object(dev, bo,
4397 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4398 align);
4399 if (ret) {
4400 DRM_ERROR("failed to attach phys object\n");
4401 goto fail_locked;
4402 }
4403 addr = obj_priv->phys_obj->handle->busaddr;
4404 }
4405
4406 if (IS_GEN2(dev))
4407 I915_WRITE(CURSIZE, (height << 12) | width);
4408
4409 finish:
4410 if (intel_crtc->cursor_bo) {
4411 if (dev_priv->info->cursor_needs_physical) {
4412 if (intel_crtc->cursor_bo != bo)
4413 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4414 } else
4415 i915_gem_object_unpin(intel_crtc->cursor_bo);
4416 drm_gem_object_unreference(intel_crtc->cursor_bo);
4417 }
4418
4419 mutex_unlock(&dev->struct_mutex);
4420
4421 intel_crtc->cursor_addr = addr;
4422 intel_crtc->cursor_bo = bo;
4423 intel_crtc->cursor_width = width;
4424 intel_crtc->cursor_height = height;
4425
4426 intel_crtc_update_cursor(crtc, true);
4427
4428 return 0;
4429 fail_unpin:
4430 i915_gem_object_unpin(bo);
4431 fail_locked:
4432 mutex_unlock(&dev->struct_mutex);
4433 fail:
4434 drm_gem_object_unreference_unlocked(bo);
4435 return ret;
4436 }
4437
4438 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4439 {
4440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4441
4442 intel_crtc->cursor_x = x;
4443 intel_crtc->cursor_y = y;
4444
4445 intel_crtc_update_cursor(crtc, true);
4446
4447 return 0;
4448 }
4449
4450 /** Sets the color ramps on behalf of RandR */
4451 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4452 u16 blue, int regno)
4453 {
4454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4455
4456 intel_crtc->lut_r[regno] = red >> 8;
4457 intel_crtc->lut_g[regno] = green >> 8;
4458 intel_crtc->lut_b[regno] = blue >> 8;
4459 }
4460
4461 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4462 u16 *blue, int regno)
4463 {
4464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4465
4466 *red = intel_crtc->lut_r[regno] << 8;
4467 *green = intel_crtc->lut_g[regno] << 8;
4468 *blue = intel_crtc->lut_b[regno] << 8;
4469 }
4470
4471 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4472 u16 *blue, uint32_t start, uint32_t size)
4473 {
4474 int end = (start + size > 256) ? 256 : start + size, i;
4475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4476
4477 for (i = start; i < end; i++) {
4478 intel_crtc->lut_r[i] = red[i] >> 8;
4479 intel_crtc->lut_g[i] = green[i] >> 8;
4480 intel_crtc->lut_b[i] = blue[i] >> 8;
4481 }
4482
4483 intel_crtc_load_lut(crtc);
4484 }
4485
4486 /**
4487 * Get a pipe with a simple mode set on it for doing load-based monitor
4488 * detection.
4489 *
4490 * It will be up to the load-detect code to adjust the pipe as appropriate for
4491 * its requirements. The pipe will be connected to no other encoders.
4492 *
4493 * Currently this code will only succeed if there is a pipe with no encoders
4494 * configured for it. In the future, it could choose to temporarily disable
4495 * some outputs to free up a pipe for its use.
4496 *
4497 * \return crtc, or NULL if no pipes are available.
4498 */
4499
4500 /* VESA 640x480x72Hz mode to set on the pipe */
4501 static struct drm_display_mode load_detect_mode = {
4502 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4503 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4504 };
4505
4506 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4507 struct drm_connector *connector,
4508 struct drm_display_mode *mode,
4509 int *dpms_mode)
4510 {
4511 struct intel_crtc *intel_crtc;
4512 struct drm_crtc *possible_crtc;
4513 struct drm_crtc *supported_crtc =NULL;
4514 struct drm_encoder *encoder = &intel_encoder->base;
4515 struct drm_crtc *crtc = NULL;
4516 struct drm_device *dev = encoder->dev;
4517 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4518 struct drm_crtc_helper_funcs *crtc_funcs;
4519 int i = -1;
4520
4521 /*
4522 * Algorithm gets a little messy:
4523 * - if the connector already has an assigned crtc, use it (but make
4524 * sure it's on first)
4525 * - try to find the first unused crtc that can drive this connector,
4526 * and use that if we find one
4527 * - if there are no unused crtcs available, try to use the first
4528 * one we found that supports the connector
4529 */
4530
4531 /* See if we already have a CRTC for this connector */
4532 if (encoder->crtc) {
4533 crtc = encoder->crtc;
4534 /* Make sure the crtc and connector are running */
4535 intel_crtc = to_intel_crtc(crtc);
4536 *dpms_mode = intel_crtc->dpms_mode;
4537 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4538 crtc_funcs = crtc->helper_private;
4539 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4540 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4541 }
4542 return crtc;
4543 }
4544
4545 /* Find an unused one (if possible) */
4546 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4547 i++;
4548 if (!(encoder->possible_crtcs & (1 << i)))
4549 continue;
4550 if (!possible_crtc->enabled) {
4551 crtc = possible_crtc;
4552 break;
4553 }
4554 if (!supported_crtc)
4555 supported_crtc = possible_crtc;
4556 }
4557
4558 /*
4559 * If we didn't find an unused CRTC, don't use any.
4560 */
4561 if (!crtc) {
4562 return NULL;
4563 }
4564
4565 encoder->crtc = crtc;
4566 connector->encoder = encoder;
4567 intel_encoder->load_detect_temp = true;
4568
4569 intel_crtc = to_intel_crtc(crtc);
4570 *dpms_mode = intel_crtc->dpms_mode;
4571
4572 if (!crtc->enabled) {
4573 if (!mode)
4574 mode = &load_detect_mode;
4575 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4576 } else {
4577 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4578 crtc_funcs = crtc->helper_private;
4579 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4580 }
4581
4582 /* Add this connector to the crtc */
4583 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4584 encoder_funcs->commit(encoder);
4585 }
4586 /* let the connector get through one full cycle before testing */
4587 intel_wait_for_vblank(dev, intel_crtc->pipe);
4588
4589 return crtc;
4590 }
4591
4592 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4593 struct drm_connector *connector, int dpms_mode)
4594 {
4595 struct drm_encoder *encoder = &intel_encoder->base;
4596 struct drm_device *dev = encoder->dev;
4597 struct drm_crtc *crtc = encoder->crtc;
4598 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4599 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4600
4601 if (intel_encoder->load_detect_temp) {
4602 encoder->crtc = NULL;
4603 connector->encoder = NULL;
4604 intel_encoder->load_detect_temp = false;
4605 crtc->enabled = drm_helper_crtc_in_use(crtc);
4606 drm_helper_disable_unused_functions(dev);
4607 }
4608
4609 /* Switch crtc and encoder back off if necessary */
4610 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4611 if (encoder->crtc == crtc)
4612 encoder_funcs->dpms(encoder, dpms_mode);
4613 crtc_funcs->dpms(crtc, dpms_mode);
4614 }
4615 }
4616
4617 /* Returns the clock of the currently programmed mode of the given pipe. */
4618 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4619 {
4620 struct drm_i915_private *dev_priv = dev->dev_private;
4621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4622 int pipe = intel_crtc->pipe;
4623 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4624 u32 fp;
4625 intel_clock_t clock;
4626
4627 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4628 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4629 else
4630 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4631
4632 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4633 if (IS_PINEVIEW(dev)) {
4634 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4635 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4636 } else {
4637 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4638 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4639 }
4640
4641 if (!IS_GEN2(dev)) {
4642 if (IS_PINEVIEW(dev))
4643 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4644 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4645 else
4646 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4647 DPLL_FPA01_P1_POST_DIV_SHIFT);
4648
4649 switch (dpll & DPLL_MODE_MASK) {
4650 case DPLLB_MODE_DAC_SERIAL:
4651 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4652 5 : 10;
4653 break;
4654 case DPLLB_MODE_LVDS:
4655 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4656 7 : 14;
4657 break;
4658 default:
4659 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4660 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4661 return 0;
4662 }
4663
4664 /* XXX: Handle the 100Mhz refclk */
4665 intel_clock(dev, 96000, &clock);
4666 } else {
4667 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4668
4669 if (is_lvds) {
4670 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4671 DPLL_FPA01_P1_POST_DIV_SHIFT);
4672 clock.p2 = 14;
4673
4674 if ((dpll & PLL_REF_INPUT_MASK) ==
4675 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4676 /* XXX: might not be 66MHz */
4677 intel_clock(dev, 66000, &clock);
4678 } else
4679 intel_clock(dev, 48000, &clock);
4680 } else {
4681 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4682 clock.p1 = 2;
4683 else {
4684 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4685 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4686 }
4687 if (dpll & PLL_P2_DIVIDE_BY_4)
4688 clock.p2 = 4;
4689 else
4690 clock.p2 = 2;
4691
4692 intel_clock(dev, 48000, &clock);
4693 }
4694 }
4695
4696 /* XXX: It would be nice to validate the clocks, but we can't reuse
4697 * i830PllIsValid() because it relies on the xf86_config connector
4698 * configuration being accurate, which it isn't necessarily.
4699 */
4700
4701 return clock.dot;
4702 }
4703
4704 /** Returns the currently programmed mode of the given pipe. */
4705 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4706 struct drm_crtc *crtc)
4707 {
4708 struct drm_i915_private *dev_priv = dev->dev_private;
4709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4710 int pipe = intel_crtc->pipe;
4711 struct drm_display_mode *mode;
4712 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4713 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4714 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4715 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4716
4717 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4718 if (!mode)
4719 return NULL;
4720
4721 mode->clock = intel_crtc_clock_get(dev, crtc);
4722 mode->hdisplay = (htot & 0xffff) + 1;
4723 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4724 mode->hsync_start = (hsync & 0xffff) + 1;
4725 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4726 mode->vdisplay = (vtot & 0xffff) + 1;
4727 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4728 mode->vsync_start = (vsync & 0xffff) + 1;
4729 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4730
4731 drm_mode_set_name(mode);
4732 drm_mode_set_crtcinfo(mode, 0);
4733
4734 return mode;
4735 }
4736
4737 #define GPU_IDLE_TIMEOUT 500 /* ms */
4738
4739 /* When this timer fires, we've been idle for awhile */
4740 static void intel_gpu_idle_timer(unsigned long arg)
4741 {
4742 struct drm_device *dev = (struct drm_device *)arg;
4743 drm_i915_private_t *dev_priv = dev->dev_private;
4744
4745 dev_priv->busy = false;
4746
4747 queue_work(dev_priv->wq, &dev_priv->idle_work);
4748 }
4749
4750 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4751
4752 static void intel_crtc_idle_timer(unsigned long arg)
4753 {
4754 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4755 struct drm_crtc *crtc = &intel_crtc->base;
4756 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4757
4758 intel_crtc->busy = false;
4759
4760 queue_work(dev_priv->wq, &dev_priv->idle_work);
4761 }
4762
4763 static void intel_increase_pllclock(struct drm_crtc *crtc)
4764 {
4765 struct drm_device *dev = crtc->dev;
4766 drm_i915_private_t *dev_priv = dev->dev_private;
4767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4768 int pipe = intel_crtc->pipe;
4769 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4770 int dpll = I915_READ(dpll_reg);
4771
4772 if (HAS_PCH_SPLIT(dev))
4773 return;
4774
4775 if (!dev_priv->lvds_downclock_avail)
4776 return;
4777
4778 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4779 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4780
4781 /* Unlock panel regs */
4782 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4783 PANEL_UNLOCK_REGS);
4784
4785 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4786 I915_WRITE(dpll_reg, dpll);
4787 dpll = I915_READ(dpll_reg);
4788 intel_wait_for_vblank(dev, pipe);
4789 dpll = I915_READ(dpll_reg);
4790 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4791 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4792
4793 /* ...and lock them again */
4794 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4795 }
4796
4797 /* Schedule downclock */
4798 mod_timer(&intel_crtc->idle_timer, jiffies +
4799 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4800 }
4801
4802 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4803 {
4804 struct drm_device *dev = crtc->dev;
4805 drm_i915_private_t *dev_priv = dev->dev_private;
4806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4807 int pipe = intel_crtc->pipe;
4808 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4809 int dpll = I915_READ(dpll_reg);
4810
4811 if (HAS_PCH_SPLIT(dev))
4812 return;
4813
4814 if (!dev_priv->lvds_downclock_avail)
4815 return;
4816
4817 /*
4818 * Since this is called by a timer, we should never get here in
4819 * the manual case.
4820 */
4821 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4822 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4823
4824 /* Unlock panel regs */
4825 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4826 PANEL_UNLOCK_REGS);
4827
4828 dpll |= DISPLAY_RATE_SELECT_FPA1;
4829 I915_WRITE(dpll_reg, dpll);
4830 dpll = I915_READ(dpll_reg);
4831 intel_wait_for_vblank(dev, pipe);
4832 dpll = I915_READ(dpll_reg);
4833 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4834 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4835
4836 /* ...and lock them again */
4837 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4838 }
4839
4840 }
4841
4842 /**
4843 * intel_idle_update - adjust clocks for idleness
4844 * @work: work struct
4845 *
4846 * Either the GPU or display (or both) went idle. Check the busy status
4847 * here and adjust the CRTC and GPU clocks as necessary.
4848 */
4849 static void intel_idle_update(struct work_struct *work)
4850 {
4851 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4852 idle_work);
4853 struct drm_device *dev = dev_priv->dev;
4854 struct drm_crtc *crtc;
4855 struct intel_crtc *intel_crtc;
4856 int enabled = 0;
4857
4858 if (!i915_powersave)
4859 return;
4860
4861 mutex_lock(&dev->struct_mutex);
4862
4863 i915_update_gfx_val(dev_priv);
4864
4865 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4866 /* Skip inactive CRTCs */
4867 if (!crtc->fb)
4868 continue;
4869
4870 enabled++;
4871 intel_crtc = to_intel_crtc(crtc);
4872 if (!intel_crtc->busy)
4873 intel_decrease_pllclock(crtc);
4874 }
4875
4876 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4877 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4878 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4879 }
4880
4881 mutex_unlock(&dev->struct_mutex);
4882 }
4883
4884 /**
4885 * intel_mark_busy - mark the GPU and possibly the display busy
4886 * @dev: drm device
4887 * @obj: object we're operating on
4888 *
4889 * Callers can use this function to indicate that the GPU is busy processing
4890 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4891 * buffer), we'll also mark the display as busy, so we know to increase its
4892 * clock frequency.
4893 */
4894 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4895 {
4896 drm_i915_private_t *dev_priv = dev->dev_private;
4897 struct drm_crtc *crtc = NULL;
4898 struct intel_framebuffer *intel_fb;
4899 struct intel_crtc *intel_crtc;
4900
4901 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4902 return;
4903
4904 if (!dev_priv->busy) {
4905 if (IS_I945G(dev) || IS_I945GM(dev)) {
4906 u32 fw_blc_self;
4907
4908 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4909 fw_blc_self = I915_READ(FW_BLC_SELF);
4910 fw_blc_self &= ~FW_BLC_SELF_EN;
4911 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4912 }
4913 dev_priv->busy = true;
4914 } else
4915 mod_timer(&dev_priv->idle_timer, jiffies +
4916 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4917
4918 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4919 if (!crtc->fb)
4920 continue;
4921
4922 intel_crtc = to_intel_crtc(crtc);
4923 intel_fb = to_intel_framebuffer(crtc->fb);
4924 if (intel_fb->obj == obj) {
4925 if (!intel_crtc->busy) {
4926 if (IS_I945G(dev) || IS_I945GM(dev)) {
4927 u32 fw_blc_self;
4928
4929 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4930 fw_blc_self = I915_READ(FW_BLC_SELF);
4931 fw_blc_self &= ~FW_BLC_SELF_EN;
4932 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4933 }
4934 /* Non-busy -> busy, upclock */
4935 intel_increase_pllclock(crtc);
4936 intel_crtc->busy = true;
4937 } else {
4938 /* Busy -> busy, put off timer */
4939 mod_timer(&intel_crtc->idle_timer, jiffies +
4940 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4941 }
4942 }
4943 }
4944 }
4945
4946 static void intel_crtc_destroy(struct drm_crtc *crtc)
4947 {
4948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4949 struct drm_device *dev = crtc->dev;
4950 struct intel_unpin_work *work;
4951 unsigned long flags;
4952
4953 spin_lock_irqsave(&dev->event_lock, flags);
4954 work = intel_crtc->unpin_work;
4955 intel_crtc->unpin_work = NULL;
4956 spin_unlock_irqrestore(&dev->event_lock, flags);
4957
4958 if (work) {
4959 cancel_work_sync(&work->work);
4960 kfree(work);
4961 }
4962
4963 drm_crtc_cleanup(crtc);
4964
4965 kfree(intel_crtc);
4966 }
4967
4968 static void intel_unpin_work_fn(struct work_struct *__work)
4969 {
4970 struct intel_unpin_work *work =
4971 container_of(__work, struct intel_unpin_work, work);
4972
4973 mutex_lock(&work->dev->struct_mutex);
4974 i915_gem_object_unpin(work->old_fb_obj);
4975 drm_gem_object_unreference(work->pending_flip_obj);
4976 drm_gem_object_unreference(work->old_fb_obj);
4977 mutex_unlock(&work->dev->struct_mutex);
4978 kfree(work);
4979 }
4980
4981 static void do_intel_finish_page_flip(struct drm_device *dev,
4982 struct drm_crtc *crtc)
4983 {
4984 drm_i915_private_t *dev_priv = dev->dev_private;
4985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4986 struct intel_unpin_work *work;
4987 struct drm_i915_gem_object *obj_priv;
4988 struct drm_pending_vblank_event *e;
4989 struct timeval now;
4990 unsigned long flags;
4991
4992 /* Ignore early vblank irqs */
4993 if (intel_crtc == NULL)
4994 return;
4995
4996 spin_lock_irqsave(&dev->event_lock, flags);
4997 work = intel_crtc->unpin_work;
4998 if (work == NULL || !work->pending) {
4999 spin_unlock_irqrestore(&dev->event_lock, flags);
5000 return;
5001 }
5002
5003 intel_crtc->unpin_work = NULL;
5004 drm_vblank_put(dev, intel_crtc->pipe);
5005
5006 if (work->event) {
5007 e = work->event;
5008 do_gettimeofday(&now);
5009 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
5010 e->event.tv_sec = now.tv_sec;
5011 e->event.tv_usec = now.tv_usec;
5012 list_add_tail(&e->base.link,
5013 &e->base.file_priv->event_list);
5014 wake_up_interruptible(&e->base.file_priv->event_wait);
5015 }
5016
5017 spin_unlock_irqrestore(&dev->event_lock, flags);
5018
5019 obj_priv = to_intel_bo(work->old_fb_obj);
5020 atomic_clear_mask(1 << intel_crtc->plane,
5021 &obj_priv->pending_flip.counter);
5022 if (atomic_read(&obj_priv->pending_flip) == 0)
5023 wake_up(&dev_priv->pending_flip_queue);
5024 schedule_work(&work->work);
5025
5026 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5027 }
5028
5029 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5030 {
5031 drm_i915_private_t *dev_priv = dev->dev_private;
5032 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5033
5034 do_intel_finish_page_flip(dev, crtc);
5035 }
5036
5037 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5038 {
5039 drm_i915_private_t *dev_priv = dev->dev_private;
5040 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5041
5042 do_intel_finish_page_flip(dev, crtc);
5043 }
5044
5045 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5046 {
5047 drm_i915_private_t *dev_priv = dev->dev_private;
5048 struct intel_crtc *intel_crtc =
5049 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5050 unsigned long flags;
5051
5052 spin_lock_irqsave(&dev->event_lock, flags);
5053 if (intel_crtc->unpin_work) {
5054 if ((++intel_crtc->unpin_work->pending) > 1)
5055 DRM_ERROR("Prepared flip multiple times\n");
5056 } else {
5057 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5058 }
5059 spin_unlock_irqrestore(&dev->event_lock, flags);
5060 }
5061
5062 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5063 struct drm_framebuffer *fb,
5064 struct drm_pending_vblank_event *event)
5065 {
5066 struct drm_device *dev = crtc->dev;
5067 struct drm_i915_private *dev_priv = dev->dev_private;
5068 struct intel_framebuffer *intel_fb;
5069 struct drm_i915_gem_object *obj_priv;
5070 struct drm_gem_object *obj;
5071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5072 struct intel_unpin_work *work;
5073 unsigned long flags, offset;
5074 int pipe = intel_crtc->pipe;
5075 u32 pf, pipesrc;
5076 int ret;
5077
5078 work = kzalloc(sizeof *work, GFP_KERNEL);
5079 if (work == NULL)
5080 return -ENOMEM;
5081
5082 work->event = event;
5083 work->dev = crtc->dev;
5084 intel_fb = to_intel_framebuffer(crtc->fb);
5085 work->old_fb_obj = intel_fb->obj;
5086 INIT_WORK(&work->work, intel_unpin_work_fn);
5087
5088 /* We borrow the event spin lock for protecting unpin_work */
5089 spin_lock_irqsave(&dev->event_lock, flags);
5090 if (intel_crtc->unpin_work) {
5091 spin_unlock_irqrestore(&dev->event_lock, flags);
5092 kfree(work);
5093
5094 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5095 return -EBUSY;
5096 }
5097 intel_crtc->unpin_work = work;
5098 spin_unlock_irqrestore(&dev->event_lock, flags);
5099
5100 intel_fb = to_intel_framebuffer(fb);
5101 obj = intel_fb->obj;
5102
5103 mutex_lock(&dev->struct_mutex);
5104 ret = intel_pin_and_fence_fb_obj(dev, obj, true);
5105 if (ret)
5106 goto cleanup_work;
5107
5108 /* Reference the objects for the scheduled work. */
5109 drm_gem_object_reference(work->old_fb_obj);
5110 drm_gem_object_reference(obj);
5111
5112 crtc->fb = fb;
5113
5114 ret = drm_vblank_get(dev, intel_crtc->pipe);
5115 if (ret)
5116 goto cleanup_objs;
5117
5118 /* Block clients from rendering to the new back buffer until
5119 * the flip occurs and the object is no longer visible.
5120 */
5121 atomic_add(1 << intel_crtc->plane,
5122 &to_intel_bo(work->old_fb_obj)->pending_flip);
5123
5124 work->pending_flip_obj = obj;
5125 obj_priv = to_intel_bo(obj);
5126
5127 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5128 u32 flip_mask;
5129
5130 /* Can't queue multiple flips, so wait for the previous
5131 * one to finish before executing the next.
5132 */
5133 BEGIN_LP_RING(2);
5134 if (intel_crtc->plane)
5135 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5136 else
5137 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5138 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5139 OUT_RING(MI_NOOP);
5140 ADVANCE_LP_RING();
5141 }
5142
5143 work->enable_stall_check = true;
5144
5145 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5146 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5147
5148 BEGIN_LP_RING(4);
5149 switch(INTEL_INFO(dev)->gen) {
5150 case 2:
5151 OUT_RING(MI_DISPLAY_FLIP |
5152 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5153 OUT_RING(fb->pitch);
5154 OUT_RING(obj_priv->gtt_offset + offset);
5155 OUT_RING(MI_NOOP);
5156 break;
5157
5158 case 3:
5159 OUT_RING(MI_DISPLAY_FLIP_I915 |
5160 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5161 OUT_RING(fb->pitch);
5162 OUT_RING(obj_priv->gtt_offset + offset);
5163 OUT_RING(MI_NOOP);
5164 break;
5165
5166 case 4:
5167 case 5:
5168 /* i965+ uses the linear or tiled offsets from the
5169 * Display Registers (which do not change across a page-flip)
5170 * so we need only reprogram the base address.
5171 */
5172 OUT_RING(MI_DISPLAY_FLIP |
5173 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5174 OUT_RING(fb->pitch);
5175 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5176
5177 /* XXX Enabling the panel-fitter across page-flip is so far
5178 * untested on non-native modes, so ignore it for now.
5179 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5180 */
5181 pf = 0;
5182 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5183 OUT_RING(pf | pipesrc);
5184 break;
5185
5186 case 6:
5187 OUT_RING(MI_DISPLAY_FLIP |
5188 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5189 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5190 OUT_RING(obj_priv->gtt_offset);
5191
5192 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5193 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5194 OUT_RING(pf | pipesrc);
5195 break;
5196 }
5197 ADVANCE_LP_RING();
5198
5199 mutex_unlock(&dev->struct_mutex);
5200
5201 trace_i915_flip_request(intel_crtc->plane, obj);
5202
5203 return 0;
5204
5205 cleanup_objs:
5206 drm_gem_object_unreference(work->old_fb_obj);
5207 drm_gem_object_unreference(obj);
5208 cleanup_work:
5209 mutex_unlock(&dev->struct_mutex);
5210
5211 spin_lock_irqsave(&dev->event_lock, flags);
5212 intel_crtc->unpin_work = NULL;
5213 spin_unlock_irqrestore(&dev->event_lock, flags);
5214
5215 kfree(work);
5216
5217 return ret;
5218 }
5219
5220 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5221 .dpms = intel_crtc_dpms,
5222 .mode_fixup = intel_crtc_mode_fixup,
5223 .mode_set = intel_crtc_mode_set,
5224 .mode_set_base = intel_pipe_set_base,
5225 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5226 .load_lut = intel_crtc_load_lut,
5227 .disable = intel_crtc_disable,
5228 };
5229
5230 static const struct drm_crtc_funcs intel_crtc_funcs = {
5231 .cursor_set = intel_crtc_cursor_set,
5232 .cursor_move = intel_crtc_cursor_move,
5233 .gamma_set = intel_crtc_gamma_set,
5234 .set_config = drm_crtc_helper_set_config,
5235 .destroy = intel_crtc_destroy,
5236 .page_flip = intel_crtc_page_flip,
5237 };
5238
5239
5240 static void intel_crtc_init(struct drm_device *dev, int pipe)
5241 {
5242 drm_i915_private_t *dev_priv = dev->dev_private;
5243 struct intel_crtc *intel_crtc;
5244 int i;
5245
5246 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5247 if (intel_crtc == NULL)
5248 return;
5249
5250 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5251
5252 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5253 for (i = 0; i < 256; i++) {
5254 intel_crtc->lut_r[i] = i;
5255 intel_crtc->lut_g[i] = i;
5256 intel_crtc->lut_b[i] = i;
5257 }
5258
5259 /* Swap pipes & planes for FBC on pre-965 */
5260 intel_crtc->pipe = pipe;
5261 intel_crtc->plane = pipe;
5262 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5263 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5264 intel_crtc->plane = !pipe;
5265 }
5266
5267 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5268 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5269 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5270 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5271
5272 intel_crtc->cursor_addr = 0;
5273 intel_crtc->dpms_mode = -1;
5274 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5275
5276 if (HAS_PCH_SPLIT(dev)) {
5277 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5278 intel_helper_funcs.commit = ironlake_crtc_commit;
5279 } else {
5280 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5281 intel_helper_funcs.commit = i9xx_crtc_commit;
5282 }
5283
5284 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5285
5286 intel_crtc->busy = false;
5287
5288 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5289 (unsigned long)intel_crtc);
5290 }
5291
5292 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5293 struct drm_file *file_priv)
5294 {
5295 drm_i915_private_t *dev_priv = dev->dev_private;
5296 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5297 struct drm_mode_object *drmmode_obj;
5298 struct intel_crtc *crtc;
5299
5300 if (!dev_priv) {
5301 DRM_ERROR("called with no initialization\n");
5302 return -EINVAL;
5303 }
5304
5305 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5306 DRM_MODE_OBJECT_CRTC);
5307
5308 if (!drmmode_obj) {
5309 DRM_ERROR("no such CRTC id\n");
5310 return -EINVAL;
5311 }
5312
5313 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5314 pipe_from_crtc_id->pipe = crtc->pipe;
5315
5316 return 0;
5317 }
5318
5319 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5320 {
5321 struct intel_encoder *encoder;
5322 int index_mask = 0;
5323 int entry = 0;
5324
5325 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5326 if (type_mask & encoder->clone_mask)
5327 index_mask |= (1 << entry);
5328 entry++;
5329 }
5330
5331 return index_mask;
5332 }
5333
5334 static void intel_setup_outputs(struct drm_device *dev)
5335 {
5336 struct drm_i915_private *dev_priv = dev->dev_private;
5337 struct intel_encoder *encoder;
5338 bool dpd_is_edp = false;
5339
5340 if (IS_MOBILE(dev) && !IS_I830(dev))
5341 intel_lvds_init(dev);
5342
5343 if (HAS_PCH_SPLIT(dev)) {
5344 dpd_is_edp = intel_dpd_is_edp(dev);
5345
5346 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5347 intel_dp_init(dev, DP_A);
5348
5349 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5350 intel_dp_init(dev, PCH_DP_D);
5351 }
5352
5353 intel_crt_init(dev);
5354
5355 if (HAS_PCH_SPLIT(dev)) {
5356 int found;
5357
5358 if (I915_READ(HDMIB) & PORT_DETECTED) {
5359 /* PCH SDVOB multiplex with HDMIB */
5360 found = intel_sdvo_init(dev, PCH_SDVOB);
5361 if (!found)
5362 intel_hdmi_init(dev, HDMIB);
5363 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5364 intel_dp_init(dev, PCH_DP_B);
5365 }
5366
5367 if (I915_READ(HDMIC) & PORT_DETECTED)
5368 intel_hdmi_init(dev, HDMIC);
5369
5370 if (I915_READ(HDMID) & PORT_DETECTED)
5371 intel_hdmi_init(dev, HDMID);
5372
5373 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5374 intel_dp_init(dev, PCH_DP_C);
5375
5376 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5377 intel_dp_init(dev, PCH_DP_D);
5378
5379 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5380 bool found = false;
5381
5382 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5383 DRM_DEBUG_KMS("probing SDVOB\n");
5384 found = intel_sdvo_init(dev, SDVOB);
5385 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5386 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5387 intel_hdmi_init(dev, SDVOB);
5388 }
5389
5390 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5391 DRM_DEBUG_KMS("probing DP_B\n");
5392 intel_dp_init(dev, DP_B);
5393 }
5394 }
5395
5396 /* Before G4X SDVOC doesn't have its own detect register */
5397
5398 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5399 DRM_DEBUG_KMS("probing SDVOC\n");
5400 found = intel_sdvo_init(dev, SDVOC);
5401 }
5402
5403 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5404
5405 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5406 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5407 intel_hdmi_init(dev, SDVOC);
5408 }
5409 if (SUPPORTS_INTEGRATED_DP(dev)) {
5410 DRM_DEBUG_KMS("probing DP_C\n");
5411 intel_dp_init(dev, DP_C);
5412 }
5413 }
5414
5415 if (SUPPORTS_INTEGRATED_DP(dev) &&
5416 (I915_READ(DP_D) & DP_DETECTED)) {
5417 DRM_DEBUG_KMS("probing DP_D\n");
5418 intel_dp_init(dev, DP_D);
5419 }
5420 } else if (IS_GEN2(dev))
5421 intel_dvo_init(dev);
5422
5423 if (SUPPORTS_TV(dev))
5424 intel_tv_init(dev);
5425
5426 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5427 encoder->base.possible_crtcs = encoder->crtc_mask;
5428 encoder->base.possible_clones =
5429 intel_encoder_clones(dev, encoder->clone_mask);
5430 }
5431 }
5432
5433 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5434 {
5435 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5436
5437 drm_framebuffer_cleanup(fb);
5438 drm_gem_object_unreference_unlocked(intel_fb->obj);
5439
5440 kfree(intel_fb);
5441 }
5442
5443 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5444 struct drm_file *file_priv,
5445 unsigned int *handle)
5446 {
5447 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5448 struct drm_gem_object *object = intel_fb->obj;
5449
5450 return drm_gem_handle_create(file_priv, object, handle);
5451 }
5452
5453 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5454 .destroy = intel_user_framebuffer_destroy,
5455 .create_handle = intel_user_framebuffer_create_handle,
5456 };
5457
5458 int intel_framebuffer_init(struct drm_device *dev,
5459 struct intel_framebuffer *intel_fb,
5460 struct drm_mode_fb_cmd *mode_cmd,
5461 struct drm_gem_object *obj)
5462 {
5463 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5464 int ret;
5465
5466 if (obj_priv->tiling_mode == I915_TILING_Y)
5467 return -EINVAL;
5468
5469 if (mode_cmd->pitch & 63)
5470 return -EINVAL;
5471
5472 switch (mode_cmd->bpp) {
5473 case 8:
5474 case 16:
5475 case 24:
5476 case 32:
5477 break;
5478 default:
5479 return -EINVAL;
5480 }
5481
5482 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5483 if (ret) {
5484 DRM_ERROR("framebuffer init failed %d\n", ret);
5485 return ret;
5486 }
5487
5488 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5489 intel_fb->obj = obj;
5490 return 0;
5491 }
5492
5493 static struct drm_framebuffer *
5494 intel_user_framebuffer_create(struct drm_device *dev,
5495 struct drm_file *filp,
5496 struct drm_mode_fb_cmd *mode_cmd)
5497 {
5498 struct drm_gem_object *obj;
5499 struct intel_framebuffer *intel_fb;
5500 int ret;
5501
5502 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5503 if (!obj)
5504 return ERR_PTR(-ENOENT);
5505
5506 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5507 if (!intel_fb)
5508 return ERR_PTR(-ENOMEM);
5509
5510 ret = intel_framebuffer_init(dev, intel_fb,
5511 mode_cmd, obj);
5512 if (ret) {
5513 drm_gem_object_unreference_unlocked(obj);
5514 kfree(intel_fb);
5515 return ERR_PTR(ret);
5516 }
5517
5518 return &intel_fb->base;
5519 }
5520
5521 static const struct drm_mode_config_funcs intel_mode_funcs = {
5522 .fb_create = intel_user_framebuffer_create,
5523 .output_poll_changed = intel_fb_output_poll_changed,
5524 };
5525
5526 static struct drm_gem_object *
5527 intel_alloc_context_page(struct drm_device *dev)
5528 {
5529 struct drm_gem_object *ctx;
5530 int ret;
5531
5532 ctx = i915_gem_alloc_object(dev, 4096);
5533 if (!ctx) {
5534 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5535 return NULL;
5536 }
5537
5538 mutex_lock(&dev->struct_mutex);
5539 ret = i915_gem_object_pin(ctx, 4096);
5540 if (ret) {
5541 DRM_ERROR("failed to pin power context: %d\n", ret);
5542 goto err_unref;
5543 }
5544
5545 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5546 if (ret) {
5547 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5548 goto err_unpin;
5549 }
5550 mutex_unlock(&dev->struct_mutex);
5551
5552 return ctx;
5553
5554 err_unpin:
5555 i915_gem_object_unpin(ctx);
5556 err_unref:
5557 drm_gem_object_unreference(ctx);
5558 mutex_unlock(&dev->struct_mutex);
5559 return NULL;
5560 }
5561
5562 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5563 {
5564 struct drm_i915_private *dev_priv = dev->dev_private;
5565 u16 rgvswctl;
5566
5567 rgvswctl = I915_READ16(MEMSWCTL);
5568 if (rgvswctl & MEMCTL_CMD_STS) {
5569 DRM_DEBUG("gpu busy, RCS change rejected\n");
5570 return false; /* still busy with another command */
5571 }
5572
5573 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5574 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5575 I915_WRITE16(MEMSWCTL, rgvswctl);
5576 POSTING_READ16(MEMSWCTL);
5577
5578 rgvswctl |= MEMCTL_CMD_STS;
5579 I915_WRITE16(MEMSWCTL, rgvswctl);
5580
5581 return true;
5582 }
5583
5584 void ironlake_enable_drps(struct drm_device *dev)
5585 {
5586 struct drm_i915_private *dev_priv = dev->dev_private;
5587 u32 rgvmodectl = I915_READ(MEMMODECTL);
5588 u8 fmax, fmin, fstart, vstart;
5589
5590 /* Enable temp reporting */
5591 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5592 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5593
5594 /* 100ms RC evaluation intervals */
5595 I915_WRITE(RCUPEI, 100000);
5596 I915_WRITE(RCDNEI, 100000);
5597
5598 /* Set max/min thresholds to 90ms and 80ms respectively */
5599 I915_WRITE(RCBMAXAVG, 90000);
5600 I915_WRITE(RCBMINAVG, 80000);
5601
5602 I915_WRITE(MEMIHYST, 1);
5603
5604 /* Set up min, max, and cur for interrupt handling */
5605 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5606 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5607 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5608 MEMMODE_FSTART_SHIFT;
5609
5610 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5611 PXVFREQ_PX_SHIFT;
5612
5613 dev_priv->fmax = fmax; /* IPS callback will increase this */
5614 dev_priv->fstart = fstart;
5615
5616 dev_priv->max_delay = fstart;
5617 dev_priv->min_delay = fmin;
5618 dev_priv->cur_delay = fstart;
5619
5620 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5621 fmax, fmin, fstart);
5622
5623 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5624
5625 /*
5626 * Interrupts will be enabled in ironlake_irq_postinstall
5627 */
5628
5629 I915_WRITE(VIDSTART, vstart);
5630 POSTING_READ(VIDSTART);
5631
5632 rgvmodectl |= MEMMODE_SWMODE_EN;
5633 I915_WRITE(MEMMODECTL, rgvmodectl);
5634
5635 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5636 DRM_ERROR("stuck trying to change perf mode\n");
5637 msleep(1);
5638
5639 ironlake_set_drps(dev, fstart);
5640
5641 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5642 I915_READ(0x112e0);
5643 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5644 dev_priv->last_count2 = I915_READ(0x112f4);
5645 getrawmonotonic(&dev_priv->last_time2);
5646 }
5647
5648 void ironlake_disable_drps(struct drm_device *dev)
5649 {
5650 struct drm_i915_private *dev_priv = dev->dev_private;
5651 u16 rgvswctl = I915_READ16(MEMSWCTL);
5652
5653 /* Ack interrupts, disable EFC interrupt */
5654 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5655 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5656 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5657 I915_WRITE(DEIIR, DE_PCU_EVENT);
5658 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5659
5660 /* Go back to the starting frequency */
5661 ironlake_set_drps(dev, dev_priv->fstart);
5662 msleep(1);
5663 rgvswctl |= MEMCTL_CMD_STS;
5664 I915_WRITE(MEMSWCTL, rgvswctl);
5665 msleep(1);
5666
5667 }
5668
5669 static unsigned long intel_pxfreq(u32 vidfreq)
5670 {
5671 unsigned long freq;
5672 int div = (vidfreq & 0x3f0000) >> 16;
5673 int post = (vidfreq & 0x3000) >> 12;
5674 int pre = (vidfreq & 0x7);
5675
5676 if (!pre)
5677 return 0;
5678
5679 freq = ((div * 133333) / ((1<<post) * pre));
5680
5681 return freq;
5682 }
5683
5684 void intel_init_emon(struct drm_device *dev)
5685 {
5686 struct drm_i915_private *dev_priv = dev->dev_private;
5687 u32 lcfuse;
5688 u8 pxw[16];
5689 int i;
5690
5691 /* Disable to program */
5692 I915_WRITE(ECR, 0);
5693 POSTING_READ(ECR);
5694
5695 /* Program energy weights for various events */
5696 I915_WRITE(SDEW, 0x15040d00);
5697 I915_WRITE(CSIEW0, 0x007f0000);
5698 I915_WRITE(CSIEW1, 0x1e220004);
5699 I915_WRITE(CSIEW2, 0x04000004);
5700
5701 for (i = 0; i < 5; i++)
5702 I915_WRITE(PEW + (i * 4), 0);
5703 for (i = 0; i < 3; i++)
5704 I915_WRITE(DEW + (i * 4), 0);
5705
5706 /* Program P-state weights to account for frequency power adjustment */
5707 for (i = 0; i < 16; i++) {
5708 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5709 unsigned long freq = intel_pxfreq(pxvidfreq);
5710 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5711 PXVFREQ_PX_SHIFT;
5712 unsigned long val;
5713
5714 val = vid * vid;
5715 val *= (freq / 1000);
5716 val *= 255;
5717 val /= (127*127*900);
5718 if (val > 0xff)
5719 DRM_ERROR("bad pxval: %ld\n", val);
5720 pxw[i] = val;
5721 }
5722 /* Render standby states get 0 weight */
5723 pxw[14] = 0;
5724 pxw[15] = 0;
5725
5726 for (i = 0; i < 4; i++) {
5727 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5728 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5729 I915_WRITE(PXW + (i * 4), val);
5730 }
5731
5732 /* Adjust magic regs to magic values (more experimental results) */
5733 I915_WRITE(OGW0, 0);
5734 I915_WRITE(OGW1, 0);
5735 I915_WRITE(EG0, 0x00007f00);
5736 I915_WRITE(EG1, 0x0000000e);
5737 I915_WRITE(EG2, 0x000e0000);
5738 I915_WRITE(EG3, 0x68000300);
5739 I915_WRITE(EG4, 0x42000000);
5740 I915_WRITE(EG5, 0x00140031);
5741 I915_WRITE(EG6, 0);
5742 I915_WRITE(EG7, 0);
5743
5744 for (i = 0; i < 8; i++)
5745 I915_WRITE(PXWL + (i * 4), 0);
5746
5747 /* Enable PMON + select events */
5748 I915_WRITE(ECR, 0x80000019);
5749
5750 lcfuse = I915_READ(LCFUSE02);
5751
5752 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5753 }
5754
5755 void intel_init_clock_gating(struct drm_device *dev)
5756 {
5757 struct drm_i915_private *dev_priv = dev->dev_private;
5758
5759 /*
5760 * Disable clock gating reported to work incorrectly according to the
5761 * specs, but enable as much else as we can.
5762 */
5763 if (HAS_PCH_SPLIT(dev)) {
5764 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5765
5766 if (IS_GEN5(dev)) {
5767 /* Required for FBC */
5768 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5769 /* Required for CxSR */
5770 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5771
5772 I915_WRITE(PCH_3DCGDIS0,
5773 MARIUNIT_CLOCK_GATE_DISABLE |
5774 SVSMUNIT_CLOCK_GATE_DISABLE);
5775 }
5776
5777 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5778
5779 /*
5780 * On Ibex Peak and Cougar Point, we need to disable clock
5781 * gating for the panel power sequencer or it will fail to
5782 * start up when no ports are active.
5783 */
5784 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5785
5786 /*
5787 * According to the spec the following bits should be set in
5788 * order to enable memory self-refresh
5789 * The bit 22/21 of 0x42004
5790 * The bit 5 of 0x42020
5791 * The bit 15 of 0x45000
5792 */
5793 if (IS_GEN5(dev)) {
5794 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5795 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5796 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5797 I915_WRITE(ILK_DSPCLK_GATE,
5798 (I915_READ(ILK_DSPCLK_GATE) |
5799 ILK_DPARB_CLK_GATE));
5800 I915_WRITE(DISP_ARB_CTL,
5801 (I915_READ(DISP_ARB_CTL) |
5802 DISP_FBC_WM_DIS));
5803 I915_WRITE(WM3_LP_ILK, 0);
5804 I915_WRITE(WM2_LP_ILK, 0);
5805 I915_WRITE(WM1_LP_ILK, 0);
5806 }
5807 /*
5808 * Based on the document from hardware guys the following bits
5809 * should be set unconditionally in order to enable FBC.
5810 * The bit 22 of 0x42000
5811 * The bit 22 of 0x42004
5812 * The bit 7,8,9 of 0x42020.
5813 */
5814 if (IS_IRONLAKE_M(dev)) {
5815 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5816 I915_READ(ILK_DISPLAY_CHICKEN1) |
5817 ILK_FBCQ_DIS);
5818 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5819 I915_READ(ILK_DISPLAY_CHICKEN2) |
5820 ILK_DPARB_GATE);
5821 I915_WRITE(ILK_DSPCLK_GATE,
5822 I915_READ(ILK_DSPCLK_GATE) |
5823 ILK_DPFC_DIS1 |
5824 ILK_DPFC_DIS2 |
5825 ILK_CLK_FBC);
5826 }
5827 return;
5828 } else if (IS_G4X(dev)) {
5829 uint32_t dspclk_gate;
5830 I915_WRITE(RENCLK_GATE_D1, 0);
5831 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5832 GS_UNIT_CLOCK_GATE_DISABLE |
5833 CL_UNIT_CLOCK_GATE_DISABLE);
5834 I915_WRITE(RAMCLK_GATE_D, 0);
5835 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5836 OVRUNIT_CLOCK_GATE_DISABLE |
5837 OVCUNIT_CLOCK_GATE_DISABLE;
5838 if (IS_GM45(dev))
5839 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5840 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5841 } else if (IS_CRESTLINE(dev)) {
5842 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5843 I915_WRITE(RENCLK_GATE_D2, 0);
5844 I915_WRITE(DSPCLK_GATE_D, 0);
5845 I915_WRITE(RAMCLK_GATE_D, 0);
5846 I915_WRITE16(DEUC, 0);
5847 } else if (IS_BROADWATER(dev)) {
5848 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5849 I965_RCC_CLOCK_GATE_DISABLE |
5850 I965_RCPB_CLOCK_GATE_DISABLE |
5851 I965_ISC_CLOCK_GATE_DISABLE |
5852 I965_FBC_CLOCK_GATE_DISABLE);
5853 I915_WRITE(RENCLK_GATE_D2, 0);
5854 } else if (IS_GEN3(dev)) {
5855 u32 dstate = I915_READ(D_STATE);
5856
5857 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5858 DSTATE_DOT_CLOCK_GATING;
5859 I915_WRITE(D_STATE, dstate);
5860 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5861 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5862 } else if (IS_I830(dev)) {
5863 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5864 }
5865
5866 /*
5867 * GPU can automatically power down the render unit if given a page
5868 * to save state.
5869 */
5870 if (IS_IRONLAKE_M(dev)) {
5871 if (dev_priv->renderctx == NULL)
5872 dev_priv->renderctx = intel_alloc_context_page(dev);
5873 if (dev_priv->renderctx) {
5874 struct drm_i915_gem_object *obj_priv;
5875 obj_priv = to_intel_bo(dev_priv->renderctx);
5876 if (obj_priv) {
5877 BEGIN_LP_RING(4);
5878 OUT_RING(MI_SET_CONTEXT);
5879 OUT_RING(obj_priv->gtt_offset |
5880 MI_MM_SPACE_GTT |
5881 MI_SAVE_EXT_STATE_EN |
5882 MI_RESTORE_EXT_STATE_EN |
5883 MI_RESTORE_INHIBIT);
5884 OUT_RING(MI_NOOP);
5885 OUT_RING(MI_FLUSH);
5886 ADVANCE_LP_RING();
5887 }
5888 } else
5889 DRM_DEBUG_KMS("Failed to allocate render context."
5890 "Disable RC6\n");
5891 }
5892
5893 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5894 struct drm_i915_gem_object *obj_priv = NULL;
5895
5896 if (dev_priv->pwrctx) {
5897 obj_priv = to_intel_bo(dev_priv->pwrctx);
5898 } else {
5899 struct drm_gem_object *pwrctx;
5900
5901 pwrctx = intel_alloc_context_page(dev);
5902 if (pwrctx) {
5903 dev_priv->pwrctx = pwrctx;
5904 obj_priv = to_intel_bo(pwrctx);
5905 }
5906 }
5907
5908 if (obj_priv) {
5909 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5910 I915_WRITE(MCHBAR_RENDER_STANDBY,
5911 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5912 }
5913 }
5914 }
5915
5916 /* Set up chip specific display functions */
5917 static void intel_init_display(struct drm_device *dev)
5918 {
5919 struct drm_i915_private *dev_priv = dev->dev_private;
5920
5921 /* We always want a DPMS function */
5922 if (HAS_PCH_SPLIT(dev))
5923 dev_priv->display.dpms = ironlake_crtc_dpms;
5924 else
5925 dev_priv->display.dpms = i9xx_crtc_dpms;
5926
5927 if (I915_HAS_FBC(dev)) {
5928 if (IS_IRONLAKE_M(dev)) {
5929 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5930 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5931 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5932 } else if (IS_GM45(dev)) {
5933 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5934 dev_priv->display.enable_fbc = g4x_enable_fbc;
5935 dev_priv->display.disable_fbc = g4x_disable_fbc;
5936 } else if (IS_CRESTLINE(dev)) {
5937 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5938 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5939 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5940 }
5941 /* 855GM needs testing */
5942 }
5943
5944 /* Returns the core display clock speed */
5945 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5946 dev_priv->display.get_display_clock_speed =
5947 i945_get_display_clock_speed;
5948 else if (IS_I915G(dev))
5949 dev_priv->display.get_display_clock_speed =
5950 i915_get_display_clock_speed;
5951 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5952 dev_priv->display.get_display_clock_speed =
5953 i9xx_misc_get_display_clock_speed;
5954 else if (IS_I915GM(dev))
5955 dev_priv->display.get_display_clock_speed =
5956 i915gm_get_display_clock_speed;
5957 else if (IS_I865G(dev))
5958 dev_priv->display.get_display_clock_speed =
5959 i865_get_display_clock_speed;
5960 else if (IS_I85X(dev))
5961 dev_priv->display.get_display_clock_speed =
5962 i855_get_display_clock_speed;
5963 else /* 852, 830 */
5964 dev_priv->display.get_display_clock_speed =
5965 i830_get_display_clock_speed;
5966
5967 /* For FIFO watermark updates */
5968 if (HAS_PCH_SPLIT(dev)) {
5969 if (IS_GEN5(dev)) {
5970 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5971 dev_priv->display.update_wm = ironlake_update_wm;
5972 else {
5973 DRM_DEBUG_KMS("Failed to get proper latency. "
5974 "Disable CxSR\n");
5975 dev_priv->display.update_wm = NULL;
5976 }
5977 } else
5978 dev_priv->display.update_wm = NULL;
5979 } else if (IS_PINEVIEW(dev)) {
5980 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5981 dev_priv->is_ddr3,
5982 dev_priv->fsb_freq,
5983 dev_priv->mem_freq)) {
5984 DRM_INFO("failed to find known CxSR latency "
5985 "(found ddr%s fsb freq %d, mem freq %d), "
5986 "disabling CxSR\n",
5987 (dev_priv->is_ddr3 == 1) ? "3": "2",
5988 dev_priv->fsb_freq, dev_priv->mem_freq);
5989 /* Disable CxSR and never update its watermark again */
5990 pineview_disable_cxsr(dev);
5991 dev_priv->display.update_wm = NULL;
5992 } else
5993 dev_priv->display.update_wm = pineview_update_wm;
5994 } else if (IS_G4X(dev))
5995 dev_priv->display.update_wm = g4x_update_wm;
5996 else if (IS_GEN4(dev))
5997 dev_priv->display.update_wm = i965_update_wm;
5998 else if (IS_GEN3(dev)) {
5999 dev_priv->display.update_wm = i9xx_update_wm;
6000 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6001 } else if (IS_I85X(dev)) {
6002 dev_priv->display.update_wm = i9xx_update_wm;
6003 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6004 } else {
6005 dev_priv->display.update_wm = i830_update_wm;
6006 if (IS_845G(dev))
6007 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6008 else
6009 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6010 }
6011 }
6012
6013 /*
6014 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6015 * resume, or other times. This quirk makes sure that's the case for
6016 * affected systems.
6017 */
6018 static void quirk_pipea_force (struct drm_device *dev)
6019 {
6020 struct drm_i915_private *dev_priv = dev->dev_private;
6021
6022 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6023 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6024 }
6025
6026 struct intel_quirk {
6027 int device;
6028 int subsystem_vendor;
6029 int subsystem_device;
6030 void (*hook)(struct drm_device *dev);
6031 };
6032
6033 struct intel_quirk intel_quirks[] = {
6034 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6035 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6036 /* HP Mini needs pipe A force quirk (LP: #322104) */
6037 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6038
6039 /* Thinkpad R31 needs pipe A force quirk */
6040 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6041 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6042 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6043
6044 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6045 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6046 /* ThinkPad X40 needs pipe A force quirk */
6047
6048 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6049 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6050
6051 /* 855 & before need to leave pipe A & dpll A up */
6052 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6053 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6054 };
6055
6056 static void intel_init_quirks(struct drm_device *dev)
6057 {
6058 struct pci_dev *d = dev->pdev;
6059 int i;
6060
6061 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6062 struct intel_quirk *q = &intel_quirks[i];
6063
6064 if (d->device == q->device &&
6065 (d->subsystem_vendor == q->subsystem_vendor ||
6066 q->subsystem_vendor == PCI_ANY_ID) &&
6067 (d->subsystem_device == q->subsystem_device ||
6068 q->subsystem_device == PCI_ANY_ID))
6069 q->hook(dev);
6070 }
6071 }
6072
6073 /* Disable the VGA plane that we never use */
6074 static void i915_disable_vga(struct drm_device *dev)
6075 {
6076 struct drm_i915_private *dev_priv = dev->dev_private;
6077 u8 sr1;
6078 u32 vga_reg;
6079
6080 if (HAS_PCH_SPLIT(dev))
6081 vga_reg = CPU_VGACNTRL;
6082 else
6083 vga_reg = VGACNTRL;
6084
6085 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6086 outb(1, VGA_SR_INDEX);
6087 sr1 = inb(VGA_SR_DATA);
6088 outb(sr1 | 1<<5, VGA_SR_DATA);
6089 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6090 udelay(300);
6091
6092 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6093 POSTING_READ(vga_reg);
6094 }
6095
6096 void intel_modeset_init(struct drm_device *dev)
6097 {
6098 struct drm_i915_private *dev_priv = dev->dev_private;
6099 int i;
6100
6101 drm_mode_config_init(dev);
6102
6103 dev->mode_config.min_width = 0;
6104 dev->mode_config.min_height = 0;
6105
6106 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6107
6108 intel_init_quirks(dev);
6109
6110 intel_init_display(dev);
6111
6112 if (IS_GEN2(dev)) {
6113 dev->mode_config.max_width = 2048;
6114 dev->mode_config.max_height = 2048;
6115 } else if (IS_GEN3(dev)) {
6116 dev->mode_config.max_width = 4096;
6117 dev->mode_config.max_height = 4096;
6118 } else {
6119 dev->mode_config.max_width = 8192;
6120 dev->mode_config.max_height = 8192;
6121 }
6122
6123 /* set memory base */
6124 if (IS_GEN2(dev))
6125 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6126 else
6127 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6128
6129 if (IS_MOBILE(dev) || !IS_GEN2(dev))
6130 dev_priv->num_pipe = 2;
6131 else
6132 dev_priv->num_pipe = 1;
6133 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6134 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6135
6136 for (i = 0; i < dev_priv->num_pipe; i++) {
6137 intel_crtc_init(dev, i);
6138 }
6139
6140 intel_setup_outputs(dev);
6141
6142 intel_init_clock_gating(dev);
6143
6144 /* Just disable it once at startup */
6145 i915_disable_vga(dev);
6146
6147 if (IS_IRONLAKE_M(dev)) {
6148 ironlake_enable_drps(dev);
6149 intel_init_emon(dev);
6150 }
6151
6152 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6153 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6154 (unsigned long)dev);
6155
6156 intel_setup_overlay(dev);
6157 }
6158
6159 void intel_modeset_cleanup(struct drm_device *dev)
6160 {
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162 struct drm_crtc *crtc;
6163 struct intel_crtc *intel_crtc;
6164
6165 drm_kms_helper_poll_fini(dev);
6166 mutex_lock(&dev->struct_mutex);
6167
6168 intel_unregister_dsm_handler();
6169
6170
6171 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6172 /* Skip inactive CRTCs */
6173 if (!crtc->fb)
6174 continue;
6175
6176 intel_crtc = to_intel_crtc(crtc);
6177 intel_increase_pllclock(crtc);
6178 }
6179
6180 if (dev_priv->display.disable_fbc)
6181 dev_priv->display.disable_fbc(dev);
6182
6183 if (dev_priv->renderctx) {
6184 struct drm_i915_gem_object *obj_priv;
6185
6186 obj_priv = to_intel_bo(dev_priv->renderctx);
6187 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6188 I915_READ(CCID);
6189 i915_gem_object_unpin(dev_priv->renderctx);
6190 drm_gem_object_unreference(dev_priv->renderctx);
6191 }
6192
6193 if (dev_priv->pwrctx) {
6194 struct drm_i915_gem_object *obj_priv;
6195
6196 obj_priv = to_intel_bo(dev_priv->pwrctx);
6197 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6198 I915_READ(PWRCTXA);
6199 i915_gem_object_unpin(dev_priv->pwrctx);
6200 drm_gem_object_unreference(dev_priv->pwrctx);
6201 }
6202
6203 if (IS_IRONLAKE_M(dev))
6204 ironlake_disable_drps(dev);
6205
6206 mutex_unlock(&dev->struct_mutex);
6207
6208 /* Disable the irq before mode object teardown, for the irq might
6209 * enqueue unpin/hotplug work. */
6210 drm_irq_uninstall(dev);
6211 cancel_work_sync(&dev_priv->hotplug_work);
6212
6213 /* Shut off idle work before the crtcs get freed. */
6214 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6215 intel_crtc = to_intel_crtc(crtc);
6216 del_timer_sync(&intel_crtc->idle_timer);
6217 }
6218 del_timer_sync(&dev_priv->idle_timer);
6219 cancel_work_sync(&dev_priv->idle_work);
6220
6221 drm_mode_config_cleanup(dev);
6222 }
6223
6224 /*
6225 * Return which encoder is currently attached for connector.
6226 */
6227 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6228 {
6229 return &intel_attached_encoder(connector)->base;
6230 }
6231
6232 void intel_connector_attach_encoder(struct intel_connector *connector,
6233 struct intel_encoder *encoder)
6234 {
6235 connector->encoder = encoder;
6236 drm_mode_connector_attach_encoder(&connector->base,
6237 &encoder->base);
6238 }
6239
6240 /*
6241 * set vga decode state - true == enable VGA decode
6242 */
6243 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6244 {
6245 struct drm_i915_private *dev_priv = dev->dev_private;
6246 u16 gmch_ctrl;
6247
6248 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6249 if (state)
6250 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6251 else
6252 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6253 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6254 return 0;
6255 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree