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ARM: 5691/1: fix cache aliasing issues between kmap() and kmap_atomic() with highmem
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / serial / bfin_5xx.c
bloba543acf5b6a370c7b6be23267d74acd09de28d56
1 /*
2 * Blackfin On-Chip Serial Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12 #define SUPPORT_SYSRQ
13 #endif
14
15 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/sysrq.h>
20 #include <linux/platform_device.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/serial_core.h>
24
25 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
26 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
27 #include <linux/kgdb.h>
28 #include <asm/irq_regs.h>
29 #endif
30
31 #include <asm/gpio.h>
32 #include <mach/bfin_serial_5xx.h>
33
34 #ifdef CONFIG_SERIAL_BFIN_DMA
35 #include <linux/dma-mapping.h>
36 #include <asm/io.h>
37 #include <asm/irq.h>
38 #include <asm/cacheflush.h>
39 #endif
40
41 #ifdef CONFIG_SERIAL_BFIN_MODULE
42 # undef CONFIG_EARLY_PRINTK
43 #endif
44
45 /* UART name and device definitions */
46 #define BFIN_SERIAL_NAME "ttyBF"
47 #define BFIN_SERIAL_MAJOR 204
48 #define BFIN_SERIAL_MINOR 64
49
50 static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
51 static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource);
52
53 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
54 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
55
56 # ifndef CONFIG_SERIAL_BFIN_PIO
57 # error KGDB only support UART in PIO mode.
58 # endif
59
60 static int kgdboc_port_line;
61 static int kgdboc_break_enabled;
62 #endif
63 /*
64 * Setup for console. Argument comes from the menuconfig
65 */
66 #define DMA_RX_XCOUNT 512
67 #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
68
69 #define DMA_RX_FLUSH_JIFFIES (HZ / 50)
70
71 #ifdef CONFIG_SERIAL_BFIN_DMA
72 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
73 #else
74 static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
75 #endif
76
77 static void bfin_serial_reset_irda(struct uart_port *port);
78
79 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
80 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
81 static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
82 {
83 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
84 if (uart->cts_pin < 0)
85 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
86
87 /* CTS PIN is negative assertive. */
88 if (UART_GET_CTS(uart))
89 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
90 else
91 return TIOCM_DSR | TIOCM_CAR;
92 }
93
94 static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
95 {
96 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
97 if (uart->rts_pin < 0)
98 return;
99
100 /* RTS PIN is negative assertive. */
101 if (mctrl & TIOCM_RTS)
102 UART_ENABLE_RTS(uart);
103 else
104 UART_DISABLE_RTS(uart);
105 }
106
107 /*
108 * Handle any change of modem status signal.
109 */
110 static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
111 {
112 struct bfin_serial_port *uart = dev_id;
113 unsigned int status;
114
115 status = bfin_serial_get_mctrl(&uart->port);
116 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
117 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
118 uart->scts = 1;
119 UART_CLEAR_SCTS(uart);
120 UART_CLEAR_IER(uart, EDSSI);
121 #endif
122
123 return IRQ_HANDLED;
124 }
125 #else
126 static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
127 {
128 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
129 }
130
131 static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
132 {
133 }
134 #endif
135
136 /*
137 * interrupts are disabled on entry
138 */
139 static void bfin_serial_stop_tx(struct uart_port *port)
140 {
141 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
142 #ifdef CONFIG_SERIAL_BFIN_DMA
143 struct circ_buf *xmit = &uart->port.info->xmit;
144 #endif
145
146 while (!(UART_GET_LSR(uart) & TEMT))
147 cpu_relax();
148
149 #ifdef CONFIG_SERIAL_BFIN_DMA
150 disable_dma(uart->tx_dma_channel);
151 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
152 uart->port.icount.tx += uart->tx_count;
153 uart->tx_count = 0;
154 uart->tx_done = 1;
155 #else
156 #ifdef CONFIG_BF54x
157 /* Clear TFI bit */
158 UART_PUT_LSR(uart, TFI);
159 #endif
160 UART_CLEAR_IER(uart, ETBEI);
161 #endif
162 }
163
164 /*
165 * port is locked and interrupts are disabled
166 */
167 static void bfin_serial_start_tx(struct uart_port *port)
168 {
169 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
170 struct tty_struct *tty = uart->port.info->port.tty;
171
172 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
173 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
174 uart->scts = 0;
175 uart_handle_cts_change(&uart->port, uart->scts);
176 }
177 #endif
178
179 /*
180 * To avoid losting RX interrupt, we reset IR function
181 * before sending data.
182 */
183 if (tty->termios->c_line == N_IRDA)
184 bfin_serial_reset_irda(port);
185
186 #ifdef CONFIG_SERIAL_BFIN_DMA
187 if (uart->tx_done)
188 bfin_serial_dma_tx_chars(uart);
189 #else
190 UART_SET_IER(uart, ETBEI);
191 bfin_serial_tx_chars(uart);
192 #endif
193 }
194
195 /*
196 * Interrupts are enabled
197 */
198 static void bfin_serial_stop_rx(struct uart_port *port)
199 {
200 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
201
202 UART_CLEAR_IER(uart, ERBFI);
203 }
204
205 /*
206 * Set the modem control timer to fire immediately.
207 */
208 static void bfin_serial_enable_ms(struct uart_port *port)
209 {
210 }
211
212
213 #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
214 # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
215 # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
216 #else
217 # define UART_GET_ANOMALY_THRESHOLD(uart) 0
218 # define UART_SET_ANOMALY_THRESHOLD(uart, v)
219 #endif
220
221 #ifdef CONFIG_SERIAL_BFIN_PIO
222 static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
223 {
224 struct tty_struct *tty = NULL;
225 unsigned int status, ch, flg;
226 static struct timeval anomaly_start = { .tv_sec = 0 };
227
228 status = UART_GET_LSR(uart);
229 UART_CLEAR_LSR(uart);
230
231 ch = UART_GET_CHAR(uart);
232 uart->port.icount.rx++;
233
234 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
235 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
236 if (kgdb_connected && kgdboc_port_line == uart->port.line)
237 if (ch == 0x3) {/* Ctrl + C */
238 kgdb_breakpoint();
239 return;
240 }
241
242 if (!uart->port.info || !uart->port.info->port.tty)
243 return;
244 #endif
245 tty = uart->port.info->port.tty;
246
247 if (ANOMALY_05000363) {
248 /* The BF533 (and BF561) family of processors have a nice anomaly
249 * where they continuously generate characters for a "single" break.
250 * We have to basically ignore this flood until the "next" valid
251 * character comes across. Due to the nature of the flood, it is
252 * not possible to reliably catch bytes that are sent too quickly
253 * after this break. So application code talking to the Blackfin
254 * which sends a break signal must allow at least 1.5 character
255 * times after the end of the break for things to stabilize. This
256 * timeout was picked as it must absolutely be larger than 1
257 * character time +/- some percent. So 1.5 sounds good. All other
258 * Blackfin families operate properly. Woo.
259 */
260 if (anomaly_start.tv_sec) {
261 struct timeval curr;
262 suseconds_t usecs;
263
264 if ((~ch & (~ch + 1)) & 0xff)
265 goto known_good_char;
266
267 do_gettimeofday(&curr);
268 if (curr.tv_sec - anomaly_start.tv_sec > 1)
269 goto known_good_char;
270
271 usecs = 0;
272 if (curr.tv_sec != anomaly_start.tv_sec)
273 usecs += USEC_PER_SEC;
274 usecs += curr.tv_usec - anomaly_start.tv_usec;
275
276 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
277 goto known_good_char;
278
279 if (ch)
280 anomaly_start.tv_sec = 0;
281 else
282 anomaly_start = curr;
283
284 return;
285
286 known_good_char:
287 status &= ~BI;
288 anomaly_start.tv_sec = 0;
289 }
290 }
291
292 if (status & BI) {
293 if (ANOMALY_05000363)
294 if (bfin_revid() < 5)
295 do_gettimeofday(&anomaly_start);
296 uart->port.icount.brk++;
297 if (uart_handle_break(&uart->port))
298 goto ignore_char;
299 status &= ~(PE | FE);
300 }
301 if (status & PE)
302 uart->port.icount.parity++;
303 if (status & OE)
304 uart->port.icount.overrun++;
305 if (status & FE)
306 uart->port.icount.frame++;
307
308 status &= uart->port.read_status_mask;
309
310 if (status & BI)
311 flg = TTY_BREAK;
312 else if (status & PE)
313 flg = TTY_PARITY;
314 else if (status & FE)
315 flg = TTY_FRAME;
316 else
317 flg = TTY_NORMAL;
318
319 if (uart_handle_sysrq_char(&uart->port, ch))
320 goto ignore_char;
321
322 uart_insert_char(&uart->port, status, OE, ch, flg);
323
324 ignore_char:
325 tty_flip_buffer_push(tty);
326 }
327
328 static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
329 {
330 struct circ_buf *xmit = &uart->port.info->xmit;
331
332 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
333 #ifdef CONFIG_BF54x
334 /* Clear TFI bit */
335 UART_PUT_LSR(uart, TFI);
336 #endif
337 UART_CLEAR_IER(uart, ETBEI);
338 return;
339 }
340
341 if (uart->port.x_char) {
342 UART_PUT_CHAR(uart, uart->port.x_char);
343 uart->port.icount.tx++;
344 uart->port.x_char = 0;
345 }
346
347 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
348 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
349 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
350 uart->port.icount.tx++;
351 SSYNC();
352 }
353
354 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
355 uart_write_wakeup(&uart->port);
356 }
357
358 static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
359 {
360 struct bfin_serial_port *uart = dev_id;
361
362 spin_lock(&uart->port.lock);
363 while (UART_GET_LSR(uart) & DR)
364 bfin_serial_rx_chars(uart);
365 spin_unlock(&uart->port.lock);
366
367 return IRQ_HANDLED;
368 }
369
370 static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
371 {
372 struct bfin_serial_port *uart = dev_id;
373
374 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
375 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
376 uart->scts = 0;
377 uart_handle_cts_change(&uart->port, uart->scts);
378 }
379 #endif
380 spin_lock(&uart->port.lock);
381 if (UART_GET_LSR(uart) & THRE)
382 bfin_serial_tx_chars(uart);
383 spin_unlock(&uart->port.lock);
384
385 return IRQ_HANDLED;
386 }
387 #endif
388
389 #ifdef CONFIG_SERIAL_BFIN_DMA
390 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
391 {
392 struct circ_buf *xmit = &uart->port.info->xmit;
393
394 uart->tx_done = 0;
395
396 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
397 uart->tx_count = 0;
398 uart->tx_done = 1;
399 return;
400 }
401
402 if (uart->port.x_char) {
403 UART_PUT_CHAR(uart, uart->port.x_char);
404 uart->port.icount.tx++;
405 uart->port.x_char = 0;
406 }
407
408 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
409 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
410 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
411 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
412 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
413 set_dma_config(uart->tx_dma_channel,
414 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
415 INTR_ON_BUF,
416 DIMENSION_LINEAR,
417 DATA_SIZE_8,
418 DMA_SYNC_RESTART));
419 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
420 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
421 set_dma_x_modify(uart->tx_dma_channel, 1);
422 enable_dma(uart->tx_dma_channel);
423
424 UART_SET_IER(uart, ETBEI);
425 }
426
427 static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
428 {
429 struct tty_struct *tty = uart->port.info->port.tty;
430 int i, flg, status;
431
432 status = UART_GET_LSR(uart);
433 UART_CLEAR_LSR(uart);
434
435 uart->port.icount.rx +=
436 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
437 UART_XMIT_SIZE);
438
439 if (status & BI) {
440 uart->port.icount.brk++;
441 if (uart_handle_break(&uart->port))
442 goto dma_ignore_char;
443 status &= ~(PE | FE);
444 }
445 if (status & PE)
446 uart->port.icount.parity++;
447 if (status & OE)
448 uart->port.icount.overrun++;
449 if (status & FE)
450 uart->port.icount.frame++;
451
452 status &= uart->port.read_status_mask;
453
454 if (status & BI)
455 flg = TTY_BREAK;
456 else if (status & PE)
457 flg = TTY_PARITY;
458 else if (status & FE)
459 flg = TTY_FRAME;
460 else
461 flg = TTY_NORMAL;
462
463 for (i = uart->rx_dma_buf.tail; ; i++) {
464 if (i >= UART_XMIT_SIZE)
465 i = 0;
466 if (i == uart->rx_dma_buf.head)
467 break;
468 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
469 uart_insert_char(&uart->port, status, OE,
470 uart->rx_dma_buf.buf[i], flg);
471 }
472
473 dma_ignore_char:
474 tty_flip_buffer_push(tty);
475 }
476
477 void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
478 {
479 int x_pos, pos;
480 unsigned long flags;
481
482 spin_lock_irqsave(&uart->port.lock, flags);
483
484 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
485 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
486 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
487 if (uart->rx_dma_nrows == DMA_RX_YCOUNT)
488 uart->rx_dma_nrows = 0;
489 x_pos = DMA_RX_XCOUNT - x_pos;
490 if (x_pos == DMA_RX_XCOUNT)
491 x_pos = 0;
492
493 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
494 if (pos != uart->rx_dma_buf.tail) {
495 uart->rx_dma_buf.head = pos;
496 bfin_serial_dma_rx_chars(uart);
497 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
498 }
499
500 spin_unlock_irqrestore(&uart->port.lock, flags);
501
502 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
503 }
504
505 static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
506 {
507 struct bfin_serial_port *uart = dev_id;
508 struct circ_buf *xmit = &uart->port.info->xmit;
509
510 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
511 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
512 uart->scts = 0;
513 uart_handle_cts_change(&uart->port, uart->scts);
514 }
515 #endif
516
517 spin_lock(&uart->port.lock);
518 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
519 disable_dma(uart->tx_dma_channel);
520 clear_dma_irqstat(uart->tx_dma_channel);
521 UART_CLEAR_IER(uart, ETBEI);
522 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
523 uart->port.icount.tx += uart->tx_count;
524
525 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
526 uart_write_wakeup(&uart->port);
527
528 bfin_serial_dma_tx_chars(uart);
529 }
530
531 spin_unlock(&uart->port.lock);
532 return IRQ_HANDLED;
533 }
534
535 static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
536 {
537 struct bfin_serial_port *uart = dev_id;
538 unsigned short irqstat;
539
540 spin_lock(&uart->port.lock);
541 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
542 clear_dma_irqstat(uart->rx_dma_channel);
543 bfin_serial_dma_rx_chars(uart);
544 spin_unlock(&uart->port.lock);
545
546 return IRQ_HANDLED;
547 }
548 #endif
549
550 /*
551 * Return TIOCSER_TEMT when transmitter is not busy.
552 */
553 static unsigned int bfin_serial_tx_empty(struct uart_port *port)
554 {
555 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
556 unsigned short lsr;
557
558 lsr = UART_GET_LSR(uart);
559 if (lsr & TEMT)
560 return TIOCSER_TEMT;
561 else
562 return 0;
563 }
564
565 static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
566 {
567 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
568 u16 lcr = UART_GET_LCR(uart);
569 if (break_state)
570 lcr |= SB;
571 else
572 lcr &= ~SB;
573 UART_PUT_LCR(uart, lcr);
574 SSYNC();
575 }
576
577 static int bfin_serial_startup(struct uart_port *port)
578 {
579 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
580
581 #ifdef CONFIG_SERIAL_BFIN_DMA
582 dma_addr_t dma_handle;
583
584 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
585 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
586 return -EBUSY;
587 }
588
589 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
590 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
591 free_dma(uart->rx_dma_channel);
592 return -EBUSY;
593 }
594
595 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
596 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
597
598 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
599 uart->rx_dma_buf.head = 0;
600 uart->rx_dma_buf.tail = 0;
601 uart->rx_dma_nrows = 0;
602
603 set_dma_config(uart->rx_dma_channel,
604 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
605 INTR_ON_ROW, DIMENSION_2D,
606 DATA_SIZE_8,
607 DMA_SYNC_RESTART));
608 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
609 set_dma_x_modify(uart->rx_dma_channel, 1);
610 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
611 set_dma_y_modify(uart->rx_dma_channel, 1);
612 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
613 enable_dma(uart->rx_dma_channel);
614
615 uart->rx_dma_timer.data = (unsigned long)(uart);
616 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
617 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
618 add_timer(&(uart->rx_dma_timer));
619 #else
620 # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
621 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
622 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
623 kgdboc_break_enabled = 0;
624 else {
625 # endif
626 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
627 "BFIN_UART_RX", uart)) {
628 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
629 return -EBUSY;
630 }
631
632 if (request_irq
633 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
634 "BFIN_UART_TX", uart)) {
635 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
636 free_irq(uart->port.irq, uart);
637 return -EBUSY;
638 }
639
640 # ifdef CONFIG_BF54x
641 {
642 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
643
644 switch (uart->port.irq) {
645 case IRQ_UART3_RX:
646 uart_dma_ch_rx = CH_UART3_RX;
647 uart_dma_ch_tx = CH_UART3_TX;
648 break;
649 case IRQ_UART2_RX:
650 uart_dma_ch_rx = CH_UART2_RX;
651 uart_dma_ch_tx = CH_UART2_TX;
652 break;
653 default:
654 uart_dma_ch_rx = uart_dma_ch_tx = 0;
655 break;
656 };
657
658 if (uart_dma_ch_rx &&
659 request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
660 printk(KERN_NOTICE"Fail to attach UART interrupt\n");
661 free_irq(uart->port.irq, uart);
662 free_irq(uart->port.irq + 1, uart);
663 return -EBUSY;
664 }
665 if (uart_dma_ch_tx &&
666 request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
667 printk(KERN_NOTICE "Fail to attach UART interrupt\n");
668 free_dma(uart_dma_ch_rx);
669 free_irq(uart->port.irq, uart);
670 free_irq(uart->port.irq + 1, uart);
671 return -EBUSY;
672 }
673 }
674 # endif
675 # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
676 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
677 }
678 # endif
679 #endif
680
681 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
682 if (uart->cts_pin >= 0) {
683 if (request_irq(gpio_to_irq(uart->cts_pin),
684 bfin_serial_mctrl_cts_int,
685 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
686 IRQF_DISABLED, "BFIN_UART_CTS", uart)) {
687 uart->cts_pin = -1;
688 pr_info("Unable to attach BlackFin UART CTS interrupt.\
689 So, disable it.\n");
690 }
691 }
692 if (uart->rts_pin >= 0) {
693 gpio_request(uart->rts_pin, DRIVER_NAME);
694 gpio_direction_output(uart->rts_pin, 0);
695 }
696 #endif
697 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
698 if (request_irq(uart->status_irq,
699 bfin_serial_mctrl_cts_int,
700 IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) {
701 pr_info("Unable to attach BlackFin UART Modem \
702 Status interrupt.\n");
703 }
704
705 if (uart->cts_pin >= 0) {
706 gpio_request(uart->cts_pin, DRIVER_NAME);
707 gpio_direction_output(uart->cts_pin, 1);
708 }
709 if (uart->rts_pin >= 0) {
710 gpio_request(uart->rts_pin, DRIVER_NAME);
711 gpio_direction_output(uart->rts_pin, 0);
712 }
713
714 /* CTS RTS PINs are negative assertive. */
715 UART_PUT_MCR(uart, ACTS);
716 UART_SET_IER(uart, EDSSI);
717 #endif
718
719 UART_SET_IER(uart, ERBFI);
720 return 0;
721 }
722
723 static void bfin_serial_shutdown(struct uart_port *port)
724 {
725 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
726
727 #ifdef CONFIG_SERIAL_BFIN_DMA
728 disable_dma(uart->tx_dma_channel);
729 free_dma(uart->tx_dma_channel);
730 disable_dma(uart->rx_dma_channel);
731 free_dma(uart->rx_dma_channel);
732 del_timer(&(uart->rx_dma_timer));
733 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
734 #else
735 #ifdef CONFIG_BF54x
736 switch (uart->port.irq) {
737 case IRQ_UART3_RX:
738 free_dma(CH_UART3_RX);
739 free_dma(CH_UART3_TX);
740 break;
741 case IRQ_UART2_RX:
742 free_dma(CH_UART2_RX);
743 free_dma(CH_UART2_TX);
744 break;
745 default:
746 break;
747 };
748 #endif
749 free_irq(uart->port.irq, uart);
750 free_irq(uart->port.irq+1, uart);
751 #endif
752
753 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
754 if (uart->cts_pin >= 0)
755 free_irq(gpio_to_irq(uart->cts_pin), uart);
756 if (uart->rts_pin >= 0)
757 gpio_free(uart->rts_pin);
758 #endif
759 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
760 if (uart->cts_pin >= 0)
761 gpio_free(uart->cts_pin);
762 if (uart->rts_pin >= 0)
763 gpio_free(uart->rts_pin);
764 if (UART_GET_IER(uart) && EDSSI)
765 free_irq(uart->status_irq, uart);
766 #endif
767 }
768
769 static void
770 bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
771 struct ktermios *old)
772 {
773 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
774 unsigned long flags;
775 unsigned int baud, quot;
776 unsigned short val, ier, lcr = 0;
777
778 switch (termios->c_cflag & CSIZE) {
779 case CS8:
780 lcr = WLS(8);
781 break;
782 case CS7:
783 lcr = WLS(7);
784 break;
785 case CS6:
786 lcr = WLS(6);
787 break;
788 case CS5:
789 lcr = WLS(5);
790 break;
791 default:
792 printk(KERN_ERR "%s: word lengh not supported\n",
793 __func__);
794 }
795
796 if (termios->c_cflag & CSTOPB)
797 lcr |= STB;
798 if (termios->c_cflag & PARENB)
799 lcr |= PEN;
800 if (!(termios->c_cflag & PARODD))
801 lcr |= EPS;
802 if (termios->c_cflag & CMSPAR)
803 lcr |= STP;
804
805 port->read_status_mask = OE;
806 if (termios->c_iflag & INPCK)
807 port->read_status_mask |= (FE | PE);
808 if (termios->c_iflag & (BRKINT | PARMRK))
809 port->read_status_mask |= BI;
810
811 /*
812 * Characters to ignore
813 */
814 port->ignore_status_mask = 0;
815 if (termios->c_iflag & IGNPAR)
816 port->ignore_status_mask |= FE | PE;
817 if (termios->c_iflag & IGNBRK) {
818 port->ignore_status_mask |= BI;
819 /*
820 * If we're ignoring parity and break indicators,
821 * ignore overruns too (for real raw support).
822 */
823 if (termios->c_iflag & IGNPAR)
824 port->ignore_status_mask |= OE;
825 }
826
827 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
828 quot = uart_get_divisor(port, baud) - ANOMALY_05000230;
829 spin_lock_irqsave(&uart->port.lock, flags);
830
831 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
832
833 /* Disable UART */
834 ier = UART_GET_IER(uart);
835 UART_DISABLE_INTS(uart);
836
837 /* Set DLAB in LCR to Access DLL and DLH */
838 UART_SET_DLAB(uart);
839
840 UART_PUT_DLL(uart, quot & 0xFF);
841 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
842 SSYNC();
843
844 /* Clear DLAB in LCR to Access THR RBR IER */
845 UART_CLEAR_DLAB(uart);
846
847 UART_PUT_LCR(uart, lcr);
848
849 /* Enable UART */
850 UART_ENABLE_INTS(uart, ier);
851
852 val = UART_GET_GCTL(uart);
853 val |= UCEN;
854 UART_PUT_GCTL(uart, val);
855
856 /* Port speed changed, update the per-port timeout. */
857 uart_update_timeout(port, termios->c_cflag, baud);
858
859 spin_unlock_irqrestore(&uart->port.lock, flags);
860 }
861
862 static const char *bfin_serial_type(struct uart_port *port)
863 {
864 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
865
866 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
867 }
868
869 /*
870 * Release the memory region(s) being used by 'port'.
871 */
872 static void bfin_serial_release_port(struct uart_port *port)
873 {
874 }
875
876 /*
877 * Request the memory region(s) being used by 'port'.
878 */
879 static int bfin_serial_request_port(struct uart_port *port)
880 {
881 return 0;
882 }
883
884 /*
885 * Configure/autoconfigure the port.
886 */
887 static void bfin_serial_config_port(struct uart_port *port, int flags)
888 {
889 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
890
891 if (flags & UART_CONFIG_TYPE &&
892 bfin_serial_request_port(&uart->port) == 0)
893 uart->port.type = PORT_BFIN;
894 }
895
896 /*
897 * Verify the new serial_struct (for TIOCSSERIAL).
898 * The only change we allow are to the flags and type, and
899 * even then only between PORT_BFIN and PORT_UNKNOWN
900 */
901 static int
902 bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
903 {
904 return 0;
905 }
906
907 /*
908 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
909 * In other cases, disable IrDA function.
910 */
911 static void bfin_serial_set_ldisc(struct uart_port *port)
912 {
913 int line = port->line;
914 unsigned short val;
915
916 if (line >= port->info->port.tty->driver->num)
917 return;
918
919 switch (port->info->port.tty->termios->c_line) {
920 case N_IRDA:
921 val = UART_GET_GCTL(&bfin_serial_ports[line]);
922 val |= (IREN | RPOLC);
923 UART_PUT_GCTL(&bfin_serial_ports[line], val);
924 break;
925 default:
926 val = UART_GET_GCTL(&bfin_serial_ports[line]);
927 val &= ~(IREN | RPOLC);
928 UART_PUT_GCTL(&bfin_serial_ports[line], val);
929 }
930 }
931
932 static void bfin_serial_reset_irda(struct uart_port *port)
933 {
934 int line = port->line;
935 unsigned short val;
936
937 val = UART_GET_GCTL(&bfin_serial_ports[line]);
938 val &= ~(IREN | RPOLC);
939 UART_PUT_GCTL(&bfin_serial_ports[line], val);
940 SSYNC();
941 val |= (IREN | RPOLC);
942 UART_PUT_GCTL(&bfin_serial_ports[line], val);
943 SSYNC();
944 }
945
946 #ifdef CONFIG_CONSOLE_POLL
947 static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
948 {
949 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
950
951 while (!(UART_GET_LSR(uart) & THRE))
952 cpu_relax();
953
954 UART_CLEAR_DLAB(uart);
955 UART_PUT_CHAR(uart, (unsigned char)chr);
956 }
957
958 static int bfin_serial_poll_get_char(struct uart_port *port)
959 {
960 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
961 unsigned char chr;
962
963 while (!(UART_GET_LSR(uart) & DR))
964 cpu_relax();
965
966 UART_CLEAR_DLAB(uart);
967 chr = UART_GET_CHAR(uart);
968
969 return chr;
970 }
971 #endif
972
973 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
974 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
975 static void bfin_kgdboc_port_shutdown(struct uart_port *port)
976 {
977 if (kgdboc_break_enabled) {
978 kgdboc_break_enabled = 0;
979 bfin_serial_shutdown(port);
980 }
981 }
982
983 static int bfin_kgdboc_port_startup(struct uart_port *port)
984 {
985 kgdboc_port_line = port->line;
986 kgdboc_break_enabled = !bfin_serial_startup(port);
987 return 0;
988 }
989 #endif
990
991 static struct uart_ops bfin_serial_pops = {
992 .tx_empty = bfin_serial_tx_empty,
993 .set_mctrl = bfin_serial_set_mctrl,
994 .get_mctrl = bfin_serial_get_mctrl,
995 .stop_tx = bfin_serial_stop_tx,
996 .start_tx = bfin_serial_start_tx,
997 .stop_rx = bfin_serial_stop_rx,
998 .enable_ms = bfin_serial_enable_ms,
999 .break_ctl = bfin_serial_break_ctl,
1000 .startup = bfin_serial_startup,
1001 .shutdown = bfin_serial_shutdown,
1002 .set_termios = bfin_serial_set_termios,
1003 .set_ldisc = bfin_serial_set_ldisc,
1004 .type = bfin_serial_type,
1005 .release_port = bfin_serial_release_port,
1006 .request_port = bfin_serial_request_port,
1007 .config_port = bfin_serial_config_port,
1008 .verify_port = bfin_serial_verify_port,
1009 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1010 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1011 .kgdboc_port_startup = bfin_kgdboc_port_startup,
1012 .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown,
1013 #endif
1014 #ifdef CONFIG_CONSOLE_POLL
1015 .poll_put_char = bfin_serial_poll_put_char,
1016 .poll_get_char = bfin_serial_poll_get_char,
1017 #endif
1018 };
1019
1020 static void __init bfin_serial_hw_init(void)
1021 {
1022 #ifdef CONFIG_SERIAL_BFIN_UART0
1023 peripheral_request(P_UART0_TX, DRIVER_NAME);
1024 peripheral_request(P_UART0_RX, DRIVER_NAME);
1025 #endif
1026
1027 #ifdef CONFIG_SERIAL_BFIN_UART1
1028 peripheral_request(P_UART1_TX, DRIVER_NAME);
1029 peripheral_request(P_UART1_RX, DRIVER_NAME);
1030
1031 # if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x)
1032 peripheral_request(P_UART1_RTS, DRIVER_NAME);
1033 peripheral_request(P_UART1_CTS, DRIVER_NAME);
1034 # endif
1035 #endif
1036
1037 #ifdef CONFIG_SERIAL_BFIN_UART2
1038 peripheral_request(P_UART2_TX, DRIVER_NAME);
1039 peripheral_request(P_UART2_RX, DRIVER_NAME);
1040 #endif
1041
1042 #ifdef CONFIG_SERIAL_BFIN_UART3
1043 peripheral_request(P_UART3_TX, DRIVER_NAME);
1044 peripheral_request(P_UART3_RX, DRIVER_NAME);
1045
1046 # if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x)
1047 peripheral_request(P_UART3_RTS, DRIVER_NAME);
1048 peripheral_request(P_UART3_CTS, DRIVER_NAME);
1049 # endif
1050 #endif
1051 }
1052
1053 static void __init bfin_serial_init_ports(void)
1054 {
1055 static int first = 1;
1056 int i;
1057
1058 if (!first)
1059 return;
1060 first = 0;
1061
1062 bfin_serial_hw_init();
1063
1064 for (i = 0; i < nr_active_ports; i++) {
1065 spin_lock_init(&bfin_serial_ports[i].port.lock);
1066 bfin_serial_ports[i].port.uartclk = get_sclk();
1067 bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE;
1068 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
1069 bfin_serial_ports[i].port.line = i;
1070 bfin_serial_ports[i].port.iotype = UPIO_MEM;
1071 bfin_serial_ports[i].port.membase =
1072 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
1073 bfin_serial_ports[i].port.mapbase =
1074 bfin_serial_resource[i].uart_base_addr;
1075 bfin_serial_ports[i].port.irq =
1076 bfin_serial_resource[i].uart_irq;
1077 bfin_serial_ports[i].status_irq =
1078 bfin_serial_resource[i].uart_status_irq;
1079 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
1080 #ifdef CONFIG_SERIAL_BFIN_DMA
1081 bfin_serial_ports[i].tx_done = 1;
1082 bfin_serial_ports[i].tx_count = 0;
1083 bfin_serial_ports[i].tx_dma_channel =
1084 bfin_serial_resource[i].uart_tx_dma_channel;
1085 bfin_serial_ports[i].rx_dma_channel =
1086 bfin_serial_resource[i].uart_rx_dma_channel;
1087 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
1088 #endif
1089 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1090 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1091 bfin_serial_ports[i].cts_pin =
1092 bfin_serial_resource[i].uart_cts_pin;
1093 bfin_serial_ports[i].rts_pin =
1094 bfin_serial_resource[i].uart_rts_pin;
1095 #endif
1096 }
1097 }
1098
1099 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1100 /*
1101 * If the port was already initialised (eg, by a boot loader),
1102 * try to determine the current setup.
1103 */
1104 static void __init
1105 bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1106 int *parity, int *bits)
1107 {
1108 unsigned short status;
1109
1110 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1111 if (status == (ERBFI | ETBEI)) {
1112 /* ok, the port was enabled */
1113 u16 lcr, dlh, dll;
1114
1115 lcr = UART_GET_LCR(uart);
1116
1117 *parity = 'n';
1118 if (lcr & PEN) {
1119 if (lcr & EPS)
1120 *parity = 'e';
1121 else
1122 *parity = 'o';
1123 }
1124 switch (lcr & 0x03) {
1125 case 0: *bits = 5; break;
1126 case 1: *bits = 6; break;
1127 case 2: *bits = 7; break;
1128 case 3: *bits = 8; break;
1129 }
1130 /* Set DLAB in LCR to Access DLL and DLH */
1131 UART_SET_DLAB(uart);
1132
1133 dll = UART_GET_DLL(uart);
1134 dlh = UART_GET_DLH(uart);
1135
1136 /* Clear DLAB in LCR to Access THR RBR IER */
1137 UART_CLEAR_DLAB(uart);
1138
1139 *baud = get_sclk() / (16*(dll | dlh << 8));
1140 }
1141 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
1142 }
1143
1144 static struct uart_driver bfin_serial_reg;
1145
1146 static int __init
1147 bfin_serial_console_setup(struct console *co, char *options)
1148 {
1149 struct bfin_serial_port *uart;
1150 int baud = 57600;
1151 int bits = 8;
1152 int parity = 'n';
1153 # if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1154 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1155 int flow = 'r';
1156 # else
1157 int flow = 'n';
1158 # endif
1159
1160 /*
1161 * Check whether an invalid uart number has been specified, and
1162 * if so, search for the first available port that does have
1163 * console support.
1164 */
1165 if (co->index == -1 || co->index >= nr_active_ports)
1166 co->index = 0;
1167 uart = &bfin_serial_ports[co->index];
1168
1169 if (options)
1170 uart_parse_options(options, &baud, &parity, &bits, &flow);
1171 else
1172 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1173
1174 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
1175 }
1176 #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1177 defined (CONFIG_EARLY_PRINTK) */
1178
1179 #ifdef CONFIG_SERIAL_BFIN_CONSOLE
1180 static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1181 {
1182 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1183 while (!(UART_GET_LSR(uart) & THRE))
1184 barrier();
1185 UART_PUT_CHAR(uart, ch);
1186 SSYNC();
1187 }
1188
1189 /*
1190 * Interrupts are disabled on entering
1191 */
1192 static void
1193 bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1194 {
1195 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
1196 unsigned long flags;
1197
1198 spin_lock_irqsave(&uart->port.lock, flags);
1199 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1200 spin_unlock_irqrestore(&uart->port.lock, flags);
1201
1202 }
1203
1204 static struct console bfin_serial_console = {
1205 .name = BFIN_SERIAL_NAME,
1206 .write = bfin_serial_console_write,
1207 .device = uart_console_device,
1208 .setup = bfin_serial_console_setup,
1209 .flags = CON_PRINTBUFFER,
1210 .index = -1,
1211 .data = &bfin_serial_reg,
1212 };
1213
1214 static int __init bfin_serial_rs_console_init(void)
1215 {
1216 bfin_serial_init_ports();
1217 register_console(&bfin_serial_console);
1218
1219 return 0;
1220 }
1221 console_initcall(bfin_serial_rs_console_init);
1222
1223 #define BFIN_SERIAL_CONSOLE &bfin_serial_console
1224 #else
1225 #define BFIN_SERIAL_CONSOLE NULL
1226 #endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1227
1228
1229 #ifdef CONFIG_EARLY_PRINTK
1230 static __init void early_serial_putc(struct uart_port *port, int ch)
1231 {
1232 unsigned timeout = 0xffff;
1233 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1234
1235 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1236 cpu_relax();
1237 UART_PUT_CHAR(uart, ch);
1238 }
1239
1240 static __init void early_serial_write(struct console *con, const char *s,
1241 unsigned int n)
1242 {
1243 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1244 unsigned int i;
1245
1246 for (i = 0; i < n; i++, s++) {
1247 if (*s == '\n')
1248 early_serial_putc(&uart->port, '\r');
1249 early_serial_putc(&uart->port, *s);
1250 }
1251 }
1252
1253 static struct __initdata console bfin_early_serial_console = {
1254 .name = "early_BFuart",
1255 .write = early_serial_write,
1256 .device = uart_console_device,
1257 .flags = CON_PRINTBUFFER,
1258 .setup = bfin_serial_console_setup,
1259 .index = -1,
1260 .data = &bfin_serial_reg,
1261 };
1262
1263 struct console __init *bfin_earlyserial_init(unsigned int port,
1264 unsigned int cflag)
1265 {
1266 struct bfin_serial_port *uart;
1267 struct ktermios t;
1268
1269 if (port == -1 || port >= nr_active_ports)
1270 port = 0;
1271 bfin_serial_init_ports();
1272 bfin_early_serial_console.index = port;
1273 uart = &bfin_serial_ports[port];
1274 t.c_cflag = cflag;
1275 t.c_iflag = 0;
1276 t.c_oflag = 0;
1277 t.c_lflag = ICANON;
1278 t.c_line = port;
1279 bfin_serial_set_termios(&uart->port, &t, &t);
1280 return &bfin_early_serial_console;
1281 }
1282
1283 #endif /* CONFIG_EARLY_PRINTK */
1284
1285 static struct uart_driver bfin_serial_reg = {
1286 .owner = THIS_MODULE,
1287 .driver_name = "bfin-uart",
1288 .dev_name = BFIN_SERIAL_NAME,
1289 .major = BFIN_SERIAL_MAJOR,
1290 .minor = BFIN_SERIAL_MINOR,
1291 .nr = BFIN_UART_NR_PORTS,
1292 .cons = BFIN_SERIAL_CONSOLE,
1293 };
1294
1295 static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1296 {
1297 int i;
1298
1299 for (i = 0; i < nr_active_ports; i++) {
1300 if (bfin_serial_ports[i].port.dev != &dev->dev)
1301 continue;
1302 uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1303 }
1304
1305 return 0;
1306 }
1307
1308 static int bfin_serial_resume(struct platform_device *dev)
1309 {
1310 int i;
1311
1312 for (i = 0; i < nr_active_ports; i++) {
1313 if (bfin_serial_ports[i].port.dev != &dev->dev)
1314 continue;
1315 uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1316 }
1317
1318 return 0;
1319 }
1320
1321 static int bfin_serial_probe(struct platform_device *dev)
1322 {
1323 struct resource *res = dev->resource;
1324 int i;
1325
1326 for (i = 0; i < dev->num_resources; i++, res++)
1327 if (res->flags & IORESOURCE_MEM)
1328 break;
1329
1330 if (i < dev->num_resources) {
1331 for (i = 0; i < nr_active_ports; i++, res++) {
1332 if (bfin_serial_ports[i].port.mapbase != res->start)
1333 continue;
1334 bfin_serial_ports[i].port.dev = &dev->dev;
1335 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1336 }
1337 }
1338
1339 return 0;
1340 }
1341
1342 static int bfin_serial_remove(struct platform_device *dev)
1343 {
1344 int i;
1345
1346 for (i = 0; i < nr_active_ports; i++) {
1347 if (bfin_serial_ports[i].port.dev != &dev->dev)
1348 continue;
1349 uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1350 bfin_serial_ports[i].port.dev = NULL;
1351 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1352 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1353 gpio_free(bfin_serial_ports[i].cts_pin);
1354 gpio_free(bfin_serial_ports[i].rts_pin);
1355 #endif
1356 }
1357
1358 return 0;
1359 }
1360
1361 static struct platform_driver bfin_serial_driver = {
1362 .probe = bfin_serial_probe,
1363 .remove = bfin_serial_remove,
1364 .suspend = bfin_serial_suspend,
1365 .resume = bfin_serial_resume,
1366 .driver = {
1367 .name = "bfin-uart",
1368 .owner = THIS_MODULE,
1369 },
1370 };
1371
1372 static int __init bfin_serial_init(void)
1373 {
1374 int ret;
1375
1376 pr_info("Serial: Blackfin serial driver\n");
1377
1378 bfin_serial_init_ports();
1379
1380 ret = uart_register_driver(&bfin_serial_reg);
1381 if (ret == 0) {
1382 ret = platform_driver_register(&bfin_serial_driver);
1383 if (ret) {
1384 pr_debug("uart register failed\n");
1385 uart_unregister_driver(&bfin_serial_reg);
1386 }
1387 }
1388 return ret;
1389 }
1390
1391 static void __exit bfin_serial_exit(void)
1392 {
1393 platform_driver_unregister(&bfin_serial_driver);
1394 uart_unregister_driver(&bfin_serial_reg);
1395 }
1396
1397
1398 module_init(bfin_serial_init);
1399 module_exit(bfin_serial_exit);
1400
1401 MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1402 MODULE_DESCRIPTION("Blackfin generic serial port driver");
1403 MODULE_LICENSE("GPL");
1404 MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
1405 MODULE_ALIAS("platform:bfin-uart");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree