2 * This file is provided under a dual BSD/GPLv2 license. When using or
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10 * it under the terms of version 2 of the GNU General Public License as
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59 #include "scu_event_codes.h"
60 #include "probe_roms.h"
62 /* Maximum arbitration wait time in micro-seconds */
63 #define SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME (700)
65 enum sas_linkrate
sci_phy_linkrate(struct isci_phy
*iphy
)
67 return iphy
->max_negotiated_speed
;
71 * *****************************************************************************
72 * * SCIC SDS PHY Internal Methods
73 * ***************************************************************************** */
76 * This method will initialize the phy transport layer registers
78 * @transport_layer_registers
82 static enum sci_status
scic_sds_phy_transport_layer_initialization(
83 struct isci_phy
*iphy
,
84 struct scu_transport_layer_registers __iomem
*transport_layer_registers
)
88 iphy
->transport_layer_registers
= transport_layer_registers
;
90 writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX
,
91 &iphy
->transport_layer_registers
->stp_rni
);
94 * Hardware team recommends that we enable the STP prefetch for all
97 tl_control
= readl(&iphy
->transport_layer_registers
->control
);
98 tl_control
|= SCU_TLCR_GEN_BIT(STP_WRITE_DATA_PREFETCH
);
99 writel(tl_control
, &iphy
->transport_layer_registers
->control
);
105 * This method will initialize the phy link layer registers
107 * @link_layer_registers:
111 static enum sci_status
112 scic_sds_phy_link_layer_initialization(struct isci_phy
*iphy
,
113 struct scu_link_layer_registers __iomem
*link_layer_registers
)
115 struct scic_sds_controller
*scic
=
116 iphy
->owning_port
->owning_controller
;
117 int phy_idx
= iphy
->phy_index
;
118 struct sci_phy_user_params
*phy_user
=
119 &scic
->user_parameters
.sds1
.phys
[phy_idx
];
120 struct sci_phy_oem_params
*phy_oem
=
121 &scic
->oem_parameters
.sds1
.phys
[phy_idx
];
122 u32 phy_configuration
;
123 struct scic_phy_cap phy_cap
;
124 u32 parity_check
= 0;
125 u32 parity_count
= 0;
126 u32 llctl
, link_rate
;
129 iphy
->link_layer_registers
= link_layer_registers
;
131 /* Set our IDENTIFY frame data */
132 #define SCI_END_DEVICE 0x01
134 writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR
) |
135 SCU_SAS_TIID_GEN_BIT(SSP_INITIATOR
) |
136 SCU_SAS_TIID_GEN_BIT(STP_INITIATOR
) |
137 SCU_SAS_TIID_GEN_BIT(DA_SATA_HOST
) |
138 SCU_SAS_TIID_GEN_VAL(DEVICE_TYPE
, SCI_END_DEVICE
),
139 &iphy
->link_layer_registers
->transmit_identification
);
141 /* Write the device SAS Address */
143 &iphy
->link_layer_registers
->sas_device_name_high
);
144 writel(phy_idx
, &iphy
->link_layer_registers
->sas_device_name_low
);
146 /* Write the source SAS Address */
147 writel(phy_oem
->sas_address
.high
,
148 &iphy
->link_layer_registers
->source_sas_address_high
);
149 writel(phy_oem
->sas_address
.low
,
150 &iphy
->link_layer_registers
->source_sas_address_low
);
152 /* Clear and Set the PHY Identifier */
153 writel(0, &iphy
->link_layer_registers
->identify_frame_phy_id
);
154 writel(SCU_SAS_TIPID_GEN_VALUE(ID
, phy_idx
),
155 &iphy
->link_layer_registers
->identify_frame_phy_id
);
157 /* Change the initial state of the phy configuration register */
159 readl(&iphy
->link_layer_registers
->phy_configuration
);
161 /* Hold OOB state machine in reset */
162 phy_configuration
|= SCU_SAS_PCFG_GEN_BIT(OOB_RESET
);
163 writel(phy_configuration
,
164 &iphy
->link_layer_registers
->phy_configuration
);
166 /* Configure the SNW capabilities */
169 phy_cap
.gen3_no_ssc
= 1;
170 phy_cap
.gen2_no_ssc
= 1;
171 phy_cap
.gen1_no_ssc
= 1;
172 if (scic
->oem_parameters
.sds1
.controller
.do_enable_ssc
== true) {
173 phy_cap
.gen3_ssc
= 1;
174 phy_cap
.gen2_ssc
= 1;
175 phy_cap
.gen1_ssc
= 1;
179 * The SAS specification indicates that the phy_capabilities that
180 * are transmitted shall have an even parity. Calculate the parity. */
181 parity_check
= phy_cap
.all
;
182 while (parity_check
!= 0) {
183 if (parity_check
& 0x1)
189 * If parity indicates there are an odd number of bits set, then
190 * set the parity bit to 1 in the phy capabilities. */
191 if ((parity_count
% 2) != 0)
194 writel(phy_cap
.all
, &iphy
->link_layer_registers
->phy_capabilities
);
196 /* Set the enable spinup period but disable the ability to send
197 * notify enable spinup
199 writel(SCU_ENSPINUP_GEN_VAL(COUNT
,
200 phy_user
->notify_enable_spin_up_insertion_frequency
),
201 &iphy
->link_layer_registers
->notify_enable_spinup_control
);
203 /* Write the ALIGN Insertion Ferequency for connected phy and
204 * inpendent of connected state
206 clksm_value
= SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(CONNECTED
,
207 phy_user
->in_connection_align_insertion_frequency
);
209 clksm_value
|= SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(GENERAL
,
210 phy_user
->align_insertion_frequency
);
212 writel(clksm_value
, &iphy
->link_layer_registers
->clock_skew_management
);
214 /* @todo Provide a way to write this register correctly */
216 &iphy
->link_layer_registers
->afe_lookup_table_control
);
218 llctl
= SCU_SAS_LLCTL_GEN_VAL(NO_OUTBOUND_TASK_TIMEOUT
,
219 (u8
)scic
->user_parameters
.sds1
.no_outbound_task_timeout
);
221 switch(phy_user
->max_speed_generation
) {
222 case SCIC_SDS_PARM_GEN3_SPEED
:
223 link_rate
= SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3
;
225 case SCIC_SDS_PARM_GEN2_SPEED
:
226 link_rate
= SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2
;
229 link_rate
= SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1
;
232 llctl
|= SCU_SAS_LLCTL_GEN_VAL(MAX_LINK_RATE
, link_rate
);
233 writel(llctl
, &iphy
->link_layer_registers
->link_layer_control
);
235 if (is_a0() || is_a2()) {
236 /* Program the max ARB time for the PHY to 700us so we inter-operate with
237 * the PMC expander which shuts down PHYs if the expander PHY generates too
238 * many breaks. This time value will guarantee that the initiator PHY will
239 * generate the break.
241 writel(SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME
,
242 &iphy
->link_layer_registers
->maximum_arbitration_wait_timer_timeout
);
245 /* Disable link layer hang detection, rely on the OS timeout for I/O timeouts. */
246 writel(0, &iphy
->link_layer_registers
->link_layer_hang_detection_timeout
);
248 /* We can exit the initial state to the stopped state */
249 sci_change_state(&iphy
->sm
, SCI_PHY_STOPPED
);
254 static void phy_sata_timeout(unsigned long data
)
256 struct sci_timer
*tmr
= (struct sci_timer
*)data
;
257 struct isci_phy
*iphy
= container_of(tmr
, typeof(*iphy
), sata_timer
);
258 struct isci_host
*ihost
= scic_to_ihost(iphy
->owning_port
->owning_controller
);
261 spin_lock_irqsave(&ihost
->scic_lock
, flags
);
266 dev_dbg(sciphy_to_dev(iphy
),
267 "%s: SCIC SDS Phy 0x%p did not receive signature fis before "
272 sci_change_state(&iphy
->sm
, SCI_PHY_STARTING
);
274 spin_unlock_irqrestore(&ihost
->scic_lock
, flags
);
278 * This method returns the port currently containing this phy. If the phy is
279 * currently contained by the dummy port, then the phy is considered to not
281 * @sci_phy: This parameter specifies the phy for which to retrieve the
284 * This method returns a handle to a port that contains the supplied phy.
285 * NULL This value is returned if the phy is not part of a real
286 * port (i.e. it's contained in the dummy port). !NULL All other
287 * values indicate a handle/pointer to the port containing the phy.
289 struct scic_sds_port
*phy_get_non_dummy_port(
290 struct isci_phy
*iphy
)
292 if (scic_sds_port_get_index(iphy
->owning_port
) == SCIC_SDS_DUMMY_PORT
)
295 return iphy
->owning_port
;
299 * This method will assign a port to the phy object.
300 * @out]: iphy This parameter specifies the phy for which to assign a port
305 void scic_sds_phy_set_port(
306 struct isci_phy
*iphy
,
307 struct scic_sds_port
*sci_port
)
309 iphy
->owning_port
= sci_port
;
311 if (iphy
->bcn_received_while_port_unassigned
) {
312 iphy
->bcn_received_while_port_unassigned
= false;
313 scic_sds_port_broadcast_change_received(iphy
->owning_port
, iphy
);
318 * This method will initialize the constructed phy
320 * @link_layer_registers:
324 enum sci_status
scic_sds_phy_initialize(
325 struct isci_phy
*iphy
,
326 struct scu_transport_layer_registers __iomem
*transport_layer_registers
,
327 struct scu_link_layer_registers __iomem
*link_layer_registers
)
329 /* Perfrom the initialization of the TL hardware */
330 scic_sds_phy_transport_layer_initialization(
332 transport_layer_registers
);
334 /* Perofrm the initialization of the PE hardware */
335 scic_sds_phy_link_layer_initialization(iphy
, link_layer_registers
);
338 * There is nothing that needs to be done in this state just
339 * transition to the stopped state. */
340 sci_change_state(&iphy
->sm
, SCI_PHY_STOPPED
);
346 * This method assigns the direct attached device ID for this phy.
348 * @iphy The phy for which the direct attached device id is to
350 * @device_id The direct attached device ID to assign to the phy.
351 * This will either be the RNi for the device or an invalid RNi if there
352 * is no current device assigned to the phy.
354 void scic_sds_phy_setup_transport(
355 struct isci_phy
*iphy
,
360 writel(device_id
, &iphy
->transport_layer_registers
->stp_rni
);
363 * The read should guarantee that the first write gets posted
364 * before the next write
366 tl_control
= readl(&iphy
->transport_layer_registers
->control
);
367 tl_control
|= SCU_TLCR_GEN_BIT(CLEAR_TCI_NCQ_MAPPING_TABLE
);
368 writel(tl_control
, &iphy
->transport_layer_registers
->control
);
373 * @sci_phy: The phy object to be suspended.
375 * This function will perform the register reads/writes to suspend the SCU
376 * hardware protocol engine. none
378 static void scic_sds_phy_suspend(
379 struct isci_phy
*iphy
)
381 u32 scu_sas_pcfg_value
;
384 readl(&iphy
->link_layer_registers
->phy_configuration
);
385 scu_sas_pcfg_value
|= SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE
);
386 writel(scu_sas_pcfg_value
,
387 &iphy
->link_layer_registers
->phy_configuration
);
389 scic_sds_phy_setup_transport(
391 SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX
);
394 void scic_sds_phy_resume(struct isci_phy
*iphy
)
396 u32 scu_sas_pcfg_value
;
399 readl(&iphy
->link_layer_registers
->phy_configuration
);
400 scu_sas_pcfg_value
&= ~SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE
);
401 writel(scu_sas_pcfg_value
,
402 &iphy
->link_layer_registers
->phy_configuration
);
405 void scic_sds_phy_get_sas_address(struct isci_phy
*iphy
,
406 struct sci_sas_address
*sas_address
)
408 sas_address
->high
= readl(&iphy
->link_layer_registers
->source_sas_address_high
);
409 sas_address
->low
= readl(&iphy
->link_layer_registers
->source_sas_address_low
);
412 void scic_sds_phy_get_attached_sas_address(struct isci_phy
*iphy
,
413 struct sci_sas_address
*sas_address
)
415 struct sas_identify_frame
*iaf
;
417 iaf
= &iphy
->frame_rcvd
.iaf
;
418 memcpy(sas_address
, iaf
->sas_addr
, SAS_ADDR_SIZE
);
421 void scic_sds_phy_get_protocols(struct isci_phy
*iphy
,
422 struct scic_phy_proto
*protocols
)
426 link_layer_registers
->transmit_identification
) &
430 enum sci_status
scic_sds_phy_start(struct isci_phy
*iphy
)
432 enum scic_sds_phy_states state
= iphy
->sm
.current_state_id
;
434 if (state
!= SCI_PHY_STOPPED
) {
435 dev_dbg(sciphy_to_dev(iphy
),
436 "%s: in wrong state: %d\n", __func__
, state
);
437 return SCI_FAILURE_INVALID_STATE
;
440 sci_change_state(&iphy
->sm
, SCI_PHY_STARTING
);
444 enum sci_status
scic_sds_phy_stop(struct isci_phy
*iphy
)
446 enum scic_sds_phy_states state
= iphy
->sm
.current_state_id
;
449 case SCI_PHY_SUB_INITIAL
:
450 case SCI_PHY_SUB_AWAIT_OSSP_EN
:
451 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN
:
452 case SCI_PHY_SUB_AWAIT_SAS_POWER
:
453 case SCI_PHY_SUB_AWAIT_SATA_POWER
:
454 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN
:
455 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN
:
456 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF
:
457 case SCI_PHY_SUB_FINAL
:
461 dev_dbg(sciphy_to_dev(iphy
),
462 "%s: in wrong state: %d\n", __func__
, state
);
463 return SCI_FAILURE_INVALID_STATE
;
466 sci_change_state(&iphy
->sm
, SCI_PHY_STOPPED
);
470 enum sci_status
scic_sds_phy_reset(struct isci_phy
*iphy
)
472 enum scic_sds_phy_states state
= iphy
->sm
.current_state_id
;
474 if (state
!= SCI_PHY_READY
) {
475 dev_dbg(sciphy_to_dev(iphy
),
476 "%s: in wrong state: %d\n", __func__
, state
);
477 return SCI_FAILURE_INVALID_STATE
;
480 sci_change_state(&iphy
->sm
, SCI_PHY_RESETTING
);
484 enum sci_status
scic_sds_phy_consume_power_handler(struct isci_phy
*iphy
)
486 enum scic_sds_phy_states state
= iphy
->sm
.current_state_id
;
489 case SCI_PHY_SUB_AWAIT_SAS_POWER
: {
492 enable_spinup
= readl(&iphy
->link_layer_registers
->notify_enable_spinup_control
);
493 enable_spinup
|= SCU_ENSPINUP_GEN_BIT(ENABLE
);
494 writel(enable_spinup
, &iphy
->link_layer_registers
->notify_enable_spinup_control
);
496 /* Change state to the final state this substate machine has run to completion */
497 sci_change_state(&iphy
->sm
, SCI_PHY_SUB_FINAL
);
501 case SCI_PHY_SUB_AWAIT_SATA_POWER
: {
502 u32 scu_sas_pcfg_value
;
504 /* Release the spinup hold state and reset the OOB state machine */
506 readl(&iphy
->link_layer_registers
->phy_configuration
);
507 scu_sas_pcfg_value
&=
508 ~(SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD
) | SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE
));
509 scu_sas_pcfg_value
|= SCU_SAS_PCFG_GEN_BIT(OOB_RESET
);
510 writel(scu_sas_pcfg_value
,
511 &iphy
->link_layer_registers
->phy_configuration
);
513 /* Now restart the OOB operation */
514 scu_sas_pcfg_value
&= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET
);
515 scu_sas_pcfg_value
|= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE
);
516 writel(scu_sas_pcfg_value
,
517 &iphy
->link_layer_registers
->phy_configuration
);
519 /* Change state to the final state this substate machine has run to completion */
520 sci_change_state(&iphy
->sm
, SCI_PHY_SUB_AWAIT_SATA_PHY_EN
);
525 dev_dbg(sciphy_to_dev(iphy
),
526 "%s: in wrong state: %d\n", __func__
, state
);
527 return SCI_FAILURE_INVALID_STATE
;
532 * *****************************************************************************
533 * * SCIC SDS PHY HELPER FUNCTIONS
534 * ***************************************************************************** */
539 * @sci_phy: The phy object that received SAS PHY DETECTED.
541 * This method continues the link training for the phy as if it were a SAS PHY
542 * instead of a SATA PHY. This is done because the completion queue had a SAS
543 * PHY DETECTED event when the state machine was expecting a SATA PHY event.
546 static void scic_sds_phy_start_sas_link_training(
547 struct isci_phy
*iphy
)
552 readl(&iphy
->link_layer_registers
->phy_configuration
);
553 phy_control
|= SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD
);
555 &iphy
->link_layer_registers
->phy_configuration
);
557 sci_change_state(&iphy
->sm
, SCI_PHY_SUB_AWAIT_SAS_SPEED_EN
);
559 iphy
->protocol
= SCIC_SDS_PHY_PROTOCOL_SAS
;
564 * @sci_phy: The phy object that received a SATA SPINUP HOLD event
566 * This method continues the link training for the phy as if it were a SATA PHY
567 * instead of a SAS PHY. This is done because the completion queue had a SATA
568 * SPINUP HOLD event when the state machine was expecting a SAS PHY event. none
570 static void scic_sds_phy_start_sata_link_training(
571 struct isci_phy
*iphy
)
573 sci_change_state(&iphy
->sm
, SCI_PHY_SUB_AWAIT_SATA_POWER
);
575 iphy
->protocol
= SCIC_SDS_PHY_PROTOCOL_SATA
;
579 * scic_sds_phy_complete_link_training - perform processing common to
580 * all protocols upon completion of link training.
581 * @sci_phy: This parameter specifies the phy object for which link training
583 * @max_link_rate: This parameter specifies the maximum link rate to be
584 * associated with this phy.
585 * @next_state: This parameter specifies the next state for the phy's starting
589 static void scic_sds_phy_complete_link_training(
590 struct isci_phy
*iphy
,
591 enum sas_linkrate max_link_rate
,
594 iphy
->max_negotiated_speed
= max_link_rate
;
596 sci_change_state(&iphy
->sm
, next_state
);
599 enum sci_status
scic_sds_phy_event_handler(struct isci_phy
*iphy
,
602 enum scic_sds_phy_states state
= iphy
->sm
.current_state_id
;
605 case SCI_PHY_SUB_AWAIT_OSSP_EN
:
606 switch (scu_get_event_code(event_code
)) {
607 case SCU_EVENT_SAS_PHY_DETECTED
:
608 scic_sds_phy_start_sas_link_training(iphy
);
609 iphy
->is_in_link_training
= true;
611 case SCU_EVENT_SATA_SPINUP_HOLD
:
612 scic_sds_phy_start_sata_link_training(iphy
);
613 iphy
->is_in_link_training
= true;
616 dev_dbg(sciphy_to_dev(iphy
),
617 "%s: PHY starting substate machine received "
618 "unexpected event_code %x\n",
624 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN
:
625 switch (scu_get_event_code(event_code
)) {
626 case SCU_EVENT_SAS_PHY_DETECTED
:
628 * Why is this being reported again by the controller?
629 * We would re-enter this state so just stay here */
631 case SCU_EVENT_SAS_15
:
632 case SCU_EVENT_SAS_15_SSC
:
633 scic_sds_phy_complete_link_training(
635 SAS_LINK_RATE_1_5_GBPS
,
636 SCI_PHY_SUB_AWAIT_IAF_UF
);
638 case SCU_EVENT_SAS_30
:
639 case SCU_EVENT_SAS_30_SSC
:
640 scic_sds_phy_complete_link_training(
642 SAS_LINK_RATE_3_0_GBPS
,
643 SCI_PHY_SUB_AWAIT_IAF_UF
);
645 case SCU_EVENT_SAS_60
:
646 case SCU_EVENT_SAS_60_SSC
:
647 scic_sds_phy_complete_link_training(
649 SAS_LINK_RATE_6_0_GBPS
,
650 SCI_PHY_SUB_AWAIT_IAF_UF
);
652 case SCU_EVENT_SATA_SPINUP_HOLD
:
654 * We were doing SAS PHY link training and received a SATA PHY event
655 * continue OOB/SN as if this were a SATA PHY */
656 scic_sds_phy_start_sata_link_training(iphy
);
658 case SCU_EVENT_LINK_FAILURE
:
659 /* Link failure change state back to the starting state */
660 sci_change_state(&iphy
->sm
, SCI_PHY_STARTING
);
663 dev_warn(sciphy_to_dev(iphy
),
664 "%s: PHY starting substate machine received "
665 "unexpected event_code %x\n",
666 __func__
, event_code
);
672 case SCI_PHY_SUB_AWAIT_IAF_UF
:
673 switch (scu_get_event_code(event_code
)) {
674 case SCU_EVENT_SAS_PHY_DETECTED
:
675 /* Backup the state machine */
676 scic_sds_phy_start_sas_link_training(iphy
);
678 case SCU_EVENT_SATA_SPINUP_HOLD
:
679 /* We were doing SAS PHY link training and received a
680 * SATA PHY event continue OOB/SN as if this were a
683 scic_sds_phy_start_sata_link_training(iphy
);
685 case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT
:
686 case SCU_EVENT_LINK_FAILURE
:
687 case SCU_EVENT_HARD_RESET_RECEIVED
:
688 /* Start the oob/sn state machine over again */
689 sci_change_state(&iphy
->sm
, SCI_PHY_STARTING
);
692 dev_warn(sciphy_to_dev(iphy
),
693 "%s: PHY starting substate machine received "
694 "unexpected event_code %x\n",
695 __func__
, event_code
);
699 case SCI_PHY_SUB_AWAIT_SAS_POWER
:
700 switch (scu_get_event_code(event_code
)) {
701 case SCU_EVENT_LINK_FAILURE
:
702 /* Link failure change state back to the starting state */
703 sci_change_state(&iphy
->sm
, SCI_PHY_STARTING
);
706 dev_warn(sciphy_to_dev(iphy
),
707 "%s: PHY starting substate machine received unexpected "
714 case SCI_PHY_SUB_AWAIT_SATA_POWER
:
715 switch (scu_get_event_code(event_code
)) {
716 case SCU_EVENT_LINK_FAILURE
:
717 /* Link failure change state back to the starting state */
718 sci_change_state(&iphy
->sm
, SCI_PHY_STARTING
);
720 case SCU_EVENT_SATA_SPINUP_HOLD
:
721 /* These events are received every 10ms and are
722 * expected while in this state
726 case SCU_EVENT_SAS_PHY_DETECTED
:
727 /* There has been a change in the phy type before OOB/SN for the
728 * SATA finished start down the SAS link traning path.
730 scic_sds_phy_start_sas_link_training(iphy
);
734 dev_warn(sciphy_to_dev(iphy
),
735 "%s: PHY starting substate machine received "
736 "unexpected event_code %x\n",
737 __func__
, event_code
);
742 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN
:
743 switch (scu_get_event_code(event_code
)) {
744 case SCU_EVENT_LINK_FAILURE
:
745 /* Link failure change state back to the starting state */
746 sci_change_state(&iphy
->sm
, SCI_PHY_STARTING
);
748 case SCU_EVENT_SATA_SPINUP_HOLD
:
749 /* These events might be received since we dont know how many may be in
750 * the completion queue while waiting for power
753 case SCU_EVENT_SATA_PHY_DETECTED
:
754 iphy
->protocol
= SCIC_SDS_PHY_PROTOCOL_SATA
;
756 /* We have received the SATA PHY notification change state */
757 sci_change_state(&iphy
->sm
, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN
);
759 case SCU_EVENT_SAS_PHY_DETECTED
:
760 /* There has been a change in the phy type before OOB/SN for the
761 * SATA finished start down the SAS link traning path.
763 scic_sds_phy_start_sas_link_training(iphy
);
766 dev_warn(sciphy_to_dev(iphy
),
767 "%s: PHY starting substate machine received "
768 "unexpected event_code %x\n",
775 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN
:
776 switch (scu_get_event_code(event_code
)) {
777 case SCU_EVENT_SATA_PHY_DETECTED
:
779 * The hardware reports multiple SATA PHY detected events
780 * ignore the extras */
782 case SCU_EVENT_SATA_15
:
783 case SCU_EVENT_SATA_15_SSC
:
784 scic_sds_phy_complete_link_training(
786 SAS_LINK_RATE_1_5_GBPS
,
787 SCI_PHY_SUB_AWAIT_SIG_FIS_UF
);
789 case SCU_EVENT_SATA_30
:
790 case SCU_EVENT_SATA_30_SSC
:
791 scic_sds_phy_complete_link_training(
793 SAS_LINK_RATE_3_0_GBPS
,
794 SCI_PHY_SUB_AWAIT_SIG_FIS_UF
);
796 case SCU_EVENT_SATA_60
:
797 case SCU_EVENT_SATA_60_SSC
:
798 scic_sds_phy_complete_link_training(
800 SAS_LINK_RATE_6_0_GBPS
,
801 SCI_PHY_SUB_AWAIT_SIG_FIS_UF
);
803 case SCU_EVENT_LINK_FAILURE
:
804 /* Link failure change state back to the starting state */
805 sci_change_state(&iphy
->sm
, SCI_PHY_STARTING
);
807 case SCU_EVENT_SAS_PHY_DETECTED
:
809 * There has been a change in the phy type before OOB/SN for the
810 * SATA finished start down the SAS link traning path. */
811 scic_sds_phy_start_sas_link_training(iphy
);
814 dev_warn(sciphy_to_dev(iphy
),
815 "%s: PHY starting substate machine received "
816 "unexpected event_code %x\n",
817 __func__
, event_code
);
823 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF
:
824 switch (scu_get_event_code(event_code
)) {
825 case SCU_EVENT_SATA_PHY_DETECTED
:
826 /* Backup the state machine */
827 sci_change_state(&iphy
->sm
, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN
);
830 case SCU_EVENT_LINK_FAILURE
:
831 /* Link failure change state back to the starting state */
832 sci_change_state(&iphy
->sm
, SCI_PHY_STARTING
);
836 dev_warn(sciphy_to_dev(iphy
),
837 "%s: PHY starting substate machine received "
838 "unexpected event_code %x\n",
846 switch (scu_get_event_code(event_code
)) {
847 case SCU_EVENT_LINK_FAILURE
:
848 /* Link failure change state back to the starting state */
849 sci_change_state(&iphy
->sm
, SCI_PHY_STARTING
);
851 case SCU_EVENT_BROADCAST_CHANGE
:
852 /* Broadcast change received. Notify the port. */
853 if (phy_get_non_dummy_port(iphy
) != NULL
)
854 scic_sds_port_broadcast_change_received(iphy
->owning_port
, iphy
);
856 iphy
->bcn_received_while_port_unassigned
= true;
859 dev_warn(sciphy_to_dev(iphy
),
860 "%sP SCIC PHY 0x%p ready state machine received "
861 "unexpected event_code %x\n",
862 __func__
, iphy
, event_code
);
863 return SCI_FAILURE_INVALID_STATE
;
866 case SCI_PHY_RESETTING
:
867 switch (scu_get_event_code(event_code
)) {
868 case SCU_EVENT_HARD_RESET_TRANSMITTED
:
869 /* Link failure change state back to the starting state */
870 sci_change_state(&iphy
->sm
, SCI_PHY_STARTING
);
873 dev_warn(sciphy_to_dev(iphy
),
874 "%s: SCIC PHY 0x%p resetting state machine received "
875 "unexpected event_code %x\n",
876 __func__
, iphy
, event_code
);
878 return SCI_FAILURE_INVALID_STATE
;
883 dev_dbg(sciphy_to_dev(iphy
),
884 "%s: in wrong state: %d\n", __func__
, state
);
885 return SCI_FAILURE_INVALID_STATE
;
889 enum sci_status
scic_sds_phy_frame_handler(struct isci_phy
*iphy
,
892 enum scic_sds_phy_states state
= iphy
->sm
.current_state_id
;
893 struct scic_sds_controller
*scic
= iphy
->owning_port
->owning_controller
;
894 enum sci_status result
;
898 case SCI_PHY_SUB_AWAIT_IAF_UF
: {
900 struct sas_identify_frame iaf
;
902 result
= scic_sds_unsolicited_frame_control_get_header(&scic
->uf_control
,
904 (void **)&frame_words
);
906 if (result
!= SCI_SUCCESS
)
909 sci_swab32_cpy(&iaf
, frame_words
, sizeof(iaf
) / sizeof(u32
));
910 if (iaf
.frame_type
== 0) {
913 spin_lock_irqsave(&iphy
->sas_phy
.frame_rcvd_lock
, flags
);
914 memcpy(&iphy
->frame_rcvd
.iaf
, &iaf
, sizeof(iaf
));
915 spin_unlock_irqrestore(&iphy
->sas_phy
.frame_rcvd_lock
, flags
);
917 /* We got the IAF for an expander PHY go to the final
918 * state since there are no power requirements for
921 state
= SCI_PHY_SUB_FINAL
;
923 /* We got the IAF we can now go to the await spinup
926 state
= SCI_PHY_SUB_AWAIT_SAS_POWER
;
928 sci_change_state(&iphy
->sm
, state
);
929 result
= SCI_SUCCESS
;
931 dev_warn(sciphy_to_dev(iphy
),
932 "%s: PHY starting substate machine received "
933 "unexpected frame id %x\n",
934 __func__
, frame_index
);
936 scic_sds_controller_release_frame(scic
, frame_index
);
939 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF
: {
940 struct dev_to_host_fis
*frame_header
;
943 result
= scic_sds_unsolicited_frame_control_get_header(
944 &(scic_sds_phy_get_controller(iphy
)->uf_control
),
946 (void **)&frame_header
);
948 if (result
!= SCI_SUCCESS
)
951 if ((frame_header
->fis_type
== FIS_REGD2H
) &&
952 !(frame_header
->status
& ATA_BUSY
)) {
953 scic_sds_unsolicited_frame_control_get_buffer(&scic
->uf_control
,
955 (void **)&fis_frame_data
);
957 spin_lock_irqsave(&iphy
->sas_phy
.frame_rcvd_lock
, flags
);
958 scic_sds_controller_copy_sata_response(&iphy
->frame_rcvd
.fis
,
961 spin_unlock_irqrestore(&iphy
->sas_phy
.frame_rcvd_lock
, flags
);
963 /* got IAF we can now go to the await spinup semaphore state */
964 sci_change_state(&iphy
->sm
, SCI_PHY_SUB_FINAL
);
966 result
= SCI_SUCCESS
;
968 dev_warn(sciphy_to_dev(iphy
),
969 "%s: PHY starting substate machine received "
970 "unexpected frame id %x\n",
971 __func__
, frame_index
);
973 /* Regardless of the result we are done with this frame with it */
974 scic_sds_controller_release_frame(scic
, frame_index
);
979 dev_dbg(sciphy_to_dev(iphy
),
980 "%s: in wrong state: %d\n", __func__
, state
);
981 return SCI_FAILURE_INVALID_STATE
;
986 static void scic_sds_phy_starting_initial_substate_enter(struct sci_base_state_machine
*sm
)
988 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
990 /* This is just an temporary state go off to the starting state */
991 sci_change_state(&iphy
->sm
, SCI_PHY_SUB_AWAIT_OSSP_EN
);
994 static void scic_sds_phy_starting_await_sas_power_substate_enter(struct sci_base_state_machine
*sm
)
996 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
997 struct scic_sds_controller
*scic
= iphy
->owning_port
->owning_controller
;
999 scic_sds_controller_power_control_queue_insert(scic
, iphy
);
1002 static void scic_sds_phy_starting_await_sas_power_substate_exit(struct sci_base_state_machine
*sm
)
1004 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1005 struct scic_sds_controller
*scic
= iphy
->owning_port
->owning_controller
;
1007 scic_sds_controller_power_control_queue_remove(scic
, iphy
);
1010 static void scic_sds_phy_starting_await_sata_power_substate_enter(struct sci_base_state_machine
*sm
)
1012 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1013 struct scic_sds_controller
*scic
= iphy
->owning_port
->owning_controller
;
1015 scic_sds_controller_power_control_queue_insert(scic
, iphy
);
1018 static void scic_sds_phy_starting_await_sata_power_substate_exit(struct sci_base_state_machine
*sm
)
1020 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1021 struct scic_sds_controller
*scic
= iphy
->owning_port
->owning_controller
;
1023 scic_sds_controller_power_control_queue_remove(scic
, iphy
);
1026 static void scic_sds_phy_starting_await_sata_phy_substate_enter(struct sci_base_state_machine
*sm
)
1028 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1030 sci_mod_timer(&iphy
->sata_timer
, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT
);
1033 static void scic_sds_phy_starting_await_sata_phy_substate_exit(struct sci_base_state_machine
*sm
)
1035 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1037 sci_del_timer(&iphy
->sata_timer
);
1040 static void scic_sds_phy_starting_await_sata_speed_substate_enter(struct sci_base_state_machine
*sm
)
1042 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1044 sci_mod_timer(&iphy
->sata_timer
, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT
);
1047 static void scic_sds_phy_starting_await_sata_speed_substate_exit(struct sci_base_state_machine
*sm
)
1049 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1051 sci_del_timer(&iphy
->sata_timer
);
1054 static void scic_sds_phy_starting_await_sig_fis_uf_substate_enter(struct sci_base_state_machine
*sm
)
1056 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1058 if (scic_sds_port_link_detected(iphy
->owning_port
, iphy
)) {
1061 * Clear the PE suspend condition so we can actually
1063 * The hardware will not respond to the XRDY until the PE
1064 * suspend condition is cleared.
1066 scic_sds_phy_resume(iphy
);
1068 sci_mod_timer(&iphy
->sata_timer
,
1069 SCIC_SDS_SIGNATURE_FIS_TIMEOUT
);
1071 iphy
->is_in_link_training
= false;
1074 static void scic_sds_phy_starting_await_sig_fis_uf_substate_exit(struct sci_base_state_machine
*sm
)
1076 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1078 sci_del_timer(&iphy
->sata_timer
);
1081 static void scic_sds_phy_starting_final_substate_enter(struct sci_base_state_machine
*sm
)
1083 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1085 /* State machine has run to completion so exit out and change
1086 * the base state machine to the ready state
1088 sci_change_state(&iphy
->sm
, SCI_PHY_READY
);
1093 * @sci_phy: This is the struct isci_phy object to stop.
1095 * This method will stop the struct isci_phy object. This does not reset the
1096 * protocol engine it just suspends it and places it in a state where it will
1097 * not cause the end device to power up. none
1099 static void scu_link_layer_stop_protocol_engine(
1100 struct isci_phy
*iphy
)
1102 u32 scu_sas_pcfg_value
;
1103 u32 enable_spinup_value
;
1105 /* Suspend the protocol engine and place it in a sata spinup hold state */
1106 scu_sas_pcfg_value
=
1107 readl(&iphy
->link_layer_registers
->phy_configuration
);
1108 scu_sas_pcfg_value
|=
1109 (SCU_SAS_PCFG_GEN_BIT(OOB_RESET
) |
1110 SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE
) |
1111 SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD
));
1112 writel(scu_sas_pcfg_value
,
1113 &iphy
->link_layer_registers
->phy_configuration
);
1115 /* Disable the notify enable spinup primitives */
1116 enable_spinup_value
= readl(&iphy
->link_layer_registers
->notify_enable_spinup_control
);
1117 enable_spinup_value
&= ~SCU_ENSPINUP_GEN_BIT(ENABLE
);
1118 writel(enable_spinup_value
, &iphy
->link_layer_registers
->notify_enable_spinup_control
);
1124 * This method will start the OOB/SN state machine for this struct isci_phy object.
1126 static void scu_link_layer_start_oob(
1127 struct isci_phy
*iphy
)
1129 u32 scu_sas_pcfg_value
;
1131 scu_sas_pcfg_value
=
1132 readl(&iphy
->link_layer_registers
->phy_configuration
);
1133 scu_sas_pcfg_value
|= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE
);
1134 scu_sas_pcfg_value
&=
1135 ~(SCU_SAS_PCFG_GEN_BIT(OOB_RESET
) |
1136 SCU_SAS_PCFG_GEN_BIT(HARD_RESET
));
1137 writel(scu_sas_pcfg_value
,
1138 &iphy
->link_layer_registers
->phy_configuration
);
1144 * This method will transmit a hard reset request on the specified phy. The SCU
1145 * hardware requires that we reset the OOB state machine and set the hard reset
1146 * bit in the phy configuration register. We then must start OOB over with the
1147 * hard reset bit set.
1149 static void scu_link_layer_tx_hard_reset(
1150 struct isci_phy
*iphy
)
1152 u32 phy_configuration_value
;
1155 * SAS Phys must wait for the HARD_RESET_TX event notification to transition
1156 * to the starting state. */
1157 phy_configuration_value
=
1158 readl(&iphy
->link_layer_registers
->phy_configuration
);
1159 phy_configuration_value
|=
1160 (SCU_SAS_PCFG_GEN_BIT(HARD_RESET
) |
1161 SCU_SAS_PCFG_GEN_BIT(OOB_RESET
));
1162 writel(phy_configuration_value
,
1163 &iphy
->link_layer_registers
->phy_configuration
);
1165 /* Now take the OOB state machine out of reset */
1166 phy_configuration_value
|= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE
);
1167 phy_configuration_value
&= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET
);
1168 writel(phy_configuration_value
,
1169 &iphy
->link_layer_registers
->phy_configuration
);
1172 static void scic_sds_phy_stopped_state_enter(struct sci_base_state_machine
*sm
)
1174 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1177 * @todo We need to get to the controller to place this PE in a
1180 sci_del_timer(&iphy
->sata_timer
);
1182 scu_link_layer_stop_protocol_engine(iphy
);
1184 if (iphy
->sm
.previous_state_id
!= SCI_PHY_INITIAL
)
1185 scic_sds_controller_link_down(scic_sds_phy_get_controller(iphy
),
1186 phy_get_non_dummy_port(iphy
),
1190 static void scic_sds_phy_starting_state_enter(struct sci_base_state_machine
*sm
)
1192 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1194 scu_link_layer_stop_protocol_engine(iphy
);
1195 scu_link_layer_start_oob(iphy
);
1197 /* We don't know what kind of phy we are going to be just yet */
1198 iphy
->protocol
= SCIC_SDS_PHY_PROTOCOL_UNKNOWN
;
1199 iphy
->bcn_received_while_port_unassigned
= false;
1201 if (iphy
->sm
.previous_state_id
== SCI_PHY_READY
)
1202 scic_sds_controller_link_down(scic_sds_phy_get_controller(iphy
),
1203 phy_get_non_dummy_port(iphy
),
1206 sci_change_state(&iphy
->sm
, SCI_PHY_SUB_INITIAL
);
1209 static void scic_sds_phy_ready_state_enter(struct sci_base_state_machine
*sm
)
1211 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1213 scic_sds_controller_link_up(scic_sds_phy_get_controller(iphy
),
1214 phy_get_non_dummy_port(iphy
),
1219 static void scic_sds_phy_ready_state_exit(struct sci_base_state_machine
*sm
)
1221 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1223 scic_sds_phy_suspend(iphy
);
1226 static void scic_sds_phy_resetting_state_enter(struct sci_base_state_machine
*sm
)
1228 struct isci_phy
*iphy
= container_of(sm
, typeof(*iphy
), sm
);
1230 /* The phy is being reset, therefore deactivate it from the port. In
1231 * the resetting state we don't notify the user regarding link up and
1232 * link down notifications
1234 scic_sds_port_deactivate_phy(iphy
->owning_port
, iphy
, false);
1236 if (iphy
->protocol
== SCIC_SDS_PHY_PROTOCOL_SAS
) {
1237 scu_link_layer_tx_hard_reset(iphy
);
1239 /* The SCU does not need to have a discrete reset state so
1240 * just go back to the starting state.
1242 sci_change_state(&iphy
->sm
, SCI_PHY_STARTING
);
1246 static const struct sci_base_state scic_sds_phy_state_table
[] = {
1247 [SCI_PHY_INITIAL
] = { },
1248 [SCI_PHY_STOPPED
] = {
1249 .enter_state
= scic_sds_phy_stopped_state_enter
,
1251 [SCI_PHY_STARTING
] = {
1252 .enter_state
= scic_sds_phy_starting_state_enter
,
1254 [SCI_PHY_SUB_INITIAL
] = {
1255 .enter_state
= scic_sds_phy_starting_initial_substate_enter
,
1257 [SCI_PHY_SUB_AWAIT_OSSP_EN
] = { },
1258 [SCI_PHY_SUB_AWAIT_SAS_SPEED_EN
] = { },
1259 [SCI_PHY_SUB_AWAIT_IAF_UF
] = { },
1260 [SCI_PHY_SUB_AWAIT_SAS_POWER
] = {
1261 .enter_state
= scic_sds_phy_starting_await_sas_power_substate_enter
,
1262 .exit_state
= scic_sds_phy_starting_await_sas_power_substate_exit
,
1264 [SCI_PHY_SUB_AWAIT_SATA_POWER
] = {
1265 .enter_state
= scic_sds_phy_starting_await_sata_power_substate_enter
,
1266 .exit_state
= scic_sds_phy_starting_await_sata_power_substate_exit
1268 [SCI_PHY_SUB_AWAIT_SATA_PHY_EN
] = {
1269 .enter_state
= scic_sds_phy_starting_await_sata_phy_substate_enter
,
1270 .exit_state
= scic_sds_phy_starting_await_sata_phy_substate_exit
1272 [SCI_PHY_SUB_AWAIT_SATA_SPEED_EN
] = {
1273 .enter_state
= scic_sds_phy_starting_await_sata_speed_substate_enter
,
1274 .exit_state
= scic_sds_phy_starting_await_sata_speed_substate_exit
1276 [SCI_PHY_SUB_AWAIT_SIG_FIS_UF
] = {
1277 .enter_state
= scic_sds_phy_starting_await_sig_fis_uf_substate_enter
,
1278 .exit_state
= scic_sds_phy_starting_await_sig_fis_uf_substate_exit
1280 [SCI_PHY_SUB_FINAL
] = {
1281 .enter_state
= scic_sds_phy_starting_final_substate_enter
,
1284 .enter_state
= scic_sds_phy_ready_state_enter
,
1285 .exit_state
= scic_sds_phy_ready_state_exit
,
1287 [SCI_PHY_RESETTING
] = {
1288 .enter_state
= scic_sds_phy_resetting_state_enter
,
1290 [SCI_PHY_FINAL
] = { },
1293 void scic_sds_phy_construct(struct isci_phy
*iphy
,
1294 struct scic_sds_port
*owning_port
, u8 phy_index
)
1296 sci_init_sm(&iphy
->sm
, scic_sds_phy_state_table
, SCI_PHY_INITIAL
);
1298 /* Copy the rest of the input data to our locals */
1299 iphy
->owning_port
= owning_port
;
1300 iphy
->phy_index
= phy_index
;
1301 iphy
->bcn_received_while_port_unassigned
= false;
1302 iphy
->protocol
= SCIC_SDS_PHY_PROTOCOL_UNKNOWN
;
1303 iphy
->link_layer_registers
= NULL
;
1304 iphy
->max_negotiated_speed
= SAS_LINK_RATE_UNKNOWN
;
1306 /* Create the SIGNATURE FIS Timeout timer for this phy */
1307 sci_init_timer(&iphy
->sata_timer
, phy_sata_timeout
);
1310 void isci_phy_init(struct isci_phy
*iphy
, struct isci_host
*ihost
, int index
)
1312 union scic_oem_parameters oem
;
1316 scic_oem_parameters_get(&ihost
->sci
, &oem
);
1317 sci_sas_addr
= oem
.sds1
.phys
[index
].sas_address
.high
;
1318 sci_sas_addr
<<= 32;
1319 sci_sas_addr
|= oem
.sds1
.phys
[index
].sas_address
.low
;
1320 sas_addr
= cpu_to_be64(sci_sas_addr
);
1321 memcpy(iphy
->sas_addr
, &sas_addr
, sizeof(sas_addr
));
1323 iphy
->isci_port
= NULL
;
1324 iphy
->sas_phy
.enabled
= 0;
1325 iphy
->sas_phy
.id
= index
;
1326 iphy
->sas_phy
.sas_addr
= &iphy
->sas_addr
[0];
1327 iphy
->sas_phy
.frame_rcvd
= (u8
*)&iphy
->frame_rcvd
;
1328 iphy
->sas_phy
.ha
= &ihost
->sas_ha
;
1329 iphy
->sas_phy
.lldd_phy
= iphy
;
1330 iphy
->sas_phy
.enabled
= 1;
1331 iphy
->sas_phy
.class = SAS
;
1332 iphy
->sas_phy
.iproto
= SAS_PROTOCOL_ALL
;
1333 iphy
->sas_phy
.tproto
= 0;
1334 iphy
->sas_phy
.type
= PHY_TYPE_PHYSICAL
;
1335 iphy
->sas_phy
.role
= PHY_ROLE_INITIATOR
;
1336 iphy
->sas_phy
.oob_mode
= OOB_NOT_CONNECTED
;
1337 iphy
->sas_phy
.linkrate
= SAS_LINK_RATE_UNKNOWN
;
1338 memset(&iphy
->frame_rcvd
, 0, sizeof(iphy
->frame_rcvd
));
1343 * isci_phy_control() - This function is one of the SAS Domain Template
1344 * functions. This is a phy management function.
1345 * @phy: This parameter specifies the sphy being controlled.
1346 * @func: This parameter specifies the phy control function being invoked.
1347 * @buf: This parameter is specific to the phy function being invoked.
1349 * status, zero indicates success.
1351 int isci_phy_control(struct asd_sas_phy
*sas_phy
,
1356 struct isci_phy
*iphy
= sas_phy
->lldd_phy
;
1357 struct isci_port
*iport
= iphy
->isci_port
;
1358 struct isci_host
*ihost
= sas_phy
->ha
->lldd_ha
;
1359 unsigned long flags
;
1361 dev_dbg(&ihost
->pdev
->dev
,
1362 "%s: phy %p; func %d; buf %p; isci phy %p, port %p\n",
1363 __func__
, sas_phy
, func
, buf
, iphy
, iport
);
1366 case PHY_FUNC_DISABLE
:
1367 spin_lock_irqsave(&ihost
->scic_lock
, flags
);
1368 scic_sds_phy_stop(iphy
);
1369 spin_unlock_irqrestore(&ihost
->scic_lock
, flags
);
1372 case PHY_FUNC_LINK_RESET
:
1373 spin_lock_irqsave(&ihost
->scic_lock
, flags
);
1374 scic_sds_phy_stop(iphy
);
1375 scic_sds_phy_start(iphy
);
1376 spin_unlock_irqrestore(&ihost
->scic_lock
, flags
);
1379 case PHY_FUNC_HARD_RESET
:
1383 /* Perform the port reset. */
1384 ret
= isci_port_perform_hard_reset(ihost
, iport
, iphy
);
1389 dev_dbg(&ihost
->pdev
->dev
,
1390 "%s: phy %p; func %d NOT IMPLEMENTED!\n",
1391 __func__
, sas_phy
, func
);