2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include "ar9003_mac.h"
19 static void ar9003_hw_rx_enable(struct ath_hw
*hw
)
21 REG_WRITE(hw
, AR_CR
, 0);
25 ar9003_set_txdesc(struct ath_hw
*ah
, void *ds
, struct ath_tx_info
*i
)
27 struct ar9003_txc
*ads
= ds
;
29 u32 val
, ctl12
, ctl17
;
31 val
= (ATHEROS_VENDOR_ID
<< AR_DescId_S
) |
32 (1 << AR_TxRxDesc_S
) |
33 (1 << AR_CtrlStat_S
) |
34 (i
->qcu
<< AR_TxQcuNum_S
) | 0x17;
37 ACCESS_ONCE(ads
->info
) = val
;
40 ACCESS_ONCE(ads
->link
) = i
->link
;
42 checksum
+= i
->buf_addr
[0];
43 ACCESS_ONCE(ads
->data0
) = i
->buf_addr
[0];
44 checksum
+= i
->buf_addr
[1];
45 ACCESS_ONCE(ads
->data1
) = i
->buf_addr
[1];
46 checksum
+= i
->buf_addr
[2];
47 ACCESS_ONCE(ads
->data2
) = i
->buf_addr
[2];
48 checksum
+= i
->buf_addr
[3];
49 ACCESS_ONCE(ads
->data3
) = i
->buf_addr
[3];
51 checksum
+= (val
= (i
->buf_len
[0] << AR_BufLen_S
) & AR_BufLen
);
52 ACCESS_ONCE(ads
->ctl3
) = val
;
53 checksum
+= (val
= (i
->buf_len
[1] << AR_BufLen_S
) & AR_BufLen
);
54 ACCESS_ONCE(ads
->ctl5
) = val
;
55 checksum
+= (val
= (i
->buf_len
[2] << AR_BufLen_S
) & AR_BufLen
);
56 ACCESS_ONCE(ads
->ctl7
) = val
;
57 checksum
+= (val
= (i
->buf_len
[3] << AR_BufLen_S
) & AR_BufLen
);
58 ACCESS_ONCE(ads
->ctl9
) = val
;
60 checksum
= (u16
) (((checksum
& 0xffff) + (checksum
>> 16)) & 0xffff);
61 ACCESS_ONCE(ads
->ctl10
) = checksum
;
63 if (i
->is_first
|| i
->is_last
) {
64 ACCESS_ONCE(ads
->ctl13
) = set11nTries(i
->rates
, 0)
65 | set11nTries(i
->rates
, 1)
66 | set11nTries(i
->rates
, 2)
67 | set11nTries(i
->rates
, 3)
68 | (i
->dur_update
? AR_DurUpdateEna
: 0)
71 ACCESS_ONCE(ads
->ctl14
) = set11nRate(i
->rates
, 0)
72 | set11nRate(i
->rates
, 1)
73 | set11nRate(i
->rates
, 2)
74 | set11nRate(i
->rates
, 3);
76 ACCESS_ONCE(ads
->ctl13
) = 0;
77 ACCESS_ONCE(ads
->ctl14
) = 0;
84 ctl17
= SM(i
->keytype
, AR_EncrType
);
86 ACCESS_ONCE(ads
->ctl11
) = 0;
87 ACCESS_ONCE(ads
->ctl12
) = i
->is_last
? 0 : AR_TxMore
;
88 ACCESS_ONCE(ads
->ctl15
) = 0;
89 ACCESS_ONCE(ads
->ctl16
) = 0;
90 ACCESS_ONCE(ads
->ctl17
) = ctl17
;
91 ACCESS_ONCE(ads
->ctl18
) = 0;
92 ACCESS_ONCE(ads
->ctl19
) = 0;
96 ACCESS_ONCE(ads
->ctl11
) = (i
->pkt_len
& AR_FrameLen
)
97 | (i
->flags
& ATH9K_TXDESC_VMF
? AR_VirtMoreFrag
: 0)
98 | SM(i
->txpower
, AR_XmitPower
)
99 | (i
->flags
& ATH9K_TXDESC_VEOL
? AR_VEOL
: 0)
100 | (i
->keyix
!= ATH9K_TXKEYIX_INVALID
? AR_DestIdxValid
: 0)
101 | (i
->flags
& ATH9K_TXDESC_LOWRXCHAIN
? AR_LowRxChain
: 0)
102 | (i
->flags
& ATH9K_TXDESC_CLRDMASK
? AR_ClrDestMask
: 0)
103 | (i
->flags
& ATH9K_TXDESC_RTSENA
? AR_RTSEnable
:
104 (i
->flags
& ATH9K_TXDESC_CTSENA
? AR_CTSEnable
: 0));
106 ctl12
= (i
->keyix
!= ATH9K_TXKEYIX_INVALID
?
107 SM(i
->keyix
, AR_DestIdx
) : 0)
108 | SM(i
->type
, AR_FrameType
)
109 | (i
->flags
& ATH9K_TXDESC_NOACK
? AR_NoAck
: 0)
110 | (i
->flags
& ATH9K_TXDESC_EXT_ONLY
? AR_ExtOnly
: 0)
111 | (i
->flags
& ATH9K_TXDESC_EXT_AND_CTL
? AR_ExtAndCtl
: 0);
113 ctl17
|= (i
->flags
& ATH9K_TXDESC_LDPC
? AR_LDPC
: 0);
116 ctl17
|= SM(i
->aggr_len
, AR_AggrLen
);
118 case AGGR_BUF_MIDDLE
:
119 ctl12
|= AR_IsAggr
| AR_MoreAggr
;
120 ctl17
|= SM(i
->ndelim
, AR_PadDelim
);
129 val
= (i
->flags
& ATH9K_TXDESC_PAPRD
) >> ATH9K_TXDESC_PAPRD_S
;
130 ctl12
|= SM(val
, AR_PAPRDChainMask
);
132 ACCESS_ONCE(ads
->ctl12
) = ctl12
;
133 ACCESS_ONCE(ads
->ctl17
) = ctl17
;
135 ACCESS_ONCE(ads
->ctl15
) = set11nPktDurRTSCTS(i
->rates
, 0)
136 | set11nPktDurRTSCTS(i
->rates
, 1);
138 ACCESS_ONCE(ads
->ctl16
) = set11nPktDurRTSCTS(i
->rates
, 2)
139 | set11nPktDurRTSCTS(i
->rates
, 3);
141 ACCESS_ONCE(ads
->ctl18
) = set11nRateFlags(i
->rates
, 0)
142 | set11nRateFlags(i
->rates
, 1)
143 | set11nRateFlags(i
->rates
, 2)
144 | set11nRateFlags(i
->rates
, 3)
145 | SM(i
->rtscts_rate
, AR_RTSCTSRate
);
147 ACCESS_ONCE(ads
->ctl19
) = AR_Not_Sounding
;
150 static u16
ar9003_calc_ptr_chksum(struct ar9003_txc
*ads
)
154 checksum
= ads
->info
+ ads
->link
155 + ads
->data0
+ ads
->ctl3
156 + ads
->data1
+ ads
->ctl5
157 + ads
->data2
+ ads
->ctl7
158 + ads
->data3
+ ads
->ctl9
;
160 return ((checksum
& 0xffff) + (checksum
>> 16)) & AR_TxPtrChkSum
;
163 static void ar9003_hw_set_desc_link(void *ds
, u32 ds_link
)
165 struct ar9003_txc
*ads
= ds
;
168 ads
->ctl10
&= ~AR_TxPtrChkSum
;
169 ads
->ctl10
|= ar9003_calc_ptr_chksum(ads
);
172 static bool ar9003_hw_get_isr(struct ath_hw
*ah
, enum ath9k_int
*masked
)
176 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
178 struct ath_common
*common
= ath9k_hw_common(ah
);
180 if (REG_READ(ah
, AR_INTR_ASYNC_CAUSE
) & AR_INTR_MAC_IRQ
) {
181 if ((REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
)
183 isr
= REG_READ(ah
, AR_ISR
);
186 sync_cause
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
) & AR_INTR_SYNC_DEFAULT
;
190 if (!isr
&& !sync_cause
)
194 if (isr
& AR_ISR_BCNMISC
) {
196 isr2
= REG_READ(ah
, AR_ISR_S2
);
198 mask2
|= ((isr2
& AR_ISR_S2_TIM
) >>
200 mask2
|= ((isr2
& AR_ISR_S2_DTIM
) >>
202 mask2
|= ((isr2
& AR_ISR_S2_DTIMSYNC
) >>
203 MAP_ISR_S2_DTIMSYNC
);
204 mask2
|= ((isr2
& AR_ISR_S2_CABEND
) >>
206 mask2
|= ((isr2
& AR_ISR_S2_GTT
) <<
208 mask2
|= ((isr2
& AR_ISR_S2_CST
) <<
210 mask2
|= ((isr2
& AR_ISR_S2_TSFOOR
) >>
212 mask2
|= ((isr2
& AR_ISR_S2_BB_WATCHDOG
) >>
213 MAP_ISR_S2_BB_WATCHDOG
);
215 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_RAC_SUPPORTED
)) {
216 REG_WRITE(ah
, AR_ISR_S2
, isr2
);
217 isr
&= ~AR_ISR_BCNMISC
;
221 if ((pCap
->hw_caps
& ATH9K_HW_CAP_RAC_SUPPORTED
))
222 isr
= REG_READ(ah
, AR_ISR_RAC
);
224 if (isr
== 0xffffffff) {
229 *masked
= isr
& ATH9K_INT_COMMON
;
231 if (ah
->config
.rx_intr_mitigation
)
232 if (isr
& (AR_ISR_RXMINTR
| AR_ISR_RXINTM
))
233 *masked
|= ATH9K_INT_RXLP
;
235 if (ah
->config
.tx_intr_mitigation
)
236 if (isr
& (AR_ISR_TXMINTR
| AR_ISR_TXINTM
))
237 *masked
|= ATH9K_INT_TX
;
239 if (isr
& (AR_ISR_LP_RXOK
| AR_ISR_RXERR
))
240 *masked
|= ATH9K_INT_RXLP
;
242 if (isr
& AR_ISR_HP_RXOK
)
243 *masked
|= ATH9K_INT_RXHP
;
245 if (isr
& (AR_ISR_TXOK
| AR_ISR_TXERR
| AR_ISR_TXEOL
)) {
246 *masked
|= ATH9K_INT_TX
;
248 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_RAC_SUPPORTED
)) {
250 s0
= REG_READ(ah
, AR_ISR_S0
);
251 REG_WRITE(ah
, AR_ISR_S0
, s0
);
252 s1
= REG_READ(ah
, AR_ISR_S1
);
253 REG_WRITE(ah
, AR_ISR_S1
, s1
);
255 isr
&= ~(AR_ISR_TXOK
| AR_ISR_TXERR
|
260 if (isr
& AR_ISR_GENTMR
) {
263 if (pCap
->hw_caps
& ATH9K_HW_CAP_RAC_SUPPORTED
)
264 s5
= REG_READ(ah
, AR_ISR_S5_S
);
266 s5
= REG_READ(ah
, AR_ISR_S5
);
268 ah
->intr_gen_timer_trigger
=
269 MS(s5
, AR_ISR_S5_GENTIMER_TRIG
);
271 ah
->intr_gen_timer_thresh
=
272 MS(s5
, AR_ISR_S5_GENTIMER_THRESH
);
274 if (ah
->intr_gen_timer_trigger
)
275 *masked
|= ATH9K_INT_GENTIMER
;
277 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_RAC_SUPPORTED
)) {
278 REG_WRITE(ah
, AR_ISR_S5
, s5
);
279 isr
&= ~AR_ISR_GENTMR
;
286 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_RAC_SUPPORTED
)) {
287 REG_WRITE(ah
, AR_ISR
, isr
);
289 (void) REG_READ(ah
, AR_ISR
);
292 if (*masked
& ATH9K_INT_BB_WATCHDOG
)
293 ar9003_hw_bb_watchdog_read(ah
);
297 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_TIMEOUT
) {
298 REG_WRITE(ah
, AR_RC
, AR_RC_HOSTIF
);
299 REG_WRITE(ah
, AR_RC
, 0);
300 *masked
|= ATH9K_INT_FATAL
;
303 if (sync_cause
& AR_INTR_SYNC_LOCAL_TIMEOUT
)
304 ath_dbg(common
, ATH_DBG_INTERRUPT
,
305 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
307 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE_CLR
, sync_cause
);
308 (void) REG_READ(ah
, AR_INTR_SYNC_CAUSE_CLR
);
314 static int ar9003_hw_proc_txdesc(struct ath_hw
*ah
, void *ds
,
315 struct ath_tx_status
*ts
)
317 struct ar9003_txc
*txc
= (struct ar9003_txc
*) ds
;
318 struct ar9003_txs
*ads
;
321 ads
= &ah
->ts_ring
[ah
->ts_tail
];
323 status
= ACCESS_ONCE(ads
->status8
);
324 if ((status
& AR_TxDone
) == 0)
327 ts
->qid
= MS(ads
->ds_info
, AR_TxQcuNum
);
328 if (!txc
|| (MS(txc
->info
, AR_TxQcuNum
) == ts
->qid
))
329 ah
->ts_tail
= (ah
->ts_tail
+ 1) % ah
->ts_size
;
333 if ((MS(ads
->ds_info
, AR_DescId
) != ATHEROS_VENDOR_ID
) ||
334 (MS(ads
->ds_info
, AR_TxRxDesc
) != 1)) {
335 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_XMIT
,
336 "Tx Descriptor error %x\n", ads
->ds_info
);
337 memset(ads
, 0, sizeof(*ads
));
341 ts
->ts_rateindex
= MS(status
, AR_FinalTxIdx
);
342 ts
->ts_seqnum
= MS(status
, AR_SeqNum
);
343 ts
->tid
= MS(status
, AR_TxTid
);
345 ts
->desc_id
= MS(ads
->status1
, AR_TxDescId
);
346 ts
->ts_tstamp
= ads
->status4
;
350 if (status
& AR_TxOpExceeded
)
351 ts
->ts_status
|= ATH9K_TXERR_XTXOP
;
352 status
= ACCESS_ONCE(ads
->status2
);
353 ts
->ts_rssi_ctl0
= MS(status
, AR_TxRSSIAnt00
);
354 ts
->ts_rssi_ctl1
= MS(status
, AR_TxRSSIAnt01
);
355 ts
->ts_rssi_ctl2
= MS(status
, AR_TxRSSIAnt02
);
356 if (status
& AR_TxBaStatus
) {
357 ts
->ts_flags
|= ATH9K_TX_BA
;
358 ts
->ba_low
= ads
->status5
;
359 ts
->ba_high
= ads
->status6
;
362 status
= ACCESS_ONCE(ads
->status3
);
363 if (status
& AR_ExcessiveRetries
)
364 ts
->ts_status
|= ATH9K_TXERR_XRETRY
;
365 if (status
& AR_Filtered
)
366 ts
->ts_status
|= ATH9K_TXERR_FILT
;
367 if (status
& AR_FIFOUnderrun
) {
368 ts
->ts_status
|= ATH9K_TXERR_FIFO
;
369 ath9k_hw_updatetxtriglevel(ah
, true);
371 if (status
& AR_TxTimerExpired
)
372 ts
->ts_status
|= ATH9K_TXERR_TIMER_EXPIRED
;
373 if (status
& AR_DescCfgErr
)
374 ts
->ts_flags
|= ATH9K_TX_DESC_CFG_ERR
;
375 if (status
& AR_TxDataUnderrun
) {
376 ts
->ts_flags
|= ATH9K_TX_DATA_UNDERRUN
;
377 ath9k_hw_updatetxtriglevel(ah
, true);
379 if (status
& AR_TxDelimUnderrun
) {
380 ts
->ts_flags
|= ATH9K_TX_DELIM_UNDERRUN
;
381 ath9k_hw_updatetxtriglevel(ah
, true);
383 ts
->ts_shortretry
= MS(status
, AR_RTSFailCnt
);
384 ts
->ts_longretry
= MS(status
, AR_DataFailCnt
);
385 ts
->ts_virtcol
= MS(status
, AR_VirtRetryCnt
);
387 status
= ACCESS_ONCE(ads
->status7
);
388 ts
->ts_rssi
= MS(status
, AR_TxRSSICombined
);
389 ts
->ts_rssi_ext0
= MS(status
, AR_TxRSSIAnt10
);
390 ts
->ts_rssi_ext1
= MS(status
, AR_TxRSSIAnt11
);
391 ts
->ts_rssi_ext2
= MS(status
, AR_TxRSSIAnt12
);
393 memset(ads
, 0, sizeof(*ads
));
398 void ar9003_hw_attach_mac_ops(struct ath_hw
*hw
)
400 struct ath_hw_ops
*ops
= ath9k_hw_ops(hw
);
402 ops
->rx_enable
= ar9003_hw_rx_enable
;
403 ops
->set_desc_link
= ar9003_hw_set_desc_link
;
404 ops
->get_isr
= ar9003_hw_get_isr
;
405 ops
->set_txdesc
= ar9003_set_txdesc
;
406 ops
->proc_txdesc
= ar9003_hw_proc_txdesc
;
409 void ath9k_hw_set_rx_bufsize(struct ath_hw
*ah
, u16 buf_size
)
411 REG_WRITE(ah
, AR_DATABUF_SIZE
, buf_size
& AR_DATABUF_SIZE_MASK
);
413 EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize
);
415 void ath9k_hw_addrxbuf_edma(struct ath_hw
*ah
, u32 rxdp
,
416 enum ath9k_rx_qtype qtype
)
418 if (qtype
== ATH9K_RX_QUEUE_HP
)
419 REG_WRITE(ah
, AR_HP_RXDP
, rxdp
);
421 REG_WRITE(ah
, AR_LP_RXDP
, rxdp
);
423 EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma
);
425 int ath9k_hw_process_rxdesc_edma(struct ath_hw
*ah
, struct ath_rx_status
*rxs
,
428 struct ar9003_rxs
*rxsp
= (struct ar9003_rxs
*) buf_addr
;
431 /* TODO: byte swap on big endian for ar9300_10 */
434 if ((rxsp
->status11
& AR_RxDone
) == 0)
437 if (MS(rxsp
->ds_info
, AR_DescId
) != 0x168c)
440 if ((rxsp
->ds_info
& (AR_TxRxDesc
| AR_CtrlStat
)) != 0)
449 rxs
->rs_datalen
= rxsp
->status2
& AR_DataLen
;
450 rxs
->rs_tstamp
= rxsp
->status3
;
453 rxs
->rs_rssi
= MS(rxsp
->status5
, AR_RxRSSICombined
);
454 rxs
->rs_rssi_ctl0
= MS(rxsp
->status1
, AR_RxRSSIAnt00
);
455 rxs
->rs_rssi_ctl1
= MS(rxsp
->status1
, AR_RxRSSIAnt01
);
456 rxs
->rs_rssi_ctl2
= MS(rxsp
->status1
, AR_RxRSSIAnt02
);
457 rxs
->rs_rssi_ext0
= MS(rxsp
->status5
, AR_RxRSSIAnt10
);
458 rxs
->rs_rssi_ext1
= MS(rxsp
->status5
, AR_RxRSSIAnt11
);
459 rxs
->rs_rssi_ext2
= MS(rxsp
->status5
, AR_RxRSSIAnt12
);
461 if (rxsp
->status11
& AR_RxKeyIdxValid
)
462 rxs
->rs_keyix
= MS(rxsp
->status11
, AR_KeyIdx
);
464 rxs
->rs_keyix
= ATH9K_RXKEYIX_INVALID
;
466 rxs
->rs_rate
= MS(rxsp
->status1
, AR_RxRate
);
467 rxs
->rs_more
= (rxsp
->status2
& AR_RxMore
) ? 1 : 0;
469 rxs
->rs_isaggr
= (rxsp
->status11
& AR_RxAggr
) ? 1 : 0;
470 rxs
->rs_moreaggr
= (rxsp
->status11
& AR_RxMoreAggr
) ? 1 : 0;
471 rxs
->rs_antenna
= (MS(rxsp
->status4
, AR_RxAntenna
) & 0x7);
472 rxs
->rs_flags
= (rxsp
->status4
& AR_GI
) ? ATH9K_RX_GI
: 0;
473 rxs
->rs_flags
|= (rxsp
->status4
& AR_2040
) ? ATH9K_RX_2040
: 0;
475 rxs
->evm0
= rxsp
->status6
;
476 rxs
->evm1
= rxsp
->status7
;
477 rxs
->evm2
= rxsp
->status8
;
478 rxs
->evm3
= rxsp
->status9
;
479 rxs
->evm4
= (rxsp
->status10
& 0xffff);
481 if (rxsp
->status11
& AR_PreDelimCRCErr
)
482 rxs
->rs_flags
|= ATH9K_RX_DELIM_CRC_PRE
;
484 if (rxsp
->status11
& AR_PostDelimCRCErr
)
485 rxs
->rs_flags
|= ATH9K_RX_DELIM_CRC_POST
;
487 if (rxsp
->status11
& AR_DecryptBusyErr
)
488 rxs
->rs_flags
|= ATH9K_RX_DECRYPT_BUSY
;
490 if ((rxsp
->status11
& AR_RxFrameOK
) == 0) {
492 * AR_CRCErr will bet set to true if we're on the last
493 * subframe and the AR_PostDelimCRCErr is caught.
494 * In a way this also gives us a guarantee that when
495 * (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot
496 * possibly be reviewing the last subframe. AR_CRCErr
497 * is the CRC of the actual data.
499 if (rxsp
->status11
& AR_CRCErr
)
500 rxs
->rs_status
|= ATH9K_RXERR_CRC
;
501 else if (rxsp
->status11
& AR_PHYErr
) {
502 phyerr
= MS(rxsp
->status11
, AR_PHYErrCode
);
504 * If we reach a point here where AR_PostDelimCRCErr is
505 * true it implies we're *not* on the last subframe. In
506 * in that case that we know already that the CRC of
507 * the frame was OK, and MAC would send an ACK for that
508 * subframe, even if we did get a phy error of type
509 * ATH9K_PHYERR_OFDM_RESTART. This is only applicable
510 * to frame that are prior to the last subframe.
511 * The AR_PostDelimCRCErr is the CRC for the MPDU
512 * delimiter, which contains the 4 reserved bits,
513 * the MPDU length (12 bits), and follows the MPDU
514 * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII).
516 if ((phyerr
== ATH9K_PHYERR_OFDM_RESTART
) &&
517 (rxsp
->status11
& AR_PostDelimCRCErr
)) {
520 rxs
->rs_status
|= ATH9K_RXERR_PHY
;
521 rxs
->rs_phyerr
= phyerr
;
524 } else if (rxsp
->status11
& AR_DecryptCRCErr
)
525 rxs
->rs_status
|= ATH9K_RXERR_DECRYPT
;
526 else if (rxsp
->status11
& AR_MichaelErr
)
527 rxs
->rs_status
|= ATH9K_RXERR_MIC
;
528 if (rxsp
->status11
& AR_KeyMiss
)
529 rxs
->rs_status
|= ATH9K_RXERR_KEYMISS
;
534 EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma
);
536 void ath9k_hw_reset_txstatus_ring(struct ath_hw
*ah
)
540 memset((void *) ah
->ts_ring
, 0,
541 ah
->ts_size
* sizeof(struct ar9003_txs
));
543 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_XMIT
,
544 "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
545 ah
->ts_paddr_start
, ah
->ts_paddr_end
,
546 ah
->ts_ring
, ah
->ts_size
);
548 REG_WRITE(ah
, AR_Q_STATUS_RING_START
, ah
->ts_paddr_start
);
549 REG_WRITE(ah
, AR_Q_STATUS_RING_END
, ah
->ts_paddr_end
);
552 void ath9k_hw_setup_statusring(struct ath_hw
*ah
, void *ts_start
,
557 ah
->ts_paddr_start
= ts_paddr_start
;
558 ah
->ts_paddr_end
= ts_paddr_start
+ (size
* sizeof(struct ar9003_txs
));
560 ah
->ts_ring
= (struct ar9003_txs
*) ts_start
;
562 ath9k_hw_reset_txstatus_ring(ah
);
564 EXPORT_SYMBOL(ath9k_hw_setup_statusring
);