arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/cpu.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23
  24 #include <asm/uv/uv_mmrs.h>
  25 #include <asm/uv/uv_hub.h>
  26 #include <asm/current.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/uv/bios.h>
  29 #include <asm/uv/uv.h>
  30 #include <asm/apic.h>
  31 #include <asm/ipi.h>
  32 #include <asm/smp.h>
  33 #include <asm/x86_init.h>
  34
  35 DEFINE_PER_CPU(int, x2apic_extra_bits);
  36
  37 static enum uv_system_type uv_system_type;
  38 static u64 gru_start_paddr, gru_end_paddr;
  39 int uv_min_hub_revision_id;
  40 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  41
  42 static inline bool is_GRU_range(u64 start, u64 end)
  43 {
  44         return start >= gru_start_paddr && end <= gru_end_paddr;
  45 }
  46
  47 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  48 {
  49         return is_ISA_range(start, end) || is_GRU_range(start, end);
  50 }
  51
  52 static int early_get_nodeid(void)
  53 {
  54         union uvh_node_id_u node_id;
  55         unsigned long *mmr;
  56
  57         mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr));
  58         node_id.v = *mmr;
  59         early_iounmap(mmr, sizeof(*mmr));
  60
  61         /* Currently, all blades have same revision number */
  62         uv_min_hub_revision_id = node_id.s.revision;
  63
  64         return node_id.s.node_id;
  65 }
  66
  67 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  68 {
  69         int nodeid;
  70
  71         if (!strcmp(oem_id, "SGI")) {
  72                 nodeid = early_get_nodeid();
  73                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
  74                 if (!strcmp(oem_table_id, "UVL"))
  75                         uv_system_type = UV_LEGACY_APIC;
  76                 else if (!strcmp(oem_table_id, "UVX"))
  77                         uv_system_type = UV_X2APIC;
  78                 else if (!strcmp(oem_table_id, "UVH")) {
  79                         __get_cpu_var(x2apic_extra_bits) =
  80                                 nodeid << (UV_APIC_PNODE_SHIFT - 1);
  81                         uv_system_type = UV_NON_UNIQUE_APIC;
  82                         return 1;
  83                 }
  84         }
  85         return 0;
  86 }
  87
  88 enum uv_system_type get_uv_system_type(void)
  89 {
  90         return uv_system_type;
  91 }
  92
  93 int is_uv_system(void)
  94 {
  95         return uv_system_type != UV_NONE;
  96 }
  97 EXPORT_SYMBOL_GPL(is_uv_system);
  98
  99 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 100 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
 101
 102 struct uv_blade_info *uv_blade_info;
 103 EXPORT_SYMBOL_GPL(uv_blade_info);
 104
 105 short *uv_node_to_blade;
 106 EXPORT_SYMBOL_GPL(uv_node_to_blade);
 107
 108 short *uv_cpu_to_blade;
 109 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
 110
 111 short uv_possible_blades;
 112 EXPORT_SYMBOL_GPL(uv_possible_blades);
 113
 114 unsigned long sn_rtc_cycles_per_second;
 115 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 116
 117 static const struct cpumask *uv_target_cpus(void)
 118 {
 119         return cpu_online_mask;
 120 }
 121
 122 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
 123 {
 124         cpumask_clear(retmask);
 125         cpumask_set_cpu(cpu, retmask);
 126 }
 127
 128 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 129 {
 130 #ifdef CONFIG_SMP
 131         unsigned long val;
 132         int pnode;
 133
 134         pnode = uv_apicid_to_pnode(phys_apicid);
 135         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 136             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 137             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 138             APIC_DM_INIT;
 139         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 140         mdelay(10);
 141
 142         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 143             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 144             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 145             APIC_DM_STARTUP;
 146         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 147
 148         atomic_set(&init_deasserted, 1);
 149 #endif
 150         return 0;
 151 }
 152
 153 static void uv_send_IPI_one(int cpu, int vector)
 154 {
 155         unsigned long apicid;
 156         int pnode;
 157
 158         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 159         pnode = uv_apicid_to_pnode(apicid);
 160         uv_hub_send_ipi(pnode, apicid, vector);
 161 }
 162
 163 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 164 {
 165         unsigned int cpu;
 166
 167         for_each_cpu(cpu, mask)
 168                 uv_send_IPI_one(cpu, vector);
 169 }
 170
 171 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 172 {
 173         unsigned int this_cpu = smp_processor_id();
 174         unsigned int cpu;
 175
 176         for_each_cpu(cpu, mask) {
 177                 if (cpu != this_cpu)
 178                         uv_send_IPI_one(cpu, vector);
 179         }
 180 }
 181
 182 static void uv_send_IPI_allbutself(int vector)
 183 {
 184         unsigned int this_cpu = smp_processor_id();
 185         unsigned int cpu;
 186
 187         for_each_online_cpu(cpu) {
 188                 if (cpu != this_cpu)
 189                         uv_send_IPI_one(cpu, vector);
 190         }
 191 }
 192
 193 static void uv_send_IPI_all(int vector)
 194 {
 195         uv_send_IPI_mask(cpu_online_mask, vector);
 196 }
 197
 198 static int uv_apic_id_registered(void)
 199 {
 200         return 1;
 201 }
 202
 203 static void uv_init_apic_ldr(void)
 204 {
 205 }
 206
 207 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 208 {
 209         /*
 210          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 211          * May as well be the first.
 212          */
 213         int cpu = cpumask_first(cpumask);
 214
 215         if ((unsigned)cpu < nr_cpu_ids)
 216                 return per_cpu(x86_cpu_to_apicid, cpu);
 217         else
 218                 return BAD_APICID;
 219 }
 220
 221 static unsigned int
 222 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 223                           const struct cpumask *andmask)
 224 {
 225         int cpu;
 226
 227         /*
 228          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 229          * May as well be the first.
 230          */
 231         for_each_cpu_and(cpu, cpumask, andmask) {
 232                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 233                         break;
 234         }
 235         return per_cpu(x86_cpu_to_apicid, cpu);
 236 }
 237
 238 static unsigned int x2apic_get_apic_id(unsigned long x)
 239 {
 240         unsigned int id;
 241
 242         WARN_ON(preemptible() && num_online_cpus() > 1);
 243         id = x | __get_cpu_var(x2apic_extra_bits);
 244
 245         return id;
 246 }
 247
 248 static unsigned long set_apic_id(unsigned int id)
 249 {
 250         unsigned long x;
 251
 252         /* maskout x2apic_extra_bits ? */
 253         x = id;
 254         return x;
 255 }
 256
 257 static unsigned int uv_read_apic_id(void)
 258 {
 259
 260         return x2apic_get_apic_id(apic_read(APIC_ID));
 261 }
 262
 263 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 264 {
 265         return uv_read_apic_id() >> index_msb;
 266 }
 267
 268 static void uv_send_IPI_self(int vector)
 269 {
 270         apic_write(APIC_SELF_IPI, vector);
 271 }
 272
 273 struct apic __refdata apic_x2apic_uv_x = {
 274
 275         .name                           = "UV large system",
 276         .probe                          = NULL,
 277         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 278         .apic_id_registered             = uv_apic_id_registered,
 279
 280         .irq_delivery_mode              = dest_Fixed,
 281         .irq_dest_mode                  = 0, /* physical */
 282
 283         .target_cpus                    = uv_target_cpus,
 284         .disable_esr                    = 0,
 285         .dest_logical                   = APIC_DEST_LOGICAL,
 286         .check_apicid_used              = NULL,
 287         .check_apicid_present           = NULL,
 288
 289         .vector_allocation_domain       = uv_vector_allocation_domain,
 290         .init_apic_ldr                  = uv_init_apic_ldr,
 291
 292         .ioapic_phys_id_map             = NULL,
 293         .setup_apic_routing             = NULL,
 294         .multi_timer_check              = NULL,
 295         .apicid_to_node                 = NULL,
 296         .cpu_to_logical_apicid          = NULL,
 297         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 298         .apicid_to_cpu_present          = NULL,
 299         .setup_portio_remap             = NULL,
 300         .check_phys_apicid_present      = default_check_phys_apicid_present,
 301         .enable_apic_mode               = NULL,
 302         .phys_pkg_id                    = uv_phys_pkg_id,
 303         .mps_oem_check                  = NULL,
 304
 305         .get_apic_id                    = x2apic_get_apic_id,
 306         .set_apic_id                    = set_apic_id,
 307         .apic_id_mask                   = 0xFFFFFFFFu,
 308
 309         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
 310         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 311
 312         .send_IPI_mask                  = uv_send_IPI_mask,
 313         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 314         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 315         .send_IPI_all                   = uv_send_IPI_all,
 316         .send_IPI_self                  = uv_send_IPI_self,
 317
 318         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 319         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 320         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 321         .wait_for_init_deassert         = NULL,
 322         .smp_callin_clear_local_apic    = NULL,
 323         .inquire_remote_apic            = NULL,
 324
 325         .read                           = native_apic_msr_read,
 326         .write                          = native_apic_msr_write,
 327         .icr_read                       = native_x2apic_icr_read,
 328         .icr_write                      = native_x2apic_icr_write,
 329         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 330         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 331 };
 332
 333 static __cpuinit void set_x2apic_extra_bits(int pnode)
 334 {
 335         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 336 }
 337
 338 /*
 339  * Called on boot cpu.
 340  */
 341 static __init int boot_pnode_to_blade(int pnode)
 342 {
 343         int blade;
 344
 345         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 346                 if (pnode == uv_blade_info[blade].pnode)
 347                         return blade;
 348         BUG();
 349 }
 350
 351 struct redir_addr {
 352         unsigned long redirect;
 353         unsigned long alias;
 354 };
 355
 356 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 357
 358 static __initdata struct redir_addr redir_addrs[] = {
 359         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 360         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 361         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 362 };
 363
 364 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 365 {
 366         union uvh_si_alias0_overlay_config_u alias;
 367         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 368         int i;
 369
 370         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 371                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 372                 if (alias.s.enable && alias.s.base == 0) {
 373                         *size = (1UL << alias.s.m_alias);
 374                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 375                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 376                         return;
 377                 }
 378         }
 379         *base = *size = 0;
 380 }
 381
 382 enum map_type {map_wb, map_uc};
 383
 384 static __init void map_high(char *id, unsigned long base, int pshift,
 385                         int bshift, int max_pnode, enum map_type map_type)
 386 {
 387         unsigned long bytes, paddr;
 388
 389         paddr = base << pshift;
 390         bytes = (1UL << bshift) * (max_pnode + 1);
 391         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 392                                                 paddr + bytes);
 393         if (map_type == map_uc)
 394                 init_extra_mapping_uc(paddr, bytes);
 395         else
 396                 init_extra_mapping_wb(paddr, bytes);
 397
 398 }
 399 static __init void map_gru_high(int max_pnode)
 400 {
 401         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 402         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 403
 404         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 405         if (gru.s.enable) {
 406                 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
 407                 gru_start_paddr = ((u64)gru.s.base << shift);
 408                 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 409
 410         }
 411 }
 412
 413 static __init void map_mmr_high(int max_pnode)
 414 {
 415         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 416         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 417
 418         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 419         if (mmr.s.enable)
 420                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 421 }
 422
 423 static __init void map_mmioh_high(int max_pnode)
 424 {
 425         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 426         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 427
 428         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 429         if (mmioh.s.enable)
 430                 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
 431                         max_pnode, map_uc);
 432 }
 433
 434 static __init void map_low_mmrs(void)
 435 {
 436         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 437         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 438 }
 439
 440 static __init void uv_rtc_init(void)
 441 {
 442         long status;
 443         u64 ticks_per_sec;
 444
 445         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 446                                         &ticks_per_sec);
 447         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 448                 printk(KERN_WARNING
 449                         "unable to determine platform RTC clock frequency, "
 450                         "guessing.\n");
 451                 /* BIOS gives wrong value for clock freq. so guess */
 452                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 453         } else
 454                 sn_rtc_cycles_per_second = ticks_per_sec;
 455 }
 456
 457 /*
 458  * percpu heartbeat timer
 459  */
 460 static void uv_heartbeat(unsigned long ignored)
 461 {
 462         struct timer_list *timer = &uv_hub_info->scir.timer;
 463         unsigned char bits = uv_hub_info->scir.state;
 464
 465         /* flip heartbeat bit */
 466         bits ^= SCIR_CPU_HEARTBEAT;
 467
 468         /* is this cpu idle? */
 469         if (idle_cpu(raw_smp_processor_id()))
 470                 bits &= ~SCIR_CPU_ACTIVITY;
 471         else
 472                 bits |= SCIR_CPU_ACTIVITY;
 473
 474         /* update system controller interface reg */
 475         uv_set_scir_bits(bits);
 476
 477         /* enable next timer period */
 478         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 479 }
 480
 481 static void __cpuinit uv_heartbeat_enable(int cpu)
 482 {
 483         if (!uv_cpu_hub_info(cpu)->scir.enabled) {
 484                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 485
 486                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 487                 setup_timer(timer, uv_heartbeat, cpu);
 488                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 489                 add_timer_on(timer, cpu);
 490                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 491         }
 492
 493         /* check boot cpu */
 494         if (!uv_cpu_hub_info(0)->scir.enabled)
 495                 uv_heartbeat_enable(0);
 496 }
 497
 498 #ifdef CONFIG_HOTPLUG_CPU
 499 static void __cpuinit uv_heartbeat_disable(int cpu)
 500 {
 501         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 502                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 503                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 504         }
 505         uv_set_cpu_scir_bits(cpu, 0xff);
 506 }
 507
 508 /*
 509  * cpu hotplug notifier
 510  */
 511 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 512                                        unsigned long action, void *hcpu)
 513 {
 514         long cpu = (long)hcpu;
 515
 516         switch (action) {
 517         case CPU_ONLINE:
 518                 uv_heartbeat_enable(cpu);
 519                 break;
 520         case CPU_DOWN_PREPARE:
 521                 uv_heartbeat_disable(cpu);
 522                 break;
 523         default:
 524                 break;
 525         }
 526         return NOTIFY_OK;
 527 }
 528
 529 static __init void uv_scir_register_cpu_notifier(void)
 530 {
 531         hotcpu_notifier(uv_scir_cpu_notify, 0);
 532 }
 533
 534 #else /* !CONFIG_HOTPLUG_CPU */
 535
 536 static __init void uv_scir_register_cpu_notifier(void)
 537 {
 538 }
 539
 540 static __init int uv_init_heartbeat(void)
 541 {
 542         int cpu;
 543
 544         if (is_uv_system())
 545                 for_each_online_cpu(cpu)
 546                         uv_heartbeat_enable(cpu);
 547         return 0;
 548 }
 549
 550 late_initcall(uv_init_heartbeat);
 551
 552 #endif /* !CONFIG_HOTPLUG_CPU */
 553
 554 /*
 555  * Called on each cpu to initialize the per_cpu UV data area.
 556  * FIXME: hotplug not supported yet
 557  */
 558 void __cpuinit uv_cpu_init(void)
 559 {
 560         /* CPU 0 initilization will be done via uv_system_init. */
 561         if (!uv_blade_info)
 562                 return;
 563
 564         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 565
 566         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 567                 set_x2apic_extra_bits(uv_hub_info->pnode);
 568 }
 569
 570
 571 void __init uv_system_init(void)
 572 {
 573         union uvh_si_addr_map_config_u m_n_config;
 574         union uvh_node_id_u node_id;
 575         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 576         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 577         int gnode_extra, max_pnode = 0;
 578         unsigned long mmr_base, present, paddr;
 579         unsigned short pnode_mask;
 580
 581         map_low_mmrs();
 582
 583         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 584         m_val = m_n_config.s.m_skt;
 585         n_val = m_n_config.s.n_skt;
 586         mmr_base =
 587             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 588             ~UV_MMR_ENABLE;
 589         pnode_mask = (1 << n_val) - 1;
 590         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 591         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
 592         gnode_upper = ((unsigned long)gnode_extra  << m_val);
 593         printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
 594                         n_val, m_val, gnode_upper, gnode_extra);
 595
 596         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 597
 598         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 599                 uv_possible_blades +=
 600                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 601         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 602
 603         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 604         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 605         BUG_ON(!uv_blade_info);
 606         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 607                 uv_blade_info[blade].memory_nid = -1;
 608
 609         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 610
 611         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 612         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 613         BUG_ON(!uv_node_to_blade);
 614         memset(uv_node_to_blade, 255, bytes);
 615
 616         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 617         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 618         BUG_ON(!uv_cpu_to_blade);
 619         memset(uv_cpu_to_blade, 255, bytes);
 620
 621         blade = 0;
 622         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 623                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 624                 for (j = 0; j < 64; j++) {
 625                         if (!test_bit(j, &present))
 626                                 continue;
 627                         uv_blade_info[blade].pnode = (i * 64 + j);
 628                         uv_blade_info[blade].nr_possible_cpus = 0;
 629                         uv_blade_info[blade].nr_online_cpus = 0;
 630                         blade++;
 631                 }
 632         }
 633
 634         uv_bios_init();
 635         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
 636                             &sn_coherency_id, &sn_region_size);
 637         uv_rtc_init();
 638
 639         for_each_present_cpu(cpu) {
 640                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
 641
 642                 nid = cpu_to_node(cpu);
 643                 pnode = uv_apicid_to_pnode(apicid);
 644                 blade = boot_pnode_to_blade(pnode);
 645                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 646                 uv_blade_info[blade].nr_possible_cpus++;
 647
 648                 /* Any node on the blade, else will contain -1. */
 649                 uv_blade_info[blade].memory_nid = nid;
 650
 651                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 652                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 653                 uv_cpu_hub_info(cpu)->m_val = m_val;
 654                 uv_cpu_hub_info(cpu)->n_val = n_val;
 655                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 656                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 657                 uv_cpu_hub_info(cpu)->pnode = pnode;
 658                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
 659                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 660                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 661                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 662                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 663                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 664                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
 665                 uv_node_to_blade[nid] = blade;
 666                 uv_cpu_to_blade[cpu] = blade;
 667                 max_pnode = max(pnode, max_pnode);
 668
 669                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, lcpu %d, blade %d\n",
 670                         cpu, apicid, pnode, nid, lcpu, blade);
 671         }
 672
 673         /* Add blade/pnode info for nodes without cpus */
 674         for_each_online_node(nid) {
 675                 if (uv_node_to_blade[nid] >= 0)
 676                         continue;
 677                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
 678                 paddr = uv_soc_phys_ram_to_gpa(paddr);
 679                 pnode = (paddr >> m_val) & pnode_mask;
 680                 blade = boot_pnode_to_blade(pnode);
 681                 uv_node_to_blade[nid] = blade;
 682                 max_pnode = max(pnode, max_pnode);
 683         }
 684
 685         map_gru_high(max_pnode);
 686         map_mmr_high(max_pnode);
 687         map_mmioh_high(max_pnode);
 688
 689         uv_cpu_init();
 690         uv_scir_register_cpu_notifier();
 691         proc_mkdir("sgi_uv", NULL);
 692 }