drivers/gpu/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "drm_sarea.h"
  30 #include "radeon.h"
  31 #include "radeon_drm.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35
  36 int radeon_driver_unload_kms(struct drm_device *dev)
  37 {
  38         struct radeon_device *rdev = dev->dev_private;
  39
  40         if (rdev == NULL)
  41                 return 0;
  42         radeon_modeset_fini(rdev);
  43         radeon_device_fini(rdev);
  44         kfree(rdev);
  45         dev->dev_private = NULL;
  46         return 0;
  47 }
  48
  49 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  50 {
  51         struct radeon_device *rdev;
  52         int r, acpi_status;
  53
  54         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  55         if (rdev == NULL) {
  56                 return -ENOMEM;
  57         }
  58         dev->dev_private = (void *)rdev;
  59
  60         /* update BUS flag */
  61         if (drm_pci_device_is_agp(dev)) {
  62                 flags |= RADEON_IS_AGP;
  63         } else if (drm_pci_device_is_pcie(dev)) {
  64                 flags |= RADEON_IS_PCIE;
  65         } else {
  66                 flags |= RADEON_IS_PCI;
  67         }
  68
  69         /* radeon_device_init should report only fatal error
  70          * like memory allocation failure or iomapping failure,
  71          * or memory manager initialization failure, it must
  72          * properly initialize the GPU MC controller and permit
  73          * VRAM allocation
  74          */
  75         r = radeon_device_init(rdev, dev, dev->pdev, flags);
  76         if (r) {
  77                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
  78                 goto out;
  79         }
  80
  81         /* Call ACPI methods */
  82         acpi_status = radeon_acpi_init(rdev);
  83         if (acpi_status)
  84                 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
  85
  86         /* Again modeset_init should fail only on fatal error
  87          * otherwise it should provide enough functionalities
  88          * for shadowfb to run
  89          */
  90         r = radeon_modeset_init(rdev);
  91         if (r)
  92                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
  93 out:
  94         if (r)
  95                 radeon_driver_unload_kms(dev);
  96         return r;
  97 }
  98
  99 static void radeon_set_filp_rights(struct drm_device *dev,
 100                                    struct drm_file **owner,
 101                                    struct drm_file *applier,
 102                                    uint32_t *value)
 103 {
 104         mutex_lock(&dev->struct_mutex);
 105         if (*value == 1) {
 106                 /* wants rights */
 107                 if (!*owner)
 108                         *owner = applier;
 109         } else if (*value == 0) {
 110                 /* revokes rights */
 111                 if (*owner == applier)
 112                         *owner = NULL;
 113         }
 114         *value = *owner == applier ? 1 : 0;
 115         mutex_unlock(&dev->struct_mutex);
 116 }
 117
 118 /*
 119  * Userspace get information ioctl
 120  */
 121 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 122 {
 123         struct radeon_device *rdev = dev->dev_private;
 124         struct drm_radeon_info *info;
 125         struct radeon_mode_info *minfo = &rdev->mode_info;
 126         uint32_t *value_ptr;
 127         uint32_t value;
 128         struct drm_crtc *crtc;
 129         int i, found;
 130
 131         info = data;
 132         value_ptr = (uint32_t *)((unsigned long)info->value);
 133         if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
 134                 return -EFAULT;
 135
 136         switch (info->request) {
 137         case RADEON_INFO_DEVICE_ID:
 138                 value = dev->pci_device;
 139                 break;
 140         case RADEON_INFO_NUM_GB_PIPES:
 141                 value = rdev->num_gb_pipes;
 142                 break;
 143         case RADEON_INFO_NUM_Z_PIPES:
 144                 value = rdev->num_z_pipes;
 145                 break;
 146         case RADEON_INFO_ACCEL_WORKING:
 147                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
 148                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
 149                         value = false;
 150                 else
 151                         value = rdev->accel_working;
 152                 break;
 153         case RADEON_INFO_CRTC_FROM_ID:
 154                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
 155                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 156                         if (crtc && crtc->base.id == value) {
 157                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 158                                 value = radeon_crtc->crtc_id;
 159                                 found = 1;
 160                                 break;
 161                         }
 162                 }
 163                 if (!found) {
 164                         DRM_DEBUG_KMS("unknown crtc id %d\n", value);
 165                         return -EINVAL;
 166                 }
 167                 break;
 168         case RADEON_INFO_ACCEL_WORKING2:
 169                 value = rdev->accel_working;
 170                 break;
 171         case RADEON_INFO_TILING_CONFIG:
 172                 if (rdev->family >= CHIP_CEDAR)
 173                         value = rdev->config.evergreen.tile_config;
 174                 else if (rdev->family >= CHIP_RV770)
 175                         value = rdev->config.rv770.tile_config;
 176                 else if (rdev->family >= CHIP_R600)
 177                         value = rdev->config.r600.tile_config;
 178                 else {
 179                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
 180                         return -EINVAL;
 181                 }
 182                 break;
 183         case RADEON_INFO_WANT_HYPERZ:
 184                 /* The "value" here is both an input and output parameter.
 185                  * If the input value is 1, filp requests hyper-z access.
 186                  * If the input value is 0, filp revokes its hyper-z access.
 187                  *
 188                  * When returning, the value is 1 if filp owns hyper-z access,
 189                  * 0 otherwise. */
 190                 if (value >= 2) {
 191                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
 192                         return -EINVAL;
 193                 }
 194                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
 195                 break;
 196         case RADEON_INFO_WANT_CMASK:
 197                 /* The same logic as Hyper-Z. */
 198                 if (value >= 2) {
 199                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
 200                         return -EINVAL;
 201                 }
 202                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
 203                 break;
 204         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
 205                 /* return clock value in KHz */
 206                 value = rdev->clock.spll.reference_freq * 10;
 207                 break;
 208         default:
 209                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 210                 return -EINVAL;
 211         }
 212         if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
 213                 DRM_ERROR("copy_to_user\n");
 214                 return -EFAULT;
 215         }
 216         return 0;
 217 }
 218
 219
 220 /*
 221  * Outdated mess for old drm with Xorg being in charge (void function now).
 222  */
 223 int radeon_driver_firstopen_kms(struct drm_device *dev)
 224 {
 225         return 0;
 226 }
 227
 228
 229 void radeon_driver_lastclose_kms(struct drm_device *dev)
 230 {
 231         vga_switcheroo_process_delayed_switch();
 232 }
 233
 234 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 235 {
 236         return 0;
 237 }
 238
 239 void radeon_driver_postclose_kms(struct drm_device *dev,
 240                                  struct drm_file *file_priv)
 241 {
 242 }
 243
 244 void radeon_driver_preclose_kms(struct drm_device *dev,
 245                                 struct drm_file *file_priv)
 246 {
 247         struct radeon_device *rdev = dev->dev_private;
 248         if (rdev->hyperz_filp == file_priv)
 249                 rdev->hyperz_filp = NULL;
 250         if (rdev->cmask_filp == file_priv)
 251                 rdev->cmask_filp = NULL;
 252 }
 253
 254 /*
 255  * VBlank related functions.
 256  */
 257 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
 258 {
 259         struct radeon_device *rdev = dev->dev_private;
 260
 261         if (crtc < 0 || crtc >= rdev->num_crtc) {
 262                 DRM_ERROR("Invalid crtc %d\n", crtc);
 263                 return -EINVAL;
 264         }
 265
 266         return radeon_get_vblank_counter(rdev, crtc);
 267 }
 268
 269 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 270 {
 271         struct radeon_device *rdev = dev->dev_private;
 272
 273         if (crtc < 0 || crtc >= rdev->num_crtc) {
 274                 DRM_ERROR("Invalid crtc %d\n", crtc);
 275                 return -EINVAL;
 276         }
 277
 278         rdev->irq.crtc_vblank_int[crtc] = true;
 279
 280         return radeon_irq_set(rdev);
 281 }
 282
 283 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 284 {
 285         struct radeon_device *rdev = dev->dev_private;
 286
 287         if (crtc < 0 || crtc >= rdev->num_crtc) {
 288                 DRM_ERROR("Invalid crtc %d\n", crtc);
 289                 return;
 290         }
 291
 292         rdev->irq.crtc_vblank_int[crtc] = false;
 293
 294         radeon_irq_set(rdev);
 295 }
 296
 297 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
 298                                     int *max_error,
 299                                     struct timeval *vblank_time,
 300                                     unsigned flags)
 301 {
 302         struct drm_crtc *drmcrtc;
 303         struct radeon_device *rdev = dev->dev_private;
 304
 305         if (crtc < 0 || crtc >= dev->num_crtcs) {
 306                 DRM_ERROR("Invalid crtc %d\n", crtc);
 307                 return -EINVAL;
 308         }
 309
 310         /* Get associated drm_crtc: */
 311         drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
 312
 313         /* Helper routine in DRM core does all the work: */
 314         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
 315                                                      vblank_time, flags,
 316                                                      drmcrtc);
 317 }
 318
 319 /*
 320  * IOCTL.
 321  */
 322 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
 323                          struct drm_file *file_priv)
 324 {
 325         /* Not valid in KMS. */
 326         return -EINVAL;
 327 }
 328
 329 #define KMS_INVALID_IOCTL(name)                                         \
 330 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
 331 {                                                                       \
 332         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
 333         return -EINVAL;                                                 \
 334 }
 335
 336 /*
 337  * All these ioctls are invalid in kms world.
 338  */
 339 KMS_INVALID_IOCTL(radeon_cp_init_kms)
 340 KMS_INVALID_IOCTL(radeon_cp_start_kms)
 341 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
 342 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
 343 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
 344 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
 345 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
 346 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
 347 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
 348 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
 349 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
 350 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
 351 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
 352 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
 353 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
 354 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
 355 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
 356 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
 357 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
 358 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
 359 KMS_INVALID_IOCTL(radeon_mem_free_kms)
 360 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
 361 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
 362 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
 363 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
 364 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
 365 KMS_INVALID_IOCTL(radeon_surface_free_kms)
 366
 367
 368 struct drm_ioctl_desc radeon_ioctls_kms[] = {
 369         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 370         DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 371         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 372         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 373         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
 374         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
 375         DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
 376         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
 377         DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
 378         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
 379         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
 380         DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
 381         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
 382         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
 383         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 384         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
 385         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
 386         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
 387         DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
 388         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
 389         DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
 390         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 391         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
 392         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
 393         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
 394         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
 395         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
 396         /* KMS */
 397         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 398         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
 399         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
 400         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
 401         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
 402         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
 403         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
 404         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
 405         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 406         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 407         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 408         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
 409 };
 410 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);