2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3 * Copyright 2005 Stephane Marchesin
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "drm_sarea.h"
37 #include "nouveau_drv.h"
38 #include "nouveau_pm.h"
39 #include "nouveau_mm.h"
40 #include "nouveau_vm.h"
43 * NV10-NV40 tiling helpers
47 nv10_mem_update_tile_region(struct drm_device
*dev
,
48 struct nouveau_tile_reg
*tile
, uint32_t addr
,
49 uint32_t size
, uint32_t pitch
, uint32_t flags
)
51 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
52 struct nouveau_fifo_engine
*pfifo
= &dev_priv
->engine
.fifo
;
53 struct nouveau_fb_engine
*pfb
= &dev_priv
->engine
.fb
;
54 struct nouveau_pgraph_engine
*pgraph
= &dev_priv
->engine
.graph
;
55 int i
= tile
- dev_priv
->tile
.reg
;
58 nouveau_fence_unref(&tile
->fence
);
61 pfb
->free_tile_region(dev
, i
);
64 pfb
->init_tile_region(dev
, i
, addr
, size
, pitch
, flags
);
66 spin_lock_irqsave(&dev_priv
->context_switch_lock
, save
);
67 pfifo
->reassign(dev
, false);
68 pfifo
->cache_pull(dev
, false);
70 nouveau_wait_for_idle(dev
);
72 pfb
->set_tile_region(dev
, i
);
73 pgraph
->set_tile_region(dev
, i
);
75 pfifo
->cache_pull(dev
, true);
76 pfifo
->reassign(dev
, true);
77 spin_unlock_irqrestore(&dev_priv
->context_switch_lock
, save
);
80 static struct nouveau_tile_reg
*
81 nv10_mem_get_tile_region(struct drm_device
*dev
, int i
)
83 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
84 struct nouveau_tile_reg
*tile
= &dev_priv
->tile
.reg
[i
];
86 spin_lock(&dev_priv
->tile
.lock
);
89 (!tile
->fence
|| nouveau_fence_signalled(tile
->fence
)))
94 spin_unlock(&dev_priv
->tile
.lock
);
99 nv10_mem_put_tile_region(struct drm_device
*dev
, struct nouveau_tile_reg
*tile
,
100 struct nouveau_fence
*fence
)
102 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
105 spin_lock(&dev_priv
->tile
.lock
);
107 /* Mark it as pending. */
109 nouveau_fence_ref(fence
);
113 spin_unlock(&dev_priv
->tile
.lock
);
117 struct nouveau_tile_reg
*
118 nv10_mem_set_tiling(struct drm_device
*dev
, uint32_t addr
, uint32_t size
,
119 uint32_t pitch
, uint32_t flags
)
121 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
122 struct nouveau_fb_engine
*pfb
= &dev_priv
->engine
.fb
;
123 struct nouveau_tile_reg
*tile
, *found
= NULL
;
126 for (i
= 0; i
< pfb
->num_tiles
; i
++) {
127 tile
= nv10_mem_get_tile_region(dev
, i
);
129 if (pitch
&& !found
) {
133 } else if (tile
&& tile
->pitch
) {
134 /* Kill an unused tile region. */
135 nv10_mem_update_tile_region(dev
, tile
, 0, 0, 0, 0);
138 nv10_mem_put_tile_region(dev
, tile
, NULL
);
142 nv10_mem_update_tile_region(dev
, found
, addr
, size
,
151 nouveau_mem_vram_fini(struct drm_device
*dev
)
153 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
155 nouveau_bo_unpin(dev_priv
->vga_ram
);
156 nouveau_bo_ref(NULL
, &dev_priv
->vga_ram
);
158 ttm_bo_device_release(&dev_priv
->ttm
.bdev
);
160 nouveau_ttm_global_release(dev_priv
);
162 if (dev_priv
->fb_mtrr
>= 0) {
163 drm_mtrr_del(dev_priv
->fb_mtrr
,
164 pci_resource_start(dev
->pdev
, 1),
165 pci_resource_len(dev
->pdev
, 1), DRM_MTRR_WC
);
166 dev_priv
->fb_mtrr
= -1;
171 nouveau_mem_gart_fini(struct drm_device
*dev
)
173 nouveau_sgdma_takedown(dev
);
175 if (drm_core_has_AGP(dev
) && dev
->agp
) {
176 struct drm_agp_mem
*entry
, *tempe
;
178 /* Remove AGP resources, but leave dev->agp
179 intact until drv_cleanup is called. */
180 list_for_each_entry_safe(entry
, tempe
, &dev
->agp
->memory
, head
) {
182 drm_unbind_agp(entry
->memory
);
183 drm_free_agp(entry
->memory
, entry
->pages
);
186 INIT_LIST_HEAD(&dev
->agp
->memory
);
188 if (dev
->agp
->acquired
)
189 drm_agp_release(dev
);
191 dev
->agp
->acquired
= 0;
192 dev
->agp
->enabled
= 0;
197 nouveau_mem_detect_nv04(struct drm_device
*dev
)
199 uint32_t boot0
= nv_rd32(dev
, NV04_PFB_BOOT_0
);
201 if (boot0
& 0x00000100)
202 return (((boot0
>> 12) & 0xf) * 2 + 2) * 1024 * 1024;
204 switch (boot0
& NV04_PFB_BOOT_0_RAM_AMOUNT
) {
205 case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB
:
206 return 32 * 1024 * 1024;
207 case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB
:
208 return 16 * 1024 * 1024;
209 case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB
:
210 return 8 * 1024 * 1024;
211 case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB
:
212 return 4 * 1024 * 1024;
219 nouveau_mem_detect_nforce(struct drm_device
*dev
)
221 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
222 struct pci_dev
*bridge
;
225 bridge
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
227 NV_ERROR(dev
, "no bridge device\n");
231 if (dev_priv
->flags
& NV_NFORCE
) {
232 pci_read_config_dword(bridge
, 0x7C, &mem
);
233 return (uint64_t)(((mem
>> 6) & 31) + 1)*1024*1024;
235 if (dev_priv
->flags
& NV_NFORCE2
) {
236 pci_read_config_dword(bridge
, 0x84, &mem
);
237 return (uint64_t)(((mem
>> 4) & 127) + 1)*1024*1024;
240 NV_ERROR(dev
, "impossible!\n");
245 nouveau_mem_detect(struct drm_device
*dev
)
247 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
249 if (dev_priv
->card_type
== NV_04
) {
250 dev_priv
->vram_size
= nouveau_mem_detect_nv04(dev
);
252 if (dev_priv
->flags
& (NV_NFORCE
| NV_NFORCE2
)) {
253 dev_priv
->vram_size
= nouveau_mem_detect_nforce(dev
);
255 if (dev_priv
->card_type
< NV_50
) {
256 dev_priv
->vram_size
= nv_rd32(dev
, NV04_PFB_FIFO_DATA
);
257 dev_priv
->vram_size
&= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK
;
260 if (dev_priv
->vram_size
)
266 nouveau_mem_flags_valid(struct drm_device
*dev
, u32 tile_flags
)
268 if (!(tile_flags
& NOUVEAU_GEM_TILE_LAYOUT_MASK
))
276 get_agp_mode(struct drm_device
*dev
, unsigned long mode
)
278 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
281 * FW seems to be broken on nv18, it makes the card lock up
284 if (dev_priv
->chipset
== 0x18)
285 mode
&= ~PCI_AGP_COMMAND_FW
;
288 * AGP mode set in the command line.
290 if (nouveau_agpmode
> 0) {
291 bool agpv3
= mode
& 0x8;
292 int rate
= agpv3
? nouveau_agpmode
/ 4 : nouveau_agpmode
;
294 mode
= (mode
& ~0x7) | (rate
& 0x7);
302 nouveau_mem_reset_agp(struct drm_device
*dev
)
305 uint32_t saved_pci_nv_1
, pmc_enable
;
308 /* First of all, disable fast writes, otherwise if it's
309 * already enabled in the AGP bridge and we disable the card's
310 * AGP controller we might be locking ourselves out of it. */
311 if ((nv_rd32(dev
, NV04_PBUS_PCI_NV_19
) |
312 dev
->agp
->mode
) & PCI_AGP_COMMAND_FW
) {
313 struct drm_agp_info info
;
314 struct drm_agp_mode mode
;
316 ret
= drm_agp_info(dev
, &info
);
320 mode
.mode
= get_agp_mode(dev
, info
.mode
) & ~PCI_AGP_COMMAND_FW
;
321 ret
= drm_agp_enable(dev
, mode
);
326 saved_pci_nv_1
= nv_rd32(dev
, NV04_PBUS_PCI_NV_1
);
328 /* clear busmaster bit */
329 nv_wr32(dev
, NV04_PBUS_PCI_NV_1
, saved_pci_nv_1
& ~0x4);
331 nv_wr32(dev
, NV04_PBUS_PCI_NV_19
, 0);
333 /* power cycle pgraph, if enabled */
334 pmc_enable
= nv_rd32(dev
, NV03_PMC_ENABLE
);
335 if (pmc_enable
& NV_PMC_ENABLE_PGRAPH
) {
336 nv_wr32(dev
, NV03_PMC_ENABLE
,
337 pmc_enable
& ~NV_PMC_ENABLE_PGRAPH
);
338 nv_wr32(dev
, NV03_PMC_ENABLE
, nv_rd32(dev
, NV03_PMC_ENABLE
) |
339 NV_PMC_ENABLE_PGRAPH
);
342 /* and restore (gives effect of resetting AGP) */
343 nv_wr32(dev
, NV04_PBUS_PCI_NV_1
, saved_pci_nv_1
);
350 nouveau_mem_init_agp(struct drm_device
*dev
)
353 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
354 struct drm_agp_info info
;
355 struct drm_agp_mode mode
;
358 if (!dev
->agp
->acquired
) {
359 ret
= drm_agp_acquire(dev
);
361 NV_ERROR(dev
, "Unable to acquire AGP: %d\n", ret
);
366 nouveau_mem_reset_agp(dev
);
368 ret
= drm_agp_info(dev
, &info
);
370 NV_ERROR(dev
, "Unable to get AGP info: %d\n", ret
);
374 /* see agp.h for the AGPSTAT_* modes available */
375 mode
.mode
= get_agp_mode(dev
, info
.mode
);
376 ret
= drm_agp_enable(dev
, mode
);
378 NV_ERROR(dev
, "Unable to enable AGP: %d\n", ret
);
382 dev_priv
->gart_info
.type
= NOUVEAU_GART_AGP
;
383 dev_priv
->gart_info
.aper_base
= info
.aperture_base
;
384 dev_priv
->gart_info
.aper_size
= info
.aperture_size
;
390 nouveau_mem_vram_init(struct drm_device
*dev
)
392 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
393 struct ttm_bo_device
*bdev
= &dev_priv
->ttm
.bdev
;
396 if (dev_priv
->card_type
>= NV_50
&&
397 pci_dma_supported(dev
->pdev
, DMA_BIT_MASK(40)))
402 ret
= pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(dma_bits
));
406 dev_priv
->fb_phys
= pci_resource_start(dev
->pdev
, 1);
408 ret
= nouveau_ttm_global_init(dev_priv
);
412 ret
= ttm_bo_device_init(&dev_priv
->ttm
.bdev
,
413 dev_priv
->ttm
.bo_global_ref
.ref
.object
,
414 &nouveau_bo_driver
, DRM_FILE_PAGE_OFFSET
,
415 dma_bits
<= 32 ? true : false);
417 NV_ERROR(dev
, "Error initialising bo driver: %d\n", ret
);
421 /* reserve space at end of VRAM for PRAMIN */
422 if (dev_priv
->chipset
== 0x40 || dev_priv
->chipset
== 0x47 ||
423 dev_priv
->chipset
== 0x49 || dev_priv
->chipset
== 0x4b)
424 dev_priv
->ramin_rsvd_vram
= (2 * 1024 * 1024);
426 if (dev_priv
->card_type
>= NV_40
)
427 dev_priv
->ramin_rsvd_vram
= (1 * 1024 * 1024);
429 dev_priv
->ramin_rsvd_vram
= (512 * 1024);
431 ret
= dev_priv
->engine
.vram
.init(dev
);
435 NV_INFO(dev
, "Detected %dMiB VRAM\n", (int)(dev_priv
->vram_size
>> 20));
436 if (dev_priv
->vram_sys_base
) {
437 NV_INFO(dev
, "Stolen system memory at: 0x%010llx\n",
438 dev_priv
->vram_sys_base
);
441 dev_priv
->fb_available_size
= dev_priv
->vram_size
;
442 dev_priv
->fb_mappable_pages
= dev_priv
->fb_available_size
;
443 if (dev_priv
->fb_mappable_pages
> pci_resource_len(dev
->pdev
, 1))
444 dev_priv
->fb_mappable_pages
= pci_resource_len(dev
->pdev
, 1);
445 dev_priv
->fb_mappable_pages
>>= PAGE_SHIFT
;
447 dev_priv
->fb_available_size
-= dev_priv
->ramin_rsvd_vram
;
448 dev_priv
->fb_aper_free
= dev_priv
->fb_available_size
;
451 ret
= ttm_bo_init_mm(bdev
, TTM_PL_VRAM
,
452 dev_priv
->fb_available_size
>> PAGE_SHIFT
);
454 NV_ERROR(dev
, "Failed VRAM mm init: %d\n", ret
);
458 ret
= nouveau_bo_new(dev
, NULL
, 256*1024, 0, TTM_PL_FLAG_VRAM
,
459 0, 0, true, true, &dev_priv
->vga_ram
);
461 ret
= nouveau_bo_pin(dev_priv
->vga_ram
, TTM_PL_FLAG_VRAM
);
463 NV_WARN(dev
, "failed to reserve VGA memory\n");
464 nouveau_bo_ref(NULL
, &dev_priv
->vga_ram
);
467 dev_priv
->fb_mtrr
= drm_mtrr_add(pci_resource_start(dev
->pdev
, 1),
468 pci_resource_len(dev
->pdev
, 1),
474 nouveau_mem_gart_init(struct drm_device
*dev
)
476 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
477 struct ttm_bo_device
*bdev
= &dev_priv
->ttm
.bdev
;
480 dev_priv
->gart_info
.type
= NOUVEAU_GART_NONE
;
482 #if !defined(__powerpc__) && !defined(__ia64__)
483 if (drm_pci_device_is_agp(dev
) && dev
->agp
&& nouveau_agpmode
) {
484 ret
= nouveau_mem_init_agp(dev
);
486 NV_ERROR(dev
, "Error initialising AGP: %d\n", ret
);
490 if (dev_priv
->gart_info
.type
== NOUVEAU_GART_NONE
) {
491 ret
= nouveau_sgdma_init(dev
);
493 NV_ERROR(dev
, "Error initialising PCI(E): %d\n", ret
);
498 NV_INFO(dev
, "%d MiB GART (aperture)\n",
499 (int)(dev_priv
->gart_info
.aper_size
>> 20));
500 dev_priv
->gart_info
.aper_free
= dev_priv
->gart_info
.aper_size
;
502 ret
= ttm_bo_init_mm(bdev
, TTM_PL_TT
,
503 dev_priv
->gart_info
.aper_size
>> PAGE_SHIFT
);
505 NV_ERROR(dev
, "Failed TT mm init: %d\n", ret
);
513 nouveau_mem_timing_init(struct drm_device
*dev
)
515 /* cards < NVC0 only */
516 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
517 struct nouveau_pm_engine
*pm
= &dev_priv
->engine
.pm
;
518 struct nouveau_pm_memtimings
*memtimings
= &pm
->memtimings
;
519 struct nvbios
*bios
= &dev_priv
->vbios
;
521 u8 tUNK_0
, tUNK_1
, tUNK_2
;
523 u8 tRAS
; /* Byte 5 */
524 u8 tRFC
; /* Byte 7 */
526 u8 tUNK_10
, tUNK_11
, tUNK_12
, tUNK_13
, tUNK_14
;
527 u8 tUNK_18
, tUNK_19
, tUNK_20
, tUNK_21
;
528 u8
*mem
= NULL
, *entry
;
529 int i
, recordlen
, entries
;
531 if (bios
->type
== NVBIOS_BIT
) {
532 if (bit_table(dev
, 'P', &P
))
536 mem
= ROMPTR(bios
, P
.data
[4]);
539 mem
= ROMPTR(bios
, P
.data
[8]);
541 NV_WARN(dev
, "unknown mem for BIT P %d\n", P
.version
);
544 NV_DEBUG(dev
, "BMP version too old for memory\n");
549 NV_DEBUG(dev
, "memory timing table pointer invalid\n");
553 if (mem
[0] != 0x10) {
554 NV_WARN(dev
, "memory timing table 0x%02x unknown\n", mem
[0]);
558 /* validate record length */
561 if (recordlen
< 15) {
562 NV_ERROR(dev
, "mem timing table length unknown: %d\n", mem
[3]);
566 /* parse vbios entries into common format */
568 kcalloc(entries
, sizeof(*memtimings
->timing
), GFP_KERNEL
);
569 if (!memtimings
->timing
)
572 entry
= mem
+ mem
[1];
573 for (i
= 0; i
< entries
; i
++, entry
+= recordlen
) {
574 struct nouveau_pm_memtiming
*timing
= &pm
->memtimings
.timing
[i
];
582 switch (min(recordlen
, 22)) {
607 timing
->reg_100220
= (tRC
<< 24 | tRFC
<< 16 | tRAS
<< 8 | tRP
);
609 /* XXX: I don't trust the -1's and +1's... they must come
611 timing
->reg_100224
= ((tUNK_0
+ tUNK_19
+ 1) << 24 |
613 (tUNK_1
+ tUNK_19
+ 1) << 8 |
616 timing
->reg_100228
= (tUNK_12
<< 16 | tUNK_11
<< 8 | tUNK_10
);
618 timing
->reg_100228
+= (tUNK_19
- 1) << 24;
619 }/* I cannot back-up this else-statement right now
621 timing->reg_100228 += tUNK_12 << 24;
624 /* XXX: reg_10022c */
625 timing
->reg_10022c
= tUNK_2
- 1;
627 timing
->reg_100230
= (tUNK_20
<< 24 | tUNK_21
<< 16 |
628 tUNK_13
<< 8 | tUNK_13
);
631 timing
->reg_100234
= (tRAS
<< 24 | (tUNK_19
+ 6) << 8 | tRC
);
632 timing
->reg_100234
+= max(tUNK_10
,tUNK_11
) << 16;
634 /* XXX; reg_100238, reg_10023c
637 * 0 for pre-NV50 cards
638 * 0x????0202 for NV50+ cards (empirical evidence) */
639 if(dev_priv
->card_type
>= NV_50
) {
640 timing
->reg_10023c
= 0x202;
643 NV_DEBUG(dev
, "Entry %d: 220: %08x %08x %08x %08x\n", i
,
644 timing
->reg_100220
, timing
->reg_100224
,
645 timing
->reg_100228
, timing
->reg_10022c
);
646 NV_DEBUG(dev
, " 230: %08x %08x %08x %08x\n",
647 timing
->reg_100230
, timing
->reg_100234
,
648 timing
->reg_100238
, timing
->reg_10023c
);
651 memtimings
->nr_timing
= entries
;
652 memtimings
->supported
= true;
656 nouveau_mem_timing_fini(struct drm_device
*dev
)
658 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
659 struct nouveau_pm_memtimings
*mem
= &dev_priv
->engine
.pm
.memtimings
;
665 nouveau_vram_manager_init(struct ttm_mem_type_manager
*man
, unsigned long p_size
)
667 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(man
->bdev
);
668 struct nouveau_mm
*mm
;
672 p_size
= (p_size
<< PAGE_SHIFT
) >> 12;
673 b_size
= dev_priv
->vram_rblock_size
>> 12;
675 ret
= nouveau_mm_init(&mm
, 0, p_size
, b_size
);
684 nouveau_vram_manager_fini(struct ttm_mem_type_manager
*man
)
686 struct nouveau_mm
*mm
= man
->priv
;
689 ret
= nouveau_mm_fini(&mm
);
698 nouveau_vram_manager_del(struct ttm_mem_type_manager
*man
,
699 struct ttm_mem_reg
*mem
)
701 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(man
->bdev
);
702 struct nouveau_vram_engine
*vram
= &dev_priv
->engine
.vram
;
703 struct drm_device
*dev
= dev_priv
->dev
;
705 vram
->put(dev
, (struct nouveau_vram
**)&mem
->mm_node
);
709 nouveau_vram_manager_new(struct ttm_mem_type_manager
*man
,
710 struct ttm_buffer_object
*bo
,
711 struct ttm_placement
*placement
,
712 struct ttm_mem_reg
*mem
)
714 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(man
->bdev
);
715 struct nouveau_vram_engine
*vram
= &dev_priv
->engine
.vram
;
716 struct drm_device
*dev
= dev_priv
->dev
;
717 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
718 struct nouveau_vram
*node
;
722 if (nvbo
->tile_flags
& NOUVEAU_GEM_TILE_NONCONTIG
)
723 size_nc
= 1 << nvbo
->vma
.node
->type
;
725 ret
= vram
->get(dev
, mem
->num_pages
<< PAGE_SHIFT
,
726 mem
->page_alignment
<< PAGE_SHIFT
, size_nc
,
727 (nvbo
->tile_flags
>> 8) & 0xff, &node
);
731 node
->page_shift
= 12;
733 node
->page_shift
= nvbo
->vma
.node
->type
;
736 mem
->start
= node
->offset
>> PAGE_SHIFT
;
741 nouveau_vram_manager_debug(struct ttm_mem_type_manager
*man
, const char *prefix
)
743 struct nouveau_mm
*mm
= man
->priv
;
744 struct nouveau_mm_node
*r
;
745 u32 total
= 0, free
= 0;
747 mutex_lock(&mm
->mutex
);
748 list_for_each_entry(r
, &mm
->nodes
, nl_entry
) {
749 printk(KERN_DEBUG
"%s %d: 0x%010llx 0x%010llx\n",
750 prefix
, r
->type
, ((u64
)r
->offset
<< 12),
751 (((u64
)r
->offset
+ r
->length
) << 12));
757 mutex_unlock(&mm
->mutex
);
759 printk(KERN_DEBUG
"%s total: 0x%010llx free: 0x%010llx\n",
760 prefix
, (u64
)total
<< 12, (u64
)free
<< 12);
761 printk(KERN_DEBUG
"%s block: 0x%08x\n",
762 prefix
, mm
->block_size
<< 12);
765 const struct ttm_mem_type_manager_func nouveau_vram_manager
= {
766 nouveau_vram_manager_init
,
767 nouveau_vram_manager_fini
,
768 nouveau_vram_manager_new
,
769 nouveau_vram_manager_del
,
770 nouveau_vram_manager_debug