arch/x86/include/asm/amd_iommu_types.h

   1 /*
   2  * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <joerg.roedel@amd.com>
   4  *         Leo Duran <leo.duran@amd.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
  21 #define _ASM_X86_AMD_IOMMU_TYPES_H
  22
  23 #include <linux/types.h>
  24 #include <linux/list.h>
  25 #include <linux/spinlock.h>
  26
  27 /*
  28  * some size calculation constants
  29  */
  30 #define DEV_TABLE_ENTRY_SIZE            32
  31 #define ALIAS_TABLE_ENTRY_SIZE          2
  32 #define RLOOKUP_TABLE_ENTRY_SIZE        (sizeof(void *))
  33
  34 /* Length of the MMIO region for the AMD IOMMU */
  35 #define MMIO_REGION_LENGTH       0x4000
  36
  37 /* Capability offsets used by the driver */
  38 #define MMIO_CAP_HDR_OFFSET     0x00
  39 #define MMIO_RANGE_OFFSET       0x0c
  40 #define MMIO_MISC_OFFSET        0x10
  41
  42 /* Masks, shifts and macros to parse the device range capability */
  43 #define MMIO_RANGE_LD_MASK      0xff000000
  44 #define MMIO_RANGE_FD_MASK      0x00ff0000
  45 #define MMIO_RANGE_BUS_MASK     0x0000ff00
  46 #define MMIO_RANGE_LD_SHIFT     24
  47 #define MMIO_RANGE_FD_SHIFT     16
  48 #define MMIO_RANGE_BUS_SHIFT    8
  49 #define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
  50 #define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
  51 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
  52 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
  53
  54 /* Flag masks for the AMD IOMMU exclusion range */
  55 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
  56 #define MMIO_EXCL_ALLOW_MASK  0x02ULL
  57
  58 /* Used offsets into the MMIO space */
  59 #define MMIO_DEV_TABLE_OFFSET   0x0000
  60 #define MMIO_CMD_BUF_OFFSET     0x0008
  61 #define MMIO_EVT_BUF_OFFSET     0x0010
  62 #define MMIO_CONTROL_OFFSET     0x0018
  63 #define MMIO_EXCL_BASE_OFFSET   0x0020
  64 #define MMIO_EXCL_LIMIT_OFFSET  0x0028
  65 #define MMIO_CMD_HEAD_OFFSET    0x2000
  66 #define MMIO_CMD_TAIL_OFFSET    0x2008
  67 #define MMIO_EVT_HEAD_OFFSET    0x2010
  68 #define MMIO_EVT_TAIL_OFFSET    0x2018
  69 #define MMIO_STATUS_OFFSET      0x2020
  70
  71 /* MMIO status bits */
  72 #define MMIO_STATUS_COM_WAIT_INT_MASK   0x04
  73
  74 /* event logging constants */
  75 #define EVENT_ENTRY_SIZE        0x10
  76 #define EVENT_TYPE_SHIFT        28
  77 #define EVENT_TYPE_MASK         0xf
  78 #define EVENT_TYPE_ILL_DEV      0x1
  79 #define EVENT_TYPE_IO_FAULT     0x2
  80 #define EVENT_TYPE_DEV_TAB_ERR  0x3
  81 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
  82 #define EVENT_TYPE_ILL_CMD      0x5
  83 #define EVENT_TYPE_CMD_HARD_ERR 0x6
  84 #define EVENT_TYPE_IOTLB_INV_TO 0x7
  85 #define EVENT_TYPE_INV_DEV_REQ  0x8
  86 #define EVENT_DEVID_MASK        0xffff
  87 #define EVENT_DEVID_SHIFT       0
  88 #define EVENT_DOMID_MASK        0xffff
  89 #define EVENT_DOMID_SHIFT       0
  90 #define EVENT_FLAGS_MASK        0xfff
  91 #define EVENT_FLAGS_SHIFT       0x10
  92
  93 /* feature control bits */
  94 #define CONTROL_IOMMU_EN        0x00ULL
  95 #define CONTROL_HT_TUN_EN       0x01ULL
  96 #define CONTROL_EVT_LOG_EN      0x02ULL
  97 #define CONTROL_EVT_INT_EN      0x03ULL
  98 #define CONTROL_COMWAIT_EN      0x04ULL
  99 #define CONTROL_PASSPW_EN       0x08ULL
 100 #define CONTROL_RESPASSPW_EN    0x09ULL
 101 #define CONTROL_COHERENT_EN     0x0aULL
 102 #define CONTROL_ISOC_EN         0x0bULL
 103 #define CONTROL_CMDBUF_EN       0x0cULL
 104 #define CONTROL_PPFLOG_EN       0x0dULL
 105 #define CONTROL_PPFINT_EN       0x0eULL
 106
 107 /* command specific defines */
 108 #define CMD_COMPL_WAIT          0x01
 109 #define CMD_INV_DEV_ENTRY       0x02
 110 #define CMD_INV_IOMMU_PAGES     0x03
 111
 112 #define CMD_COMPL_WAIT_STORE_MASK       0x01
 113 #define CMD_COMPL_WAIT_INT_MASK         0x02
 114 #define CMD_INV_IOMMU_PAGES_SIZE_MASK   0x01
 115 #define CMD_INV_IOMMU_PAGES_PDE_MASK    0x02
 116
 117 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
 118
 119 /* macros and definitions for device table entries */
 120 #define DEV_ENTRY_VALID         0x00
 121 #define DEV_ENTRY_TRANSLATION   0x01
 122 #define DEV_ENTRY_IR            0x3d
 123 #define DEV_ENTRY_IW            0x3e
 124 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
 125 #define DEV_ENTRY_EX            0x67
 126 #define DEV_ENTRY_SYSMGT1       0x68
 127 #define DEV_ENTRY_SYSMGT2       0x69
 128 #define DEV_ENTRY_INIT_PASS     0xb8
 129 #define DEV_ENTRY_EINT_PASS     0xb9
 130 #define DEV_ENTRY_NMI_PASS      0xba
 131 #define DEV_ENTRY_LINT0_PASS    0xbe
 132 #define DEV_ENTRY_LINT1_PASS    0xbf
 133 #define DEV_ENTRY_MODE_MASK     0x07
 134 #define DEV_ENTRY_MODE_SHIFT    0x09
 135
 136 /* constants to configure the command buffer */
 137 #define CMD_BUFFER_SIZE    8192
 138 #define CMD_BUFFER_ENTRIES 512
 139 #define MMIO_CMD_SIZE_SHIFT 56
 140 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
 141
 142 /* constants for event buffer handling */
 143 #define EVT_BUFFER_SIZE         8192 /* 512 entries */
 144 #define EVT_LEN_MASK            (0x9ULL << 56)
 145
 146 #define PAGE_MODE_1_LEVEL 0x01
 147 #define PAGE_MODE_2_LEVEL 0x02
 148 #define PAGE_MODE_3_LEVEL 0x03
 149
 150 #define IOMMU_PDE_NL_0   0x000ULL
 151 #define IOMMU_PDE_NL_1   0x200ULL
 152 #define IOMMU_PDE_NL_2   0x400ULL
 153 #define IOMMU_PDE_NL_3   0x600ULL
 154
 155 #define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL)
 156 #define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL)
 157 #define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL)
 158
 159 #define IOMMU_MAP_SIZE_L1 (1ULL << 21)
 160 #define IOMMU_MAP_SIZE_L2 (1ULL << 30)
 161 #define IOMMU_MAP_SIZE_L3 (1ULL << 39)
 162
 163 #define IOMMU_PTE_P  (1ULL << 0)
 164 #define IOMMU_PTE_TV (1ULL << 1)
 165 #define IOMMU_PTE_U  (1ULL << 59)
 166 #define IOMMU_PTE_FC (1ULL << 60)
 167 #define IOMMU_PTE_IR (1ULL << 61)
 168 #define IOMMU_PTE_IW (1ULL << 62)
 169
 170 #define IOMMU_L1_PDE(address) \
 171         ((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
 172 #define IOMMU_L2_PDE(address) \
 173         ((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
 174
 175 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
 176 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
 177 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
 178 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
 179
 180 #define IOMMU_PROT_MASK 0x03
 181 #define IOMMU_PROT_IR 0x01
 182 #define IOMMU_PROT_IW 0x02
 183
 184 /* IOMMU capabilities */
 185 #define IOMMU_CAP_IOTLB   24
 186 #define IOMMU_CAP_NPCACHE 26
 187
 188 #define MAX_DOMAIN_ID 65536
 189
 190 /* FIXME: move this macro to <linux/pci.h> */
 191 #define PCI_BUS(x) (((x) >> 8) & 0xff)
 192
 193 /* Protection domain flags */
 194 #define PD_DMA_OPS_MASK         (1UL << 0) /* domain used for dma_ops */
 195 #define PD_DEFAULT_MASK         (1UL << 1) /* domain is a default dma_ops
 196                                               domain for an IOMMU */
 197 extern bool amd_iommu_dump;
 198 #define DUMP_printk(format, arg...)                                     \
 199         do {                                                            \
 200                 if (amd_iommu_dump)                                             \
 201                         printk(KERN_INFO "AMD IOMMU: " format, ## arg); \
 202         } while(0);
 203
 204 /*
 205  * Make iterating over all IOMMUs easier
 206  */
 207 #define for_each_iommu(iommu) \
 208         list_for_each_entry((iommu), &amd_iommu_list, list)
 209 #define for_each_iommu_safe(iommu, next) \
 210         list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
 211
 212 #define APERTURE_RANGE_SHIFT    27      /* 128 MB */
 213 #define APERTURE_RANGE_SIZE     (1ULL << APERTURE_RANGE_SHIFT)
 214 #define APERTURE_RANGE_PAGES    (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
 215 #define APERTURE_MAX_RANGES     32      /* allows 4GB of DMA address space */
 216 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
 217 #define APERTURE_PAGE_INDEX(a)  (((a) >> 21) & 0x3fULL)
 218
 219 /*
 220  * This structure contains generic data for  IOMMU protection domains
 221  * independent of their use.
 222  */
 223 struct protection_domain {
 224         spinlock_t lock;        /* mostly used to lock the page table*/
 225         u16 id;                 /* the domain id written to the device table */
 226         int mode;               /* paging mode (0-6 levels) */
 227         u64 *pt_root;           /* page table root pointer */
 228         unsigned long flags;    /* flags to find out type of domain */
 229         unsigned dev_cnt;       /* devices assigned to this domain */
 230         void *priv;             /* private data */
 231 };
 232
 233 /*
 234  * For dynamic growth the aperture size is split into ranges of 128MB of
 235  * DMA address space each. This struct represents one such range.
 236  */
 237 struct aperture_range {
 238
 239         /* address allocation bitmap */
 240         unsigned long *bitmap;
 241
 242         /*
 243          * Array of PTE pages for the aperture. In this array we save all the
 244          * leaf pages of the domain page table used for the aperture. This way
 245          * we don't need to walk the page table to find a specific PTE. We can
 246          * just calculate its address in constant time.
 247          */
 248         u64 *pte_pages[64];
 249
 250         unsigned long offset;
 251 };
 252
 253 /*
 254  * Data container for a dma_ops specific protection domain
 255  */
 256 struct dma_ops_domain {
 257         struct list_head list;
 258
 259         /* generic protection domain information */
 260         struct protection_domain domain;
 261
 262         /* size of the aperture for the mappings */
 263         unsigned long aperture_size;
 264
 265         /* address we start to search for free addresses */
 266         unsigned long next_address;
 267
 268         /* address space relevant data */
 269         struct aperture_range *aperture[APERTURE_MAX_RANGES];
 270
 271         /* This will be set to true when TLB needs to be flushed */
 272         bool need_flush;
 273
 274         /*
 275          * if this is a preallocated domain, keep the device for which it was
 276          * preallocated in this variable
 277          */
 278         u16 target_dev;
 279 };
 280
 281 /*
 282  * Structure where we save information about one hardware AMD IOMMU in the
 283  * system.
 284  */
 285 struct amd_iommu {
 286         struct list_head list;
 287
 288         /* locks the accesses to the hardware */
 289         spinlock_t lock;
 290
 291         /* Pointer to PCI device of this IOMMU */
 292         struct pci_dev *dev;
 293
 294         /* physical address of MMIO space */
 295         u64 mmio_phys;
 296         /* virtual address of MMIO space */
 297         u8 *mmio_base;
 298
 299         /* capabilities of that IOMMU read from ACPI */
 300         u32 cap;
 301
 302         /*
 303          * Capability pointer. There could be more than one IOMMU per PCI
 304          * device function if there are more than one AMD IOMMU capability
 305          * pointers.
 306          */
 307         u16 cap_ptr;
 308
 309         /* pci domain of this IOMMU */
 310         u16 pci_seg;
 311
 312         /* first device this IOMMU handles. read from PCI */
 313         u16 first_device;
 314         /* last device this IOMMU handles. read from PCI */
 315         u16 last_device;
 316
 317         /* start of exclusion range of that IOMMU */
 318         u64 exclusion_start;
 319         /* length of exclusion range of that IOMMU */
 320         u64 exclusion_length;
 321
 322         /* command buffer virtual address */
 323         u8 *cmd_buf;
 324         /* size of command buffer */
 325         u32 cmd_buf_size;
 326
 327         /* size of event buffer */
 328         u32 evt_buf_size;
 329         /* event buffer virtual address */
 330         u8 *evt_buf;
 331         /* MSI number for event interrupt */
 332         u16 evt_msi_num;
 333
 334         /* true if interrupts for this IOMMU are already enabled */
 335         bool int_enabled;
 336
 337         /* if one, we need to send a completion wait command */
 338         bool need_sync;
 339
 340         /* default dma_ops domain for that IOMMU */
 341         struct dma_ops_domain *default_dom;
 342 };
 343
 344 /*
 345  * List with all IOMMUs in the system. This list is not locked because it is
 346  * only written and read at driver initialization or suspend time
 347  */
 348 extern struct list_head amd_iommu_list;
 349
 350 /*
 351  * Structure defining one entry in the device table
 352  */
 353 struct dev_table_entry {
 354         u32 data[8];
 355 };
 356
 357 /*
 358  * One entry for unity mappings parsed out of the ACPI table.
 359  */
 360 struct unity_map_entry {
 361         struct list_head list;
 362
 363         /* starting device id this entry is used for (including) */
 364         u16 devid_start;
 365         /* end device id this entry is used for (including) */
 366         u16 devid_end;
 367
 368         /* start address to unity map (including) */
 369         u64 address_start;
 370         /* end address to unity map (including) */
 371         u64 address_end;
 372
 373         /* required protection */
 374         int prot;
 375 };
 376
 377 /*
 378  * List of all unity mappings. It is not locked because as runtime it is only
 379  * read. It is created at ACPI table parsing time.
 380  */
 381 extern struct list_head amd_iommu_unity_map;
 382
 383 /*
 384  * Data structures for device handling
 385  */
 386
 387 /*
 388  * Device table used by hardware. Read and write accesses by software are
 389  * locked with the amd_iommu_pd_table lock.
 390  */
 391 extern struct dev_table_entry *amd_iommu_dev_table;
 392
 393 /*
 394  * Alias table to find requestor ids to device ids. Not locked because only
 395  * read on runtime.
 396  */
 397 extern u16 *amd_iommu_alias_table;
 398
 399 /*
 400  * Reverse lookup table to find the IOMMU which translates a specific device.
 401  */
 402 extern struct amd_iommu **amd_iommu_rlookup_table;
 403
 404 /* size of the dma_ops aperture as power of 2 */
 405 extern unsigned amd_iommu_aperture_order;
 406
 407 /* largest PCI device id we expect translation requests for */
 408 extern u16 amd_iommu_last_bdf;
 409
 410 /* data structures for protection domain handling */
 411 extern struct protection_domain **amd_iommu_pd_table;
 412
 413 /* allocation bitmap for domain ids */
 414 extern unsigned long *amd_iommu_pd_alloc_bitmap;
 415
 416 /* will be 1 if device isolation is enabled */
 417 extern bool amd_iommu_isolate;
 418
 419 /*
 420  * If true, the addresses will be flushed on unmap time, not when
 421  * they are reused
 422  */
 423 extern bool amd_iommu_unmap_flush;
 424
 425 /* takes bus and device/function and returns the device id
 426  * FIXME: should that be in generic PCI code? */
 427 static inline u16 calc_devid(u8 bus, u8 devfn)
 428 {
 429         return (((u16)bus) << 8) | devfn;
 430 }
 431
 432 #ifdef CONFIG_AMD_IOMMU_STATS
 433
 434 struct __iommu_counter {
 435         char *name;
 436         struct dentry *dent;
 437         u64 value;
 438 };
 439
 440 #define DECLARE_STATS_COUNTER(nm) \
 441         static struct __iommu_counter nm = {    \
 442                 .name = #nm,                    \
 443         }
 444
 445 #define INC_STATS_COUNTER(name)         name.value += 1
 446 #define ADD_STATS_COUNTER(name, x)      name.value += (x)
 447 #define SUB_STATS_COUNTER(name, x)      name.value -= (x)
 448
 449 #else /* CONFIG_AMD_IOMMU_STATS */
 450
 451 #define DECLARE_STATS_COUNTER(name)
 452 #define INC_STATS_COUNTER(name)
 453 #define ADD_STATS_COUNTER(name, x)
 454 #define SUB_STATS_COUNTER(name, x)
 455
 456 static inline void amd_iommu_stats_init(void) { }
 457
 458 #endif /* CONFIG_AMD_IOMMU_STATS */
 459
 460 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */