2 * linux/drivers/ide/pci/cmd64x.c Version 1.50 May 10, 2007
4 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
5 * Due to massive hardware bugs, UltraDMA is only supported
6 * on the 646U2 and not on the 646U.
8 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
11 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/hdreg.h>
20 #include <linux/ide.h>
21 #include <linux/init.h>
25 #define DISPLAY_CMD64X_TIMINGS
30 #define cmdprintk(x...) printk(x)
32 #define cmdprintk(x...)
36 * CMD64x specific registers definition.
39 #define CFR_INTR_CH0 0x04
41 #define CNTRL_ENA_1ST 0x04
42 #define CNTRL_ENA_2ND 0x08
43 #define CNTRL_DIS_RA0 0x40
44 #define CNTRL_DIS_RA1 0x80
52 #define ARTTIM23_DIS_RA2 0x04
53 #define ARTTIM23_DIS_RA3 0x08
54 #define ARTTIM23_INTR_CH1 0x10
61 #define MRDMODE_INTR_CH0 0x04
62 #define MRDMODE_INTR_CH1 0x08
63 #define MRDMODE_BLK_CH0 0x10
64 #define MRDMODE_BLK_CH1 0x20
66 #define UDIDETCR0 0x73
71 #define UDIDETCR1 0x7B
74 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
75 #include <linux/stat.h>
76 #include <linux/proc_fs.h>
78 static u8 cmd64x_proc
= 0;
80 #define CMD_MAX_DEVS 5
82 static struct pci_dev
*cmd_devs
[CMD_MAX_DEVS
];
83 static int n_cmd_devs
;
85 static char * print_cmd64x_get_info (char *buf
, struct pci_dev
*dev
, int index
)
88 u8 reg72
= 0, reg73
= 0; /* primary */
89 u8 reg7a
= 0, reg7b
= 0; /* secondary */
90 u8 reg50
= 1, reg51
= 1, reg57
= 0, reg71
= 0; /* extra */
93 p
+= sprintf(p
, "\nController: %d\n", index
);
94 p
+= sprintf(p
, "PCI-%x Chipset.\n", dev
->device
);
96 (void) pci_read_config_byte(dev
, CFR
, ®50
);
97 (void) pci_read_config_byte(dev
, CNTRL
, ®51
);
98 (void) pci_read_config_byte(dev
, ARTTIM23
, ®57
);
99 (void) pci_read_config_byte(dev
, MRDMODE
, ®71
);
100 (void) pci_read_config_byte(dev
, BMIDESR0
, ®72
);
101 (void) pci_read_config_byte(dev
, UDIDETCR0
, ®73
);
102 (void) pci_read_config_byte(dev
, BMIDESR1
, ®7a
);
103 (void) pci_read_config_byte(dev
, UDIDETCR1
, ®7b
);
105 /* PCI0643/6 originally didn't have the primary channel enable bit */
106 (void) pci_read_config_byte(dev
, PCI_REVISION_ID
, &rev
);
107 if ((dev
->device
== PCI_DEVICE_ID_CMD_643
) ||
108 (dev
->device
== PCI_DEVICE_ID_CMD_646
&& rev
< 3))
109 reg51
|= CNTRL_ENA_1ST
;
111 p
+= sprintf(p
, "---------------- Primary Channel "
112 "---------------- Secondary Channel ------------\n");
113 p
+= sprintf(p
, " %s %s\n",
114 (reg51
& CNTRL_ENA_1ST
) ? "enabled " : "disabled",
115 (reg51
& CNTRL_ENA_2ND
) ? "enabled " : "disabled");
116 p
+= sprintf(p
, "---------------- drive0 --------- drive1 "
117 "-------- drive0 --------- drive1 ------\n");
118 p
+= sprintf(p
, "DMA enabled: %s %s"
120 (reg72
& 0x20) ? "yes" : "no ", (reg72
& 0x40) ? "yes" : "no ",
121 (reg7a
& 0x20) ? "yes" : "no ", (reg7a
& 0x40) ? "yes" : "no ");
122 p
+= sprintf(p
, "UltraDMA mode: %s (%c) %s (%c)",
123 ( reg73
& 0x01) ? " on" : "off",
124 ((reg73
& 0x30) == 0x30) ? ((reg73
& 0x04) ? '3' : '0') :
125 ((reg73
& 0x30) == 0x20) ? ((reg73
& 0x04) ? '3' : '1') :
126 ((reg73
& 0x30) == 0x10) ? ((reg73
& 0x04) ? '4' : '2') :
127 ((reg73
& 0x30) == 0x00) ? ((reg73
& 0x04) ? '5' : '2') : '?',
128 ( reg73
& 0x02) ? " on" : "off",
129 ((reg73
& 0xC0) == 0xC0) ? ((reg73
& 0x08) ? '3' : '0') :
130 ((reg73
& 0xC0) == 0x80) ? ((reg73
& 0x08) ? '3' : '1') :
131 ((reg73
& 0xC0) == 0x40) ? ((reg73
& 0x08) ? '4' : '2') :
132 ((reg73
& 0xC0) == 0x00) ? ((reg73
& 0x08) ? '5' : '2') : '?');
133 p
+= sprintf(p
, " %s (%c) %s (%c)\n",
134 ( reg7b
& 0x01) ? " on" : "off",
135 ((reg7b
& 0x30) == 0x30) ? ((reg7b
& 0x04) ? '3' : '0') :
136 ((reg7b
& 0x30) == 0x20) ? ((reg7b
& 0x04) ? '3' : '1') :
137 ((reg7b
& 0x30) == 0x10) ? ((reg7b
& 0x04) ? '4' : '2') :
138 ((reg7b
& 0x30) == 0x00) ? ((reg7b
& 0x04) ? '5' : '2') : '?',
139 ( reg7b
& 0x02) ? " on" : "off",
140 ((reg7b
& 0xC0) == 0xC0) ? ((reg7b
& 0x08) ? '3' : '0') :
141 ((reg7b
& 0xC0) == 0x80) ? ((reg7b
& 0x08) ? '3' : '1') :
142 ((reg7b
& 0xC0) == 0x40) ? ((reg7b
& 0x08) ? '4' : '2') :
143 ((reg7b
& 0xC0) == 0x00) ? ((reg7b
& 0x08) ? '5' : '2') : '?');
144 p
+= sprintf(p
, "Interrupt: %s, %s %s, %s\n",
145 (reg71
& MRDMODE_BLK_CH0
) ? "blocked" : "enabled",
146 (reg50
& CFR_INTR_CH0
) ? "pending" : "clear ",
147 (reg71
& MRDMODE_BLK_CH1
) ? "blocked" : "enabled",
148 (reg57
& ARTTIM23_INTR_CH1
) ? "pending" : "clear ");
153 static int cmd64x_get_info (char *buffer
, char **addr
, off_t offset
, int count
)
158 for (i
= 0; i
< n_cmd_devs
; i
++) {
159 struct pci_dev
*dev
= cmd_devs
[i
];
160 p
= print_cmd64x_get_info(p
, dev
, i
);
162 return p
-buffer
; /* => must be less than 4k! */
165 #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
167 static u8
quantize_timing(int timing
, int quant
)
169 return (timing
+ quant
- 1) / quant
;
173 * This routine calculates active/recovery counts and then writes them into
174 * the chipset registers.
176 static void program_cycle_times (ide_drive_t
*drive
, int cycle_time
, int active_time
)
178 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
179 int clock_time
= 1000 / system_bus_clock();
180 u8 cycle_count
, active_count
, recovery_count
, drwtim
;
181 static const u8 recovery_values
[] =
182 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
183 static const u8 drwtim_regs
[4] = {DRWTIM0
, DRWTIM1
, DRWTIM2
, DRWTIM3
};
185 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
186 cycle_time
, active_time
);
188 cycle_count
= quantize_timing( cycle_time
, clock_time
);
189 active_count
= quantize_timing(active_time
, clock_time
);
190 recovery_count
= cycle_count
- active_count
;
193 * In case we've got too long recovery phase, try to lengthen
196 if (recovery_count
> 16) {
197 active_count
+= recovery_count
- 16;
200 if (active_count
> 16) /* shouldn't actually happen... */
203 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
204 cycle_count
, active_count
, recovery_count
);
207 * Convert values to internal chipset representation
209 recovery_count
= recovery_values
[recovery_count
];
210 active_count
&= 0x0f;
212 /* Program the active/recovery counts into the DRWTIM register */
213 drwtim
= (active_count
<< 4) | recovery_count
;
214 (void) pci_write_config_byte(dev
, drwtim_regs
[drive
->dn
], drwtim
);
215 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim
, drwtim_regs
[drive
->dn
]);
219 * This routine selects drive's best PIO mode and writes into the chipset
220 * registers setup/active/recovery timings.
222 static u8
cmd64x_tune_pio (ide_drive_t
*drive
, u8 mode_wanted
)
224 ide_hwif_t
*hwif
= HWIF(drive
);
225 struct pci_dev
*dev
= hwif
->pci_dev
;
227 u8 pio_mode
, setup_count
, arttim
= 0;
228 static const u8 setup_values
[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
229 static const u8 arttim_regs
[4] = {ARTTIM0
, ARTTIM1
, ARTTIM23
, ARTTIM23
};
230 pio_mode
= ide_get_best_pio_mode(drive
, mode_wanted
, 5, &pio
);
232 cmdprintk("%s: PIO mode wanted %d, selected %d (%d ns)%s\n",
233 drive
->name
, mode_wanted
, pio_mode
, pio
.cycle_time
,
234 pio
.overridden
? " (overriding vendor mode)" : "");
236 program_cycle_times(drive
, pio
.cycle_time
,
237 ide_pio_timings
[pio_mode
].active_time
);
239 setup_count
= quantize_timing(ide_pio_timings
[pio_mode
].setup_time
,
240 1000 / system_bus_clock());
243 * The primary channel has individual address setup timing registers
244 * for each drive and the hardware selects the slowest timing itself.
245 * The secondary channel has one common register and we have to select
246 * the slowest address setup timing ourselves.
249 ide_drive_t
*drives
= hwif
->drives
;
251 drive
->drive_data
= setup_count
;
252 setup_count
= max(drives
[0].drive_data
, drives
[1].drive_data
);
255 if (setup_count
> 5) /* shouldn't actually happen... */
257 cmdprintk("Final address setup count: %d\n", setup_count
);
260 * Program the address setup clocks into the ARTTIM registers.
261 * Avoid clearing the secondary channel's interrupt bit.
263 (void) pci_read_config_byte (dev
, arttim_regs
[drive
->dn
], &arttim
);
265 arttim
&= ~ARTTIM23_INTR_CH1
;
267 arttim
|= setup_values
[setup_count
];
268 (void) pci_write_config_byte(dev
, arttim_regs
[drive
->dn
], arttim
);
269 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim
, arttim_regs
[drive
->dn
]);
275 * Attempts to set drive's PIO mode.
276 * Special cases are 8: prefetch off, 9: prefetch on (both never worked),
277 * and 255: auto-select best mode (used at boot time).
279 static void cmd64x_tune_drive (ide_drive_t
*drive
, u8 pio
)
282 * Filter out the prefetch control values
283 * to prevent PIO5 from being programmed
285 if (pio
== 8 || pio
== 9)
288 pio
= cmd64x_tune_pio(drive
, pio
);
289 (void) ide_config_drive_speed(drive
, XFER_PIO_0
+ pio
);
292 static int cmd64x_tune_chipset (ide_drive_t
*drive
, u8 speed
)
294 ide_hwif_t
*hwif
= HWIF(drive
);
295 struct pci_dev
*dev
= hwif
->pci_dev
;
296 u8 unit
= drive
->dn
& 0x01;
297 u8 regU
= 0, pciU
= hwif
->channel
? UDIDETCR1
: UDIDETCR0
;
299 speed
= ide_rate_filter(drive
, speed
);
301 if (speed
>= XFER_SW_DMA_0
) {
302 (void) pci_read_config_byte(dev
, pciU
, ®U
);
303 regU
&= ~(unit
? 0xCA : 0x35);
308 regU
|= unit
? 0x0A : 0x05;
311 regU
|= unit
? 0x4A : 0x15;
314 regU
|= unit
? 0x8A : 0x25;
317 regU
|= unit
? 0x42 : 0x11;
320 regU
|= unit
? 0x82 : 0x21;
323 regU
|= unit
? 0xC2 : 0x31;
326 program_cycle_times(drive
, 120, 70);
329 program_cycle_times(drive
, 150, 80);
332 program_cycle_times(drive
, 480, 215);
340 (void) cmd64x_tune_pio(drive
, speed
- XFER_PIO_0
);
346 if (speed
>= XFER_SW_DMA_0
)
347 (void) pci_write_config_byte(dev
, pciU
, regU
);
349 return ide_config_drive_speed(drive
, speed
);
352 static int cmd64x_config_drive_for_dma (ide_drive_t
*drive
)
354 if (ide_tune_dma(drive
))
357 if (ide_use_fast_pio(drive
))
358 cmd64x_tune_drive(drive
, 255);
363 static int cmd648_ide_dma_end (ide_drive_t
*drive
)
365 ide_hwif_t
*hwif
= HWIF(drive
);
366 int err
= __ide_dma_end(drive
);
367 u8 irq_mask
= hwif
->channel
? MRDMODE_INTR_CH1
:
369 u8 mrdmode
= inb(hwif
->dma_master
+ 0x01);
371 /* clear the interrupt bit */
372 outb(mrdmode
| irq_mask
, hwif
->dma_master
+ 0x01);
377 static int cmd64x_ide_dma_end (ide_drive_t
*drive
)
379 ide_hwif_t
*hwif
= HWIF(drive
);
380 struct pci_dev
*dev
= hwif
->pci_dev
;
381 int irq_reg
= hwif
->channel
? ARTTIM23
: CFR
;
382 u8 irq_mask
= hwif
->channel
? ARTTIM23_INTR_CH1
:
385 int err
= __ide_dma_end(drive
);
387 (void) pci_read_config_byte(dev
, irq_reg
, &irq_stat
);
388 /* clear the interrupt bit */
389 (void) pci_write_config_byte(dev
, irq_reg
, irq_stat
| irq_mask
);
394 static int cmd648_ide_dma_test_irq (ide_drive_t
*drive
)
396 ide_hwif_t
*hwif
= HWIF(drive
);
397 u8 irq_mask
= hwif
->channel
? MRDMODE_INTR_CH1
:
399 u8 dma_stat
= inb(hwif
->dma_status
);
400 u8 mrdmode
= inb(hwif
->dma_master
+ 0x01);
403 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
404 drive
->name
, dma_stat
, mrdmode
, irq_mask
);
406 if (!(mrdmode
& irq_mask
))
409 /* return 1 if INTR asserted */
416 static int cmd64x_ide_dma_test_irq (ide_drive_t
*drive
)
418 ide_hwif_t
*hwif
= HWIF(drive
);
419 struct pci_dev
*dev
= hwif
->pci_dev
;
420 int irq_reg
= hwif
->channel
? ARTTIM23
: CFR
;
421 u8 irq_mask
= hwif
->channel
? ARTTIM23_INTR_CH1
:
423 u8 dma_stat
= inb(hwif
->dma_status
);
426 (void) pci_read_config_byte(dev
, irq_reg
, &irq_stat
);
429 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
430 drive
->name
, dma_stat
, irq_stat
, irq_mask
);
432 if (!(irq_stat
& irq_mask
))
435 /* return 1 if INTR asserted */
443 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
444 * event order for DMA transfers.
447 static int cmd646_1_ide_dma_end (ide_drive_t
*drive
)
449 ide_hwif_t
*hwif
= HWIF(drive
);
450 u8 dma_stat
= 0, dma_cmd
= 0;
452 drive
->waiting_for_dma
= 0;
454 dma_stat
= inb(hwif
->dma_status
);
455 /* read DMA command state */
456 dma_cmd
= inb(hwif
->dma_command
);
458 outb(dma_cmd
& ~1, hwif
->dma_command
);
459 /* clear the INTR & ERROR bits */
460 outb(dma_stat
| 6, hwif
->dma_status
);
461 /* and free any DMA resources */
462 ide_destroy_dmatable(drive
);
463 /* verify good DMA status */
464 return (dma_stat
& 7) != 4;
467 static unsigned int __devinit
init_chipset_cmd64x(struct pci_dev
*dev
, const char *name
)
471 if (dev
->device
== PCI_DEVICE_ID_CMD_646
) {
474 pci_read_config_byte(dev
, PCI_REVISION_ID
, &rev
);
479 printk("%s: UltraDMA capable", name
);
483 printk("%s: MultiWord DMA force limited", name
);
486 printk("%s: MultiWord DMA limited, "
487 "IRQ workaround enabled\n", name
);
492 /* Set a good latency timer and cache line size value. */
493 (void) pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 64);
494 /* FIXME: pci_set_master() to ensure a good latency timer value */
497 * Enable interrupts, select MEMORY READ LINE for reads.
499 * NOTE: although not mentioned in the PCI0646U specs,
500 * bits 0-1 are write only and won't be read back as
501 * set or not -- PCI0646U2 specs clarify this point.
503 (void) pci_read_config_byte (dev
, MRDMODE
, &mrdmode
);
505 (void) pci_write_config_byte(dev
, MRDMODE
, (mrdmode
| 0x02));
507 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
509 cmd_devs
[n_cmd_devs
++] = dev
;
513 ide_pci_create_host_proc("cmd64x", cmd64x_get_info
);
515 #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_IDE_PROC_FS */
520 static unsigned int __devinit
ata66_cmd64x(ide_hwif_t
*hwif
)
522 struct pci_dev
*dev
= hwif
->pci_dev
;
523 u8 bmidecsr
= 0, mask
= hwif
->channel
? 0x02 : 0x01;
525 switch (dev
->device
) {
526 case PCI_DEVICE_ID_CMD_648
:
527 case PCI_DEVICE_ID_CMD_649
:
528 pci_read_config_byte(dev
, BMIDECSR
, &bmidecsr
);
529 return (bmidecsr
& mask
) ? 1 : 0;
535 static void __devinit
init_hwif_cmd64x(ide_hwif_t
*hwif
)
537 struct pci_dev
*dev
= hwif
->pci_dev
;
540 pci_read_config_byte(dev
, PCI_REVISION_ID
, &rev
);
542 hwif
->tuneproc
= &cmd64x_tune_drive
;
543 hwif
->speedproc
= &cmd64x_tune_chipset
;
545 hwif
->drives
[0].autotune
= hwif
->drives
[1].autotune
= 1;
551 hwif
->mwdma_mask
= 0x07;
552 hwif
->ultra_mask
= hwif
->cds
->udma_mask
;
555 * UltraDMA only supported on PCI646U and PCI646U2, which
556 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
557 * Actually, although the CMD tech support people won't
558 * tell me the details, the 0x03 revision cannot support
559 * UDMA correctly without hardware modifications, and even
560 * then it only works with Quantum disks due to some
561 * hold time assumptions in the 646U part which are fixed
564 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
566 if (dev
->device
== PCI_DEVICE_ID_CMD_646
&& rev
< 5)
567 hwif
->ultra_mask
= 0x00;
569 hwif
->ide_dma_check
= &cmd64x_config_drive_for_dma
;
571 if (!hwif
->udma_four
)
572 hwif
->udma_four
= ata66_cmd64x(hwif
);
574 switch (dev
->device
) {
575 case PCI_DEVICE_ID_CMD_648
:
576 case PCI_DEVICE_ID_CMD_649
:
578 hwif
->ide_dma_end
= &cmd648_ide_dma_end
;
579 hwif
->ide_dma_test_irq
= &cmd648_ide_dma_test_irq
;
581 case PCI_DEVICE_ID_CMD_646
:
582 hwif
->chipset
= ide_cmd646
;
584 hwif
->ide_dma_end
= &cmd646_1_ide_dma_end
;
586 } else if (rev
>= 0x03)
590 hwif
->ide_dma_end
= &cmd64x_ide_dma_end
;
591 hwif
->ide_dma_test_irq
= &cmd64x_ide_dma_test_irq
;
597 hwif
->drives
[0].autodma
= hwif
->drives
[1].autodma
= hwif
->autodma
;
600 static int __devinit
init_setup_cmd64x(struct pci_dev
*dev
, ide_pci_device_t
*d
)
602 return ide_setup_pci_device(dev
, d
);
605 static int __devinit
init_setup_cmd646(struct pci_dev
*dev
, ide_pci_device_t
*d
)
610 * The original PCI0646 didn't have the primary channel enable bit,
611 * it appeared starting with PCI0646U (i.e. revision ID 3).
613 pci_read_config_byte(dev
, PCI_REVISION_ID
, &rev
);
615 d
->enablebits
[0].reg
= 0;
617 return ide_setup_pci_device(dev
, d
);
620 static ide_pci_device_t cmd64x_chipsets
[] __devinitdata
= {
623 .init_setup
= init_setup_cmd64x
,
624 .init_chipset
= init_chipset_cmd64x
,
625 .init_hwif
= init_hwif_cmd64x
,
628 .enablebits
= {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
629 .bootable
= ON_BOARD
,
630 .udma_mask
= 0x00, /* no udma */
633 .init_setup
= init_setup_cmd646
,
634 .init_chipset
= init_chipset_cmd64x
,
635 .init_hwif
= init_hwif_cmd64x
,
638 .enablebits
= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
639 .bootable
= ON_BOARD
,
640 .udma_mask
= 0x07, /* udma0-2 */
643 .init_setup
= init_setup_cmd64x
,
644 .init_chipset
= init_chipset_cmd64x
,
645 .init_hwif
= init_hwif_cmd64x
,
648 .enablebits
= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
649 .bootable
= ON_BOARD
,
650 .udma_mask
= 0x1f, /* udma0-4 */
653 .init_setup
= init_setup_cmd64x
,
654 .init_chipset
= init_chipset_cmd64x
,
655 .init_hwif
= init_hwif_cmd64x
,
658 .enablebits
= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
659 .bootable
= ON_BOARD
,
660 .udma_mask
= 0x3f, /* udma0-5 */
665 * We may have to modify enablebits for PCI0646, so we'd better pass
666 * a local copy of the ide_pci_device_t structure down the call chain...
668 static int __devinit
cmd64x_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
670 ide_pci_device_t d
= cmd64x_chipsets
[id
->driver_data
];
672 return d
.init_setup(dev
, &d
);
675 static struct pci_device_id cmd64x_pci_tbl
[] = {
676 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_CMD_643
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
677 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_CMD_646
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 1},
678 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_CMD_648
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 2},
679 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_CMD_649
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 3},
682 MODULE_DEVICE_TABLE(pci
, cmd64x_pci_tbl
);
684 static struct pci_driver driver
= {
685 .name
= "CMD64x_IDE",
686 .id_table
= cmd64x_pci_tbl
,
687 .probe
= cmd64x_init_one
,
690 static int __init
cmd64x_ide_init(void)
692 return ide_pci_register_driver(&driver
);
695 module_init(cmd64x_ide_init
);
697 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
698 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
699 MODULE_LICENSE("GPL");