| blob | 91cc8cbdd440dd8f2f7ce8da0c653e221f014e13 |
1 /*
2 * File Name:
3 * defxx.c
4 *
5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996.
7 *
8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License, incorporated herein by reference.
10 *
11 * Abstract:
12 * A Linux device driver supporting the Digital Equipment Corporation
13 * FDDI EISA and PCI controller families. Supported adapters include:
14 *
15 * DEC FDDIcontroller/EISA (DEFEA)
16 * DEC FDDIcontroller/PCI (DEFPA)
17 *
18 * The original author:
19 * LVS Lawrence V. Stefani <lstefani@yahoo.com>
20 *
21 * Maintainers:
22 * macro Maciej W. Rozycki <macro@linux-mips.org>
23 *
24 * Credits:
25 * I'd like to thank Patricia Cross for helping me get started with
26 * Linux, David Davies for a lot of help upgrading and configuring
27 * my development system and for answering many OS and driver
28 * development questions, and Alan Cox for recommendations and
29 * integration help on getting FDDI support into Linux. LVS
30 *
31 * Driver Architecture:
32 * The driver architecture is largely based on previous driver work
33 * for other operating systems. The upper edge interface and
34 * functions were largely taken from existing Linux device drivers
35 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
36 * driver.
37 *
38 * Adapter Probe -
39 * The driver scans for supported EISA adapters by reading the
40 * SLOT ID register for each EISA slot and making a match
41 * against the expected value.
42 *
43 * Bus-Specific Initialization -
44 * This driver currently supports both EISA and PCI controller
45 * families. While the custom DMA chip and FDDI logic is similar
46 * or identical, the bus logic is very different. After
47 * initialization, the only bus-specific differences is in how the
48 * driver enables and disables interrupts. Other than that, the
49 * run-time critical code behaves the same on both families.
50 * It's important to note that both adapter families are configured
51 * to I/O map, rather than memory map, the adapter registers.
52 *
53 * Driver Open/Close -
54 * In the driver open routine, the driver ISR (interrupt service
55 * routine) is registered and the adapter is brought to an
56 * operational state. In the driver close routine, the opposite
57 * occurs; the driver ISR is deregistered and the adapter is
58 * brought to a safe, but closed state. Users may use consecutive
59 * commands to bring the adapter up and down as in the following
60 * example:
61 * ifconfig fddi0 up
62 * ifconfig fddi0 down
63 * ifconfig fddi0 up
64 *
65 * Driver Shutdown -
66 * Apparently, there is no shutdown or halt routine support under
67 * Linux. This routine would be called during "reboot" or
68 * "shutdown" to allow the driver to place the adapter in a safe
69 * state before a warm reboot occurs. To be really safe, the user
70 * should close the adapter before shutdown (eg. ifconfig fddi0 down)
71 * to ensure that the adapter DMA engine is taken off-line. However,
72 * the current driver code anticipates this problem and always issues
73 * a soft reset of the adapter at the beginning of driver initialization.
74 * A future driver enhancement in this area may occur in 2.1.X where
75 * Alan indicated that a shutdown handler may be implemented.
76 *
77 * Interrupt Service Routine -
78 * The driver supports shared interrupts, so the ISR is registered for
79 * each board with the appropriate flag and the pointer to that board's
80 * device structure. This provides the context during interrupt
81 * processing to support shared interrupts and multiple boards.
82 *
83 * Interrupt enabling/disabling can occur at many levels. At the host
84 * end, you can disable system interrupts, or disable interrupts at the
85 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
86 * have a bus-logic chip interrupt enable/disable as well as a DMA
87 * controller interrupt enable/disable.
88 *
89 * The driver currently enables and disables adapter interrupts at the
90 * bus-logic chip and assumes that Linux will take care of clearing or
91 * acknowledging any host-based interrupt chips.
92 *
93 * Control Functions -
94 * Control functions are those used to support functions such as adding
95 * or deleting multicast addresses, enabling or disabling packet
96 * reception filters, or other custom/proprietary commands. Presently,
97 * the driver supports the "get statistics", "set multicast list", and
98 * "set mac address" functions defined by Linux. A list of possible
99 * enhancements include:
100 *
101 * - Custom ioctl interface for executing port interface commands
102 * - Custom ioctl interface for adding unicast addresses to
103 * adapter CAM (to support bridge functions).
104 * - Custom ioctl interface for supporting firmware upgrades.
105 *
106 * Hardware (port interface) Support Routines -
107 * The driver function names that start with "dfx_hw_" represent
108 * low-level port interface routines that are called frequently. They
109 * include issuing a DMA or port control command to the adapter,
110 * resetting the adapter, or reading the adapter state. Since the
111 * driver initialization and run-time code must make calls into the
112 * port interface, these routines were written to be as generic and
113 * usable as possible.
114 *
115 * Receive Path -
116 * The adapter DMA engine supports a 256 entry receive descriptor block
117 * of which up to 255 entries can be used at any given time. The
118 * architecture is a standard producer, consumer, completion model in
119 * which the driver "produces" receive buffers to the adapter, the
120 * adapter "consumes" the receive buffers by DMAing incoming packet data,
121 * and the driver "completes" the receive buffers by servicing the
122 * incoming packet, then "produces" a new buffer and starts the cycle
123 * again. Receive buffers can be fragmented in up to 16 fragments
124 * (descriptor entries). For simplicity, this driver posts
125 * single-fragment receive buffers of 4608 bytes, then allocates a
126 * sk_buff, copies the data, then reposts the buffer. To reduce CPU
127 * utilization, a better approach would be to pass up the receive
128 * buffer (no extra copy) then allocate and post a replacement buffer.
129 * This is a performance enhancement that should be looked into at
130 * some point.
131 *
132 * Transmit Path -
133 * Like the receive path, the adapter DMA engine supports a 256 entry
134 * transmit descriptor block of which up to 255 entries can be used at
135 * any given time. Transmit buffers can be fragmented in up to 255
136 * fragments (descriptor entries). This driver always posts one
137 * fragment per transmit packet request.
138 *
139 * The fragment contains the entire packet from FC to end of data.
140 * Before posting the buffer to the adapter, the driver sets a three-byte
141 * packet request header (PRH) which is required by the Motorola MAC chip
142 * used on the adapters. The PRH tells the MAC the type of token to
143 * receive/send, whether or not to generate and append the CRC, whether
144 * synchronous or asynchronous framing is used, etc. Since the PRH
145 * definition is not necessarily consistent across all FDDI chipsets,
146 * the driver, rather than the common FDDI packet handler routines,
147 * sets these bytes.
148 *
149 * To reduce the amount of descriptor fetches needed per transmit request,
150 * the driver takes advantage of the fact that there are at least three
151 * bytes available before the skb->data field on the outgoing transmit
152 * request. This is guaranteed by having fddi_setup() in net_init.c set
153 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
154 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
155 * bytes which we'll use to store the PRH.
156 *
157 * There's a subtle advantage to adding these pad bytes to the
158 * hard_header_len, it ensures that the data portion of the packet for
159 * an 802.2 SNAP frame is longword aligned. Other FDDI driver
160 * implementations may not need the extra padding and can start copying
161 * or DMAing directly from the FC byte which starts at skb->data. Should
162 * another driver implementation need ADDITIONAL padding, the net_init.c
163 * module should be updated and dev->hard_header_len should be increased.
164 * NOTE: To maintain the alignment on the data portion of the packet,
165 * dev->hard_header_len should always be evenly divisible by 4 and at
166 * least 24 bytes in size.
167 *
168 * Modification History:
169 * Date Name Description
170 * 16-Aug-96 LVS Created.
171 * 20-Aug-96 LVS Updated dfx_probe so that version information
172 * string is only displayed if 1 or more cards are
173 * found. Changed dfx_rcv_queue_process to copy
174 * 3 NULL bytes before FC to ensure that data is
175 * longword aligned in receive buffer.
176 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
177 * LLC group promiscuous mode if multicast list
178 * is too large. LLC individual/group promiscuous
179 * mode is now disabled if IFF_PROMISC flag not set.
180 * dfx_xmt_queue_pkt no longer checks for NULL skb
181 * on Alan Cox recommendation. Added node address
182 * override support.
183 * 12-Sep-96 LVS Reset current address to factory address during
184 * device open. Updated transmit path to post a
185 * single fragment which includes PRH->end of data.
186 * Mar 2000 AC Did various cleanups for 2.3.x
187 * Jun 2000 jgarzik PCI and resource alloc cleanups
188 * Jul 2000 tjeerd Much cleanup and some bug fixes
189 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup
190 * Feb 2001 Skb allocation fixes
191 * Feb 2001 davej PCI enable cleanups.
192 * 04 Aug 2003 macro Converted to the DMA API.
193 * 14 Aug 2004 macro Fix device names reported.
194 * 14 Jun 2005 macro Use irqreturn_t.
195 */
197 /* Include files */
199 #include <linux/module.h>
200 #include <linux/kernel.h>
201 #include <linux/string.h>
202 #include <linux/errno.h>
203 #include <linux/ioport.h>
204 #include <linux/slab.h>
205 #include <linux/interrupt.h>
206 #include <linux/pci.h>
207 #include <linux/delay.h>
208 #include <linux/init.h>
209 #include <linux/netdevice.h>
210 #include <linux/fddidevice.h>
211 #include <linux/skbuff.h>
212 #include <linux/bitops.h>
214 #include <asm/byteorder.h>
215 #include <asm/io.h>
219 /* Version information string should be updated prior to each new release! */
228 #define DYNAMIC_BUFFERS 1
230 #define SKBUFF_RX_COPYBREAK 200
231 /*
232 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
233 * alignment for compatibility with old EISA boards.
234 */
235 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
237 /* Define module-wide (static) routines */
261 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
274 /* Define module-wide (static) variables */
278 \f
279 /*
280 * =======================
281 * = dfx_port_write_byte =
282 * = dfx_port_read_byte =
283 * = dfx_port_write_long =
284 * = dfx_port_read_long =
285 * =======================
286 *
287 * Overview:
288 * Routines for reading and writing values from/to adapter
289 *
290 * Returns:
291 * None
292 *
293 * Arguments:
294 * bp - pointer to board information
295 * offset - register offset from base I/O address
296 * data - for dfx_port_write_byte and dfx_port_write_long, this
297 * is a value to write.
298 * for dfx_port_read_byte and dfx_port_read_byte, this
299 * is a pointer to store the read value.
300 *
301 * Functional Description:
302 * These routines perform the correct operation to read or write
303 * the adapter register.
304 *
305 * EISA port block base addresses are based on the slot number in which the
306 * controller is installed. For example, if the EISA controller is installed
307 * in slot 4, the port block base address is 0x4000. If the controller is
308 * installed in slot 2, the port block base address is 0x2000, and so on.
309 * This port block can be used to access PDQ, ESIC, and DEFEA on-board
310 * registers using the register offsets defined in DEFXX.H.
311 *
312 * PCI port block base addresses are assigned by the PCI BIOS or system
313 * firmware. There is one 128 byte port block which can be accessed. It
314 * allows for I/O mapping of both PDQ and PFI registers using the register
315 * offsets defined in DEFXX.H.
316 *
317 * Return Codes:
318 * None
319 *
320 * Assumptions:
321 * bp->base_addr is a valid base I/O address for this adapter.
322 * offset is a valid register offset for this adapter.
323 *
324 * Side Effects:
325 * Rather than produce macros for these functions, these routines
326 * are defined using "inline" to ensure that the compiler will
327 * generate inline code and not waste a procedure call and return.
328 * This provides all the benefits of macros, but with the
329 * advantage of strict data type checking.
330 */
335 u8 data
336 )
338 {
342 }
347 u8 *data
348 )
350 {
354 }
359 u32 data
360 )
362 {
366 }
371 u32 *data
372 )
374 {
378 }
380 \f
381 /*
382 * =============
383 * = dfx_init_one_pci_or_eisa =
384 * =============
385 *
386 * Overview:
387 * Initializes a supported FDDI EISA or PCI controller
388 *
389 * Returns:
390 * Condition code
391 *
392 * Arguments:
393 * pdev - pointer to pci device information (NULL for EISA)
394 * ioaddr - pointer to port (NULL for PCI)
395 *
396 * Functional Description:
397 *
398 * Return Codes:
399 * 0 - This device (fddi0, fddi1, etc) configured successfully
400 * -EBUSY - Failed to get resources, or dfx_driver_init failed.
401 *
402 * Assumptions:
403 * It compiles so it should work :-( (PCI cards do :-)
404 *
405 * Side Effects:
406 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
407 * initialized and the board resources are read and stored in
408 * the device structure.
409 */
411 {
422 }
430 print_name);
432 }
434 /* Enable PCI device. */
439 }
449 print_name)) {
455 }
457 /* Initialize new device structure */
469 /* EISA board */
474 /* PCI board */
479 }
484 }
493 err_out_kfree:
496 #ifndef DYNAMIC_BUFFERS
498 #endif
504 err_out_region:
506 err_out:
509 }
512 {
514 }
517 {
525 /* Scan for FDDI EISA controllers */
528 {
532 {
536 }
537 }
539 }
540 \f
541 /*
542 * ================
543 * = dfx_bus_init =
544 * ================
545 *
546 * Overview:
547 * Initializes EISA and PCI controller bus-specific logic.
548 *
549 * Returns:
550 * None
551 *
552 * Arguments:
553 * dev - pointer to device information
554 *
555 * Functional Description:
556 * Determine and save adapter IRQ in device table,
557 * then perform bus-specific logic initialization.
558 *
559 * Return Codes:
560 * None
561 *
562 * Assumptions:
563 * dev->base_addr has already been set with the proper
564 * base I/O address for this device.
565 *
566 * Side Effects:
567 * Interrupts are enabled at the adapter bus-specific logic.
568 * Note: Interrupts at the DMA engine (PDQ chip) are not
569 * enabled yet.
570 */
573 {
579 /*
580 * Initialize base I/O address field in bp structure
581 *
582 * Note: bp->base_addr is the same as dev->base_addr.
583 * It's useful because often we'll need to read
584 * or write registers where we already have the
585 * bp pointer instead of the dev pointer. Having
586 * the base address in the bp structure will
587 * save a pointer dereference.
588 *
589 * IMPORTANT!! This field must be defined before
590 * any of the dfx_port_* inline functions are
591 * called.
592 */
596 /* And a pointer back to the net_device struct */
599 /* Initialize adapter based on bus type */
602 {
603 /* Get the interrupt level from the ESIC chip */
607 {
623 }
625 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */
629 /* Set the I/O decode range of the board */
635 /* Enable access to rest of module (including PDQ and packet memory) */
639 /*
640 * Map PDQ registers into I/O space. This is done by clearing a bit
641 * in Burst Holdoff register.
642 */
647 /* Enable interrupts at EISA bus interface chip (ESIC) */
651 }
652 else
653 {
656 /* Get the interrupt level from the PCI Configuration Table */
660 /* Check Latency Timer and set if less than minimal */
664 {
667 }
669 /* Enable interrupts at PCI bus interface chip (PFI) */
672 }
673 }
675 \f
676 /*
677 * ========================
678 * = dfx_bus_config_check =
679 * ========================
680 *
681 * Overview:
682 * Checks the configuration (burst size, full-duplex, etc.) If any parameters
683 * are illegal, then this routine will set new defaults.
684 *
685 * Returns:
686 * None
687 *
688 * Arguments:
689 * bp - pointer to board information
690 *
691 * Functional Description:
692 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
693 * PDQ, and all FDDI PCI controllers, all values are legal.
694 *
695 * Return Codes:
696 * None
697 *
698 * Assumptions:
699 * dfx_adap_init has NOT been called yet so burst size and other items have
700 * not been set.
701 *
702 * Side Effects:
703 * None
704 */
707 {
714 /* Configuration check only valid for EISA adapter */
717 {
720 /*
721 * First check if revision 2 EISA controller. Rev. 1 cards used
722 * PDQ revision B, so no workaround needed in this case. Rev. 3
723 * cards used PDQ revision E, so no workaround needed in this
724 * case, either. Only Rev. 2 cards used either Rev. D or E
725 * chips, so we must verify the chip revision on Rev. 2 cards.
726 */
729 {
730 /*
731 * Revision 2 FDDI EISA controller found, so let's check PDQ
732 * revision of adapter.
733 */
736 PI_PCTRL_M_SUB_CMD,
737 PI_SUB_CMD_K_PDQ_REV_GET,
741 {
742 /*
743 * Either we couldn't determine the PDQ revision, or
744 * we determined that it is at revision D. In either case,
745 * we need to implement the workaround.
746 */
748 /* Ensure that the burst size is set to 8 longwords or less */
751 {
759 }
761 /* Ensure that full-duplex mode is not enabled */
764 }
765 }
766 }
767 }
769 \f
770 /*
771 * ===================
772 * = dfx_driver_init =
773 * ===================
774 *
775 * Overview:
776 * Initializes remaining adapter board structure information
777 * and makes sure adapter is in a safe state prior to dfx_open().
778 *
779 * Returns:
780 * Condition code
781 *
782 * Arguments:
783 * dev - pointer to device information
784 * print_name - printable device name
785 *
786 * Functional Description:
787 * This function allocates additional resources such as the host memory
788 * blocks needed by the adapter (eg. descriptor and consumer blocks).
789 * Remaining bus initialization steps are also completed. The adapter
790 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
791 * must call dfx_open() to open the adapter and bring it on-line.
792 *
793 * Return Codes:
794 * DFX_K_SUCCESS - initialization succeeded
795 * DFX_K_FAILURE - initialization failed - could not allocate memory
796 * or read adapter MAC address
797 *
798 * Assumptions:
799 * Memory allocated from pci_alloc_consistent() call is physically
800 * contiguous, locked memory.
801 *
802 * Side Effects:
803 * Adapter is reset and should be in DMA_UNAVAILABLE state before
804 * returning from this routine.
805 */
809 {
818 /* Initialize bus-specific hardware registers */
822 /*
823 * Initialize default values for configurable parameters
824 *
825 * Note: All of these parameters are ones that a user may
826 * want to customize. It'd be nice to break these
827 * out into Space.c or someplace else that's more
828 * accessible/understandable than this file.
829 */
836 /*
837 * Ensure that HW configuration is OK
838 *
839 * Note: Depending on the hardware revision, we may need to modify
840 * some of the configurable parameters to workaround hardware
841 * limitations. We'll perform this configuration check AFTER
842 * setting the parameters to their default values.
843 */
847 /* Disable PDQ interrupts first */
851 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
855 /* Read the factory MAC address from the adapter then save it */
860 print_name);
862 }
868 print_name);
870 }
873 /*
874 * Set current address to factory address
875 *
876 * Note: Node address override support is handled through
877 * dfx_ctl_set_mac_address.
878 */
888 else
896 /*
897 * Get memory for descriptor block, consumer block, and other buffers
898 * that need to be DMA read or written to by the adapter.
899 */
902 PI_CMD_REQ_K_SIZE_MAX +
903 PI_CMD_RSP_K_SIZE_MAX +
904 #ifndef DYNAMIC_BUFFERS
906 #endif
915 }
919 /*
920 * To guarantee the 8K alignment required for the descriptor block, 8K - 1
921 * plus the amount of memory needed was allocated. The physical address
922 * is now 8K aligned. By carving up the memory in a specific order,
923 * we'll guarantee the alignment requirements for all other structures.
924 *
925 * Note: If the assumptions change regarding the non-paged, non-cached,
926 * physically contiguous nature of the memory block or the address
927 * alignments, then we'll need to implement a different algorithm
928 * for allocating the needed memory.
929 */
934 /* Reserve space for descriptor block */
941 /* Reserve space for command request buffer */
948 /* Reserve space for command response buffer */
955 /* Reserve space for the LLC host receive queue buffers */
960 #ifndef DYNAMIC_BUFFERS
963 #endif
965 /* Reserve space for the consumer block */
970 /* Display virtual and physical addresses if debug driver */
973 print_name,
985 }
987 \f
988 /*
989 * =================
990 * = dfx_adap_init =
991 * =================
992 *
993 * Overview:
994 * Brings the adapter to the link avail/link unavailable state.
995 *
996 * Returns:
997 * Condition code
998 *
999 * Arguments:
1000 * bp - pointer to board information
1001 * get_buffers - non-zero if buffers to be allocated
1002 *
1003 * Functional Description:
1004 * Issues the low-level firmware/hardware calls necessary to bring
1005 * the adapter up, or to properly reset and restore adapter during
1006 * run-time.
1007 *
1008 * Return Codes:
1009 * DFX_K_SUCCESS - Adapter brought up successfully
1010 * DFX_K_FAILURE - Adapter initialization failed
1011 *
1012 * Assumptions:
1013 * bp->reset_type should be set to a valid reset type value before
1014 * calling this routine.
1015 *
1016 * Side Effects:
1017 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1018 * upon a successful return of this routine.
1019 */
1022 {
1025 /* Disable PDQ interrupts first */
1029 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1032 {
1035 }
1037 /*
1038 * When the PDQ is reset, some false Type 0 interrupts may be pending,
1039 * so we'll acknowledge all Type 0 interrupts now before continuing.
1040 */
1044 /*
1045 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1046 *
1047 * Note: We only need to clear host copies of these registers. The PDQ reset
1048 * takes care of the on-board register values.
1049 */
1055 /* Clear consumer block before going to DMA_AVAILABLE state */
1059 /* Initialize the DMA Burst Size */
1062 PI_PCTRL_M_SUB_CMD,
1063 PI_SUB_CMD_K_BURST_SIZE_SET,
1066 {
1069 }
1071 /*
1072 * Set base address of Consumer Block
1073 *
1074 * Assumption: 32-bit physical address of consumer block is 64 byte
1075 * aligned. That is, bits 0-5 of the address must be zero.
1076 */
1079 PI_PCTRL_M_CONS_BLOCK,
1083 {
1086 }
1088 /*
1089 * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state
1090 *
1091 * Note: We also set the literal and data swapping requirements in this
1092 * command. Since this driver presently runs on Intel platforms
1093 * which are Little Endian, we'll tell the adapter to byte swap
1094 * data only. This code will need to change when we support
1095 * Big Endian systems (eg. PowerPC).
1096 *
1097 * Assumption: 32-bit physical address of descriptor block is 8Kbyte
1098 * aligned. That is, bits 0-12 of the address must be zero.
1099 */
1102 PI_PCTRL_M_INIT,
1106 {
1109 }
1111 /* Set transmit flush timeout value */
1119 {
1122 }
1124 /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1135 {
1138 }
1140 /* Initialize adapter CAM */
1143 {
1146 }
1148 /* Initialize adapter filters */
1151 {
1154 }
1156 /*
1157 * Remove any existing dynamic buffers (i.e. if the adapter is being
1158 * reinitialized)
1159 */
1164 /* Initialize receive descriptor block and produce buffers */
1167 {
1172 }
1174 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1178 {
1183 }
1185 /* Initialization succeeded, reenable PDQ interrupts */
1189 }
1191 \f
1192 /*
1193 * ============
1194 * = dfx_open =
1195 * ============
1196 *
1197 * Overview:
1198 * Opens the adapter
1199 *
1200 * Returns:
1201 * Condition code
1202 *
1203 * Arguments:
1204 * dev - pointer to device information
1205 *
1206 * Functional Description:
1207 * This function brings the adapter to an operational state.
1208 *
1209 * Return Codes:
1210 * 0 - Adapter was successfully opened
1211 * -EAGAIN - Could not register IRQ or adapter initialization failed
1212 *
1213 * Assumptions:
1214 * This routine should only be called for a device that was
1215 * initialized successfully.
1216 *
1217 * Side Effects:
1218 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1219 * if the open is successful.
1220 */
1223 {
1229 /* Register IRQ - support shared interrupts by passing device ptr */
1235 }
1237 /*
1238 * Set current address to factory MAC address
1239 *
1240 * Note: We've already done this step in dfx_driver_init.
1241 * However, it's possible that a user has set a node
1242 * address override, then closed and reopened the
1243 * adapter. Unless we reset the device address field
1244 * now, we'll continue to use the existing modified
1245 * address.
1246 */
1250 /* Clear local unicast/multicast address tables and counts */
1257 /* Disable promiscuous filter settings */
1264 /* Reset and initialize adapter */
1268 {
1272 }
1274 /* Set device structure info */
1277 }
1279 \f
1280 /*
1281 * =============
1282 * = dfx_close =
1283 * =============
1284 *
1285 * Overview:
1286 * Closes the device/module.
1287 *
1288 * Returns:
1289 * Condition code
1290 *
1291 * Arguments:
1292 * dev - pointer to device information
1293 *
1294 * Functional Description:
1295 * This routine closes the adapter and brings it to a safe state.
1296 * The interrupt service routine is deregistered with the OS.
1297 * The adapter can be opened again with another call to dfx_open().
1298 *
1299 * Return Codes:
1300 * Always return 0.
1301 *
1302 * Assumptions:
1303 * No further requests for this adapter are made after this routine is
1304 * called. dfx_open() can be called to reset and reinitialize the
1305 * adapter.
1306 *
1307 * Side Effects:
1308 * Adapter should be in DMA_UNAVAILABLE state upon completion of this
1309 * routine.
1310 */
1313 {
1318 /* Disable PDQ interrupts first */
1322 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1326 /*
1327 * Flush any pending transmit buffers
1328 *
1329 * Note: It's important that we flush the transmit buffers
1330 * BEFORE we clear our copy of the Type 2 register.
1331 * Otherwise, we'll have no idea how many buffers
1332 * we need to free.
1333 */
1337 /*
1338 * Clear Type 1 and Type 2 registers after adapter reset
1339 *
1340 * Note: Even though we're closing the adapter, it's
1341 * possible that an interrupt will occur after
1342 * dfx_close is called. Without some assurance to
1343 * the contrary we want to make sure that we don't
1344 * process receive and transmit LLC frames and update
1345 * the Type 2 register with bad information.
1346 */
1352 /* Clear consumer block for the same reason given above */
1356 /* Release all dynamically allocate skb in the receive ring. */
1360 /* Clear device structure flags */
1364 /* Deregister (free) IRQ */
1369 }
1371 \f
1372 /*
1373 * ======================
1374 * = dfx_int_pr_halt_id =
1375 * ======================
1376 *
1377 * Overview:
1378 * Displays halt id's in string form.
1379 *
1380 * Returns:
1381 * None
1382 *
1383 * Arguments:
1384 * bp - pointer to board information
1385 *
1386 * Functional Description:
1387 * Determine current halt id and display appropriate string.
1388 *
1389 * Return Codes:
1390 * None
1391 *
1392 * Assumptions:
1393 * None
1394 *
1395 * Side Effects:
1396 * None
1397 */
1400 {
1404 /* Read the latest port status */
1408 /* Display halt state transition information */
1412 {
1452 }
1453 }
1455 \f
1456 /*
1457 * ==========================
1458 * = dfx_int_type_0_process =
1459 * ==========================
1460 *
1461 * Overview:
1462 * Processes Type 0 interrupts.
1463 *
1464 * Returns:
1465 * None
1466 *
1467 * Arguments:
1468 * bp - pointer to board information
1469 *
1470 * Functional Description:
1471 * Processes all enabled Type 0 interrupts. If the reason for the interrupt
1472 * is a serious fault on the adapter, then an error message is displayed
1473 * and the adapter is reset.
1474 *
1475 * One tricky potential timing window is the rapid succession of "link avail"
1476 * "link unavail" state change interrupts. The acknowledgement of the Type 0
1477 * interrupt must be done before reading the state from the Port Status
1478 * register. This is true because a state change could occur after reading
1479 * the data, but before acknowledging the interrupt. If this state change
1480 * does happen, it would be lost because the driver is using the old state,
1481 * and it will never know about the new state because it subsequently
1482 * acknowledges the state change interrupt.
1483 *
1484 * INCORRECT CORRECT
1485 * read type 0 int reasons read type 0 int reasons
1486 * read adapter state ack type 0 interrupts
1487 * ack type 0 interrupts read adapter state
1488 * ... process interrupt ... ... process interrupt ...
1489 *
1490 * Return Codes:
1491 * None
1492 *
1493 * Assumptions:
1494 * None
1495 *
1496 * Side Effects:
1497 * An adapter reset may occur if the adapter has any Type 0 error interrupts
1498 * or if the port status indicates that the adapter is halted. The driver
1499 * is responsible for reinitializing the adapter with the current CAM
1500 * contents and adapter filter settings.
1501 */
1505 {
1509 /*
1510 * Read host interrupt Type 0 register to determine which Type 0
1511 * interrupts are pending. Immediately write it back out to clear
1512 * those interrupts.
1513 */
1518 /* Check for Type 0 error interrupts */
1521 PI_TYPE_0_STAT_M_PM_PAR_ERR |
1522 PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1523 {
1524 /* Check for Non-Existent Memory error */
1529 /* Check for Packet Memory Parity error */
1534 /* Check for Host Bus Parity error */
1539 /* Reset adapter and bring it back on-line */
1545 {
1549 }
1552 }
1554 /* Check for transmit flush interrupt */
1557 {
1558 /* Flush any pending xmt's and acknowledge the flush interrupt */
1563 PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1566 NULL);
1567 }
1569 /* Check for adapter state change */
1572 {
1573 /* Get latest adapter state */
1577 {
1578 /*
1579 * Adapter has transitioned to HALTED state, try to reset
1580 * adapter to bring it back on-line. If reset fails,
1581 * leave the adapter in the broken state.
1582 */
1587 /* Reset adapter and bring it back on-line */
1593 {
1597 }
1599 }
1601 {
1603 }
1604 }
1605 }
1607 \f
1608 /*
1609 * ==================
1610 * = dfx_int_common =
1611 * ==================
1612 *
1613 * Overview:
1614 * Interrupt service routine (ISR)
1615 *
1616 * Returns:
1617 * None
1618 *
1619 * Arguments:
1620 * bp - pointer to board information
1621 *
1622 * Functional Description:
1623 * This is the ISR which processes incoming adapter interrupts.
1624 *
1625 * Return Codes:
1626 * None
1627 *
1628 * Assumptions:
1629 * This routine assumes PDQ interrupts have not been disabled.
1630 * When interrupts are disabled at the PDQ, the Port Status register
1631 * is automatically cleared. This routine uses the Port Status
1632 * register value to determine whether a Type 0 interrupt occurred,
1633 * so it's important that adapter interrupts are not normally
1634 * enabled/disabled at the PDQ.
1635 *
1636 * It's vital that this routine is NOT reentered for the
1637 * same board and that the OS is not in another section of
1638 * code (eg. dfx_xmt_queue_pkt) for the same board on a
1639 * different thread.
1640 *
1641 * Side Effects:
1642 * Pending interrupts are serviced. Depending on the type of
1643 * interrupt, acknowledging and clearing the interrupt at the
1644 * PDQ involves writing a register to clear the interrupt bit
1645 * or updating completion indices.
1646 */
1649 {
1653 /* Process xmt interrupts - frequent case, so always call this routine */
1658 /* Process rcv interrupts - frequent case, so always call this routine */
1662 /*
1663 * Transmit and receive producer and completion indices are updated on the
1664 * adapter by writing to the Type 2 Producer register. Since the frequent
1665 * case is that we'll be processing either LLC transmit or receive buffers,
1666 * we'll optimize I/O writes by doing a single register write here.
1667 */
1671 /* Read PDQ Port Status register to find out which interrupts need processing */
1675 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1679 }
1681 \f
1682 /*
1683 * =================
1684 * = dfx_interrupt =
1685 * =================
1686 *
1687 * Overview:
1688 * Interrupt processing routine
1689 *
1690 * Returns:
1691 * Whether a valid interrupt was seen.
1692 *
1693 * Arguments:
1694 * irq - interrupt vector
1695 * dev_id - pointer to device information
1696 * regs - pointer to registers structure
1697 *
1698 * Functional Description:
1699 * This routine calls the interrupt processing routine for this adapter. It
1700 * disables and reenables adapter interrupts, as appropriate. We can support
1701 * shared interrupts since the incoming dev_id pointer provides our device
1702 * structure context.
1703 *
1704 * Return Codes:
1705 * IRQ_HANDLED - an IRQ was handled.
1706 * IRQ_NONE - no IRQ was handled.
1707 *
1708 * Assumptions:
1709 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1710 * on Intel-based systems) is done by the operating system outside this
1711 * routine.
1712 *
1713 * System interrupts are enabled through this call.
1714 *
1715 * Side Effects:
1716 * Interrupts are disabled, then reenabled at the adapter.
1717 */
1720 {
1724 /* Get board pointer only if device structure is valid */
1728 /* See if we're already servicing an interrupt */
1730 /* Service adapter interrupts */
1733 u32 status;
1741 /* Disable PDQ-PFI interrupts at PFI */
1743 PFI_MODE_M_DMA_ENB);
1745 /* Call interrupt service routine for this adapter */
1748 /* Clear PDQ interrupt status bit and reenable interrupts */
1750 PFI_STATUS_M_PDQ_INT);
1753 PFI_MODE_M_DMA_ENB));
1757 u8 status;
1765 /* Disable interrupts at the ESIC */
1769 /* Call interrupt service routine for this adapter */
1772 /* Reenable interrupts at the ESIC */
1778 }
1781 }
1783 \f
1784 /*
1785 * =====================
1786 * = dfx_ctl_get_stats =
1787 * =====================
1788 *
1789 * Overview:
1790 * Get statistics for FDDI adapter
1791 *
1792 * Returns:
1793 * Pointer to FDDI statistics structure
1794 *
1795 * Arguments:
1796 * dev - pointer to device information
1797 *
1798 * Functional Description:
1799 * Gets current MIB objects from adapter, then
1800 * returns FDDI statistics structure as defined
1801 * in if_fddi.h.
1802 *
1803 * Note: Since the FDDI statistics structure is
1804 * still new and the device structure doesn't
1805 * have an FDDI-specific get statistics handler,
1806 * we'll return the FDDI statistics structure as
1807 * a pointer to an Ethernet statistics structure.
1808 * That way, at least the first part of the statistics
1809 * structure can be decoded properly, and it allows
1810 * "smart" applications to perform a second cast to
1811 * decode the FDDI-specific statistics.
1812 *
1813 * We'll have to pay attention to this routine as the
1814 * device structure becomes more mature and LAN media
1815 * independent.
1816 *
1817 * Return Codes:
1818 * None
1819 *
1820 * Assumptions:
1821 * None
1822 *
1823 * Side Effects:
1824 * None
1825 */
1828 {
1831 /* Fill the bp->stats structure with driver-maintained counters */
1846 /* Get FDDI SMT MIB objects */
1852 /* Fill the bp->stats structure with the SMT MIB object values */
1854 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
1858 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
1873 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
1877 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
1878 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
1883 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
1884 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
1885 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
1886 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
1890 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
1907 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
1912 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
1913 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
1918 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
1919 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
1926 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
1927 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
1947 /* Get FDDI counters */
1953 /* Fill the bp->stats structure with the FDDI counter values */
1968 }
1970 \f
1971 /*
1972 * ==============================
1973 * = dfx_ctl_set_multicast_list =
1974 * ==============================
1975 *
1976 * Overview:
1977 * Enable/Disable LLC frame promiscuous mode reception
1978 * on the adapter and/or update multicast address table.
1979 *
1980 * Returns:
1981 * None
1982 *
1983 * Arguments:
1984 * dev - pointer to device information
1985 *
1986 * Functional Description:
1987 * This routine follows a fairly simple algorithm for setting the
1988 * adapter filters and CAM:
1989 *
1990 * if IFF_PROMISC flag is set
1991 * enable LLC individual/group promiscuous mode
1992 * else
1993 * disable LLC individual/group promiscuous mode
1994 * if number of incoming multicast addresses >
1995 * (CAM max size - number of unicast addresses in CAM)
1996 * enable LLC group promiscuous mode
1997 * set driver-maintained multicast address count to zero
1998 * else
1999 * disable LLC group promiscuous mode
2000 * set driver-maintained multicast address count to incoming count
2001 * update adapter CAM
2002 * update adapter filters
2003 *
2004 * Return Codes:
2005 * None
2006 *
2007 * Assumptions:
2008 * Multicast addresses are presented in canonical (LSB) format.
2009 *
2010 * Side Effects:
2011 * On-board adapter CAM and filters are updated.
2012 */
2015 {
2020 /* Enable LLC frame promiscuous mode, if necessary */
2025 /* Else, update multicast address table */
2027 else
2028 {
2030 /*
2031 * Check whether incoming multicast address count exceeds table size
2032 *
2033 * Note: The adapters utilize an on-board 64 entry CAM for
2034 * supporting perfect filtering of multicast packets
2035 * and bridge functions when adding unicast addresses.
2036 * There is no hash function available. To support
2037 * additional multicast addresses, the all multicast
2038 * filter (LLC group promiscuous mode) must be enabled.
2039 *
2040 * The firmware reserves two CAM entries for SMT-related
2041 * multicast addresses, which leaves 62 entries available.
2042 * The following code ensures that we're not being asked
2043 * to add more than 62 addresses to the CAM. If we are,
2044 * the driver will enable the all multicast filter.
2045 * Should the number of multicast addresses drop below
2046 * the high water mark, the filter will be disabled and
2047 * perfect filtering will be used.
2048 */
2051 {
2054 }
2055 else
2056 {
2059 }
2061 /* Copy addresses to multicast address table, then update adapter CAM */
2065 {
2068 }
2070 {
2072 }
2073 else
2074 {
2075 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
2076 }
2077 }
2079 /* Update adapter filters */
2082 {
2084 }
2085 else
2086 {
2088 }
2089 }
2091 \f
2092 /*
2093 * ===========================
2094 * = dfx_ctl_set_mac_address =
2095 * ===========================
2096 *
2097 * Overview:
2098 * Add node address override (unicast address) to adapter
2099 * CAM and update dev_addr field in device table.
2100 *
2101 * Returns:
2102 * None
2103 *
2104 * Arguments:
2105 * dev - pointer to device information
2106 * addr - pointer to sockaddr structure containing unicast address to add
2107 *
2108 * Functional Description:
2109 * The adapter supports node address overrides by adding one or more
2110 * unicast addresses to the adapter CAM. This is similar to adding
2111 * multicast addresses. In this routine we'll update the driver and
2112 * device structures with the new address, then update the adapter CAM
2113 * to ensure that the adapter will copy and strip frames destined and
2114 * sourced by that address.
2115 *
2116 * Return Codes:
2117 * Always returns zero.
2118 *
2119 * Assumptions:
2120 * The address pointed to by addr->sa_data is a valid unicast
2121 * address and is presented in canonical (LSB) format.
2122 *
2123 * Side Effects:
2124 * On-board adapter CAM is updated. On-board adapter filters
2125 * may be updated.
2126 */
2129 {
2133 /* Copy unicast address to driver-maintained structs and update count */
2139 /*
2140 * Verify we're not exceeding the CAM size by adding unicast address
2141 *
2142 * Note: It's possible that before entering this routine we've
2143 * already filled the CAM with 62 multicast addresses.
2144 * Since we need to place the node address override into
2145 * the CAM, we have to check to see that we're not
2146 * exceeding the CAM size. If we are, we have to enable
2147 * the LLC group (multicast) promiscuous mode filter as
2148 * in dfx_ctl_set_multicast_list.
2149 */
2152 {
2156 /* Update adapter filters */
2159 {
2161 }
2162 else
2163 {
2165 }
2166 }
2168 /* Update adapter CAM with new unicast address */
2171 {
2173 }
2174 else
2175 {
2177 }
2179 }
2181 \f
2182 /*
2183 * ======================
2184 * = dfx_ctl_update_cam =
2185 * ======================
2186 *
2187 * Overview:
2188 * Procedure to update adapter CAM (Content Addressable Memory)
2189 * with desired unicast and multicast address entries.
2190 *
2191 * Returns:
2192 * Condition code
2193 *
2194 * Arguments:
2195 * bp - pointer to board information
2196 *
2197 * Functional Description:
2198 * Updates adapter CAM with current contents of board structure
2199 * unicast and multicast address tables. Since there are only 62
2200 * free entries in CAM, this routine ensures that the command
2201 * request buffer is not overrun.
2202 *
2203 * Return Codes:
2204 * DFX_K_SUCCESS - Request succeeded
2205 * DFX_K_FAILURE - Request failed
2206 *
2207 * Assumptions:
2208 * All addresses being added (unicast and multicast) are in canonical
2209 * order.
2210 *
2211 * Side Effects:
2212 * On-board adapter CAM is updated.
2213 */
2216 {
2220 /*
2221 * Fill in command request information
2222 *
2223 * Note: Even though both the unicast and multicast address
2224 * table entries are stored as contiguous 6 byte entries,
2225 * the firmware address filter set command expects each
2226 * entry to be two longwords (8 bytes total). We must be
2227 * careful to only copy the six bytes of each unicast and
2228 * multicast table entry into each command entry. This
2229 * is also why we must first clear the entire command
2230 * request buffer.
2231 */
2237 /* Now add unicast addresses to command request buffer, if any */
2240 {
2242 {
2245 }
2246 }
2248 /* Now add multicast addresses to command request buffer, if any */
2251 {
2253 {
2256 }
2257 }
2259 /* Issue command to update adapter CAM, then return */
2264 }
2266 \f
2267 /*
2268 * ==========================
2269 * = dfx_ctl_update_filters =
2270 * ==========================
2271 *
2272 * Overview:
2273 * Procedure to update adapter filters with desired
2274 * filter settings.
2275 *
2276 * Returns:
2277 * Condition code
2278 *
2279 * Arguments:
2280 * bp - pointer to board information
2281 *
2282 * Functional Description:
2283 * Enables or disables filter using current filter settings.
2284 *
2285 * Return Codes:
2286 * DFX_K_SUCCESS - Request succeeded.
2287 * DFX_K_FAILURE - Request failed.
2288 *
2289 * Assumptions:
2290 * We must always pass up packets destined to the broadcast
2291 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2292 * broadcast filter enabled.
2293 *
2294 * Side Effects:
2295 * On-board adapter filters are updated.
2296 */
2299 {
2302 /* Fill in command request information */
2306 /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2311 /* Initialize LLC Individual/Group Promiscuous filter */
2316 /* Initialize LLC Group Promiscuous filter */
2321 /* Terminate the item code list */
2325 /* Issue command to update adapter filters, then return */
2330 }
2332 \f
2333 /*
2334 * ======================
2335 * = dfx_hw_dma_cmd_req =
2336 * ======================
2337 *
2338 * Overview:
2339 * Sends PDQ DMA command to adapter firmware
2340 *
2341 * Returns:
2342 * Condition code
2343 *
2344 * Arguments:
2345 * bp - pointer to board information
2346 *
2347 * Functional Description:
2348 * The command request and response buffers are posted to the adapter in the manner
2349 * described in the PDQ Port Specification:
2350 *
2351 * 1. Command Response Buffer is posted to adapter.
2352 * 2. Command Request Buffer is posted to adapter.
2353 * 3. Command Request consumer index is polled until it indicates that request
2354 * buffer has been DMA'd to adapter.
2355 * 4. Command Response consumer index is polled until it indicates that response
2356 * buffer has been DMA'd from adapter.
2357 *
2358 * This ordering ensures that a response buffer is already available for the firmware
2359 * to use once it's done processing the request buffer.
2360 *
2361 * Return Codes:
2362 * DFX_K_SUCCESS - DMA command succeeded
2363 * DFX_K_OUTSTATE - Adapter is NOT in proper state
2364 * DFX_K_HW_TIMEOUT - DMA command timed out
2365 *
2366 * Assumptions:
2367 * Command request buffer has already been filled with desired DMA command.
2368 *
2369 * Side Effects:
2370 * None
2371 */
2374 {
2378 /* Make sure the adapter is in a state that we can issue the DMA command in */
2387 /* Put response buffer on the command response queue */
2393 /* Bump (and wrap) the producer index and write out to register */
2399 /* Put request buffer on the command request queue */
2405 /* Bump (and wrap) the producer index and write out to register */
2411 /*
2412 * Here we wait for the command request consumer index to be equal
2413 * to the producer, indicating that the adapter has DMAed the request.
2414 */
2417 {
2421 }
2425 /* Bump (and wrap) the completion index and write out to register */
2431 /*
2432 * Here we wait for the command response consumer index to be equal
2433 * to the producer, indicating that the adapter has DMAed the response.
2434 */
2437 {
2441 }
2445 /* Bump (and wrap) the completion index and write out to register */
2451 }
2453 \f
2454 /*
2455 * ========================
2456 * = dfx_hw_port_ctrl_req =
2457 * ========================
2458 *
2459 * Overview:
2460 * Sends PDQ port control command to adapter firmware
2461 *
2462 * Returns:
2463 * Host data register value in host_data if ptr is not NULL
2464 *
2465 * Arguments:
2466 * bp - pointer to board information
2467 * command - port control command
2468 * data_a - port data A register value
2469 * data_b - port data B register value
2470 * host_data - ptr to host data register value
2471 *
2472 * Functional Description:
2473 * Send generic port control command to adapter by writing
2474 * to various PDQ port registers, then polling for completion.
2475 *
2476 * Return Codes:
2477 * DFX_K_SUCCESS - port control command succeeded
2478 * DFX_K_HW_TIMEOUT - port control command timed out
2479 *
2480 * Assumptions:
2481 * None
2482 *
2483 * Side Effects:
2484 * None
2485 */
2489 PI_UINT32 command,
2490 PI_UINT32 data_a,
2491 PI_UINT32 data_b,
2492 PI_UINT32 *host_data
2493 )
2495 {
2499 /* Set Command Error bit in command longword */
2503 /* Issue port command to the adapter */
2509 /* Now wait for command to complete */
2513 else
2517 {
2522 }
2526 /*
2527 * If the address of host_data is non-zero, assume caller has supplied a
2528 * non NULL pointer, and return the contents of the HOST_DATA register in
2529 * it.
2530 */
2535 }
2537 \f
2538 /*
2539 * =====================
2540 * = dfx_hw_adap_reset =
2541 * =====================
2542 *
2543 * Overview:
2544 * Resets adapter
2545 *
2546 * Returns:
2547 * None
2548 *
2549 * Arguments:
2550 * bp - pointer to board information
2551 * type - type of reset to perform
2552 *
2553 * Functional Description:
2554 * Issue soft reset to adapter by writing to PDQ Port Reset
2555 * register. Use incoming reset type to tell adapter what
2556 * kind of reset operation to perform.
2557 *
2558 * Return Codes:
2559 * None
2560 *
2561 * Assumptions:
2562 * This routine merely issues a soft reset to the adapter.
2563 * It is expected that after this routine returns, the caller
2564 * will appropriately poll the Port Status register for the
2565 * adapter to enter the proper state.
2566 *
2567 * Side Effects:
2568 * Internal adapter registers are cleared.
2569 */
2573 PI_UINT32 type
2574 )
2576 {
2577 /* Set Reset type and assert reset */
2582 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2586 /* Deassert reset */
2589 }
2591 \f
2592 /*
2593 * ========================
2594 * = dfx_hw_adap_state_rd =
2595 * ========================
2596 *
2597 * Overview:
2598 * Returns current adapter state
2599 *
2600 * Returns:
2601 * Adapter state per PDQ Port Specification
2602 *
2603 * Arguments:
2604 * bp - pointer to board information
2605 *
2606 * Functional Description:
2607 * Reads PDQ Port Status register and returns adapter state.
2608 *
2609 * Return Codes:
2610 * None
2611 *
2612 * Assumptions:
2613 * None
2614 *
2615 * Side Effects:
2616 * None
2617 */
2620 {
2625 }
2627 \f
2628 /*
2629 * =====================
2630 * = dfx_hw_dma_uninit =
2631 * =====================
2632 *
2633 * Overview:
2634 * Brings adapter to DMA_UNAVAILABLE state
2635 *
2636 * Returns:
2637 * Condition code
2638 *
2639 * Arguments:
2640 * bp - pointer to board information
2641 * type - type of reset to perform
2642 *
2643 * Functional Description:
2644 * Bring adapter to DMA_UNAVAILABLE state by performing the following:
2645 * 1. Set reset type bit in Port Data A Register then reset adapter.
2646 * 2. Check that adapter is in DMA_UNAVAILABLE state.
2647 *
2648 * Return Codes:
2649 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
2650 * DFX_K_HW_TIMEOUT - adapter did not reset properly
2651 *
2652 * Assumptions:
2653 * None
2654 *
2655 * Side Effects:
2656 * Internal adapter registers are cleared.
2657 */
2660 {
2663 /* Set reset type bit and reset adapter */
2667 /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2670 {
2674 }
2678 }
2679 \f
2680 /*
2681 * Align an sk_buff to a boundary power of 2
2682 *
2683 */
2686 {
2693 }
2695 \f
2696 /*
2697 * ================
2698 * = dfx_rcv_init =
2699 * ================
2700 *
2701 * Overview:
2702 * Produces buffers to adapter LLC Host receive descriptor block
2703 *
2704 * Returns:
2705 * None
2706 *
2707 * Arguments:
2708 * bp - pointer to board information
2709 * get_buffers - non-zero if buffers to be allocated
2710 *
2711 * Functional Description:
2712 * This routine can be called during dfx_adap_init() or during an adapter
2713 * reset. It initializes the descriptor block and produces all allocated
2714 * LLC Host queue receive buffers.
2715 *
2716 * Return Codes:
2717 * Return 0 on success or -ENOMEM if buffer allocation failed (when using
2718 * dynamic buffer allocation). If the buffer allocation failed, the
2719 * already allocated buffers will not be released and the caller should do
2720 * this.
2721 *
2722 * Assumptions:
2723 * The PDQ has been reset and the adapter and driver maintained Type 2
2724 * register indices are cleared.
2725 *
2726 * Side Effects:
2727 * Receive buffers are posted to the adapter LLC queue and the adapter
2728 * is notified.
2729 */
2732 {
2735 /*
2736 * Since each receive buffer is a single fragment of same length, initialize
2737 * first longword in each receive descriptor for entire LLC Host descriptor
2738 * block. Also initialize second longword in each receive descriptor with
2739 * physical address of receive buffer. We'll always allocate receive
2740 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2741 * block and produce new receive buffers by simply updating the receive
2742 * producer index.
2743 *
2744 * Assumptions:
2745 * To support all shipping versions of PDQ, the receive buffer size
2746 * must be mod 128 in length and the physical address must be 128 byte
2747 * aligned. In other words, bits 0-6 of the length and address must
2748 * be zero for the following descriptor field entries to be correct on
2749 * all PDQ-based boards. We guaranteed both requirements during
2750 * driver initialization when we allocated memory for the receive buffers.
2751 */
2754 #ifdef DYNAMIC_BUFFERS
2757 {
2763 /*
2764 * align to 128 bytes for compatibility with
2765 * the old EISA boards.
2766 */
2771 NEW_SKB_SIZE,
2772 PCI_DMA_FROMDEVICE);
2773 /*
2774 * p_rcv_buff_va is only used inside the
2775 * kernel so we put the skb pointer here.
2776 */
2778 }
2779 #else
2782 {
2785 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2787 }
2788 #endif
2789 }
2791 /* Update receive producer and Type 2 register */
2796 }
2798 \f
2799 /*
2800 * =========================
2801 * = dfx_rcv_queue_process =
2802 * =========================
2803 *
2804 * Overview:
2805 * Process received LLC frames.
2806 *
2807 * Returns:
2808 * None
2809 *
2810 * Arguments:
2811 * bp - pointer to board information
2812 *
2813 * Functional Description:
2814 * Received LLC frames are processed until there are no more consumed frames.
2815 * Once all frames are processed, the receive buffers are returned to the
2816 * adapter. Note that this algorithm fixes the length of time that can be spent
2817 * in this routine, because there are a fixed number of receive buffers to
2818 * process and buffers are not produced until this routine exits and returns
2819 * to the ISR.
2820 *
2821 * Return Codes:
2822 * None
2823 *
2824 * Assumptions:
2825 * None
2826 *
2827 * Side Effects:
2828 * None
2829 */
2832 DFX_board_t *bp
2833 )
2835 {
2841 /* Service all consumed LLC receive frames */
2845 {
2846 /* Process any errors */
2851 #ifdef DYNAMIC_BUFFERS
2853 #else
2855 #endif
2859 {
2862 else
2864 }
2865 else
2866 {
2869 /* The frame was received without errors - verify packet length */
2876 #ifdef DYNAMIC_BUFFERS
2888 NEW_SKB_SIZE,
2889 PCI_DMA_FROMDEVICE);
2895 NEW_SKB_SIZE,
2896 PCI_DMA_FROMDEVICE);
2900 #endif
2903 {
2907 }
2909 #ifndef DYNAMIC_BUFFERS
2911 #endif
2912 {
2913 /* Receive buffer allocated, pass receive packet up */
2916 }
2926 /* Update the rcv counters */
2931 }
2932 }
2933 }
2935 /*
2936 * Advance the producer (for recycling) and advance the completion
2937 * (for servicing received frames). Note that it is okay to
2938 * advance the producer without checking that it passes the
2939 * completion index because they are both advanced at the same
2940 * rate.
2941 */
2945 }
2946 }
2948 \f
2949 /*
2950 * =====================
2951 * = dfx_xmt_queue_pkt =
2952 * =====================
2953 *
2954 * Overview:
2955 * Queues packets for transmission
2956 *
2957 * Returns:
2958 * Condition code
2959 *
2960 * Arguments:
2961 * skb - pointer to sk_buff to queue for transmission
2962 * dev - pointer to device information
2963 *
2964 * Functional Description:
2965 * Here we assume that an incoming skb transmit request
2966 * is contained in a single physically contiguous buffer
2967 * in which the virtual address of the start of packet
2968 * (skb->data) can be converted to a physical address
2969 * by using pci_map_single().
2970 *
2971 * Since the adapter architecture requires a three byte
2972 * packet request header to prepend the start of packet,
2973 * we'll write the three byte field immediately prior to
2974 * the FC byte. This assumption is valid because we've
2975 * ensured that dev->hard_header_len includes three pad
2976 * bytes. By posting a single fragment to the adapter,
2977 * we'll reduce the number of descriptor fetches and
2978 * bus traffic needed to send the request.
2979 *
2980 * Also, we can't free the skb until after it's been DMA'd
2981 * out by the adapter, so we'll queue it in the driver and
2982 * return it in dfx_xmt_done.
2983 *
2984 * Return Codes:
2985 * 0 - driver queued packet, link is unavailable, or skbuff was bad
2986 * 1 - caller should requeue the sk_buff for later transmission
2987 *
2988 * Assumptions:
2989 * First and foremost, we assume the incoming skb pointer
2990 * is NOT NULL and is pointing to a valid sk_buff structure.
2991 *
2992 * The outgoing packet is complete, starting with the
2993 * frame control byte including the last byte of data,
2994 * but NOT including the 4 byte CRC. We'll let the
2995 * adapter hardware generate and append the CRC.
2996 *
2997 * The entire packet is stored in one physically
2998 * contiguous buffer which is not cached and whose
2999 * 32-bit physical address can be determined.
3000 *
3001 * It's vital that this routine is NOT reentered for the
3002 * same board and that the OS is not in another section of
3003 * code (eg. dfx_int_common) for the same board on a
3004 * different thread.
3005 *
3006 * Side Effects:
3007 * None
3008 */
3013 )
3015 {
3024 /*
3025 * Verify that incoming transmit request is OK
3026 *
3027 * Note: The packet size check is consistent with other
3028 * Linux device drivers, although the correct packet
3029 * size should be verified before calling the
3030 * transmit routine.
3031 */
3034 {
3041 }
3042 /*
3043 * See if adapter link is available, if not, free buffer
3044 *
3045 * Note: If the link isn't available, free buffer and return 0
3046 * rather than tell the upper layer to requeue the packet.
3047 * The methodology here is that by the time the link
3048 * becomes available, the packet to be sent will be
3049 * fairly stale. By simply dropping the packet, the
3050 * higher layer protocols will eventually time out
3051 * waiting for response packets which it won't receive.
3052 */
3055 {
3058 else
3059 {
3064 }
3065 }
3069 /* Get the current producer and the next free xmt data descriptor */
3074 /*
3075 * Get pointer to auxiliary queue entry to contain information
3076 * for this packet.
3077 *
3078 * Note: The current xmt producer index will become the
3079 * current xmt completion index when we complete this
3080 * packet later on. So, we'll get the pointer to the
3081 * next auxiliary queue entry now before we bump the
3082 * producer index.
3083 */
3087 /* Write the three PRH bytes immediately before the FC byte */
3094 /*
3095 * Write the descriptor with buffer info and bump producer
3096 *
3097 * Note: Since we need to start DMA from the packet request
3098 * header, we'll add 3 bytes to the DMA buffer length,
3099 * and we'll determine the physical address of the
3100 * buffer from the PRH, not skb->data.
3101 *
3102 * Assumptions:
3103 * 1. Packet starts with the frame control (FC) byte
3104 * at skb->data.
3105 * 2. The 4-byte CRC is not appended to the buffer or
3106 * included in the length.
3107 * 3. Packet length (skb->len) is from FC to end of
3108 * data, inclusive.
3109 * 4. The packet length does not exceed the maximum
3110 * FDDI LLC frame length of 4491 bytes.
3111 * 5. The entire packet is contained in a physically
3112 * contiguous, non-cached, locked memory space
3113 * comprised of a single buffer pointed to by
3114 * skb->data.
3115 * 6. The physical address of the start of packet
3116 * can be determined from the virtual address
3117 * by using pci_map_single() and is only 32-bits
3118 * wide.
3119 */
3121 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
3125 /*
3126 * Verify that descriptor is actually available
3127 *
3128 * Note: If descriptor isn't available, return 1 which tells
3129 * the upper layer to requeue the packet for later
3130 * transmission.
3131 *
3132 * We need to ensure that the producer never reaches the
3133 * completion, except to indicate that the queue is empty.
3134 */
3137 {
3141 }
3143 /*
3144 * Save info for this packet for xmt done indication routine
3145 *
3146 * Normally, we'd save the producer index in the p_xmt_drv_descr
3147 * structure so that we'd have it handy when we complete this
3148 * packet later (in dfx_xmt_done). However, since the current
3149 * transmit architecture guarantees a single fragment for the
3150 * entire packet, we can simply bump the completion index by
3151 * one (1) for each completed packet.
3152 *
3153 * Note: If this assumption changes and we're presented with
3154 * an inconsistent number of transmit fragments for packet
3155 * data, we'll need to modify this code to save the current
3156 * transmit producer index.
3157 */
3161 /* Update Type 2 register */
3168 }
3170 \f
3171 /*
3172 * ================
3173 * = dfx_xmt_done =
3174 * ================
3175 *
3176 * Overview:
3177 * Processes all frames that have been transmitted.
3178 *
3179 * Returns:
3180 * None
3181 *
3182 * Arguments:
3183 * bp - pointer to board information
3184 *
3185 * Functional Description:
3186 * For all consumed transmit descriptors that have not
3187 * yet been completed, we'll free the skb we were holding
3188 * onto using dev_kfree_skb and bump the appropriate
3189 * counters.
3190 *
3191 * Return Codes:
3192 * None
3193 *
3194 * Assumptions:
3195 * The Type 2 register is not updated in this routine. It is
3196 * assumed that it will be updated in the ISR when dfx_xmt_done
3197 * returns.
3198 *
3199 * Side Effects:
3200 * None
3201 */
3204 {
3210 /* Service all consumed transmit frames */
3214 {
3215 /* Get pointer to the transmit driver descriptor block information */
3219 /* Increment transmit counters */
3224 /* Return skb to operating system */
3229 PCI_DMA_TODEVICE);
3232 /*
3233 * Move to start of next packet by updating completion index
3234 *
3235 * Here we assume that a transmit packet request is always
3236 * serviced by posting one fragment. We can therefore
3237 * simplify the completion code by incrementing the
3238 * completion index by one. This code will need to be
3239 * modified if this assumption changes. See comments
3240 * in dfx_xmt_queue_pkt for more details.
3241 */
3244 freed++;
3245 }
3247 }
3249 \f
3250 /*
3251 * =================
3252 * = dfx_rcv_flush =
3253 * =================
3254 *
3255 * Overview:
3256 * Remove all skb's in the receive ring.
3257 *
3258 * Returns:
3259 * None
3260 *
3261 * Arguments:
3262 * bp - pointer to board information
3263 *
3264 * Functional Description:
3265 * Free's all the dynamically allocated skb's that are
3266 * currently attached to the device receive ring. This
3267 * function is typically only used when the device is
3268 * initialized or reinitialized.
3269 *
3270 * Return Codes:
3271 * None
3272 *
3273 * Side Effects:
3274 * None
3275 */
3276 #ifdef DYNAMIC_BUFFERS
3278 {
3283 {
3289 }
3291 }
3292 #else
3294 {
3295 }
3298 /*
3299 * =================
3300 * = dfx_xmt_flush =
3301 * =================
3302 *
3303 * Overview:
3304 * Processes all frames whether they've been transmitted
3305 * or not.
3306 *
3307 * Returns:
3308 * None
3309 *
3310 * Arguments:
3311 * bp - pointer to board information
3312 *
3313 * Functional Description:
3314 * For all produced transmit descriptors that have not
3315 * yet been completed, we'll free the skb we were holding
3316 * onto using dev_kfree_skb and bump the appropriate
3317 * counters. Of course, it's possible that some of
3318 * these transmit requests actually did go out, but we
3319 * won't make that distinction here. Finally, we'll
3320 * update the consumer index to match the producer.
3321 *
3322 * Return Codes:
3323 * None
3324 *
3325 * Assumptions:
3326 * This routine does NOT update the Type 2 register. It
3327 * is assumed that this routine is being called during a
3328 * transmit flush interrupt, or a shutdown or close routine.
3329 *
3330 * Side Effects:
3331 * None
3332 */
3335 {
3340 /* Flush all outstanding transmit frames */
3343 {
3344 /* Get pointer to the transmit driver descriptor block information */
3348 /* Return skb to operating system */
3353 PCI_DMA_TODEVICE);
3356 /* Increment transmit error counter */
3360 /*
3361 * Move to start of next packet by updating completion index
3362 *
3363 * Here we assume that a transmit packet request is always
3364 * serviced by posting one fragment. We can therefore
3365 * simplify the completion code by incrementing the
3366 * completion index by one. This code will need to be
3367 * modified if this assumption changes. See comments
3368 * in dfx_xmt_queue_pkt for more details.
3369 */
3372 }
3374 /* Update the transmit consumer index in the consumer block */
3379 }
3382 {
3391 #ifndef DYNAMIC_BUFFERS
3393 #endif
3400 }
3403 {
3408 }
3413 };
3421 };
3428 {
3432 {
3440 }
3441 }
3444 {
3454 }
3457 {
3463 }
3472 \f
3473 /*
3474 * Local variables:
3475 * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -c defxx.c"
3476 * End:
3477 */