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[PATCH] 9p: fix fid behavior on failed remove
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / bnx2.c
blobdb73de0d25117339ede7074548003cec7986bddf
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <asm/bitops.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
34 #include <asm/page.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #ifdef NETIF_F_HW_VLAN_TX
39 #include <linux/if_vlan.h>
40 #define BCM_VLAN 1
41 #endif
42 #ifdef NETIF_F_TSO
43 #include <net/ip.h>
44 #include <net/tcp.h>
45 #include <net/checksum.h>
46 #define BCM_TSO 1
47 #endif
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/prefetch.h>
51 #include <linux/cache.h>
52 #include <linux/zlib.h>
53
54 #include "bnx2.h"
55 #include "bnx2_fw.h"
56
57 #define DRV_MODULE_NAME "bnx2"
58 #define PFX DRV_MODULE_NAME ": "
59 #define DRV_MODULE_VERSION "1.4.43"
60 #define DRV_MODULE_RELDATE "June 28, 2006"
61
62 #define RUN_AT(x) (jiffies + (x))
63
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (5*HZ)
66
67 static const char version[] __devinitdata =
68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
69
70 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
71 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
72 MODULE_LICENSE("GPL");
73 MODULE_VERSION(DRV_MODULE_VERSION);
74
75 static int disable_msi = 0;
76
77 module_param(disable_msi, int, 0);
78 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
79
80 typedef enum {
81 BCM5706 = 0,
82 NC370T,
83 NC370I,
84 BCM5706S,
85 NC370F,
86 BCM5708,
87 BCM5708S,
88 } board_t;
89
90 /* indexed by board_t, above */
91 static const struct {
92 char *name;
93 } board_info[] __devinitdata = {
94 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
95 { "HP NC370T Multifunction Gigabit Server Adapter" },
96 { "HP NC370i Multifunction Gigabit Server Adapter" },
97 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
98 { "HP NC370F Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
100 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
101 };
102
103 static struct pci_device_id bnx2_pci_tbl[] = {
104 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
105 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
106 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
107 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
113 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
118 { 0, }
119 };
120
121 static struct flash_spec flash_table[] =
122 {
123 /* Slow EEPROM */
124 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
125 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
126 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
127 "EEPROM - slow"},
128 /* Expansion entry 0001 */
129 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
130 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
131 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
132 "Entry 0001"},
133 /* Saifun SA25F010 (non-buffered flash) */
134 /* strap, cfg1, & write1 need updates */
135 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
136 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
137 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
138 "Non-buffered flash (128kB)"},
139 /* Saifun SA25F020 (non-buffered flash) */
140 /* strap, cfg1, & write1 need updates */
141 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
142 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
143 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
144 "Non-buffered flash (256kB)"},
145 /* Expansion entry 0100 */
146 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
147 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
148 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
149 "Entry 0100"},
150 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
151 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
152 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
153 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
154 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
155 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
156 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
157 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
158 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
159 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
160 /* Saifun SA25F005 (non-buffered flash) */
161 /* strap, cfg1, & write1 need updates */
162 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
163 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
164 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
165 "Non-buffered flash (64kB)"},
166 /* Fast EEPROM */
167 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
168 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
169 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
170 "EEPROM - fast"},
171 /* Expansion entry 1001 */
172 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
173 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
175 "Entry 1001"},
176 /* Expansion entry 1010 */
177 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
178 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
179 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
180 "Entry 1010"},
181 /* ATMEL AT45DB011B (buffered flash) */
182 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
183 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
184 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
185 "Buffered flash (128kB)"},
186 /* Expansion entry 1100 */
187 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
188 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190 "Entry 1100"},
191 /* Expansion entry 1101 */
192 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
193 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
195 "Entry 1101"},
196 /* Ateml Expansion entry 1110 */
197 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
198 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
199 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
200 "Entry 1110 (Atmel)"},
201 /* ATMEL AT45DB021B (buffered flash) */
202 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
203 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
204 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
205 "Buffered flash (256kB)"},
206 };
207
208 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
209
210 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
211 {
212 u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
213
214 if (diff > MAX_TX_DESC_CNT)
215 diff = (diff & MAX_TX_DESC_CNT) - 1;
216 return (bp->tx_ring_size - diff);
217 }
218
219 static u32
220 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
221 {
222 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
223 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
224 }
225
226 static void
227 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
228 {
229 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
230 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
231 }
232
233 static void
234 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
235 {
236 offset += cid_addr;
237 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
238 REG_WR(bp, BNX2_CTX_DATA, val);
239 }
240
241 static int
242 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
243 {
244 u32 val1;
245 int i, ret;
246
247 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
248 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
249 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
250
251 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
252 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
253
254 udelay(40);
255 }
256
257 val1 = (bp->phy_addr << 21) | (reg << 16) |
258 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
259 BNX2_EMAC_MDIO_COMM_START_BUSY;
260 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
261
262 for (i = 0; i < 50; i++) {
263 udelay(10);
264
265 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
266 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
267 udelay(5);
268
269 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
270 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
271
272 break;
273 }
274 }
275
276 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
277 *val = 0x0;
278 ret = -EBUSY;
279 }
280 else {
281 *val = val1;
282 ret = 0;
283 }
284
285 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
286 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
287 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
288
289 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
290 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
291
292 udelay(40);
293 }
294
295 return ret;
296 }
297
298 static int
299 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
300 {
301 u32 val1;
302 int i, ret;
303
304 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
305 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
306 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
307
308 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
309 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
310
311 udelay(40);
312 }
313
314 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
315 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
316 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
317 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
318
319 for (i = 0; i < 50; i++) {
320 udelay(10);
321
322 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
323 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
324 udelay(5);
325 break;
326 }
327 }
328
329 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
330 ret = -EBUSY;
331 else
332 ret = 0;
333
334 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
335 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
336 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
337
338 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
339 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
340
341 udelay(40);
342 }
343
344 return ret;
345 }
346
347 static void
348 bnx2_disable_int(struct bnx2 *bp)
349 {
350 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
351 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
352 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
353 }
354
355 static void
356 bnx2_enable_int(struct bnx2 *bp)
357 {
358 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
359 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
360 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
361
362 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
363 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
364
365 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
366 }
367
368 static void
369 bnx2_disable_int_sync(struct bnx2 *bp)
370 {
371 atomic_inc(&bp->intr_sem);
372 bnx2_disable_int(bp);
373 synchronize_irq(bp->pdev->irq);
374 }
375
376 static void
377 bnx2_netif_stop(struct bnx2 *bp)
378 {
379 bnx2_disable_int_sync(bp);
380 if (netif_running(bp->dev)) {
381 netif_poll_disable(bp->dev);
382 netif_tx_disable(bp->dev);
383 bp->dev->trans_start = jiffies; /* prevent tx timeout */
384 }
385 }
386
387 static void
388 bnx2_netif_start(struct bnx2 *bp)
389 {
390 if (atomic_dec_and_test(&bp->intr_sem)) {
391 if (netif_running(bp->dev)) {
392 netif_wake_queue(bp->dev);
393 netif_poll_enable(bp->dev);
394 bnx2_enable_int(bp);
395 }
396 }
397 }
398
399 static void
400 bnx2_free_mem(struct bnx2 *bp)
401 {
402 int i;
403
404 if (bp->status_blk) {
405 pci_free_consistent(bp->pdev, bp->status_stats_size,
406 bp->status_blk, bp->status_blk_mapping);
407 bp->status_blk = NULL;
408 bp->stats_blk = NULL;
409 }
410 if (bp->tx_desc_ring) {
411 pci_free_consistent(bp->pdev,
412 sizeof(struct tx_bd) * TX_DESC_CNT,
413 bp->tx_desc_ring, bp->tx_desc_mapping);
414 bp->tx_desc_ring = NULL;
415 }
416 kfree(bp->tx_buf_ring);
417 bp->tx_buf_ring = NULL;
418 for (i = 0; i < bp->rx_max_ring; i++) {
419 if (bp->rx_desc_ring[i])
420 pci_free_consistent(bp->pdev,
421 sizeof(struct rx_bd) * RX_DESC_CNT,
422 bp->rx_desc_ring[i],
423 bp->rx_desc_mapping[i]);
424 bp->rx_desc_ring[i] = NULL;
425 }
426 vfree(bp->rx_buf_ring);
427 bp->rx_buf_ring = NULL;
428 }
429
430 static int
431 bnx2_alloc_mem(struct bnx2 *bp)
432 {
433 int i, status_blk_size;
434
435 bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
436 GFP_KERNEL);
437 if (bp->tx_buf_ring == NULL)
438 return -ENOMEM;
439
440 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
441 sizeof(struct tx_bd) *
442 TX_DESC_CNT,
443 &bp->tx_desc_mapping);
444 if (bp->tx_desc_ring == NULL)
445 goto alloc_mem_err;
446
447 bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
448 bp->rx_max_ring);
449 if (bp->rx_buf_ring == NULL)
450 goto alloc_mem_err;
451
452 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
453 bp->rx_max_ring);
454
455 for (i = 0; i < bp->rx_max_ring; i++) {
456 bp->rx_desc_ring[i] =
457 pci_alloc_consistent(bp->pdev,
458 sizeof(struct rx_bd) * RX_DESC_CNT,
459 &bp->rx_desc_mapping[i]);
460 if (bp->rx_desc_ring[i] == NULL)
461 goto alloc_mem_err;
462
463 }
464
465 /* Combine status and statistics blocks into one allocation. */
466 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
467 bp->status_stats_size = status_blk_size +
468 sizeof(struct statistics_block);
469
470 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
471 &bp->status_blk_mapping);
472 if (bp->status_blk == NULL)
473 goto alloc_mem_err;
474
475 memset(bp->status_blk, 0, bp->status_stats_size);
476
477 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
478 status_blk_size);
479
480 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
481
482 return 0;
483
484 alloc_mem_err:
485 bnx2_free_mem(bp);
486 return -ENOMEM;
487 }
488
489 static void
490 bnx2_report_fw_link(struct bnx2 *bp)
491 {
492 u32 fw_link_status = 0;
493
494 if (bp->link_up) {
495 u32 bmsr;
496
497 switch (bp->line_speed) {
498 case SPEED_10:
499 if (bp->duplex == DUPLEX_HALF)
500 fw_link_status = BNX2_LINK_STATUS_10HALF;
501 else
502 fw_link_status = BNX2_LINK_STATUS_10FULL;
503 break;
504 case SPEED_100:
505 if (bp->duplex == DUPLEX_HALF)
506 fw_link_status = BNX2_LINK_STATUS_100HALF;
507 else
508 fw_link_status = BNX2_LINK_STATUS_100FULL;
509 break;
510 case SPEED_1000:
511 if (bp->duplex == DUPLEX_HALF)
512 fw_link_status = BNX2_LINK_STATUS_1000HALF;
513 else
514 fw_link_status = BNX2_LINK_STATUS_1000FULL;
515 break;
516 case SPEED_2500:
517 if (bp->duplex == DUPLEX_HALF)
518 fw_link_status = BNX2_LINK_STATUS_2500HALF;
519 else
520 fw_link_status = BNX2_LINK_STATUS_2500FULL;
521 break;
522 }
523
524 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
525
526 if (bp->autoneg) {
527 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
528
529 bnx2_read_phy(bp, MII_BMSR, &bmsr);
530 bnx2_read_phy(bp, MII_BMSR, &bmsr);
531
532 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
533 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
534 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
535 else
536 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
537 }
538 }
539 else
540 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
541
542 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
543 }
544
545 static void
546 bnx2_report_link(struct bnx2 *bp)
547 {
548 if (bp->link_up) {
549 netif_carrier_on(bp->dev);
550 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
551
552 printk("%d Mbps ", bp->line_speed);
553
554 if (bp->duplex == DUPLEX_FULL)
555 printk("full duplex");
556 else
557 printk("half duplex");
558
559 if (bp->flow_ctrl) {
560 if (bp->flow_ctrl & FLOW_CTRL_RX) {
561 printk(", receive ");
562 if (bp->flow_ctrl & FLOW_CTRL_TX)
563 printk("& transmit ");
564 }
565 else {
566 printk(", transmit ");
567 }
568 printk("flow control ON");
569 }
570 printk("\n");
571 }
572 else {
573 netif_carrier_off(bp->dev);
574 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
575 }
576
577 bnx2_report_fw_link(bp);
578 }
579
580 static void
581 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
582 {
583 u32 local_adv, remote_adv;
584
585 bp->flow_ctrl = 0;
586 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
587 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
588
589 if (bp->duplex == DUPLEX_FULL) {
590 bp->flow_ctrl = bp->req_flow_ctrl;
591 }
592 return;
593 }
594
595 if (bp->duplex != DUPLEX_FULL) {
596 return;
597 }
598
599 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
600 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
601 u32 val;
602
603 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
604 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
605 bp->flow_ctrl |= FLOW_CTRL_TX;
606 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
607 bp->flow_ctrl |= FLOW_CTRL_RX;
608 return;
609 }
610
611 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
612 bnx2_read_phy(bp, MII_LPA, &remote_adv);
613
614 if (bp->phy_flags & PHY_SERDES_FLAG) {
615 u32 new_local_adv = 0;
616 u32 new_remote_adv = 0;
617
618 if (local_adv & ADVERTISE_1000XPAUSE)
619 new_local_adv |= ADVERTISE_PAUSE_CAP;
620 if (local_adv & ADVERTISE_1000XPSE_ASYM)
621 new_local_adv |= ADVERTISE_PAUSE_ASYM;
622 if (remote_adv & ADVERTISE_1000XPAUSE)
623 new_remote_adv |= ADVERTISE_PAUSE_CAP;
624 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
625 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
626
627 local_adv = new_local_adv;
628 remote_adv = new_remote_adv;
629 }
630
631 /* See Table 28B-3 of 802.3ab-1999 spec. */
632 if (local_adv & ADVERTISE_PAUSE_CAP) {
633 if(local_adv & ADVERTISE_PAUSE_ASYM) {
634 if (remote_adv & ADVERTISE_PAUSE_CAP) {
635 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
636 }
637 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
638 bp->flow_ctrl = FLOW_CTRL_RX;
639 }
640 }
641 else {
642 if (remote_adv & ADVERTISE_PAUSE_CAP) {
643 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
644 }
645 }
646 }
647 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
648 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
649 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
650
651 bp->flow_ctrl = FLOW_CTRL_TX;
652 }
653 }
654 }
655
656 static int
657 bnx2_5708s_linkup(struct bnx2 *bp)
658 {
659 u32 val;
660
661 bp->link_up = 1;
662 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
663 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
664 case BCM5708S_1000X_STAT1_SPEED_10:
665 bp->line_speed = SPEED_10;
666 break;
667 case BCM5708S_1000X_STAT1_SPEED_100:
668 bp->line_speed = SPEED_100;
669 break;
670 case BCM5708S_1000X_STAT1_SPEED_1G:
671 bp->line_speed = SPEED_1000;
672 break;
673 case BCM5708S_1000X_STAT1_SPEED_2G5:
674 bp->line_speed = SPEED_2500;
675 break;
676 }
677 if (val & BCM5708S_1000X_STAT1_FD)
678 bp->duplex = DUPLEX_FULL;
679 else
680 bp->duplex = DUPLEX_HALF;
681
682 return 0;
683 }
684
685 static int
686 bnx2_5706s_linkup(struct bnx2 *bp)
687 {
688 u32 bmcr, local_adv, remote_adv, common;
689
690 bp->link_up = 1;
691 bp->line_speed = SPEED_1000;
692
693 bnx2_read_phy(bp, MII_BMCR, &bmcr);
694 if (bmcr & BMCR_FULLDPLX) {
695 bp->duplex = DUPLEX_FULL;
696 }
697 else {
698 bp->duplex = DUPLEX_HALF;
699 }
700
701 if (!(bmcr & BMCR_ANENABLE)) {
702 return 0;
703 }
704
705 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
706 bnx2_read_phy(bp, MII_LPA, &remote_adv);
707
708 common = local_adv & remote_adv;
709 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
710
711 if (common & ADVERTISE_1000XFULL) {
712 bp->duplex = DUPLEX_FULL;
713 }
714 else {
715 bp->duplex = DUPLEX_HALF;
716 }
717 }
718
719 return 0;
720 }
721
722 static int
723 bnx2_copper_linkup(struct bnx2 *bp)
724 {
725 u32 bmcr;
726
727 bnx2_read_phy(bp, MII_BMCR, &bmcr);
728 if (bmcr & BMCR_ANENABLE) {
729 u32 local_adv, remote_adv, common;
730
731 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
732 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
733
734 common = local_adv & (remote_adv >> 2);
735 if (common & ADVERTISE_1000FULL) {
736 bp->line_speed = SPEED_1000;
737 bp->duplex = DUPLEX_FULL;
738 }
739 else if (common & ADVERTISE_1000HALF) {
740 bp->line_speed = SPEED_1000;
741 bp->duplex = DUPLEX_HALF;
742 }
743 else {
744 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
745 bnx2_read_phy(bp, MII_LPA, &remote_adv);
746
747 common = local_adv & remote_adv;
748 if (common & ADVERTISE_100FULL) {
749 bp->line_speed = SPEED_100;
750 bp->duplex = DUPLEX_FULL;
751 }
752 else if (common & ADVERTISE_100HALF) {
753 bp->line_speed = SPEED_100;
754 bp->duplex = DUPLEX_HALF;
755 }
756 else if (common & ADVERTISE_10FULL) {
757 bp->line_speed = SPEED_10;
758 bp->duplex = DUPLEX_FULL;
759 }
760 else if (common & ADVERTISE_10HALF) {
761 bp->line_speed = SPEED_10;
762 bp->duplex = DUPLEX_HALF;
763 }
764 else {
765 bp->line_speed = 0;
766 bp->link_up = 0;
767 }
768 }
769 }
770 else {
771 if (bmcr & BMCR_SPEED100) {
772 bp->line_speed = SPEED_100;
773 }
774 else {
775 bp->line_speed = SPEED_10;
776 }
777 if (bmcr & BMCR_FULLDPLX) {
778 bp->duplex = DUPLEX_FULL;
779 }
780 else {
781 bp->duplex = DUPLEX_HALF;
782 }
783 }
784
785 return 0;
786 }
787
788 static int
789 bnx2_set_mac_link(struct bnx2 *bp)
790 {
791 u32 val;
792
793 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
794 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
795 (bp->duplex == DUPLEX_HALF)) {
796 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
797 }
798
799 /* Configure the EMAC mode register. */
800 val = REG_RD(bp, BNX2_EMAC_MODE);
801
802 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
803 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
804 BNX2_EMAC_MODE_25G);
805
806 if (bp->link_up) {
807 switch (bp->line_speed) {
808 case SPEED_10:
809 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
810 val |= BNX2_EMAC_MODE_PORT_MII_10;
811 break;
812 }
813 /* fall through */
814 case SPEED_100:
815 val |= BNX2_EMAC_MODE_PORT_MII;
816 break;
817 case SPEED_2500:
818 val |= BNX2_EMAC_MODE_25G;
819 /* fall through */
820 case SPEED_1000:
821 val |= BNX2_EMAC_MODE_PORT_GMII;
822 break;
823 }
824 }
825 else {
826 val |= BNX2_EMAC_MODE_PORT_GMII;
827 }
828
829 /* Set the MAC to operate in the appropriate duplex mode. */
830 if (bp->duplex == DUPLEX_HALF)
831 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
832 REG_WR(bp, BNX2_EMAC_MODE, val);
833
834 /* Enable/disable rx PAUSE. */
835 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
836
837 if (bp->flow_ctrl & FLOW_CTRL_RX)
838 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
839 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
840
841 /* Enable/disable tx PAUSE. */
842 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
843 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
844
845 if (bp->flow_ctrl & FLOW_CTRL_TX)
846 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
847 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
848
849 /* Acknowledge the interrupt. */
850 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
851
852 return 0;
853 }
854
855 static int
856 bnx2_set_link(struct bnx2 *bp)
857 {
858 u32 bmsr;
859 u8 link_up;
860
861 if (bp->loopback == MAC_LOOPBACK) {
862 bp->link_up = 1;
863 return 0;
864 }
865
866 link_up = bp->link_up;
867
868 bnx2_read_phy(bp, MII_BMSR, &bmsr);
869 bnx2_read_phy(bp, MII_BMSR, &bmsr);
870
871 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
872 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
873 u32 val;
874
875 val = REG_RD(bp, BNX2_EMAC_STATUS);
876 if (val & BNX2_EMAC_STATUS_LINK)
877 bmsr |= BMSR_LSTATUS;
878 else
879 bmsr &= ~BMSR_LSTATUS;
880 }
881
882 if (bmsr & BMSR_LSTATUS) {
883 bp->link_up = 1;
884
885 if (bp->phy_flags & PHY_SERDES_FLAG) {
886 if (CHIP_NUM(bp) == CHIP_NUM_5706)
887 bnx2_5706s_linkup(bp);
888 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
889 bnx2_5708s_linkup(bp);
890 }
891 else {
892 bnx2_copper_linkup(bp);
893 }
894 bnx2_resolve_flow_ctrl(bp);
895 }
896 else {
897 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
898 (bp->autoneg & AUTONEG_SPEED)) {
899
900 u32 bmcr;
901
902 bnx2_read_phy(bp, MII_BMCR, &bmcr);
903 if (!(bmcr & BMCR_ANENABLE)) {
904 bnx2_write_phy(bp, MII_BMCR, bmcr |
905 BMCR_ANENABLE);
906 }
907 }
908 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
909 bp->link_up = 0;
910 }
911
912 if (bp->link_up != link_up) {
913 bnx2_report_link(bp);
914 }
915
916 bnx2_set_mac_link(bp);
917
918 return 0;
919 }
920
921 static int
922 bnx2_reset_phy(struct bnx2 *bp)
923 {
924 int i;
925 u32 reg;
926
927 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
928
929 #define PHY_RESET_MAX_WAIT 100
930 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
931 udelay(10);
932
933 bnx2_read_phy(bp, MII_BMCR, &reg);
934 if (!(reg & BMCR_RESET)) {
935 udelay(20);
936 break;
937 }
938 }
939 if (i == PHY_RESET_MAX_WAIT) {
940 return -EBUSY;
941 }
942 return 0;
943 }
944
945 static u32
946 bnx2_phy_get_pause_adv(struct bnx2 *bp)
947 {
948 u32 adv = 0;
949
950 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
951 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
952
953 if (bp->phy_flags & PHY_SERDES_FLAG) {
954 adv = ADVERTISE_1000XPAUSE;
955 }
956 else {
957 adv = ADVERTISE_PAUSE_CAP;
958 }
959 }
960 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
961 if (bp->phy_flags & PHY_SERDES_FLAG) {
962 adv = ADVERTISE_1000XPSE_ASYM;
963 }
964 else {
965 adv = ADVERTISE_PAUSE_ASYM;
966 }
967 }
968 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
969 if (bp->phy_flags & PHY_SERDES_FLAG) {
970 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
971 }
972 else {
973 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
974 }
975 }
976 return adv;
977 }
978
979 static int
980 bnx2_setup_serdes_phy(struct bnx2 *bp)
981 {
982 u32 adv, bmcr, up1;
983 u32 new_adv = 0;
984
985 if (!(bp->autoneg & AUTONEG_SPEED)) {
986 u32 new_bmcr;
987 int force_link_down = 0;
988
989 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
990 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
991 if (up1 & BCM5708S_UP1_2G5) {
992 up1 &= ~BCM5708S_UP1_2G5;
993 bnx2_write_phy(bp, BCM5708S_UP1, up1);
994 force_link_down = 1;
995 }
996 }
997
998 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
999 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1000
1001 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1002 new_bmcr = bmcr & ~BMCR_ANENABLE;
1003 new_bmcr |= BMCR_SPEED1000;
1004 if (bp->req_duplex == DUPLEX_FULL) {
1005 adv |= ADVERTISE_1000XFULL;
1006 new_bmcr |= BMCR_FULLDPLX;
1007 }
1008 else {
1009 adv |= ADVERTISE_1000XHALF;
1010 new_bmcr &= ~BMCR_FULLDPLX;
1011 }
1012 if ((new_bmcr != bmcr) || (force_link_down)) {
1013 /* Force a link down visible on the other side */
1014 if (bp->link_up) {
1015 bnx2_write_phy(bp, MII_ADVERTISE, adv &
1016 ~(ADVERTISE_1000XFULL |
1017 ADVERTISE_1000XHALF));
1018 bnx2_write_phy(bp, MII_BMCR, bmcr |
1019 BMCR_ANRESTART | BMCR_ANENABLE);
1020
1021 bp->link_up = 0;
1022 netif_carrier_off(bp->dev);
1023 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1024 }
1025 bnx2_write_phy(bp, MII_ADVERTISE, adv);
1026 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1027 }
1028 return 0;
1029 }
1030
1031 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1032 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
1033 up1 |= BCM5708S_UP1_2G5;
1034 bnx2_write_phy(bp, BCM5708S_UP1, up1);
1035 }
1036
1037 if (bp->advertising & ADVERTISED_1000baseT_Full)
1038 new_adv |= ADVERTISE_1000XFULL;
1039
1040 new_adv |= bnx2_phy_get_pause_adv(bp);
1041
1042 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
1043 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1044
1045 bp->serdes_an_pending = 0;
1046 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1047 /* Force a link down visible on the other side */
1048 if (bp->link_up) {
1049 int i;
1050
1051 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1052 for (i = 0; i < 110; i++) {
1053 udelay(100);
1054 }
1055 }
1056
1057 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1058 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1059 BMCR_ANENABLE);
1060 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1061 /* Speed up link-up time when the link partner
1062 * does not autonegotiate which is very common
1063 * in blade servers. Some blade servers use
1064 * IPMI for kerboard input and it's important
1065 * to minimize link disruptions. Autoneg. involves
1066 * exchanging base pages plus 3 next pages and
1067 * normally completes in about 120 msec.
1068 */
1069 bp->current_interval = SERDES_AN_TIMEOUT;
1070 bp->serdes_an_pending = 1;
1071 mod_timer(&bp->timer, jiffies + bp->current_interval);
1072 }
1073 }
1074
1075 return 0;
1076 }
1077
1078 #define ETHTOOL_ALL_FIBRE_SPEED \
1079 (ADVERTISED_1000baseT_Full)
1080
1081 #define ETHTOOL_ALL_COPPER_SPEED \
1082 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1083 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1084 ADVERTISED_1000baseT_Full)
1085
1086 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1087 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1088
1089 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1090
1091 static int
1092 bnx2_setup_copper_phy(struct bnx2 *bp)
1093 {
1094 u32 bmcr;
1095 u32 new_bmcr;
1096
1097 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1098
1099 if (bp->autoneg & AUTONEG_SPEED) {
1100 u32 adv_reg, adv1000_reg;
1101 u32 new_adv_reg = 0;
1102 u32 new_adv1000_reg = 0;
1103
1104 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
1105 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1106 ADVERTISE_PAUSE_ASYM);
1107
1108 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1109 adv1000_reg &= PHY_ALL_1000_SPEED;
1110
1111 if (bp->advertising & ADVERTISED_10baseT_Half)
1112 new_adv_reg |= ADVERTISE_10HALF;
1113 if (bp->advertising & ADVERTISED_10baseT_Full)
1114 new_adv_reg |= ADVERTISE_10FULL;
1115 if (bp->advertising & ADVERTISED_100baseT_Half)
1116 new_adv_reg |= ADVERTISE_100HALF;
1117 if (bp->advertising & ADVERTISED_100baseT_Full)
1118 new_adv_reg |= ADVERTISE_100FULL;
1119 if (bp->advertising & ADVERTISED_1000baseT_Full)
1120 new_adv1000_reg |= ADVERTISE_1000FULL;
1121
1122 new_adv_reg |= ADVERTISE_CSMA;
1123
1124 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1125
1126 if ((adv1000_reg != new_adv1000_reg) ||
1127 (adv_reg != new_adv_reg) ||
1128 ((bmcr & BMCR_ANENABLE) == 0)) {
1129
1130 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1131 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1132 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1133 BMCR_ANENABLE);
1134 }
1135 else if (bp->link_up) {
1136 /* Flow ctrl may have changed from auto to forced */
1137 /* or vice-versa. */
1138
1139 bnx2_resolve_flow_ctrl(bp);
1140 bnx2_set_mac_link(bp);
1141 }
1142 return 0;
1143 }
1144
1145 new_bmcr = 0;
1146 if (bp->req_line_speed == SPEED_100) {
1147 new_bmcr |= BMCR_SPEED100;
1148 }
1149 if (bp->req_duplex == DUPLEX_FULL) {
1150 new_bmcr |= BMCR_FULLDPLX;
1151 }
1152 if (new_bmcr != bmcr) {
1153 u32 bmsr;
1154 int i = 0;
1155
1156 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1157 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1158
1159 if (bmsr & BMSR_LSTATUS) {
1160 /* Force link down */
1161 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1162 do {
1163 udelay(100);
1164 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1165 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1166 i++;
1167 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1168 }
1169
1170 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1171
1172 /* Normally, the new speed is setup after the link has
1173 * gone down and up again. In some cases, link will not go
1174 * down so we need to set up the new speed here.
1175 */
1176 if (bmsr & BMSR_LSTATUS) {
1177 bp->line_speed = bp->req_line_speed;
1178 bp->duplex = bp->req_duplex;
1179 bnx2_resolve_flow_ctrl(bp);
1180 bnx2_set_mac_link(bp);
1181 }
1182 }
1183 return 0;
1184 }
1185
1186 static int
1187 bnx2_setup_phy(struct bnx2 *bp)
1188 {
1189 if (bp->loopback == MAC_LOOPBACK)
1190 return 0;
1191
1192 if (bp->phy_flags & PHY_SERDES_FLAG) {
1193 return (bnx2_setup_serdes_phy(bp));
1194 }
1195 else {
1196 return (bnx2_setup_copper_phy(bp));
1197 }
1198 }
1199
1200 static int
1201 bnx2_init_5708s_phy(struct bnx2 *bp)
1202 {
1203 u32 val;
1204
1205 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1206 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1207 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1208
1209 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1210 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1211 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1212
1213 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1214 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1215 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1216
1217 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1218 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1219 val |= BCM5708S_UP1_2G5;
1220 bnx2_write_phy(bp, BCM5708S_UP1, val);
1221 }
1222
1223 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1224 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1225 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1226 /* increase tx signal amplitude */
1227 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1228 BCM5708S_BLK_ADDR_TX_MISC);
1229 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1230 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1231 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1232 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1233 }
1234
1235 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1236 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1237
1238 if (val) {
1239 u32 is_backplane;
1240
1241 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1242 BNX2_SHARED_HW_CFG_CONFIG);
1243 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1244 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1245 BCM5708S_BLK_ADDR_TX_MISC);
1246 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1247 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1248 BCM5708S_BLK_ADDR_DIG);
1249 }
1250 }
1251 return 0;
1252 }
1253
1254 static int
1255 bnx2_init_5706s_phy(struct bnx2 *bp)
1256 {
1257 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1258
1259 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1260 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1261 }
1262
1263 if (bp->dev->mtu > 1500) {
1264 u32 val;
1265
1266 /* Set extended packet length bit */
1267 bnx2_write_phy(bp, 0x18, 0x7);
1268 bnx2_read_phy(bp, 0x18, &val);
1269 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1270
1271 bnx2_write_phy(bp, 0x1c, 0x6c00);
1272 bnx2_read_phy(bp, 0x1c, &val);
1273 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1274 }
1275 else {
1276 u32 val;
1277
1278 bnx2_write_phy(bp, 0x18, 0x7);
1279 bnx2_read_phy(bp, 0x18, &val);
1280 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1281
1282 bnx2_write_phy(bp, 0x1c, 0x6c00);
1283 bnx2_read_phy(bp, 0x1c, &val);
1284 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1285 }
1286
1287 return 0;
1288 }
1289
1290 static int
1291 bnx2_init_copper_phy(struct bnx2 *bp)
1292 {
1293 u32 val;
1294
1295 bp->phy_flags |= PHY_CRC_FIX_FLAG;
1296
1297 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1298 bnx2_write_phy(bp, 0x18, 0x0c00);
1299 bnx2_write_phy(bp, 0x17, 0x000a);
1300 bnx2_write_phy(bp, 0x15, 0x310b);
1301 bnx2_write_phy(bp, 0x17, 0x201f);
1302 bnx2_write_phy(bp, 0x15, 0x9506);
1303 bnx2_write_phy(bp, 0x17, 0x401f);
1304 bnx2_write_phy(bp, 0x15, 0x14e2);
1305 bnx2_write_phy(bp, 0x18, 0x0400);
1306 }
1307
1308 if (bp->dev->mtu > 1500) {
1309 /* Set extended packet length bit */
1310 bnx2_write_phy(bp, 0x18, 0x7);
1311 bnx2_read_phy(bp, 0x18, &val);
1312 bnx2_write_phy(bp, 0x18, val | 0x4000);
1313
1314 bnx2_read_phy(bp, 0x10, &val);
1315 bnx2_write_phy(bp, 0x10, val | 0x1);
1316 }
1317 else {
1318 bnx2_write_phy(bp, 0x18, 0x7);
1319 bnx2_read_phy(bp, 0x18, &val);
1320 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1321
1322 bnx2_read_phy(bp, 0x10, &val);
1323 bnx2_write_phy(bp, 0x10, val & ~0x1);
1324 }
1325
1326 /* ethernet@wirespeed */
1327 bnx2_write_phy(bp, 0x18, 0x7007);
1328 bnx2_read_phy(bp, 0x18, &val);
1329 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1330 return 0;
1331 }
1332
1333
1334 static int
1335 bnx2_init_phy(struct bnx2 *bp)
1336 {
1337 u32 val;
1338 int rc = 0;
1339
1340 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1341 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1342
1343 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1344
1345 bnx2_reset_phy(bp);
1346
1347 bnx2_read_phy(bp, MII_PHYSID1, &val);
1348 bp->phy_id = val << 16;
1349 bnx2_read_phy(bp, MII_PHYSID2, &val);
1350 bp->phy_id |= val & 0xffff;
1351
1352 if (bp->phy_flags & PHY_SERDES_FLAG) {
1353 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1354 rc = bnx2_init_5706s_phy(bp);
1355 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1356 rc = bnx2_init_5708s_phy(bp);
1357 }
1358 else {
1359 rc = bnx2_init_copper_phy(bp);
1360 }
1361
1362 bnx2_setup_phy(bp);
1363
1364 return rc;
1365 }
1366
1367 static int
1368 bnx2_set_mac_loopback(struct bnx2 *bp)
1369 {
1370 u32 mac_mode;
1371
1372 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1373 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1374 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1375 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1376 bp->link_up = 1;
1377 return 0;
1378 }
1379
1380 static int bnx2_test_link(struct bnx2 *);
1381
1382 static int
1383 bnx2_set_phy_loopback(struct bnx2 *bp)
1384 {
1385 u32 mac_mode;
1386 int rc, i;
1387
1388 spin_lock_bh(&bp->phy_lock);
1389 rc = bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
1390 BMCR_SPEED1000);
1391 spin_unlock_bh(&bp->phy_lock);
1392 if (rc)
1393 return rc;
1394
1395 for (i = 0; i < 10; i++) {
1396 if (bnx2_test_link(bp) == 0)
1397 break;
1398 udelay(10);
1399 }
1400
1401 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1402 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1403 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1404 BNX2_EMAC_MODE_25G);
1405
1406 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
1407 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1408 bp->link_up = 1;
1409 return 0;
1410 }
1411
1412 static int
1413 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1414 {
1415 int i;
1416 u32 val;
1417
1418 bp->fw_wr_seq++;
1419 msg_data |= bp->fw_wr_seq;
1420
1421 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1422
1423 /* wait for an acknowledgement. */
1424 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1425 msleep(10);
1426
1427 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1428
1429 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1430 break;
1431 }
1432 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1433 return 0;
1434
1435 /* If we timed out, inform the firmware that this is the case. */
1436 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1437 if (!silent)
1438 printk(KERN_ERR PFX "fw sync timeout, reset code = "
1439 "%x\n", msg_data);
1440
1441 msg_data &= ~BNX2_DRV_MSG_CODE;
1442 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1443
1444 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1445
1446 return -EBUSY;
1447 }
1448
1449 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1450 return -EIO;
1451
1452 return 0;
1453 }
1454
1455 static void
1456 bnx2_init_context(struct bnx2 *bp)
1457 {
1458 u32 vcid;
1459
1460 vcid = 96;
1461 while (vcid) {
1462 u32 vcid_addr, pcid_addr, offset;
1463
1464 vcid--;
1465
1466 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1467 u32 new_vcid;
1468
1469 vcid_addr = GET_PCID_ADDR(vcid);
1470 if (vcid & 0x8) {
1471 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1472 }
1473 else {
1474 new_vcid = vcid;
1475 }
1476 pcid_addr = GET_PCID_ADDR(new_vcid);
1477 }
1478 else {
1479 vcid_addr = GET_CID_ADDR(vcid);
1480 pcid_addr = vcid_addr;
1481 }
1482
1483 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1484 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1485
1486 /* Zero out the context. */
1487 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1488 CTX_WR(bp, 0x00, offset, 0);
1489 }
1490
1491 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1492 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1493 }
1494 }
1495
1496 static int
1497 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1498 {
1499 u16 *good_mbuf;
1500 u32 good_mbuf_cnt;
1501 u32 val;
1502
1503 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1504 if (good_mbuf == NULL) {
1505 printk(KERN_ERR PFX "Failed to allocate memory in "
1506 "bnx2_alloc_bad_rbuf\n");
1507 return -ENOMEM;
1508 }
1509
1510 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1511 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1512
1513 good_mbuf_cnt = 0;
1514
1515 /* Allocate a bunch of mbufs and save the good ones in an array. */
1516 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1517 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1518 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1519
1520 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1521
1522 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1523
1524 /* The addresses with Bit 9 set are bad memory blocks. */
1525 if (!(val & (1 << 9))) {
1526 good_mbuf[good_mbuf_cnt] = (u16) val;
1527 good_mbuf_cnt++;
1528 }
1529
1530 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1531 }
1532
1533 /* Free the good ones back to the mbuf pool thus discarding
1534 * all the bad ones. */
1535 while (good_mbuf_cnt) {
1536 good_mbuf_cnt--;
1537
1538 val = good_mbuf[good_mbuf_cnt];
1539 val = (val << 9) | val | 1;
1540
1541 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1542 }
1543 kfree(good_mbuf);
1544 return 0;
1545 }
1546
1547 static void
1548 bnx2_set_mac_addr(struct bnx2 *bp)
1549 {
1550 u32 val;
1551 u8 *mac_addr = bp->dev->dev_addr;
1552
1553 val = (mac_addr[0] << 8) | mac_addr[1];
1554
1555 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1556
1557 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1558 (mac_addr[4] << 8) | mac_addr[5];
1559
1560 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1561 }
1562
1563 static inline int
1564 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1565 {
1566 struct sk_buff *skb;
1567 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1568 dma_addr_t mapping;
1569 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
1570 unsigned long align;
1571
1572 skb = dev_alloc_skb(bp->rx_buf_size);
1573 if (skb == NULL) {
1574 return -ENOMEM;
1575 }
1576
1577 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1578 skb_reserve(skb, 8 - align);
1579 }
1580
1581 skb->dev = bp->dev;
1582 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1583 PCI_DMA_FROMDEVICE);
1584
1585 rx_buf->skb = skb;
1586 pci_unmap_addr_set(rx_buf, mapping, mapping);
1587
1588 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1589 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1590
1591 bp->rx_prod_bseq += bp->rx_buf_use_size;
1592
1593 return 0;
1594 }
1595
1596 static void
1597 bnx2_phy_int(struct bnx2 *bp)
1598 {
1599 u32 new_link_state, old_link_state;
1600
1601 new_link_state = bp->status_blk->status_attn_bits &
1602 STATUS_ATTN_BITS_LINK_STATE;
1603 old_link_state = bp->status_blk->status_attn_bits_ack &
1604 STATUS_ATTN_BITS_LINK_STATE;
1605 if (new_link_state != old_link_state) {
1606 if (new_link_state) {
1607 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1608 STATUS_ATTN_BITS_LINK_STATE);
1609 }
1610 else {
1611 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1612 STATUS_ATTN_BITS_LINK_STATE);
1613 }
1614 bnx2_set_link(bp);
1615 }
1616 }
1617
1618 static void
1619 bnx2_tx_int(struct bnx2 *bp)
1620 {
1621 struct status_block *sblk = bp->status_blk;
1622 u16 hw_cons, sw_cons, sw_ring_cons;
1623 int tx_free_bd = 0;
1624
1625 hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
1626 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1627 hw_cons++;
1628 }
1629 sw_cons = bp->tx_cons;
1630
1631 while (sw_cons != hw_cons) {
1632 struct sw_bd *tx_buf;
1633 struct sk_buff *skb;
1634 int i, last;
1635
1636 sw_ring_cons = TX_RING_IDX(sw_cons);
1637
1638 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1639 skb = tx_buf->skb;
1640 #ifdef BCM_TSO
1641 /* partial BD completions possible with TSO packets */
1642 if (skb_is_gso(skb)) {
1643 u16 last_idx, last_ring_idx;
1644
1645 last_idx = sw_cons +
1646 skb_shinfo(skb)->nr_frags + 1;
1647 last_ring_idx = sw_ring_cons +
1648 skb_shinfo(skb)->nr_frags + 1;
1649 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1650 last_idx++;
1651 }
1652 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1653 break;
1654 }
1655 }
1656 #endif
1657 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1658 skb_headlen(skb), PCI_DMA_TODEVICE);
1659
1660 tx_buf->skb = NULL;
1661 last = skb_shinfo(skb)->nr_frags;
1662
1663 for (i = 0; i < last; i++) {
1664 sw_cons = NEXT_TX_BD(sw_cons);
1665
1666 pci_unmap_page(bp->pdev,
1667 pci_unmap_addr(
1668 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1669 mapping),
1670 skb_shinfo(skb)->frags[i].size,
1671 PCI_DMA_TODEVICE);
1672 }
1673
1674 sw_cons = NEXT_TX_BD(sw_cons);
1675
1676 tx_free_bd += last + 1;
1677
1678 dev_kfree_skb(skb);
1679
1680 hw_cons = bp->hw_tx_cons =
1681 sblk->status_tx_quick_consumer_index0;
1682
1683 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1684 hw_cons++;
1685 }
1686 }
1687
1688 bp->tx_cons = sw_cons;
1689
1690 if (unlikely(netif_queue_stopped(bp->dev))) {
1691 spin_lock(&bp->tx_lock);
1692 if ((netif_queue_stopped(bp->dev)) &&
1693 (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
1694
1695 netif_wake_queue(bp->dev);
1696 }
1697 spin_unlock(&bp->tx_lock);
1698 }
1699 }
1700
1701 static inline void
1702 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1703 u16 cons, u16 prod)
1704 {
1705 struct sw_bd *cons_rx_buf, *prod_rx_buf;
1706 struct rx_bd *cons_bd, *prod_bd;
1707
1708 cons_rx_buf = &bp->rx_buf_ring[cons];
1709 prod_rx_buf = &bp->rx_buf_ring[prod];
1710
1711 pci_dma_sync_single_for_device(bp->pdev,
1712 pci_unmap_addr(cons_rx_buf, mapping),
1713 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1714
1715 bp->rx_prod_bseq += bp->rx_buf_use_size;
1716
1717 prod_rx_buf->skb = skb;
1718
1719 if (cons == prod)
1720 return;
1721
1722 pci_unmap_addr_set(prod_rx_buf, mapping,
1723 pci_unmap_addr(cons_rx_buf, mapping));
1724
1725 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
1726 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1727 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
1728 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
1729 }
1730
1731 static int
1732 bnx2_rx_int(struct bnx2 *bp, int budget)
1733 {
1734 struct status_block *sblk = bp->status_blk;
1735 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1736 struct l2_fhdr *rx_hdr;
1737 int rx_pkt = 0;
1738
1739 hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
1740 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1741 hw_cons++;
1742 }
1743 sw_cons = bp->rx_cons;
1744 sw_prod = bp->rx_prod;
1745
1746 /* Memory barrier necessary as speculative reads of the rx
1747 * buffer can be ahead of the index in the status block
1748 */
1749 rmb();
1750 while (sw_cons != hw_cons) {
1751 unsigned int len;
1752 u32 status;
1753 struct sw_bd *rx_buf;
1754 struct sk_buff *skb;
1755 dma_addr_t dma_addr;
1756
1757 sw_ring_cons = RX_RING_IDX(sw_cons);
1758 sw_ring_prod = RX_RING_IDX(sw_prod);
1759
1760 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1761 skb = rx_buf->skb;
1762
1763 rx_buf->skb = NULL;
1764
1765 dma_addr = pci_unmap_addr(rx_buf, mapping);
1766
1767 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
1768 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1769
1770 rx_hdr = (struct l2_fhdr *) skb->data;
1771 len = rx_hdr->l2_fhdr_pkt_len - 4;
1772
1773 if ((status = rx_hdr->l2_fhdr_status) &
1774 (L2_FHDR_ERRORS_BAD_CRC |
1775 L2_FHDR_ERRORS_PHY_DECODE |
1776 L2_FHDR_ERRORS_ALIGNMENT |
1777 L2_FHDR_ERRORS_TOO_SHORT |
1778 L2_FHDR_ERRORS_GIANT_FRAME)) {
1779
1780 goto reuse_rx;
1781 }
1782
1783 /* Since we don't have a jumbo ring, copy small packets
1784 * if mtu > 1500
1785 */
1786 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1787 struct sk_buff *new_skb;
1788
1789 new_skb = dev_alloc_skb(len + 2);
1790 if (new_skb == NULL)
1791 goto reuse_rx;
1792
1793 /* aligned copy */
1794 memcpy(new_skb->data,
1795 skb->data + bp->rx_offset - 2,
1796 len + 2);
1797
1798 skb_reserve(new_skb, 2);
1799 skb_put(new_skb, len);
1800 new_skb->dev = bp->dev;
1801
1802 bnx2_reuse_rx_skb(bp, skb,
1803 sw_ring_cons, sw_ring_prod);
1804
1805 skb = new_skb;
1806 }
1807 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1808 pci_unmap_single(bp->pdev, dma_addr,
1809 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1810
1811 skb_reserve(skb, bp->rx_offset);
1812 skb_put(skb, len);
1813 }
1814 else {
1815 reuse_rx:
1816 bnx2_reuse_rx_skb(bp, skb,
1817 sw_ring_cons, sw_ring_prod);
1818 goto next_rx;
1819 }
1820
1821 skb->protocol = eth_type_trans(skb, bp->dev);
1822
1823 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1824 (ntohs(skb->protocol) != 0x8100)) {
1825
1826 dev_kfree_skb(skb);
1827 goto next_rx;
1828
1829 }
1830
1831 skb->ip_summed = CHECKSUM_NONE;
1832 if (bp->rx_csum &&
1833 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1834 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1835
1836 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
1837 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
1838 skb->ip_summed = CHECKSUM_UNNECESSARY;
1839 }
1840
1841 #ifdef BCM_VLAN
1842 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1843 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1844 rx_hdr->l2_fhdr_vlan_tag);
1845 }
1846 else
1847 #endif
1848 netif_receive_skb(skb);
1849
1850 bp->dev->last_rx = jiffies;
1851 rx_pkt++;
1852
1853 next_rx:
1854 sw_cons = NEXT_RX_BD(sw_cons);
1855 sw_prod = NEXT_RX_BD(sw_prod);
1856
1857 if ((rx_pkt == budget))
1858 break;
1859
1860 /* Refresh hw_cons to see if there is new work */
1861 if (sw_cons == hw_cons) {
1862 hw_cons = bp->hw_rx_cons =
1863 sblk->status_rx_quick_consumer_index0;
1864 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
1865 hw_cons++;
1866 rmb();
1867 }
1868 }
1869 bp->rx_cons = sw_cons;
1870 bp->rx_prod = sw_prod;
1871
1872 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1873
1874 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1875
1876 mmiowb();
1877
1878 return rx_pkt;
1879
1880 }
1881
1882 /* MSI ISR - The only difference between this and the INTx ISR
1883 * is that the MSI interrupt is always serviced.
1884 */
1885 static irqreturn_t
1886 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1887 {
1888 struct net_device *dev = dev_instance;
1889 struct bnx2 *bp = netdev_priv(dev);
1890
1891 prefetch(bp->status_blk);
1892 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1893 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1894 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1895
1896 /* Return here if interrupt is disabled. */
1897 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1898 return IRQ_HANDLED;
1899
1900 netif_rx_schedule(dev);
1901
1902 return IRQ_HANDLED;
1903 }
1904
1905 static irqreturn_t
1906 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1907 {
1908 struct net_device *dev = dev_instance;
1909 struct bnx2 *bp = netdev_priv(dev);
1910
1911 /* When using INTx, it is possible for the interrupt to arrive
1912 * at the CPU before the status block posted prior to the
1913 * interrupt. Reading a register will flush the status block.
1914 * When using MSI, the MSI message will always complete after
1915 * the status block write.
1916 */
1917 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
1918 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1919 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1920 return IRQ_NONE;
1921
1922 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1923 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1924 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1925
1926 /* Return here if interrupt is shared and is disabled. */
1927 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1928 return IRQ_HANDLED;
1929
1930 netif_rx_schedule(dev);
1931
1932 return IRQ_HANDLED;
1933 }
1934
1935 static inline int
1936 bnx2_has_work(struct bnx2 *bp)
1937 {
1938 struct status_block *sblk = bp->status_blk;
1939
1940 if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
1941 (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
1942 return 1;
1943
1944 if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
1945 bp->link_up)
1946 return 1;
1947
1948 return 0;
1949 }
1950
1951 static int
1952 bnx2_poll(struct net_device *dev, int *budget)
1953 {
1954 struct bnx2 *bp = netdev_priv(dev);
1955
1956 if ((bp->status_blk->status_attn_bits &
1957 STATUS_ATTN_BITS_LINK_STATE) !=
1958 (bp->status_blk->status_attn_bits_ack &
1959 STATUS_ATTN_BITS_LINK_STATE)) {
1960
1961 spin_lock(&bp->phy_lock);
1962 bnx2_phy_int(bp);
1963 spin_unlock(&bp->phy_lock);
1964
1965 /* This is needed to take care of transient status
1966 * during link changes.
1967 */
1968 REG_WR(bp, BNX2_HC_COMMAND,
1969 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
1970 REG_RD(bp, BNX2_HC_COMMAND);
1971 }
1972
1973 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
1974 bnx2_tx_int(bp);
1975
1976 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
1977 int orig_budget = *budget;
1978 int work_done;
1979
1980 if (orig_budget > dev->quota)
1981 orig_budget = dev->quota;
1982
1983 work_done = bnx2_rx_int(bp, orig_budget);
1984 *budget -= work_done;
1985 dev->quota -= work_done;
1986 }
1987
1988 bp->last_status_idx = bp->status_blk->status_idx;
1989 rmb();
1990
1991 if (!bnx2_has_work(bp)) {
1992 netif_rx_complete(dev);
1993 if (likely(bp->flags & USING_MSI_FLAG)) {
1994 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1995 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1996 bp->last_status_idx);
1997 return 0;
1998 }
1999 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2000 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2001 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2002 bp->last_status_idx);
2003
2004 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2005 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2006 bp->last_status_idx);
2007 return 0;
2008 }
2009
2010 return 1;
2011 }
2012
2013 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
2014 * from set_multicast.
2015 */
2016 static void
2017 bnx2_set_rx_mode(struct net_device *dev)
2018 {
2019 struct bnx2 *bp = netdev_priv(dev);
2020 u32 rx_mode, sort_mode;
2021 int i;
2022
2023 spin_lock_bh(&bp->phy_lock);
2024
2025 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2026 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2027 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2028 #ifdef BCM_VLAN
2029 if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
2030 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2031 #else
2032 if (!(bp->flags & ASF_ENABLE_FLAG))
2033 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2034 #endif
2035 if (dev->flags & IFF_PROMISC) {
2036 /* Promiscuous mode. */
2037 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2038 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
2039 }
2040 else if (dev->flags & IFF_ALLMULTI) {
2041 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2042 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2043 0xffffffff);
2044 }
2045 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2046 }
2047 else {
2048 /* Accept one or more multicast(s). */
2049 struct dev_mc_list *mclist;
2050 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2051 u32 regidx;
2052 u32 bit;
2053 u32 crc;
2054
2055 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2056
2057 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2058 i++, mclist = mclist->next) {
2059
2060 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2061 bit = crc & 0xff;
2062 regidx = (bit & 0xe0) >> 5;
2063 bit &= 0x1f;
2064 mc_filter[regidx] |= (1 << bit);
2065 }
2066
2067 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2068 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2069 mc_filter[i]);
2070 }
2071
2072 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2073 }
2074
2075 if (rx_mode != bp->rx_mode) {
2076 bp->rx_mode = rx_mode;
2077 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2078 }
2079
2080 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2081 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2082 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2083
2084 spin_unlock_bh(&bp->phy_lock);
2085 }
2086
2087 #define FW_BUF_SIZE 0x8000
2088
2089 static int
2090 bnx2_gunzip_init(struct bnx2 *bp)
2091 {
2092 if ((bp->gunzip_buf = vmalloc(FW_BUF_SIZE)) == NULL)
2093 goto gunzip_nomem1;
2094
2095 if ((bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL)) == NULL)
2096 goto gunzip_nomem2;
2097
2098 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL);
2099 if (bp->strm->workspace == NULL)
2100 goto gunzip_nomem3;
2101
2102 return 0;
2103
2104 gunzip_nomem3:
2105 kfree(bp->strm);
2106 bp->strm = NULL;
2107
2108 gunzip_nomem2:
2109 vfree(bp->gunzip_buf);
2110 bp->gunzip_buf = NULL;
2111
2112 gunzip_nomem1:
2113 printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for "
2114 "uncompression.\n", bp->dev->name);
2115 return -ENOMEM;
2116 }
2117
2118 static void
2119 bnx2_gunzip_end(struct bnx2 *bp)
2120 {
2121 kfree(bp->strm->workspace);
2122
2123 kfree(bp->strm);
2124 bp->strm = NULL;
2125
2126 if (bp->gunzip_buf) {
2127 vfree(bp->gunzip_buf);
2128 bp->gunzip_buf = NULL;
2129 }
2130 }
2131
2132 static int
2133 bnx2_gunzip(struct bnx2 *bp, u8 *zbuf, int len, void **outbuf, int *outlen)
2134 {
2135 int n, rc;
2136
2137 /* check gzip header */
2138 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
2139 return -EINVAL;
2140
2141 n = 10;
2142
2143 #define FNAME 0x8
2144 if (zbuf[3] & FNAME)
2145 while ((zbuf[n++] != 0) && (n < len));
2146
2147 bp->strm->next_in = zbuf + n;
2148 bp->strm->avail_in = len - n;
2149 bp->strm->next_out = bp->gunzip_buf;
2150 bp->strm->avail_out = FW_BUF_SIZE;
2151
2152 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
2153 if (rc != Z_OK)
2154 return rc;
2155
2156 rc = zlib_inflate(bp->strm, Z_FINISH);
2157
2158 *outlen = FW_BUF_SIZE - bp->strm->avail_out;
2159 *outbuf = bp->gunzip_buf;
2160
2161 if ((rc != Z_OK) && (rc != Z_STREAM_END))
2162 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
2163 bp->dev->name, bp->strm->msg);
2164
2165 zlib_inflateEnd(bp->strm);
2166
2167 if (rc == Z_STREAM_END)
2168 return 0;
2169
2170 return rc;
2171 }
2172
2173 static void
2174 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2175 u32 rv2p_proc)
2176 {
2177 int i;
2178 u32 val;
2179
2180
2181 for (i = 0; i < rv2p_code_len; i += 8) {
2182 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
2183 rv2p_code++;
2184 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
2185 rv2p_code++;
2186
2187 if (rv2p_proc == RV2P_PROC1) {
2188 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2189 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2190 }
2191 else {
2192 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2193 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2194 }
2195 }
2196
2197 /* Reset the processor, un-stall is done later. */
2198 if (rv2p_proc == RV2P_PROC1) {
2199 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2200 }
2201 else {
2202 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2203 }
2204 }
2205
2206 static void
2207 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2208 {
2209 u32 offset;
2210 u32 val;
2211
2212 /* Halt the CPU. */
2213 val = REG_RD_IND(bp, cpu_reg->mode);
2214 val |= cpu_reg->mode_value_halt;
2215 REG_WR_IND(bp, cpu_reg->mode, val);
2216 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2217
2218 /* Load the Text area. */
2219 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2220 if (fw->text) {
2221 int j;
2222
2223 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2224 REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
2225 }
2226 }
2227
2228 /* Load the Data area. */
2229 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2230 if (fw->data) {
2231 int j;
2232
2233 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2234 REG_WR_IND(bp, offset, fw->data[j]);
2235 }
2236 }
2237
2238 /* Load the SBSS area. */
2239 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2240 if (fw->sbss) {
2241 int j;
2242
2243 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2244 REG_WR_IND(bp, offset, fw->sbss[j]);
2245 }
2246 }
2247
2248 /* Load the BSS area. */
2249 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2250 if (fw->bss) {
2251 int j;
2252
2253 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2254 REG_WR_IND(bp, offset, fw->bss[j]);
2255 }
2256 }
2257
2258 /* Load the Read-Only area. */
2259 offset = cpu_reg->spad_base +
2260 (fw->rodata_addr - cpu_reg->mips_view_base);
2261 if (fw->rodata) {
2262 int j;
2263
2264 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2265 REG_WR_IND(bp, offset, fw->rodata[j]);
2266 }
2267 }
2268
2269 /* Clear the pre-fetch instruction. */
2270 REG_WR_IND(bp, cpu_reg->inst, 0);
2271 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2272
2273 /* Start the CPU. */
2274 val = REG_RD_IND(bp, cpu_reg->mode);
2275 val &= ~cpu_reg->mode_value_halt;
2276 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2277 REG_WR_IND(bp, cpu_reg->mode, val);
2278 }
2279
2280 static int
2281 bnx2_init_cpus(struct bnx2 *bp)
2282 {
2283 struct cpu_reg cpu_reg;
2284 struct fw_info fw;
2285 int rc = 0;
2286 void *text;
2287 u32 text_len;
2288
2289 if ((rc = bnx2_gunzip_init(bp)) != 0)
2290 return rc;
2291
2292 /* Initialize the RV2P processor. */
2293 rc = bnx2_gunzip(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), &text,
2294 &text_len);
2295 if (rc)
2296 goto init_cpu_err;
2297
2298 load_rv2p_fw(bp, text, text_len, RV2P_PROC1);
2299
2300 rc = bnx2_gunzip(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), &text,
2301 &text_len);
2302 if (rc)
2303 goto init_cpu_err;
2304
2305 load_rv2p_fw(bp, text, text_len, RV2P_PROC2);
2306
2307 /* Initialize the RX Processor. */
2308 cpu_reg.mode = BNX2_RXP_CPU_MODE;
2309 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2310 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2311 cpu_reg.state = BNX2_RXP_CPU_STATE;
2312 cpu_reg.state_value_clear = 0xffffff;
2313 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2314 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2315 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2316 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2317 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2318 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2319 cpu_reg.mips_view_base = 0x8000000;
2320
2321 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
2322 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
2323 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
2324 fw.start_addr = bnx2_RXP_b06FwStartAddr;
2325
2326 fw.text_addr = bnx2_RXP_b06FwTextAddr;
2327 fw.text_len = bnx2_RXP_b06FwTextLen;
2328 fw.text_index = 0;
2329
2330 rc = bnx2_gunzip(bp, bnx2_RXP_b06FwText, sizeof(bnx2_RXP_b06FwText),
2331 &text, &text_len);
2332 if (rc)
2333 goto init_cpu_err;
2334
2335 fw.text = text;
2336
2337 fw.data_addr = bnx2_RXP_b06FwDataAddr;
2338 fw.data_len = bnx2_RXP_b06FwDataLen;
2339 fw.data_index = 0;
2340 fw.data = bnx2_RXP_b06FwData;
2341
2342 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2343 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2344 fw.sbss_index = 0;
2345 fw.sbss = bnx2_RXP_b06FwSbss;
2346
2347 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2348 fw.bss_len = bnx2_RXP_b06FwBssLen;
2349 fw.bss_index = 0;
2350 fw.bss = bnx2_RXP_b06FwBss;
2351
2352 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2353 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2354 fw.rodata_index = 0;
2355 fw.rodata = bnx2_RXP_b06FwRodata;
2356
2357 load_cpu_fw(bp, &cpu_reg, &fw);
2358
2359 /* Initialize the TX Processor. */
2360 cpu_reg.mode = BNX2_TXP_CPU_MODE;
2361 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2362 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2363 cpu_reg.state = BNX2_TXP_CPU_STATE;
2364 cpu_reg.state_value_clear = 0xffffff;
2365 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2366 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2367 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2368 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2369 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2370 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2371 cpu_reg.mips_view_base = 0x8000000;
2372
2373 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2374 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2375 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2376 fw.start_addr = bnx2_TXP_b06FwStartAddr;
2377
2378 fw.text_addr = bnx2_TXP_b06FwTextAddr;
2379 fw.text_len = bnx2_TXP_b06FwTextLen;
2380 fw.text_index = 0;
2381
2382 rc = bnx2_gunzip(bp, bnx2_TXP_b06FwText, sizeof(bnx2_TXP_b06FwText),
2383 &text, &text_len);
2384 if (rc)
2385 goto init_cpu_err;
2386
2387 fw.text = text;
2388
2389 fw.data_addr = bnx2_TXP_b06FwDataAddr;
2390 fw.data_len = bnx2_TXP_b06FwDataLen;
2391 fw.data_index = 0;
2392 fw.data = bnx2_TXP_b06FwData;
2393
2394 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2395 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2396 fw.sbss_index = 0;
2397 fw.sbss = bnx2_TXP_b06FwSbss;
2398
2399 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2400 fw.bss_len = bnx2_TXP_b06FwBssLen;
2401 fw.bss_index = 0;
2402 fw.bss = bnx2_TXP_b06FwBss;
2403
2404 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2405 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2406 fw.rodata_index = 0;
2407 fw.rodata = bnx2_TXP_b06FwRodata;
2408
2409 load_cpu_fw(bp, &cpu_reg, &fw);
2410
2411 /* Initialize the TX Patch-up Processor. */
2412 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2413 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2414 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2415 cpu_reg.state = BNX2_TPAT_CPU_STATE;
2416 cpu_reg.state_value_clear = 0xffffff;
2417 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2418 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2419 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2420 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2421 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2422 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2423 cpu_reg.mips_view_base = 0x8000000;
2424
2425 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2426 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2427 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2428 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2429
2430 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2431 fw.text_len = bnx2_TPAT_b06FwTextLen;
2432 fw.text_index = 0;
2433
2434 rc = bnx2_gunzip(bp, bnx2_TPAT_b06FwText, sizeof(bnx2_TPAT_b06FwText),
2435 &text, &text_len);
2436 if (rc)
2437 goto init_cpu_err;
2438
2439 fw.text = text;
2440
2441 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2442 fw.data_len = bnx2_TPAT_b06FwDataLen;
2443 fw.data_index = 0;
2444 fw.data = bnx2_TPAT_b06FwData;
2445
2446 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2447 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2448 fw.sbss_index = 0;
2449 fw.sbss = bnx2_TPAT_b06FwSbss;
2450
2451 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2452 fw.bss_len = bnx2_TPAT_b06FwBssLen;
2453 fw.bss_index = 0;
2454 fw.bss = bnx2_TPAT_b06FwBss;
2455
2456 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2457 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2458 fw.rodata_index = 0;
2459 fw.rodata = bnx2_TPAT_b06FwRodata;
2460
2461 load_cpu_fw(bp, &cpu_reg, &fw);
2462
2463 /* Initialize the Completion Processor. */
2464 cpu_reg.mode = BNX2_COM_CPU_MODE;
2465 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2466 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2467 cpu_reg.state = BNX2_COM_CPU_STATE;
2468 cpu_reg.state_value_clear = 0xffffff;
2469 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2470 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2471 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2472 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2473 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2474 cpu_reg.spad_base = BNX2_COM_SCRATCH;
2475 cpu_reg.mips_view_base = 0x8000000;
2476
2477 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2478 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2479 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2480 fw.start_addr = bnx2_COM_b06FwStartAddr;
2481
2482 fw.text_addr = bnx2_COM_b06FwTextAddr;
2483 fw.text_len = bnx2_COM_b06FwTextLen;
2484 fw.text_index = 0;
2485
2486 rc = bnx2_gunzip(bp, bnx2_COM_b06FwText, sizeof(bnx2_COM_b06FwText),
2487 &text, &text_len);
2488 if (rc)
2489 goto init_cpu_err;
2490
2491 fw.text = text;
2492
2493 fw.data_addr = bnx2_COM_b06FwDataAddr;
2494 fw.data_len = bnx2_COM_b06FwDataLen;
2495 fw.data_index = 0;
2496 fw.data = bnx2_COM_b06FwData;
2497
2498 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2499 fw.sbss_len = bnx2_COM_b06FwSbssLen;
2500 fw.sbss_index = 0;
2501 fw.sbss = bnx2_COM_b06FwSbss;
2502
2503 fw.bss_addr = bnx2_COM_b06FwBssAddr;
2504 fw.bss_len = bnx2_COM_b06FwBssLen;
2505 fw.bss_index = 0;
2506 fw.bss = bnx2_COM_b06FwBss;
2507
2508 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2509 fw.rodata_len = bnx2_COM_b06FwRodataLen;
2510 fw.rodata_index = 0;
2511 fw.rodata = bnx2_COM_b06FwRodata;
2512
2513 load_cpu_fw(bp, &cpu_reg, &fw);
2514
2515 init_cpu_err:
2516 bnx2_gunzip_end(bp);
2517 return rc;
2518 }
2519
2520 static int
2521 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2522 {
2523 u16 pmcsr;
2524
2525 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2526
2527 switch (state) {
2528 case PCI_D0: {
2529 u32 val;
2530
2531 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2532 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2533 PCI_PM_CTRL_PME_STATUS);
2534
2535 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2536 /* delay required during transition out of D3hot */
2537 msleep(20);
2538
2539 val = REG_RD(bp, BNX2_EMAC_MODE);
2540 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2541 val &= ~BNX2_EMAC_MODE_MPKT;
2542 REG_WR(bp, BNX2_EMAC_MODE, val);
2543
2544 val = REG_RD(bp, BNX2_RPM_CONFIG);
2545 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2546 REG_WR(bp, BNX2_RPM_CONFIG, val);
2547 break;
2548 }
2549 case PCI_D3hot: {
2550 int i;
2551 u32 val, wol_msg;
2552
2553 if (bp->wol) {
2554 u32 advertising;
2555 u8 autoneg;
2556
2557 autoneg = bp->autoneg;
2558 advertising = bp->advertising;
2559
2560 bp->autoneg = AUTONEG_SPEED;
2561 bp->advertising = ADVERTISED_10baseT_Half |
2562 ADVERTISED_10baseT_Full |
2563 ADVERTISED_100baseT_Half |
2564 ADVERTISED_100baseT_Full |
2565 ADVERTISED_Autoneg;
2566
2567 bnx2_setup_copper_phy(bp);
2568
2569 bp->autoneg = autoneg;
2570 bp->advertising = advertising;
2571
2572 bnx2_set_mac_addr(bp);
2573
2574 val = REG_RD(bp, BNX2_EMAC_MODE);
2575
2576 /* Enable port mode. */
2577 val &= ~BNX2_EMAC_MODE_PORT;
2578 val |= BNX2_EMAC_MODE_PORT_MII |
2579 BNX2_EMAC_MODE_MPKT_RCVD |
2580 BNX2_EMAC_MODE_ACPI_RCVD |
2581 BNX2_EMAC_MODE_MPKT;
2582
2583 REG_WR(bp, BNX2_EMAC_MODE, val);
2584
2585 /* receive all multicast */
2586 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2587 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2588 0xffffffff);
2589 }
2590 REG_WR(bp, BNX2_EMAC_RX_MODE,
2591 BNX2_EMAC_RX_MODE_SORT_MODE);
2592
2593 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2594 BNX2_RPM_SORT_USER0_MC_EN;
2595 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2596 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2597 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2598 BNX2_RPM_SORT_USER0_ENA);
2599
2600 /* Need to enable EMAC and RPM for WOL. */
2601 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2602 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2603 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2604 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2605
2606 val = REG_RD(bp, BNX2_RPM_CONFIG);
2607 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2608 REG_WR(bp, BNX2_RPM_CONFIG, val);
2609
2610 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2611 }
2612 else {
2613 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2614 }
2615
2616 if (!(bp->flags & NO_WOL_FLAG))
2617 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
2618
2619 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2620 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2621 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2622
2623 if (bp->wol)
2624 pmcsr |= 3;
2625 }
2626 else {
2627 pmcsr |= 3;
2628 }
2629 if (bp->wol) {
2630 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2631 }
2632 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2633 pmcsr);
2634
2635 /* No more memory access after this point until
2636 * device is brought back to D0.
2637 */
2638 udelay(50);
2639 break;
2640 }
2641 default:
2642 return -EINVAL;
2643 }
2644 return 0;
2645 }
2646
2647 static int
2648 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2649 {
2650 u32 val;
2651 int j;
2652
2653 /* Request access to the flash interface. */
2654 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2655 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2656 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2657 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2658 break;
2659
2660 udelay(5);
2661 }
2662
2663 if (j >= NVRAM_TIMEOUT_COUNT)
2664 return -EBUSY;
2665
2666 return 0;
2667 }
2668
2669 static int
2670 bnx2_release_nvram_lock(struct bnx2 *bp)
2671 {
2672 int j;
2673 u32 val;
2674
2675 /* Relinquish nvram interface. */
2676 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2677
2678 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2679 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2680 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2681 break;
2682
2683 udelay(5);
2684 }
2685
2686 if (j >= NVRAM_TIMEOUT_COUNT)
2687 return -EBUSY;
2688
2689 return 0;
2690 }
2691
2692
2693 static int
2694 bnx2_enable_nvram_write(struct bnx2 *bp)
2695 {
2696 u32 val;
2697
2698 val = REG_RD(bp, BNX2_MISC_CFG);
2699 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2700
2701 if (!bp->flash_info->buffered) {
2702 int j;
2703
2704 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2705 REG_WR(bp, BNX2_NVM_COMMAND,
2706 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2707
2708 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2709 udelay(5);
2710
2711 val = REG_RD(bp, BNX2_NVM_COMMAND);
2712 if (val & BNX2_NVM_COMMAND_DONE)
2713 break;
2714 }
2715
2716 if (j >= NVRAM_TIMEOUT_COUNT)
2717 return -EBUSY;
2718 }
2719 return 0;
2720 }
2721
2722 static void
2723 bnx2_disable_nvram_write(struct bnx2 *bp)
2724 {
2725 u32 val;
2726
2727 val = REG_RD(bp, BNX2_MISC_CFG);
2728 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2729 }
2730
2731
2732 static void
2733 bnx2_enable_nvram_access(struct bnx2 *bp)
2734 {
2735 u32 val;
2736
2737 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2738 /* Enable both bits, even on read. */
2739 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2740 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2741 }
2742
2743 static void
2744 bnx2_disable_nvram_access(struct bnx2 *bp)
2745 {
2746 u32 val;
2747
2748 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2749 /* Disable both bits, even after read. */
2750 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2751 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2752 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2753 }
2754
2755 static int
2756 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2757 {
2758 u32 cmd;
2759 int j;
2760
2761 if (bp->flash_info->buffered)
2762 /* Buffered flash, no erase needed */
2763 return 0;
2764
2765 /* Build an erase command */
2766 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2767 BNX2_NVM_COMMAND_DOIT;
2768
2769 /* Need to clear DONE bit separately. */
2770 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2771
2772 /* Address of the NVRAM to read from. */
2773 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2774
2775 /* Issue an erase command. */
2776 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2777
2778 /* Wait for completion. */
2779 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2780 u32 val;
2781
2782 udelay(5);
2783
2784 val = REG_RD(bp, BNX2_NVM_COMMAND);
2785 if (val & BNX2_NVM_COMMAND_DONE)
2786 break;
2787 }
2788
2789 if (j >= NVRAM_TIMEOUT_COUNT)
2790 return -EBUSY;
2791
2792 return 0;
2793 }
2794
2795 static int
2796 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2797 {
2798 u32 cmd;
2799 int j;
2800
2801 /* Build the command word. */
2802 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2803
2804 /* Calculate an offset of a buffered flash. */
2805 if (bp->flash_info->buffered) {
2806 offset = ((offset / bp->flash_info->page_size) <<
2807 bp->flash_info->page_bits) +
2808 (offset % bp->flash_info->page_size);
2809 }
2810
2811 /* Need to clear DONE bit separately. */
2812 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2813
2814 /* Address of the NVRAM to read from. */
2815 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2816
2817 /* Issue a read command. */
2818 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2819
2820 /* Wait for completion. */
2821 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2822 u32 val;
2823
2824 udelay(5);
2825
2826 val = REG_RD(bp, BNX2_NVM_COMMAND);
2827 if (val & BNX2_NVM_COMMAND_DONE) {
2828 val = REG_RD(bp, BNX2_NVM_READ);
2829
2830 val = be32_to_cpu(val);
2831 memcpy(ret_val, &val, 4);
2832 break;
2833 }
2834 }
2835 if (j >= NVRAM_TIMEOUT_COUNT)
2836 return -EBUSY;
2837
2838 return 0;
2839 }
2840
2841
2842 static int
2843 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2844 {
2845 u32 cmd, val32;
2846 int j;
2847
2848 /* Build the command word. */
2849 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2850
2851 /* Calculate an offset of a buffered flash. */
2852 if (bp->flash_info->buffered) {
2853 offset = ((offset / bp->flash_info->page_size) <<
2854 bp->flash_info->page_bits) +
2855 (offset % bp->flash_info->page_size);
2856 }
2857
2858 /* Need to clear DONE bit separately. */
2859 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2860
2861 memcpy(&val32, val, 4);
2862 val32 = cpu_to_be32(val32);
2863
2864 /* Write the data. */
2865 REG_WR(bp, BNX2_NVM_WRITE, val32);
2866
2867 /* Address of the NVRAM to write to. */
2868 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2869
2870 /* Issue the write command. */
2871 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2872
2873 /* Wait for completion. */
2874 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2875 udelay(5);
2876
2877 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2878 break;
2879 }
2880 if (j >= NVRAM_TIMEOUT_COUNT)
2881 return -EBUSY;
2882
2883 return 0;
2884 }
2885
2886 static int
2887 bnx2_init_nvram(struct bnx2 *bp)
2888 {
2889 u32 val;
2890 int j, entry_count, rc;
2891 struct flash_spec *flash;
2892
2893 /* Determine the selected interface. */
2894 val = REG_RD(bp, BNX2_NVM_CFG1);
2895
2896 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2897
2898 rc = 0;
2899 if (val & 0x40000000) {
2900
2901 /* Flash interface has been reconfigured */
2902 for (j = 0, flash = &flash_table[0]; j < entry_count;
2903 j++, flash++) {
2904 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2905 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2906 bp->flash_info = flash;
2907 break;
2908 }
2909 }
2910 }
2911 else {
2912 u32 mask;
2913 /* Not yet been reconfigured */
2914
2915 if (val & (1 << 23))
2916 mask = FLASH_BACKUP_STRAP_MASK;
2917 else
2918 mask = FLASH_STRAP_MASK;
2919
2920 for (j = 0, flash = &flash_table[0]; j < entry_count;
2921 j++, flash++) {
2922
2923 if ((val & mask) == (flash->strapping & mask)) {
2924 bp->flash_info = flash;
2925
2926 /* Request access to the flash interface. */
2927 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2928 return rc;
2929
2930 /* Enable access to flash interface */
2931 bnx2_enable_nvram_access(bp);
2932
2933 /* Reconfigure the flash interface */
2934 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2935 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2936 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2937 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2938
2939 /* Disable access to flash interface */
2940 bnx2_disable_nvram_access(bp);
2941 bnx2_release_nvram_lock(bp);
2942
2943 break;
2944 }
2945 }
2946 } /* if (val & 0x40000000) */
2947
2948 if (j == entry_count) {
2949 bp->flash_info = NULL;
2950 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
2951 return -ENODEV;
2952 }
2953
2954 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
2955 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
2956 if (val)
2957 bp->flash_size = val;
2958 else
2959 bp->flash_size = bp->flash_info->total_size;
2960
2961 return rc;
2962 }
2963
2964 static int
2965 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2966 int buf_size)
2967 {
2968 int rc = 0;
2969 u32 cmd_flags, offset32, len32, extra;
2970
2971 if (buf_size == 0)
2972 return 0;
2973
2974 /* Request access to the flash interface. */
2975 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2976 return rc;
2977
2978 /* Enable access to flash interface */
2979 bnx2_enable_nvram_access(bp);
2980
2981 len32 = buf_size;
2982 offset32 = offset;
2983 extra = 0;
2984
2985 cmd_flags = 0;
2986
2987 if (offset32 & 3) {
2988 u8 buf[4];
2989 u32 pre_len;
2990
2991 offset32 &= ~3;
2992 pre_len = 4 - (offset & 3);
2993
2994 if (pre_len >= len32) {
2995 pre_len = len32;
2996 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2997 BNX2_NVM_COMMAND_LAST;
2998 }
2999 else {
3000 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3001 }
3002
3003 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3004
3005 if (rc)
3006 return rc;
3007
3008 memcpy(ret_buf, buf + (offset & 3), pre_len);
3009
3010 offset32 += 4;
3011 ret_buf += pre_len;
3012 len32 -= pre_len;
3013 }
3014 if (len32 & 3) {
3015 extra = 4 - (len32 & 3);
3016 len32 = (len32 + 4) & ~3;
3017 }
3018
3019 if (len32 == 4) {
3020 u8 buf[4];
3021
3022 if (cmd_flags)
3023 cmd_flags = BNX2_NVM_COMMAND_LAST;
3024 else
3025 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3026 BNX2_NVM_COMMAND_LAST;
3027
3028 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3029
3030 memcpy(ret_buf, buf, 4 - extra);
3031 }
3032 else if (len32 > 0) {
3033 u8 buf[4];
3034
3035 /* Read the first word. */
3036 if (cmd_flags)
3037 cmd_flags = 0;
3038 else
3039 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3040
3041 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3042
3043 /* Advance to the next dword. */
3044 offset32 += 4;
3045 ret_buf += 4;
3046 len32 -= 4;
3047
3048 while (len32 > 4 && rc == 0) {
3049 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3050
3051 /* Advance to the next dword. */
3052 offset32 += 4;
3053 ret_buf += 4;
3054 len32 -= 4;
3055 }
3056
3057 if (rc)
3058 return rc;
3059
3060 cmd_flags = BNX2_NVM_COMMAND_LAST;
3061 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3062
3063 memcpy(ret_buf, buf, 4 - extra);
3064 }
3065
3066 /* Disable access to flash interface */
3067 bnx2_disable_nvram_access(bp);
3068
3069 bnx2_release_nvram_lock(bp);
3070
3071 return rc;
3072 }
3073
3074 static int
3075 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3076 int buf_size)
3077 {
3078 u32 written, offset32, len32;
3079 u8 *buf, start[4], end[4], *flash_buffer = NULL;
3080 int rc = 0;
3081 int align_start, align_end;
3082
3083 buf = data_buf;
3084 offset32 = offset;
3085 len32 = buf_size;
3086 align_start = align_end = 0;
3087
3088 if ((align_start = (offset32 & 3))) {
3089 offset32 &= ~3;
3090 len32 += align_start;
3091 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3092 return rc;
3093 }
3094
3095 if (len32 & 3) {
3096 if ((len32 > 4) || !align_start) {
3097 align_end = 4 - (len32 & 3);
3098 len32 += align_end;
3099 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
3100 end, 4))) {
3101 return rc;
3102 }
3103 }
3104 }
3105
3106 if (align_start || align_end) {
3107 buf = kmalloc(len32, GFP_KERNEL);
3108 if (buf == 0)
3109 return -ENOMEM;
3110 if (align_start) {
3111 memcpy(buf, start, 4);
3112 }
3113 if (align_end) {
3114 memcpy(buf + len32 - 4, end, 4);
3115 }
3116 memcpy(buf + align_start, data_buf, buf_size);
3117 }
3118
3119 if (bp->flash_info->buffered == 0) {
3120 flash_buffer = kmalloc(264, GFP_KERNEL);
3121 if (flash_buffer == NULL) {
3122 rc = -ENOMEM;
3123 goto nvram_write_end;
3124 }
3125 }
3126
3127 written = 0;
3128 while ((written < len32) && (rc == 0)) {
3129 u32 page_start, page_end, data_start, data_end;
3130 u32 addr, cmd_flags;
3131 int i;
3132
3133 /* Find the page_start addr */
3134 page_start = offset32 + written;
3135 page_start -= (page_start % bp->flash_info->page_size);
3136 /* Find the page_end addr */
3137 page_end = page_start + bp->flash_info->page_size;
3138 /* Find the data_start addr */
3139 data_start = (written == 0) ? offset32 : page_start;
3140 /* Find the data_end addr */
3141 data_end = (page_end > offset32 + len32) ?
3142 (offset32 + len32) : page_end;
3143
3144 /* Request access to the flash interface. */
3145 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3146 goto nvram_write_end;
3147
3148 /* Enable access to flash interface */
3149 bnx2_enable_nvram_access(bp);
3150
3151 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3152 if (bp->flash_info->buffered == 0) {
3153 int j;
3154
3155 /* Read the whole page into the buffer
3156 * (non-buffer flash only) */
3157 for (j = 0; j < bp->flash_info->page_size; j += 4) {
3158 if (j == (bp->flash_info->page_size - 4)) {
3159 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3160 }
3161 rc = bnx2_nvram_read_dword(bp,
3162 page_start + j,
3163 &flash_buffer[j],
3164 cmd_flags);
3165
3166 if (rc)
3167 goto nvram_write_end;
3168
3169 cmd_flags = 0;
3170 }
3171 }
3172
3173 /* Enable writes to flash interface (unlock write-protect) */
3174 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
3175 goto nvram_write_end;
3176
3177 /* Erase the page */
3178 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3179 goto nvram_write_end;
3180
3181 /* Re-enable the write again for the actual write */
3182 bnx2_enable_nvram_write(bp);
3183
3184 /* Loop to write back the buffer data from page_start to
3185 * data_start */
3186 i = 0;
3187 if (bp->flash_info->buffered == 0) {
3188 for (addr = page_start; addr < data_start;
3189 addr += 4, i += 4) {
3190
3191 rc = bnx2_nvram_write_dword(bp, addr,
3192 &flash_buffer[i], cmd_flags);
3193
3194 if (rc != 0)
3195 goto nvram_write_end;
3196
3197 cmd_flags = 0;
3198 }
3199 }
3200
3201 /* Loop to write the new data from data_start to data_end */
3202 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
3203 if ((addr == page_end - 4) ||
3204 ((bp->flash_info->buffered) &&
3205 (addr == data_end - 4))) {
3206
3207 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3208 }
3209 rc = bnx2_nvram_write_dword(bp, addr, buf,
3210 cmd_flags);
3211
3212 if (rc != 0)
3213 goto nvram_write_end;
3214
3215 cmd_flags = 0;
3216 buf += 4;
3217 }
3218
3219 /* Loop to write back the buffer data from data_end
3220 * to page_end */
3221 if (bp->flash_info->buffered == 0) {
3222 for (addr = data_end; addr < page_end;
3223 addr += 4, i += 4) {
3224
3225 if (addr == page_end-4) {
3226 cmd_flags = BNX2_NVM_COMMAND_LAST;
3227 }
3228 rc = bnx2_nvram_write_dword(bp, addr,
3229 &flash_buffer[i], cmd_flags);
3230
3231 if (rc != 0)
3232 goto nvram_write_end;
3233
3234 cmd_flags = 0;
3235 }
3236 }
3237
3238 /* Disable writes to flash interface (lock write-protect) */
3239 bnx2_disable_nvram_write(bp);
3240
3241 /* Disable access to flash interface */
3242 bnx2_disable_nvram_access(bp);
3243 bnx2_release_nvram_lock(bp);
3244
3245 /* Increment written */
3246 written += data_end - data_start;
3247 }
3248
3249 nvram_write_end:
3250 if (bp->flash_info->buffered == 0)
3251 kfree(flash_buffer);
3252
3253 if (align_start || align_end)
3254 kfree(buf);
3255 return rc;
3256 }
3257
3258 static int
3259 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3260 {
3261 u32 val;
3262 int i, rc = 0;
3263
3264 /* Wait for the current PCI transaction to complete before
3265 * issuing a reset. */
3266 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3267 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3268 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3269 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3270 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3271 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3272 udelay(5);
3273
3274 /* Wait for the firmware to tell us it is ok to issue a reset. */
3275 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3276
3277 /* Deposit a driver reset signature so the firmware knows that
3278 * this is a soft reset. */
3279 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3280 BNX2_DRV_RESET_SIGNATURE_MAGIC);
3281
3282 /* Do a dummy read to force the chip to complete all current transaction
3283 * before we issue a reset. */
3284 val = REG_RD(bp, BNX2_MISC_ID);
3285
3286 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3287 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3288 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3289
3290 /* Chip reset. */
3291 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3292
3293 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3294 (CHIP_ID(bp) == CHIP_ID_5706_A1))
3295 msleep(15);
3296
3297 /* Reset takes approximate 30 usec */
3298 for (i = 0; i < 10; i++) {
3299 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3300 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3301 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3302 break;
3303 }
3304 udelay(10);
3305 }
3306
3307 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3308 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3309 printk(KERN_ERR PFX "Chip reset did not complete\n");
3310 return -EBUSY;
3311 }
3312
3313 /* Make sure byte swapping is properly configured. */
3314 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3315 if (val != 0x01020304) {
3316 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3317 return -ENODEV;
3318 }
3319
3320 /* Wait for the firmware to finish its initialization. */
3321 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3322 if (rc)
3323 return rc;
3324
3325 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3326 /* Adjust the voltage regular to two steps lower. The default
3327 * of this register is 0x0000000e. */
3328 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3329
3330 /* Remove bad rbuf memory from the free pool. */
3331 rc = bnx2_alloc_bad_rbuf(bp);
3332 }
3333
3334 return rc;
3335 }
3336
3337 static int
3338 bnx2_init_chip(struct bnx2 *bp)
3339 {
3340 u32 val;
3341 int rc;
3342
3343 /* Make sure the interrupt is not active. */
3344 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3345
3346 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3347 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3348 #ifdef __BIG_ENDIAN
3349 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3350 #endif
3351 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3352 DMA_READ_CHANS << 12 |
3353 DMA_WRITE_CHANS << 16;
3354
3355 val |= (0x2 << 20) | (1 << 11);
3356
3357 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
3358 val |= (1 << 23);
3359
3360 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3361 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3362 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3363
3364 REG_WR(bp, BNX2_DMA_CONFIG, val);
3365
3366 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3367 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3368 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3369 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3370 }
3371
3372 if (bp->flags & PCIX_FLAG) {
3373 u16 val16;
3374
3375 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3376 &val16);
3377 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3378 val16 & ~PCI_X_CMD_ERO);
3379 }
3380
3381 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3382 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3383 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3384 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3385
3386 /* Initialize context mapping and zero out the quick contexts. The
3387 * context block must have already been enabled. */
3388 bnx2_init_context(bp);
3389
3390 if ((rc = bnx2_init_cpus(bp)) != 0)
3391 return rc;
3392
3393 bnx2_init_nvram(bp);
3394
3395 bnx2_set_mac_addr(bp);
3396
3397 val = REG_RD(bp, BNX2_MQ_CONFIG);
3398 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3399 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3400 REG_WR(bp, BNX2_MQ_CONFIG, val);
3401
3402 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3403 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3404 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3405
3406 val = (BCM_PAGE_BITS - 8) << 24;
3407 REG_WR(bp, BNX2_RV2P_CONFIG, val);
3408
3409 /* Configure page size. */
3410 val = REG_RD(bp, BNX2_TBDR_CONFIG);
3411 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3412 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3413 REG_WR(bp, BNX2_TBDR_CONFIG, val);
3414
3415 val = bp->mac_addr[0] +
3416 (bp->mac_addr[1] << 8) +
3417 (bp->mac_addr[2] << 16) +
3418 bp->mac_addr[3] +
3419 (bp->mac_addr[4] << 8) +
3420 (bp->mac_addr[5] << 16);
3421 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3422
3423 /* Program the MTU. Also include 4 bytes for CRC32. */
3424 val = bp->dev->mtu + ETH_HLEN + 4;
3425 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3426 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3427 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3428
3429 bp->last_status_idx = 0;
3430 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3431
3432 /* Set up how to generate a link change interrupt. */
3433 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3434
3435 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3436 (u64) bp->status_blk_mapping & 0xffffffff);
3437 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3438
3439 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3440 (u64) bp->stats_blk_mapping & 0xffffffff);
3441 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3442 (u64) bp->stats_blk_mapping >> 32);
3443
3444 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3445 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3446
3447 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3448 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3449
3450 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3451 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3452
3453 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3454
3455 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3456
3457 REG_WR(bp, BNX2_HC_COM_TICKS,
3458 (bp->com_ticks_int << 16) | bp->com_ticks);
3459
3460 REG_WR(bp, BNX2_HC_CMD_TICKS,
3461 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3462
3463 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3464 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3465
3466 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3467 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3468 else {
3469 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3470 BNX2_HC_CONFIG_TX_TMR_MODE |
3471 BNX2_HC_CONFIG_COLLECT_STATS);
3472 }
3473
3474 /* Clear internal stats counters. */
3475 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3476
3477 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3478
3479 if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
3480 BNX2_PORT_FEATURE_ASF_ENABLED)
3481 bp->flags |= ASF_ENABLE_FLAG;
3482
3483 /* Initialize the receive filter. */
3484 bnx2_set_rx_mode(bp->dev);
3485
3486 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3487 0);
3488
3489 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3490 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3491
3492 udelay(20);
3493
3494 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
3495
3496 return rc;
3497 }
3498
3499
3500 static void
3501 bnx2_init_tx_ring(struct bnx2 *bp)
3502 {
3503 struct tx_bd *txbd;
3504 u32 val;
3505
3506 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3507
3508 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3509 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3510
3511 bp->tx_prod = 0;
3512 bp->tx_cons = 0;
3513 bp->hw_tx_cons = 0;
3514 bp->tx_prod_bseq = 0;
3515
3516 val = BNX2_L2CTX_TYPE_TYPE_L2;
3517 val |= BNX2_L2CTX_TYPE_SIZE_L2;
3518 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3519
3520 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3521 val |= 8 << 16;
3522 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3523
3524 val = (u64) bp->tx_desc_mapping >> 32;
3525 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3526
3527 val = (u64) bp->tx_desc_mapping & 0xffffffff;
3528 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3529 }
3530
3531 static void
3532 bnx2_init_rx_ring(struct bnx2 *bp)
3533 {
3534 struct rx_bd *rxbd;
3535 int i;
3536 u16 prod, ring_prod;
3537 u32 val;
3538
3539 /* 8 for CRC and VLAN */
3540 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3541 /* 8 for alignment */
3542 bp->rx_buf_size = bp->rx_buf_use_size + 8;
3543
3544 ring_prod = prod = bp->rx_prod = 0;
3545 bp->rx_cons = 0;
3546 bp->hw_rx_cons = 0;
3547 bp->rx_prod_bseq = 0;
3548
3549 for (i = 0; i < bp->rx_max_ring; i++) {
3550 int j;
3551
3552 rxbd = &bp->rx_desc_ring[i][0];
3553 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
3554 rxbd->rx_bd_len = bp->rx_buf_use_size;
3555 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3556 }
3557 if (i == (bp->rx_max_ring - 1))
3558 j = 0;
3559 else
3560 j = i + 1;
3561 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
3562 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
3563 0xffffffff;
3564 }
3565
3566 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3567 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3568 val |= 0x02 << 8;
3569 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3570
3571 val = (u64) bp->rx_desc_mapping[0] >> 32;
3572 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3573
3574 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
3575 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3576
3577 for (i = 0; i < bp->rx_ring_size; i++) {
3578 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3579 break;
3580 }
3581 prod = NEXT_RX_BD(prod);
3582 ring_prod = RX_RING_IDX(prod);
3583 }
3584 bp->rx_prod = prod;
3585
3586 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3587
3588 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3589 }
3590
3591 static void
3592 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
3593 {
3594 u32 num_rings, max;
3595
3596 bp->rx_ring_size = size;
3597 num_rings = 1;
3598 while (size > MAX_RX_DESC_CNT) {
3599 size -= MAX_RX_DESC_CNT;
3600 num_rings++;
3601 }
3602 /* round to next power of 2 */
3603 max = MAX_RX_RINGS;
3604 while ((max & num_rings) == 0)
3605 max >>= 1;
3606
3607 if (num_rings != max)
3608 max <<= 1;
3609
3610 bp->rx_max_ring = max;
3611 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
3612 }
3613
3614 static void
3615 bnx2_free_tx_skbs(struct bnx2 *bp)
3616 {
3617 int i;
3618
3619 if (bp->tx_buf_ring == NULL)
3620 return;
3621
3622 for (i = 0; i < TX_DESC_CNT; ) {
3623 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3624 struct sk_buff *skb = tx_buf->skb;
3625 int j, last;
3626
3627 if (skb == NULL) {
3628 i++;
3629 continue;
3630 }
3631
3632 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3633 skb_headlen(skb), PCI_DMA_TODEVICE);
3634
3635 tx_buf->skb = NULL;
3636
3637 last = skb_shinfo(skb)->nr_frags;
3638 for (j = 0; j < last; j++) {
3639 tx_buf = &bp->tx_buf_ring[i + j + 1];
3640 pci_unmap_page(bp->pdev,
3641 pci_unmap_addr(tx_buf, mapping),
3642 skb_shinfo(skb)->frags[j].size,
3643 PCI_DMA_TODEVICE);
3644 }
3645 dev_kfree_skb(skb);
3646 i += j + 1;
3647 }
3648
3649 }
3650
3651 static void
3652 bnx2_free_rx_skbs(struct bnx2 *bp)
3653 {
3654 int i;
3655
3656 if (bp->rx_buf_ring == NULL)
3657 return;
3658
3659 for (i = 0; i < bp->rx_max_ring_idx; i++) {
3660 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3661 struct sk_buff *skb = rx_buf->skb;
3662
3663 if (skb == NULL)
3664 continue;
3665
3666 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3667 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3668
3669 rx_buf->skb = NULL;
3670
3671 dev_kfree_skb(skb);
3672 }
3673 }
3674
3675 static void
3676 bnx2_free_skbs(struct bnx2 *bp)
3677 {
3678 bnx2_free_tx_skbs(bp);
3679 bnx2_free_rx_skbs(bp);
3680 }
3681
3682 static int
3683 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3684 {
3685 int rc;
3686
3687 rc = bnx2_reset_chip(bp, reset_code);
3688 bnx2_free_skbs(bp);
3689 if (rc)
3690 return rc;
3691
3692 if ((rc = bnx2_init_chip(bp)) != 0)
3693 return rc;
3694
3695 bnx2_init_tx_ring(bp);
3696 bnx2_init_rx_ring(bp);
3697 return 0;
3698 }
3699
3700 static int
3701 bnx2_init_nic(struct bnx2 *bp)
3702 {
3703 int rc;
3704
3705 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3706 return rc;
3707
3708 bnx2_init_phy(bp);
3709 bnx2_set_link(bp);
3710 return 0;
3711 }
3712
3713 static int
3714 bnx2_test_registers(struct bnx2 *bp)
3715 {
3716 int ret;
3717 int i;
3718 static const struct {
3719 u16 offset;
3720 u16 flags;
3721 u32 rw_mask;
3722 u32 ro_mask;
3723 } reg_tbl[] = {
3724 { 0x006c, 0, 0x00000000, 0x0000003f },
3725 { 0x0090, 0, 0xffffffff, 0x00000000 },
3726 { 0x0094, 0, 0x00000000, 0x00000000 },
3727
3728 { 0x0404, 0, 0x00003f00, 0x00000000 },
3729 { 0x0418, 0, 0x00000000, 0xffffffff },
3730 { 0x041c, 0, 0x00000000, 0xffffffff },
3731 { 0x0420, 0, 0x00000000, 0x80ffffff },
3732 { 0x0424, 0, 0x00000000, 0x00000000 },
3733 { 0x0428, 0, 0x00000000, 0x00000001 },
3734 { 0x0450, 0, 0x00000000, 0x0000ffff },
3735 { 0x0454, 0, 0x00000000, 0xffffffff },
3736 { 0x0458, 0, 0x00000000, 0xffffffff },
3737
3738 { 0x0808, 0, 0x00000000, 0xffffffff },
3739 { 0x0854, 0, 0x00000000, 0xffffffff },
3740 { 0x0868, 0, 0x00000000, 0x77777777 },
3741 { 0x086c, 0, 0x00000000, 0x77777777 },
3742 { 0x0870, 0, 0x00000000, 0x77777777 },
3743 { 0x0874, 0, 0x00000000, 0x77777777 },
3744
3745 { 0x0c00, 0, 0x00000000, 0x00000001 },
3746 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3747 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3748
3749 { 0x1000, 0, 0x00000000, 0x00000001 },
3750 { 0x1004, 0, 0x00000000, 0x000f0001 },
3751
3752 { 0x1408, 0, 0x01c00800, 0x00000000 },
3753 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3754 { 0x14a8, 0, 0x00000000, 0x000001ff },
3755 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
3756 { 0x14b0, 0, 0x00000002, 0x00000001 },
3757 { 0x14b8, 0, 0x00000000, 0x00000000 },
3758 { 0x14c0, 0, 0x00000000, 0x00000009 },
3759 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3760 { 0x14cc, 0, 0x00000000, 0x00000001 },
3761 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3762
3763 { 0x1800, 0, 0x00000000, 0x00000001 },
3764 { 0x1804, 0, 0x00000000, 0x00000003 },
3765
3766 { 0x2800, 0, 0x00000000, 0x00000001 },
3767 { 0x2804, 0, 0x00000000, 0x00003f01 },
3768 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3769 { 0x2810, 0, 0xffff0000, 0x00000000 },
3770 { 0x2814, 0, 0xffff0000, 0x00000000 },
3771 { 0x2818, 0, 0xffff0000, 0x00000000 },
3772 { 0x281c, 0, 0xffff0000, 0x00000000 },
3773 { 0x2834, 0, 0xffffffff, 0x00000000 },
3774 { 0x2840, 0, 0x00000000, 0xffffffff },
3775 { 0x2844, 0, 0x00000000, 0xffffffff },
3776 { 0x2848, 0, 0xffffffff, 0x00000000 },
3777 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3778
3779 { 0x2c00, 0, 0x00000000, 0x00000011 },
3780 { 0x2c04, 0, 0x00000000, 0x00030007 },
3781
3782 { 0x3c00, 0, 0x00000000, 0x00000001 },
3783 { 0x3c04, 0, 0x00000000, 0x00070000 },
3784 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3785 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3786 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3787 { 0x3c14, 0, 0x00000000, 0xffffffff },
3788 { 0x3c18, 0, 0x00000000, 0xffffffff },
3789 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3790 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3791
3792 { 0x5004, 0, 0x00000000, 0x0000007f },
3793 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3794 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3795
3796 { 0x5c00, 0, 0x00000000, 0x00000001 },
3797 { 0x5c04, 0, 0x00000000, 0x0003000f },
3798 { 0x5c08, 0, 0x00000003, 0x00000000 },
3799 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3800 { 0x5c10, 0, 0x00000000, 0xffffffff },
3801 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3802 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3803 { 0x5c88, 0, 0x00000000, 0x00077373 },
3804 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3805
3806 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3807 { 0x680c, 0, 0xffffffff, 0x00000000 },
3808 { 0x6810, 0, 0xffffffff, 0x00000000 },
3809 { 0x6814, 0, 0xffffffff, 0x00000000 },
3810 { 0x6818, 0, 0xffffffff, 0x00000000 },
3811 { 0x681c, 0, 0xffffffff, 0x00000000 },
3812 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3813 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3814 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3815 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3816 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3817 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3818 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3819 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3820 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3821 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3822 { 0x684c, 0, 0xffffffff, 0x00000000 },
3823 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3824 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3825 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3826 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3827 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3828 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3829
3830 { 0xffff, 0, 0x00000000, 0x00000000 },
3831 };
3832
3833 ret = 0;
3834 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3835 u32 offset, rw_mask, ro_mask, save_val, val;
3836
3837 offset = (u32) reg_tbl[i].offset;
3838 rw_mask = reg_tbl[i].rw_mask;
3839 ro_mask = reg_tbl[i].ro_mask;
3840
3841 save_val = readl(bp->regview + offset);
3842
3843 writel(0, bp->regview + offset);
3844
3845 val = readl(bp->regview + offset);
3846 if ((val & rw_mask) != 0) {
3847 goto reg_test_err;
3848 }
3849
3850 if ((val & ro_mask) != (save_val & ro_mask)) {
3851 goto reg_test_err;
3852 }
3853
3854 writel(0xffffffff, bp->regview + offset);
3855
3856 val = readl(bp->regview + offset);
3857 if ((val & rw_mask) != rw_mask) {
3858 goto reg_test_err;
3859 }
3860
3861 if ((val & ro_mask) != (save_val & ro_mask)) {
3862 goto reg_test_err;
3863 }
3864
3865 writel(save_val, bp->regview + offset);
3866 continue;
3867
3868 reg_test_err:
3869 writel(save_val, bp->regview + offset);
3870 ret = -ENODEV;
3871 break;
3872 }
3873 return ret;
3874 }
3875
3876 static int
3877 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3878 {
3879 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3880 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3881 int i;
3882
3883 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3884 u32 offset;
3885
3886 for (offset = 0; offset < size; offset += 4) {
3887
3888 REG_WR_IND(bp, start + offset, test_pattern[i]);
3889
3890 if (REG_RD_IND(bp, start + offset) !=
3891 test_pattern[i]) {
3892 return -ENODEV;
3893 }
3894 }
3895 }
3896 return 0;
3897 }
3898
3899 static int
3900 bnx2_test_memory(struct bnx2 *bp)
3901 {
3902 int ret = 0;
3903 int i;
3904 static const struct {
3905 u32 offset;
3906 u32 len;
3907 } mem_tbl[] = {
3908 { 0x60000, 0x4000 },
3909 { 0xa0000, 0x3000 },
3910 { 0xe0000, 0x4000 },
3911 { 0x120000, 0x4000 },
3912 { 0x1a0000, 0x4000 },
3913 { 0x160000, 0x4000 },
3914 { 0xffffffff, 0 },
3915 };
3916
3917 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3918 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3919 mem_tbl[i].len)) != 0) {
3920 return ret;
3921 }
3922 }
3923
3924 return ret;
3925 }
3926
3927 #define BNX2_MAC_LOOPBACK 0
3928 #define BNX2_PHY_LOOPBACK 1
3929
3930 static int
3931 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
3932 {
3933 unsigned int pkt_size, num_pkts, i;
3934 struct sk_buff *skb, *rx_skb;
3935 unsigned char *packet;
3936 u16 rx_start_idx, rx_idx;
3937 dma_addr_t map;
3938 struct tx_bd *txbd;
3939 struct sw_bd *rx_buf;
3940 struct l2_fhdr *rx_hdr;
3941 int ret = -ENODEV;
3942
3943 if (loopback_mode == BNX2_MAC_LOOPBACK) {
3944 bp->loopback = MAC_LOOPBACK;
3945 bnx2_set_mac_loopback(bp);
3946 }
3947 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
3948 bp->loopback = 0;
3949 bnx2_set_phy_loopback(bp);
3950 }
3951 else
3952 return -EINVAL;
3953
3954 pkt_size = 1514;
3955 skb = dev_alloc_skb(pkt_size);
3956 if (!skb)
3957 return -ENOMEM;
3958 packet = skb_put(skb, pkt_size);
3959 memcpy(packet, bp->mac_addr, 6);
3960 memset(packet + 6, 0x0, 8);
3961 for (i = 14; i < pkt_size; i++)
3962 packet[i] = (unsigned char) (i & 0xff);
3963
3964 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3965 PCI_DMA_TODEVICE);
3966
3967 REG_WR(bp, BNX2_HC_COMMAND,
3968 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3969
3970 REG_RD(bp, BNX2_HC_COMMAND);
3971
3972 udelay(5);
3973 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3974
3975 num_pkts = 0;
3976
3977 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
3978
3979 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3980 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3981 txbd->tx_bd_mss_nbytes = pkt_size;
3982 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3983
3984 num_pkts++;
3985 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
3986 bp->tx_prod_bseq += pkt_size;
3987
3988 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod);
3989 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
3990
3991 udelay(100);
3992
3993 REG_WR(bp, BNX2_HC_COMMAND,
3994 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3995
3996 REG_RD(bp, BNX2_HC_COMMAND);
3997
3998 udelay(5);
3999
4000 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
4001 dev_kfree_skb(skb);
4002
4003 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
4004 goto loopback_test_done;
4005 }
4006
4007 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
4008 if (rx_idx != rx_start_idx + num_pkts) {
4009 goto loopback_test_done;
4010 }
4011
4012 rx_buf = &bp->rx_buf_ring[rx_start_idx];
4013 rx_skb = rx_buf->skb;
4014
4015 rx_hdr = (struct l2_fhdr *) rx_skb->data;
4016 skb_reserve(rx_skb, bp->rx_offset);
4017
4018 pci_dma_sync_single_for_cpu(bp->pdev,
4019 pci_unmap_addr(rx_buf, mapping),
4020 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
4021
4022 if (rx_hdr->l2_fhdr_status &
4023 (L2_FHDR_ERRORS_BAD_CRC |
4024 L2_FHDR_ERRORS_PHY_DECODE |
4025 L2_FHDR_ERRORS_ALIGNMENT |
4026 L2_FHDR_ERRORS_TOO_SHORT |
4027 L2_FHDR_ERRORS_GIANT_FRAME)) {
4028
4029 goto loopback_test_done;
4030 }
4031
4032 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
4033 goto loopback_test_done;
4034 }
4035
4036 for (i = 14; i < pkt_size; i++) {
4037 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
4038 goto loopback_test_done;
4039 }
4040 }
4041
4042 ret = 0;
4043
4044 loopback_test_done:
4045 bp->loopback = 0;
4046 return ret;
4047 }
4048
4049 #define BNX2_MAC_LOOPBACK_FAILED 1
4050 #define BNX2_PHY_LOOPBACK_FAILED 2
4051 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
4052 BNX2_PHY_LOOPBACK_FAILED)
4053
4054 static int
4055 bnx2_test_loopback(struct bnx2 *bp)
4056 {
4057 int rc = 0;
4058
4059 if (!netif_running(bp->dev))
4060 return BNX2_LOOPBACK_FAILED;
4061
4062 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
4063 spin_lock_bh(&bp->phy_lock);
4064 bnx2_init_phy(bp);
4065 spin_unlock_bh(&bp->phy_lock);
4066 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
4067 rc |= BNX2_MAC_LOOPBACK_FAILED;
4068 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
4069 rc |= BNX2_PHY_LOOPBACK_FAILED;
4070 return rc;
4071 }
4072
4073 #define NVRAM_SIZE 0x200
4074 #define CRC32_RESIDUAL 0xdebb20e3
4075
4076 static int
4077 bnx2_test_nvram(struct bnx2 *bp)
4078 {
4079 u32 buf[NVRAM_SIZE / 4];
4080 u8 *data = (u8 *) buf;
4081 int rc = 0;
4082 u32 magic, csum;
4083
4084 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4085 goto test_nvram_done;
4086
4087 magic = be32_to_cpu(buf[0]);
4088 if (magic != 0x669955aa) {
4089 rc = -ENODEV;
4090 goto test_nvram_done;
4091 }
4092
4093 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4094 goto test_nvram_done;
4095
4096 csum = ether_crc_le(0x100, data);
4097 if (csum != CRC32_RESIDUAL) {
4098 rc = -ENODEV;
4099 goto test_nvram_done;
4100 }
4101
4102 csum = ether_crc_le(0x100, data + 0x100);
4103 if (csum != CRC32_RESIDUAL) {
4104 rc = -ENODEV;
4105 }
4106
4107 test_nvram_done:
4108 return rc;
4109 }
4110
4111 static int
4112 bnx2_test_link(struct bnx2 *bp)
4113 {
4114 u32 bmsr;
4115
4116 spin_lock_bh(&bp->phy_lock);
4117 bnx2_read_phy(bp, MII_BMSR, &bmsr);
4118 bnx2_read_phy(bp, MII_BMSR, &bmsr);
4119 spin_unlock_bh(&bp->phy_lock);
4120
4121 if (bmsr & BMSR_LSTATUS) {
4122 return 0;
4123 }
4124 return -ENODEV;
4125 }
4126
4127 static int
4128 bnx2_test_intr(struct bnx2 *bp)
4129 {
4130 int i;
4131 u16 status_idx;
4132
4133 if (!netif_running(bp->dev))
4134 return -ENODEV;
4135
4136 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4137
4138 /* This register is not touched during run-time. */
4139 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
4140 REG_RD(bp, BNX2_HC_COMMAND);
4141
4142 for (i = 0; i < 10; i++) {
4143 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4144 status_idx) {
4145
4146 break;
4147 }
4148
4149 msleep_interruptible(10);
4150 }
4151 if (i < 10)
4152 return 0;
4153
4154 return -ENODEV;
4155 }
4156
4157 static void
4158 bnx2_timer(unsigned long data)
4159 {
4160 struct bnx2 *bp = (struct bnx2 *) data;
4161 u32 msg;
4162
4163 if (!netif_running(bp->dev))
4164 return;
4165
4166 if (atomic_read(&bp->intr_sem) != 0)
4167 goto bnx2_restart_timer;
4168
4169 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
4170 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
4171
4172 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
4173
4174 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
4175 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
4176
4177 spin_lock(&bp->phy_lock);
4178 if (bp->serdes_an_pending) {
4179 bp->serdes_an_pending--;
4180 }
4181 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4182 u32 bmcr;
4183
4184 bp->current_interval = bp->timer_interval;
4185
4186 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4187
4188 if (bmcr & BMCR_ANENABLE) {
4189 u32 phy1, phy2;
4190
4191 bnx2_write_phy(bp, 0x1c, 0x7c00);
4192 bnx2_read_phy(bp, 0x1c, &phy1);
4193
4194 bnx2_write_phy(bp, 0x17, 0x0f01);
4195 bnx2_read_phy(bp, 0x15, &phy2);
4196 bnx2_write_phy(bp, 0x17, 0x0f01);
4197 bnx2_read_phy(bp, 0x15, &phy2);
4198
4199 if ((phy1 & 0x10) && /* SIGNAL DETECT */
4200 !(phy2 & 0x20)) { /* no CONFIG */
4201
4202 bmcr &= ~BMCR_ANENABLE;
4203 bmcr |= BMCR_SPEED1000 |
4204 BMCR_FULLDPLX;
4205 bnx2_write_phy(bp, MII_BMCR, bmcr);
4206 bp->phy_flags |=
4207 PHY_PARALLEL_DETECT_FLAG;
4208 }
4209 }
4210 }
4211 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4212 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4213 u32 phy2;
4214
4215 bnx2_write_phy(bp, 0x17, 0x0f01);
4216 bnx2_read_phy(bp, 0x15, &phy2);
4217 if (phy2 & 0x20) {
4218 u32 bmcr;
4219
4220 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4221 bmcr |= BMCR_ANENABLE;
4222 bnx2_write_phy(bp, MII_BMCR, bmcr);
4223
4224 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4225
4226 }
4227 }
4228 else
4229 bp->current_interval = bp->timer_interval;
4230
4231 spin_unlock(&bp->phy_lock);
4232 }
4233
4234 bnx2_restart_timer:
4235 mod_timer(&bp->timer, jiffies + bp->current_interval);
4236 }
4237
4238 /* Called with rtnl_lock */
4239 static int
4240 bnx2_open(struct net_device *dev)
4241 {
4242 struct bnx2 *bp = netdev_priv(dev);
4243 int rc;
4244
4245 bnx2_set_power_state(bp, PCI_D0);
4246 bnx2_disable_int(bp);
4247
4248 rc = bnx2_alloc_mem(bp);
4249 if (rc)
4250 return rc;
4251
4252 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4253 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4254 !disable_msi) {
4255
4256 if (pci_enable_msi(bp->pdev) == 0) {
4257 bp->flags |= USING_MSI_FLAG;
4258 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4259 dev);
4260 }
4261 else {
4262 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4263 IRQF_SHARED, dev->name, dev);
4264 }
4265 }
4266 else {
4267 rc = request_irq(bp->pdev->irq, bnx2_interrupt, IRQF_SHARED,
4268 dev->name, dev);
4269 }
4270 if (rc) {
4271 bnx2_free_mem(bp);
4272 return rc;
4273 }
4274
4275 rc = bnx2_init_nic(bp);
4276
4277 if (rc) {
4278 free_irq(bp->pdev->irq, dev);
4279 if (bp->flags & USING_MSI_FLAG) {
4280 pci_disable_msi(bp->pdev);
4281 bp->flags &= ~USING_MSI_FLAG;
4282 }
4283 bnx2_free_skbs(bp);
4284 bnx2_free_mem(bp);
4285 return rc;
4286 }
4287
4288 mod_timer(&bp->timer, jiffies + bp->current_interval);
4289
4290 atomic_set(&bp->intr_sem, 0);
4291
4292 bnx2_enable_int(bp);
4293
4294 if (bp->flags & USING_MSI_FLAG) {
4295 /* Test MSI to make sure it is working
4296 * If MSI test fails, go back to INTx mode
4297 */
4298 if (bnx2_test_intr(bp) != 0) {
4299 printk(KERN_WARNING PFX "%s: No interrupt was generated"
4300 " using MSI, switching to INTx mode. Please"
4301 " report this failure to the PCI maintainer"
4302 " and include system chipset information.\n",
4303 bp->dev->name);
4304
4305 bnx2_disable_int(bp);
4306 free_irq(bp->pdev->irq, dev);
4307 pci_disable_msi(bp->pdev);
4308 bp->flags &= ~USING_MSI_FLAG;
4309
4310 rc = bnx2_init_nic(bp);
4311
4312 if (!rc) {
4313 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4314 IRQF_SHARED, dev->name, dev);
4315 }
4316 if (rc) {
4317 bnx2_free_skbs(bp);
4318 bnx2_free_mem(bp);
4319 del_timer_sync(&bp->timer);
4320 return rc;
4321 }
4322 bnx2_enable_int(bp);
4323 }
4324 }
4325 if (bp->flags & USING_MSI_FLAG) {
4326 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4327 }
4328
4329 netif_start_queue(dev);
4330
4331 return 0;
4332 }
4333
4334 static void
4335 bnx2_reset_task(void *data)
4336 {
4337 struct bnx2 *bp = data;
4338
4339 if (!netif_running(bp->dev))
4340 return;
4341
4342 bp->in_reset_task = 1;
4343 bnx2_netif_stop(bp);
4344
4345 bnx2_init_nic(bp);
4346
4347 atomic_set(&bp->intr_sem, 1);
4348 bnx2_netif_start(bp);
4349 bp->in_reset_task = 0;
4350 }
4351
4352 static void
4353 bnx2_tx_timeout(struct net_device *dev)
4354 {
4355 struct bnx2 *bp = netdev_priv(dev);
4356
4357 /* This allows the netif to be shutdown gracefully before resetting */
4358 schedule_work(&bp->reset_task);
4359 }
4360
4361 #ifdef BCM_VLAN
4362 /* Called with rtnl_lock */
4363 static void
4364 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4365 {
4366 struct bnx2 *bp = netdev_priv(dev);
4367
4368 bnx2_netif_stop(bp);
4369
4370 bp->vlgrp = vlgrp;
4371 bnx2_set_rx_mode(dev);
4372
4373 bnx2_netif_start(bp);
4374 }
4375
4376 /* Called with rtnl_lock */
4377 static void
4378 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4379 {
4380 struct bnx2 *bp = netdev_priv(dev);
4381
4382 bnx2_netif_stop(bp);
4383
4384 if (bp->vlgrp)
4385 bp->vlgrp->vlan_devices[vid] = NULL;
4386 bnx2_set_rx_mode(dev);
4387
4388 bnx2_netif_start(bp);
4389 }
4390 #endif
4391
4392 /* Called with netif_tx_lock.
4393 * hard_start_xmit is pseudo-lockless - a lock is only required when
4394 * the tx queue is full. This way, we get the benefit of lockless
4395 * operations most of the time without the complexities to handle
4396 * netif_stop_queue/wake_queue race conditions.
4397 */
4398 static int
4399 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4400 {
4401 struct bnx2 *bp = netdev_priv(dev);
4402 dma_addr_t mapping;
4403 struct tx_bd *txbd;
4404 struct sw_bd *tx_buf;
4405 u32 len, vlan_tag_flags, last_frag, mss;
4406 u16 prod, ring_prod;
4407 int i;
4408
4409 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4410 netif_stop_queue(dev);
4411 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4412 dev->name);
4413
4414 return NETDEV_TX_BUSY;
4415 }
4416 len = skb_headlen(skb);
4417 prod = bp->tx_prod;
4418 ring_prod = TX_RING_IDX(prod);
4419
4420 vlan_tag_flags = 0;
4421 if (skb->ip_summed == CHECKSUM_HW) {
4422 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4423 }
4424
4425 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4426 vlan_tag_flags |=
4427 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4428 }
4429 #ifdef BCM_TSO
4430 if ((mss = skb_shinfo(skb)->gso_size) &&
4431 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4432 u32 tcp_opt_len, ip_tcp_len;
4433
4434 if (skb_header_cloned(skb) &&
4435 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4436 dev_kfree_skb(skb);
4437 return NETDEV_TX_OK;
4438 }
4439
4440 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4441 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4442
4443 tcp_opt_len = 0;
4444 if (skb->h.th->doff > 5) {
4445 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4446 }
4447 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4448
4449 skb->nh.iph->check = 0;
4450 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4451 skb->h.th->check =
4452 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4453 skb->nh.iph->daddr,
4454 0, IPPROTO_TCP, 0);
4455
4456 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4457 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4458 (tcp_opt_len >> 2)) << 8;
4459 }
4460 }
4461 else
4462 #endif
4463 {
4464 mss = 0;
4465 }
4466
4467 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4468
4469 tx_buf = &bp->tx_buf_ring[ring_prod];
4470 tx_buf->skb = skb;
4471 pci_unmap_addr_set(tx_buf, mapping, mapping);
4472
4473 txbd = &bp->tx_desc_ring[ring_prod];
4474
4475 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4476 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4477 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4478 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4479
4480 last_frag = skb_shinfo(skb)->nr_frags;
4481
4482 for (i = 0; i < last_frag; i++) {
4483 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4484
4485 prod = NEXT_TX_BD(prod);
4486 ring_prod = TX_RING_IDX(prod);
4487 txbd = &bp->tx_desc_ring[ring_prod];
4488
4489 len = frag->size;
4490 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4491 len, PCI_DMA_TODEVICE);
4492 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4493 mapping, mapping);
4494
4495 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4496 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4497 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4498 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4499
4500 }
4501 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4502
4503 prod = NEXT_TX_BD(prod);
4504 bp->tx_prod_bseq += skb->len;
4505
4506 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4507 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4508
4509 mmiowb();
4510
4511 bp->tx_prod = prod;
4512 dev->trans_start = jiffies;
4513
4514 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4515 spin_lock(&bp->tx_lock);
4516 netif_stop_queue(dev);
4517
4518 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4519 netif_wake_queue(dev);
4520 spin_unlock(&bp->tx_lock);
4521 }
4522
4523 return NETDEV_TX_OK;
4524 }
4525
4526 /* Called with rtnl_lock */
4527 static int
4528 bnx2_close(struct net_device *dev)
4529 {
4530 struct bnx2 *bp = netdev_priv(dev);
4531 u32 reset_code;
4532
4533 /* Calling flush_scheduled_work() may deadlock because
4534 * linkwatch_event() may be on the workqueue and it will try to get
4535 * the rtnl_lock which we are holding.
4536 */
4537 while (bp->in_reset_task)
4538 msleep(1);
4539
4540 bnx2_netif_stop(bp);
4541 del_timer_sync(&bp->timer);
4542 if (bp->flags & NO_WOL_FLAG)
4543 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
4544 else if (bp->wol)
4545 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4546 else
4547 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4548 bnx2_reset_chip(bp, reset_code);
4549 free_irq(bp->pdev->irq, dev);
4550 if (bp->flags & USING_MSI_FLAG) {
4551 pci_disable_msi(bp->pdev);
4552 bp->flags &= ~USING_MSI_FLAG;
4553 }
4554 bnx2_free_skbs(bp);
4555 bnx2_free_mem(bp);
4556 bp->link_up = 0;
4557 netif_carrier_off(bp->dev);
4558 bnx2_set_power_state(bp, PCI_D3hot);
4559 return 0;
4560 }
4561
4562 #define GET_NET_STATS64(ctr) \
4563 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4564 (unsigned long) (ctr##_lo)
4565
4566 #define GET_NET_STATS32(ctr) \
4567 (ctr##_lo)
4568
4569 #if (BITS_PER_LONG == 64)
4570 #define GET_NET_STATS GET_NET_STATS64
4571 #else
4572 #define GET_NET_STATS GET_NET_STATS32
4573 #endif
4574
4575 static struct net_device_stats *
4576 bnx2_get_stats(struct net_device *dev)
4577 {
4578 struct bnx2 *bp = netdev_priv(dev);
4579 struct statistics_block *stats_blk = bp->stats_blk;
4580 struct net_device_stats *net_stats = &bp->net_stats;
4581
4582 if (bp->stats_blk == NULL) {
4583 return net_stats;
4584 }
4585 net_stats->rx_packets =
4586 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4587 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4588 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4589
4590 net_stats->tx_packets =
4591 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4592 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4593 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4594
4595 net_stats->rx_bytes =
4596 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4597
4598 net_stats->tx_bytes =
4599 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4600
4601 net_stats->multicast =
4602 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4603
4604 net_stats->collisions =
4605 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4606
4607 net_stats->rx_length_errors =
4608 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4609 stats_blk->stat_EtherStatsOverrsizePkts);
4610
4611 net_stats->rx_over_errors =
4612 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4613
4614 net_stats->rx_frame_errors =
4615 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4616
4617 net_stats->rx_crc_errors =
4618 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4619
4620 net_stats->rx_errors = net_stats->rx_length_errors +
4621 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4622 net_stats->rx_crc_errors;
4623
4624 net_stats->tx_aborted_errors =
4625 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4626 stats_blk->stat_Dot3StatsLateCollisions);
4627
4628 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4629 (CHIP_ID(bp) == CHIP_ID_5708_A0))
4630 net_stats->tx_carrier_errors = 0;
4631 else {
4632 net_stats->tx_carrier_errors =
4633 (unsigned long)
4634 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4635 }
4636
4637 net_stats->tx_errors =
4638 (unsigned long)
4639 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4640 +
4641 net_stats->tx_aborted_errors +
4642 net_stats->tx_carrier_errors;
4643
4644 net_stats->rx_missed_errors =
4645 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
4646 stats_blk->stat_FwRxDrop);
4647
4648 return net_stats;
4649 }
4650
4651 /* All ethtool functions called with rtnl_lock */
4652
4653 static int
4654 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4655 {
4656 struct bnx2 *bp = netdev_priv(dev);
4657
4658 cmd->supported = SUPPORTED_Autoneg;
4659 if (bp->phy_flags & PHY_SERDES_FLAG) {
4660 cmd->supported |= SUPPORTED_1000baseT_Full |
4661 SUPPORTED_FIBRE;
4662
4663 cmd->port = PORT_FIBRE;
4664 }
4665 else {
4666 cmd->supported |= SUPPORTED_10baseT_Half |
4667 SUPPORTED_10baseT_Full |
4668 SUPPORTED_100baseT_Half |
4669 SUPPORTED_100baseT_Full |
4670 SUPPORTED_1000baseT_Full |
4671 SUPPORTED_TP;
4672
4673 cmd->port = PORT_TP;
4674 }
4675
4676 cmd->advertising = bp->advertising;
4677
4678 if (bp->autoneg & AUTONEG_SPEED) {
4679 cmd->autoneg = AUTONEG_ENABLE;
4680 }
4681 else {
4682 cmd->autoneg = AUTONEG_DISABLE;
4683 }
4684
4685 if (netif_carrier_ok(dev)) {
4686 cmd->speed = bp->line_speed;
4687 cmd->duplex = bp->duplex;
4688 }
4689 else {
4690 cmd->speed = -1;
4691 cmd->duplex = -1;
4692 }
4693
4694 cmd->transceiver = XCVR_INTERNAL;
4695 cmd->phy_address = bp->phy_addr;
4696
4697 return 0;
4698 }
4699
4700 static int
4701 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4702 {
4703 struct bnx2 *bp = netdev_priv(dev);
4704 u8 autoneg = bp->autoneg;
4705 u8 req_duplex = bp->req_duplex;
4706 u16 req_line_speed = bp->req_line_speed;
4707 u32 advertising = bp->advertising;
4708
4709 if (cmd->autoneg == AUTONEG_ENABLE) {
4710 autoneg |= AUTONEG_SPEED;
4711
4712 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4713
4714 /* allow advertising 1 speed */
4715 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4716 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4717 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4718 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4719
4720 if (bp->phy_flags & PHY_SERDES_FLAG)
4721 return -EINVAL;
4722
4723 advertising = cmd->advertising;
4724
4725 }
4726 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4727 advertising = cmd->advertising;
4728 }
4729 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4730 return -EINVAL;
4731 }
4732 else {
4733 if (bp->phy_flags & PHY_SERDES_FLAG) {
4734 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4735 }
4736 else {
4737 advertising = ETHTOOL_ALL_COPPER_SPEED;
4738 }
4739 }
4740 advertising |= ADVERTISED_Autoneg;
4741 }
4742 else {
4743 if (bp->phy_flags & PHY_SERDES_FLAG) {
4744 if ((cmd->speed != SPEED_1000) ||
4745 (cmd->duplex != DUPLEX_FULL)) {
4746 return -EINVAL;
4747 }
4748 }
4749 else if (cmd->speed == SPEED_1000) {
4750 return -EINVAL;
4751 }
4752 autoneg &= ~AUTONEG_SPEED;
4753 req_line_speed = cmd->speed;
4754 req_duplex = cmd->duplex;
4755 advertising = 0;
4756 }
4757
4758 bp->autoneg = autoneg;
4759 bp->advertising = advertising;
4760 bp->req_line_speed = req_line_speed;
4761 bp->req_duplex = req_duplex;
4762
4763 spin_lock_bh(&bp->phy_lock);
4764
4765 bnx2_setup_phy(bp);
4766
4767 spin_unlock_bh(&bp->phy_lock);
4768
4769 return 0;
4770 }
4771
4772 static void
4773 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4774 {
4775 struct bnx2 *bp = netdev_priv(dev);
4776
4777 strcpy(info->driver, DRV_MODULE_NAME);
4778 strcpy(info->version, DRV_MODULE_VERSION);
4779 strcpy(info->bus_info, pci_name(bp->pdev));
4780 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4781 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4782 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4783 info->fw_version[1] = info->fw_version[3] = '.';
4784 info->fw_version[5] = 0;
4785 }
4786
4787 #define BNX2_REGDUMP_LEN (32 * 1024)
4788
4789 static int
4790 bnx2_get_regs_len(struct net_device *dev)
4791 {
4792 return BNX2_REGDUMP_LEN;
4793 }
4794
4795 static void
4796 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
4797 {
4798 u32 *p = _p, i, offset;
4799 u8 *orig_p = _p;
4800 struct bnx2 *bp = netdev_priv(dev);
4801 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
4802 0x0800, 0x0880, 0x0c00, 0x0c10,
4803 0x0c30, 0x0d08, 0x1000, 0x101c,
4804 0x1040, 0x1048, 0x1080, 0x10a4,
4805 0x1400, 0x1490, 0x1498, 0x14f0,
4806 0x1500, 0x155c, 0x1580, 0x15dc,
4807 0x1600, 0x1658, 0x1680, 0x16d8,
4808 0x1800, 0x1820, 0x1840, 0x1854,
4809 0x1880, 0x1894, 0x1900, 0x1984,
4810 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
4811 0x1c80, 0x1c94, 0x1d00, 0x1d84,
4812 0x2000, 0x2030, 0x23c0, 0x2400,
4813 0x2800, 0x2820, 0x2830, 0x2850,
4814 0x2b40, 0x2c10, 0x2fc0, 0x3058,
4815 0x3c00, 0x3c94, 0x4000, 0x4010,
4816 0x4080, 0x4090, 0x43c0, 0x4458,
4817 0x4c00, 0x4c18, 0x4c40, 0x4c54,
4818 0x4fc0, 0x5010, 0x53c0, 0x5444,
4819 0x5c00, 0x5c18, 0x5c80, 0x5c90,
4820 0x5fc0, 0x6000, 0x6400, 0x6428,
4821 0x6800, 0x6848, 0x684c, 0x6860,
4822 0x6888, 0x6910, 0x8000 };
4823
4824 regs->version = 0;
4825
4826 memset(p, 0, BNX2_REGDUMP_LEN);
4827
4828 if (!netif_running(bp->dev))
4829 return;
4830
4831 i = 0;
4832 offset = reg_boundaries[0];
4833 p += offset;
4834 while (offset < BNX2_REGDUMP_LEN) {
4835 *p++ = REG_RD(bp, offset);
4836 offset += 4;
4837 if (offset == reg_boundaries[i + 1]) {
4838 offset = reg_boundaries[i + 2];
4839 p = (u32 *) (orig_p + offset);
4840 i += 2;
4841 }
4842 }
4843 }
4844
4845 static void
4846 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4847 {
4848 struct bnx2 *bp = netdev_priv(dev);
4849
4850 if (bp->flags & NO_WOL_FLAG) {
4851 wol->supported = 0;
4852 wol->wolopts = 0;
4853 }
4854 else {
4855 wol->supported = WAKE_MAGIC;
4856 if (bp->wol)
4857 wol->wolopts = WAKE_MAGIC;
4858 else
4859 wol->wolopts = 0;
4860 }
4861 memset(&wol->sopass, 0, sizeof(wol->sopass));
4862 }
4863
4864 static int
4865 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4866 {
4867 struct bnx2 *bp = netdev_priv(dev);
4868
4869 if (wol->wolopts & ~WAKE_MAGIC)
4870 return -EINVAL;
4871
4872 if (wol->wolopts & WAKE_MAGIC) {
4873 if (bp->flags & NO_WOL_FLAG)
4874 return -EINVAL;
4875
4876 bp->wol = 1;
4877 }
4878 else {
4879 bp->wol = 0;
4880 }
4881 return 0;
4882 }
4883
4884 static int
4885 bnx2_nway_reset(struct net_device *dev)
4886 {
4887 struct bnx2 *bp = netdev_priv(dev);
4888 u32 bmcr;
4889
4890 if (!(bp->autoneg & AUTONEG_SPEED)) {
4891 return -EINVAL;
4892 }
4893
4894 spin_lock_bh(&bp->phy_lock);
4895
4896 /* Force a link down visible on the other side */
4897 if (bp->phy_flags & PHY_SERDES_FLAG) {
4898 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4899 spin_unlock_bh(&bp->phy_lock);
4900
4901 msleep(20);
4902
4903 spin_lock_bh(&bp->phy_lock);
4904 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4905 bp->current_interval = SERDES_AN_TIMEOUT;
4906 bp->serdes_an_pending = 1;
4907 mod_timer(&bp->timer, jiffies + bp->current_interval);
4908 }
4909 }
4910
4911 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4912 bmcr &= ~BMCR_LOOPBACK;
4913 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4914
4915 spin_unlock_bh(&bp->phy_lock);
4916
4917 return 0;
4918 }
4919
4920 static int
4921 bnx2_get_eeprom_len(struct net_device *dev)
4922 {
4923 struct bnx2 *bp = netdev_priv(dev);
4924
4925 if (bp->flash_info == NULL)
4926 return 0;
4927
4928 return (int) bp->flash_size;
4929 }
4930
4931 static int
4932 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4933 u8 *eebuf)
4934 {
4935 struct bnx2 *bp = netdev_priv(dev);
4936 int rc;
4937
4938 /* parameters already validated in ethtool_get_eeprom */
4939
4940 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4941
4942 return rc;
4943 }
4944
4945 static int
4946 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4947 u8 *eebuf)
4948 {
4949 struct bnx2 *bp = netdev_priv(dev);
4950 int rc;
4951
4952 /* parameters already validated in ethtool_set_eeprom */
4953
4954 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4955
4956 return rc;
4957 }
4958
4959 static int
4960 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4961 {
4962 struct bnx2 *bp = netdev_priv(dev);
4963
4964 memset(coal, 0, sizeof(struct ethtool_coalesce));
4965
4966 coal->rx_coalesce_usecs = bp->rx_ticks;
4967 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4968 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4969 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4970
4971 coal->tx_coalesce_usecs = bp->tx_ticks;
4972 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4973 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4974 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4975
4976 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4977
4978 return 0;
4979 }
4980
4981 static int
4982 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4983 {
4984 struct bnx2 *bp = netdev_priv(dev);
4985
4986 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4987 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4988
4989 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4990 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4991
4992 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4993 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4994
4995 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4996 if (bp->rx_quick_cons_trip_int > 0xff)
4997 bp->rx_quick_cons_trip_int = 0xff;
4998
4999 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
5000 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
5001
5002 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
5003 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
5004
5005 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
5006 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
5007
5008 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
5009 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
5010 0xff;
5011
5012 bp->stats_ticks = coal->stats_block_coalesce_usecs;
5013 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
5014 bp->stats_ticks &= 0xffff00;
5015
5016 if (netif_running(bp->dev)) {
5017 bnx2_netif_stop(bp);
5018 bnx2_init_nic(bp);
5019 bnx2_netif_start(bp);
5020 }
5021
5022 return 0;
5023 }
5024
5025 static void
5026 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5027 {
5028 struct bnx2 *bp = netdev_priv(dev);
5029
5030 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
5031 ering->rx_mini_max_pending = 0;
5032 ering->rx_jumbo_max_pending = 0;
5033
5034 ering->rx_pending = bp->rx_ring_size;
5035 ering->rx_mini_pending = 0;
5036 ering->rx_jumbo_pending = 0;
5037
5038 ering->tx_max_pending = MAX_TX_DESC_CNT;
5039 ering->tx_pending = bp->tx_ring_size;
5040 }
5041
5042 static int
5043 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5044 {
5045 struct bnx2 *bp = netdev_priv(dev);
5046
5047 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
5048 (ering->tx_pending > MAX_TX_DESC_CNT) ||
5049 (ering->tx_pending <= MAX_SKB_FRAGS)) {
5050
5051 return -EINVAL;
5052 }
5053 if (netif_running(bp->dev)) {
5054 bnx2_netif_stop(bp);
5055 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5056 bnx2_free_skbs(bp);
5057 bnx2_free_mem(bp);
5058 }
5059
5060 bnx2_set_rx_ring_size(bp, ering->rx_pending);
5061 bp->tx_ring_size = ering->tx_pending;
5062
5063 if (netif_running(bp->dev)) {
5064 int rc;
5065
5066 rc = bnx2_alloc_mem(bp);
5067 if (rc)
5068 return rc;
5069 bnx2_init_nic(bp);
5070 bnx2_netif_start(bp);
5071 }
5072
5073 return 0;
5074 }
5075
5076 static void
5077 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5078 {
5079 struct bnx2 *bp = netdev_priv(dev);
5080
5081 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
5082 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
5083 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
5084 }
5085
5086 static int
5087 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5088 {
5089 struct bnx2 *bp = netdev_priv(dev);
5090
5091 bp->req_flow_ctrl = 0;
5092 if (epause->rx_pause)
5093 bp->req_flow_ctrl |= FLOW_CTRL_RX;
5094 if (epause->tx_pause)
5095 bp->req_flow_ctrl |= FLOW_CTRL_TX;
5096
5097 if (epause->autoneg) {
5098 bp->autoneg |= AUTONEG_FLOW_CTRL;
5099 }
5100 else {
5101 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
5102 }
5103
5104 spin_lock_bh(&bp->phy_lock);
5105
5106 bnx2_setup_phy(bp);
5107
5108 spin_unlock_bh(&bp->phy_lock);
5109
5110 return 0;
5111 }
5112
5113 static u32
5114 bnx2_get_rx_csum(struct net_device *dev)
5115 {
5116 struct bnx2 *bp = netdev_priv(dev);
5117
5118 return bp->rx_csum;
5119 }
5120
5121 static int
5122 bnx2_set_rx_csum(struct net_device *dev, u32 data)
5123 {
5124 struct bnx2 *bp = netdev_priv(dev);
5125
5126 bp->rx_csum = data;
5127 return 0;
5128 }
5129
5130 static int
5131 bnx2_set_tso(struct net_device *dev, u32 data)
5132 {
5133 if (data)
5134 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
5135 else
5136 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
5137 return 0;
5138 }
5139
5140 #define BNX2_NUM_STATS 46
5141
5142 static struct {
5143 char string[ETH_GSTRING_LEN];
5144 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
5145 { "rx_bytes" },
5146 { "rx_error_bytes" },
5147 { "tx_bytes" },
5148 { "tx_error_bytes" },
5149 { "rx_ucast_packets" },
5150 { "rx_mcast_packets" },
5151 { "rx_bcast_packets" },
5152 { "tx_ucast_packets" },
5153 { "tx_mcast_packets" },
5154 { "tx_bcast_packets" },
5155 { "tx_mac_errors" },
5156 { "tx_carrier_errors" },
5157 { "rx_crc_errors" },
5158 { "rx_align_errors" },
5159 { "tx_single_collisions" },
5160 { "tx_multi_collisions" },
5161 { "tx_deferred" },
5162 { "tx_excess_collisions" },
5163 { "tx_late_collisions" },
5164 { "tx_total_collisions" },
5165 { "rx_fragments" },
5166 { "rx_jabbers" },
5167 { "rx_undersize_packets" },
5168 { "rx_oversize_packets" },
5169 { "rx_64_byte_packets" },
5170 { "rx_65_to_127_byte_packets" },
5171 { "rx_128_to_255_byte_packets" },
5172 { "rx_256_to_511_byte_packets" },
5173 { "rx_512_to_1023_byte_packets" },
5174 { "rx_1024_to_1522_byte_packets" },
5175 { "rx_1523_to_9022_byte_packets" },
5176 { "tx_64_byte_packets" },
5177 { "tx_65_to_127_byte_packets" },
5178 { "tx_128_to_255_byte_packets" },
5179 { "tx_256_to_511_byte_packets" },
5180 { "tx_512_to_1023_byte_packets" },
5181 { "tx_1024_to_1522_byte_packets" },
5182 { "tx_1523_to_9022_byte_packets" },
5183 { "rx_xon_frames" },
5184 { "rx_xoff_frames" },
5185 { "tx_xon_frames" },
5186 { "tx_xoff_frames" },
5187 { "rx_mac_ctrl_frames" },
5188 { "rx_filtered_packets" },
5189 { "rx_discards" },
5190 { "rx_fw_discards" },
5191 };
5192
5193 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5194
5195 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5196 STATS_OFFSET32(stat_IfHCInOctets_hi),
5197 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5198 STATS_OFFSET32(stat_IfHCOutOctets_hi),
5199 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5200 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5201 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5202 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5203 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5204 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5205 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5206 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5207 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5208 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5209 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5210 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5211 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5212 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5213 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5214 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5215 STATS_OFFSET32(stat_EtherStatsCollisions),
5216 STATS_OFFSET32(stat_EtherStatsFragments),
5217 STATS_OFFSET32(stat_EtherStatsJabbers),
5218 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5219 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5220 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5221 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5222 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5223 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5224 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5225 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5226 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5227 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5228 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5229 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5230 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5231 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5232 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5233 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5234 STATS_OFFSET32(stat_XonPauseFramesReceived),
5235 STATS_OFFSET32(stat_XoffPauseFramesReceived),
5236 STATS_OFFSET32(stat_OutXonSent),
5237 STATS_OFFSET32(stat_OutXoffSent),
5238 STATS_OFFSET32(stat_MacControlFramesReceived),
5239 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5240 STATS_OFFSET32(stat_IfInMBUFDiscards),
5241 STATS_OFFSET32(stat_FwRxDrop),
5242 };
5243
5244 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5245 * skipped because of errata.
5246 */
5247 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
5248 8,0,8,8,8,8,8,8,8,8,
5249 4,0,4,4,4,4,4,4,4,4,
5250 4,4,4,4,4,4,4,4,4,4,
5251 4,4,4,4,4,4,4,4,4,4,
5252 4,4,4,4,4,4,
5253 };
5254
5255 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5256 8,0,8,8,8,8,8,8,8,8,
5257 4,4,4,4,4,4,4,4,4,4,
5258 4,4,4,4,4,4,4,4,4,4,
5259 4,4,4,4,4,4,4,4,4,4,
5260 4,4,4,4,4,4,
5261 };
5262
5263 #define BNX2_NUM_TESTS 6
5264
5265 static struct {
5266 char string[ETH_GSTRING_LEN];
5267 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
5268 { "register_test (offline)" },
5269 { "memory_test (offline)" },
5270 { "loopback_test (offline)" },
5271 { "nvram_test (online)" },
5272 { "interrupt_test (online)" },
5273 { "link_test (online)" },
5274 };
5275
5276 static int
5277 bnx2_self_test_count(struct net_device *dev)
5278 {
5279 return BNX2_NUM_TESTS;
5280 }
5281
5282 static void
5283 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5284 {
5285 struct bnx2 *bp = netdev_priv(dev);
5286
5287 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5288 if (etest->flags & ETH_TEST_FL_OFFLINE) {
5289 bnx2_netif_stop(bp);
5290 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5291 bnx2_free_skbs(bp);
5292
5293 if (bnx2_test_registers(bp) != 0) {
5294 buf[0] = 1;
5295 etest->flags |= ETH_TEST_FL_FAILED;
5296 }
5297 if (bnx2_test_memory(bp) != 0) {
5298 buf[1] = 1;
5299 etest->flags |= ETH_TEST_FL_FAILED;
5300 }
5301 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
5302 etest->flags |= ETH_TEST_FL_FAILED;
5303
5304 if (!netif_running(bp->dev)) {
5305 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5306 }
5307 else {
5308 bnx2_init_nic(bp);
5309 bnx2_netif_start(bp);
5310 }
5311
5312 /* wait for link up */
5313 msleep_interruptible(3000);
5314 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
5315 msleep_interruptible(4000);
5316 }
5317
5318 if (bnx2_test_nvram(bp) != 0) {
5319 buf[3] = 1;
5320 etest->flags |= ETH_TEST_FL_FAILED;
5321 }
5322 if (bnx2_test_intr(bp) != 0) {
5323 buf[4] = 1;
5324 etest->flags |= ETH_TEST_FL_FAILED;
5325 }
5326
5327 if (bnx2_test_link(bp) != 0) {
5328 buf[5] = 1;
5329 etest->flags |= ETH_TEST_FL_FAILED;
5330
5331 }
5332 }
5333
5334 static void
5335 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5336 {
5337 switch (stringset) {
5338 case ETH_SS_STATS:
5339 memcpy(buf, bnx2_stats_str_arr,
5340 sizeof(bnx2_stats_str_arr));
5341 break;
5342 case ETH_SS_TEST:
5343 memcpy(buf, bnx2_tests_str_arr,
5344 sizeof(bnx2_tests_str_arr));
5345 break;
5346 }
5347 }
5348
5349 static int
5350 bnx2_get_stats_count(struct net_device *dev)
5351 {
5352 return BNX2_NUM_STATS;
5353 }
5354
5355 static void
5356 bnx2_get_ethtool_stats(struct net_device *dev,
5357 struct ethtool_stats *stats, u64 *buf)
5358 {
5359 struct bnx2 *bp = netdev_priv(dev);
5360 int i;
5361 u32 *hw_stats = (u32 *) bp->stats_blk;
5362 u8 *stats_len_arr = NULL;
5363
5364 if (hw_stats == NULL) {
5365 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5366 return;
5367 }
5368
5369 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5370 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5371 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5372 (CHIP_ID(bp) == CHIP_ID_5708_A0))
5373 stats_len_arr = bnx2_5706_stats_len_arr;
5374 else
5375 stats_len_arr = bnx2_5708_stats_len_arr;
5376
5377 for (i = 0; i < BNX2_NUM_STATS; i++) {
5378 if (stats_len_arr[i] == 0) {
5379 /* skip this counter */
5380 buf[i] = 0;
5381 continue;
5382 }
5383 if (stats_len_arr[i] == 4) {
5384 /* 4-byte counter */
5385 buf[i] = (u64)
5386 *(hw_stats + bnx2_stats_offset_arr[i]);
5387 continue;
5388 }
5389 /* 8-byte counter */
5390 buf[i] = (((u64) *(hw_stats +
5391 bnx2_stats_offset_arr[i])) << 32) +
5392 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5393 }
5394 }
5395
5396 static int
5397 bnx2_phys_id(struct net_device *dev, u32 data)
5398 {
5399 struct bnx2 *bp = netdev_priv(dev);
5400 int i;
5401 u32 save;
5402
5403 if (data == 0)
5404 data = 2;
5405
5406 save = REG_RD(bp, BNX2_MISC_CFG);
5407 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5408
5409 for (i = 0; i < (data * 2); i++) {
5410 if ((i % 2) == 0) {
5411 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5412 }
5413 else {
5414 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5415 BNX2_EMAC_LED_1000MB_OVERRIDE |
5416 BNX2_EMAC_LED_100MB_OVERRIDE |
5417 BNX2_EMAC_LED_10MB_OVERRIDE |
5418 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5419 BNX2_EMAC_LED_TRAFFIC);
5420 }
5421 msleep_interruptible(500);
5422 if (signal_pending(current))
5423 break;
5424 }
5425 REG_WR(bp, BNX2_EMAC_LED, 0);
5426 REG_WR(bp, BNX2_MISC_CFG, save);
5427 return 0;
5428 }
5429
5430 static struct ethtool_ops bnx2_ethtool_ops = {
5431 .get_settings = bnx2_get_settings,
5432 .set_settings = bnx2_set_settings,
5433 .get_drvinfo = bnx2_get_drvinfo,
5434 .get_regs_len = bnx2_get_regs_len,
5435 .get_regs = bnx2_get_regs,
5436 .get_wol = bnx2_get_wol,
5437 .set_wol = bnx2_set_wol,
5438 .nway_reset = bnx2_nway_reset,
5439 .get_link = ethtool_op_get_link,
5440 .get_eeprom_len = bnx2_get_eeprom_len,
5441 .get_eeprom = bnx2_get_eeprom,
5442 .set_eeprom = bnx2_set_eeprom,
5443 .get_coalesce = bnx2_get_coalesce,
5444 .set_coalesce = bnx2_set_coalesce,
5445 .get_ringparam = bnx2_get_ringparam,
5446 .set_ringparam = bnx2_set_ringparam,
5447 .get_pauseparam = bnx2_get_pauseparam,
5448 .set_pauseparam = bnx2_set_pauseparam,
5449 .get_rx_csum = bnx2_get_rx_csum,
5450 .set_rx_csum = bnx2_set_rx_csum,
5451 .get_tx_csum = ethtool_op_get_tx_csum,
5452 .set_tx_csum = ethtool_op_set_tx_csum,
5453 .get_sg = ethtool_op_get_sg,
5454 .set_sg = ethtool_op_set_sg,
5455 #ifdef BCM_TSO
5456 .get_tso = ethtool_op_get_tso,
5457 .set_tso = bnx2_set_tso,
5458 #endif
5459 .self_test_count = bnx2_self_test_count,
5460 .self_test = bnx2_self_test,
5461 .get_strings = bnx2_get_strings,
5462 .phys_id = bnx2_phys_id,
5463 .get_stats_count = bnx2_get_stats_count,
5464 .get_ethtool_stats = bnx2_get_ethtool_stats,
5465 .get_perm_addr = ethtool_op_get_perm_addr,
5466 };
5467
5468 /* Called with rtnl_lock */
5469 static int
5470 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5471 {
5472 struct mii_ioctl_data *data = if_mii(ifr);
5473 struct bnx2 *bp = netdev_priv(dev);
5474 int err;
5475
5476 switch(cmd) {
5477 case SIOCGMIIPHY:
5478 data->phy_id = bp->phy_addr;
5479
5480 /* fallthru */
5481 case SIOCGMIIREG: {
5482 u32 mii_regval;
5483
5484 spin_lock_bh(&bp->phy_lock);
5485 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5486 spin_unlock_bh(&bp->phy_lock);
5487
5488 data->val_out = mii_regval;
5489
5490 return err;
5491 }
5492
5493 case SIOCSMIIREG:
5494 if (!capable(CAP_NET_ADMIN))
5495 return -EPERM;
5496
5497 spin_lock_bh(&bp->phy_lock);
5498 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5499 spin_unlock_bh(&bp->phy_lock);
5500
5501 return err;
5502
5503 default:
5504 /* do nothing */
5505 break;
5506 }
5507 return -EOPNOTSUPP;
5508 }
5509
5510 /* Called with rtnl_lock */
5511 static int
5512 bnx2_change_mac_addr(struct net_device *dev, void *p)
5513 {
5514 struct sockaddr *addr = p;
5515 struct bnx2 *bp = netdev_priv(dev);
5516
5517 if (!is_valid_ether_addr(addr->sa_data))
5518 return -EINVAL;
5519
5520 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5521 if (netif_running(dev))
5522 bnx2_set_mac_addr(bp);
5523
5524 return 0;
5525 }
5526
5527 /* Called with rtnl_lock */
5528 static int
5529 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5530 {
5531 struct bnx2 *bp = netdev_priv(dev);
5532
5533 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5534 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5535 return -EINVAL;
5536
5537 dev->mtu = new_mtu;
5538 if (netif_running(dev)) {
5539 bnx2_netif_stop(bp);
5540
5541 bnx2_init_nic(bp);
5542
5543 bnx2_netif_start(bp);
5544 }
5545 return 0;
5546 }
5547
5548 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5549 static void
5550 poll_bnx2(struct net_device *dev)
5551 {
5552 struct bnx2 *bp = netdev_priv(dev);
5553
5554 disable_irq(bp->pdev->irq);
5555 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5556 enable_irq(bp->pdev->irq);
5557 }
5558 #endif
5559
5560 static int __devinit
5561 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5562 {
5563 struct bnx2 *bp;
5564 unsigned long mem_len;
5565 int rc;
5566 u32 reg;
5567
5568 SET_MODULE_OWNER(dev);
5569 SET_NETDEV_DEV(dev, &pdev->dev);
5570 bp = netdev_priv(dev);
5571
5572 bp->flags = 0;
5573 bp->phy_flags = 0;
5574
5575 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5576 rc = pci_enable_device(pdev);
5577 if (rc) {
5578 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.");
5579 goto err_out;
5580 }
5581
5582 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5583 dev_err(&pdev->dev,
5584 "Cannot find PCI device base address, aborting.\n");
5585 rc = -ENODEV;
5586 goto err_out_disable;
5587 }
5588
5589 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5590 if (rc) {
5591 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
5592 goto err_out_disable;
5593 }
5594
5595 pci_set_master(pdev);
5596
5597 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5598 if (bp->pm_cap == 0) {
5599 dev_err(&pdev->dev,
5600 "Cannot find power management capability, aborting.\n");
5601 rc = -EIO;
5602 goto err_out_release;
5603 }
5604
5605 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5606 if (bp->pcix_cap == 0) {
5607 dev_err(&pdev->dev, "Cannot find PCIX capability, aborting.\n");
5608 rc = -EIO;
5609 goto err_out_release;
5610 }
5611
5612 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5613 bp->flags |= USING_DAC_FLAG;
5614 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5615 dev_err(&pdev->dev,
5616 "pci_set_consistent_dma_mask failed, aborting.\n");
5617 rc = -EIO;
5618 goto err_out_release;
5619 }
5620 }
5621 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5622 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
5623 rc = -EIO;
5624 goto err_out_release;
5625 }
5626
5627 bp->dev = dev;
5628 bp->pdev = pdev;
5629
5630 spin_lock_init(&bp->phy_lock);
5631 spin_lock_init(&bp->tx_lock);
5632 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5633
5634 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5635 mem_len = MB_GET_CID_ADDR(17);
5636 dev->mem_end = dev->mem_start + mem_len;
5637 dev->irq = pdev->irq;
5638
5639 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5640
5641 if (!bp->regview) {
5642 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
5643 rc = -ENOMEM;
5644 goto err_out_release;
5645 }
5646
5647 /* Configure byte swap and enable write to the reg_window registers.
5648 * Rely on CPU to do target byte swapping on big endian systems
5649 * The chip's target access swapping will not swap all accesses
5650 */
5651 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5652 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5653 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5654
5655 bnx2_set_power_state(bp, PCI_D0);
5656
5657 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5658
5659 /* Get bus information. */
5660 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5661 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5662 u32 clkreg;
5663
5664 bp->flags |= PCIX_FLAG;
5665
5666 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5667
5668 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5669 switch (clkreg) {
5670 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5671 bp->bus_speed_mhz = 133;
5672 break;
5673
5674 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5675 bp->bus_speed_mhz = 100;
5676 break;
5677
5678 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5679 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5680 bp->bus_speed_mhz = 66;
5681 break;
5682
5683 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5684 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5685 bp->bus_speed_mhz = 50;
5686 break;
5687
5688 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5689 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5690 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5691 bp->bus_speed_mhz = 33;
5692 break;
5693 }
5694 }
5695 else {
5696 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5697 bp->bus_speed_mhz = 66;
5698 else
5699 bp->bus_speed_mhz = 33;
5700 }
5701
5702 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5703 bp->flags |= PCI_32BIT_FLAG;
5704
5705 /* 5706A0 may falsely detect SERR and PERR. */
5706 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5707 reg = REG_RD(bp, PCI_COMMAND);
5708 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5709 REG_WR(bp, PCI_COMMAND, reg);
5710 }
5711 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5712 !(bp->flags & PCIX_FLAG)) {
5713
5714 dev_err(&pdev->dev,
5715 "5706 A1 can only be used in a PCIX bus, aborting.\n");
5716 goto err_out_unmap;
5717 }
5718
5719 bnx2_init_nvram(bp);
5720
5721 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
5722
5723 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
5724 BNX2_SHM_HDR_SIGNATURE_SIG)
5725 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
5726 else
5727 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
5728
5729 /* Get the permanent MAC address. First we need to make sure the
5730 * firmware is actually running.
5731 */
5732 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
5733
5734 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5735 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5736 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
5737 rc = -ENODEV;
5738 goto err_out_unmap;
5739 }
5740
5741 bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
5742
5743 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
5744 bp->mac_addr[0] = (u8) (reg >> 8);
5745 bp->mac_addr[1] = (u8) reg;
5746
5747 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
5748 bp->mac_addr[2] = (u8) (reg >> 24);
5749 bp->mac_addr[3] = (u8) (reg >> 16);
5750 bp->mac_addr[4] = (u8) (reg >> 8);
5751 bp->mac_addr[5] = (u8) reg;
5752
5753 bp->tx_ring_size = MAX_TX_DESC_CNT;
5754 bnx2_set_rx_ring_size(bp, 100);
5755
5756 bp->rx_csum = 1;
5757
5758 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5759
5760 bp->tx_quick_cons_trip_int = 20;
5761 bp->tx_quick_cons_trip = 20;
5762 bp->tx_ticks_int = 80;
5763 bp->tx_ticks = 80;
5764
5765 bp->rx_quick_cons_trip_int = 6;
5766 bp->rx_quick_cons_trip = 6;
5767 bp->rx_ticks_int = 18;
5768 bp->rx_ticks = 18;
5769
5770 bp->stats_ticks = 1000000 & 0xffff00;
5771
5772 bp->timer_interval = HZ;
5773 bp->current_interval = HZ;
5774
5775 bp->phy_addr = 1;
5776
5777 /* Disable WOL support if we are running on a SERDES chip. */
5778 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5779 bp->phy_flags |= PHY_SERDES_FLAG;
5780 bp->flags |= NO_WOL_FLAG;
5781 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5782 bp->phy_addr = 2;
5783 reg = REG_RD_IND(bp, bp->shmem_base +
5784 BNX2_SHARED_HW_CFG_CONFIG);
5785 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5786 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5787 }
5788 }
5789
5790 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
5791 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
5792 (CHIP_ID(bp) == CHIP_ID_5708_B1))
5793 bp->flags |= NO_WOL_FLAG;
5794
5795 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5796 bp->tx_quick_cons_trip_int =
5797 bp->tx_quick_cons_trip;
5798 bp->tx_ticks_int = bp->tx_ticks;
5799 bp->rx_quick_cons_trip_int =
5800 bp->rx_quick_cons_trip;
5801 bp->rx_ticks_int = bp->rx_ticks;
5802 bp->comp_prod_trip_int = bp->comp_prod_trip;
5803 bp->com_ticks_int = bp->com_ticks;
5804 bp->cmd_ticks_int = bp->cmd_ticks;
5805 }
5806
5807 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5808 bp->req_line_speed = 0;
5809 if (bp->phy_flags & PHY_SERDES_FLAG) {
5810 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5811
5812 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
5813 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5814 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5815 bp->autoneg = 0;
5816 bp->req_line_speed = bp->line_speed = SPEED_1000;
5817 bp->req_duplex = DUPLEX_FULL;
5818 }
5819 }
5820 else {
5821 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5822 }
5823
5824 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5825
5826 init_timer(&bp->timer);
5827 bp->timer.expires = RUN_AT(bp->timer_interval);
5828 bp->timer.data = (unsigned long) bp;
5829 bp->timer.function = bnx2_timer;
5830
5831 return 0;
5832
5833 err_out_unmap:
5834 if (bp->regview) {
5835 iounmap(bp->regview);
5836 bp->regview = NULL;
5837 }
5838
5839 err_out_release:
5840 pci_release_regions(pdev);
5841
5842 err_out_disable:
5843 pci_disable_device(pdev);
5844 pci_set_drvdata(pdev, NULL);
5845
5846 err_out:
5847 return rc;
5848 }
5849
5850 static int __devinit
5851 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5852 {
5853 static int version_printed = 0;
5854 struct net_device *dev = NULL;
5855 struct bnx2 *bp;
5856 int rc, i;
5857
5858 if (version_printed++ == 0)
5859 printk(KERN_INFO "%s", version);
5860
5861 /* dev zeroed in init_etherdev */
5862 dev = alloc_etherdev(sizeof(*bp));
5863
5864 if (!dev)
5865 return -ENOMEM;
5866
5867 rc = bnx2_init_board(pdev, dev);
5868 if (rc < 0) {
5869 free_netdev(dev);
5870 return rc;
5871 }
5872
5873 dev->open = bnx2_open;
5874 dev->hard_start_xmit = bnx2_start_xmit;
5875 dev->stop = bnx2_close;
5876 dev->get_stats = bnx2_get_stats;
5877 dev->set_multicast_list = bnx2_set_rx_mode;
5878 dev->do_ioctl = bnx2_ioctl;
5879 dev->set_mac_address = bnx2_change_mac_addr;
5880 dev->change_mtu = bnx2_change_mtu;
5881 dev->tx_timeout = bnx2_tx_timeout;
5882 dev->watchdog_timeo = TX_TIMEOUT;
5883 #ifdef BCM_VLAN
5884 dev->vlan_rx_register = bnx2_vlan_rx_register;
5885 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5886 #endif
5887 dev->poll = bnx2_poll;
5888 dev->ethtool_ops = &bnx2_ethtool_ops;
5889 dev->weight = 64;
5890
5891 bp = netdev_priv(dev);
5892
5893 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5894 dev->poll_controller = poll_bnx2;
5895 #endif
5896
5897 if ((rc = register_netdev(dev))) {
5898 dev_err(&pdev->dev, "Cannot register net device\n");
5899 if (bp->regview)
5900 iounmap(bp->regview);
5901 pci_release_regions(pdev);
5902 pci_disable_device(pdev);
5903 pci_set_drvdata(pdev, NULL);
5904 free_netdev(dev);
5905 return rc;
5906 }
5907
5908 pci_set_drvdata(pdev, dev);
5909
5910 memcpy(dev->dev_addr, bp->mac_addr, 6);
5911 memcpy(dev->perm_addr, bp->mac_addr, 6);
5912 bp->name = board_info[ent->driver_data].name,
5913 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5914 "IRQ %d, ",
5915 dev->name,
5916 bp->name,
5917 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5918 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5919 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5920 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5921 bp->bus_speed_mhz,
5922 dev->base_addr,
5923 bp->pdev->irq);
5924
5925 printk("node addr ");
5926 for (i = 0; i < 6; i++)
5927 printk("%2.2x", dev->dev_addr[i]);
5928 printk("\n");
5929
5930 dev->features |= NETIF_F_SG;
5931 if (bp->flags & USING_DAC_FLAG)
5932 dev->features |= NETIF_F_HIGHDMA;
5933 dev->features |= NETIF_F_IP_CSUM;
5934 #ifdef BCM_VLAN
5935 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5936 #endif
5937 #ifdef BCM_TSO
5938 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
5939 #endif
5940
5941 netif_carrier_off(bp->dev);
5942
5943 return 0;
5944 }
5945
5946 static void __devexit
5947 bnx2_remove_one(struct pci_dev *pdev)
5948 {
5949 struct net_device *dev = pci_get_drvdata(pdev);
5950 struct bnx2 *bp = netdev_priv(dev);
5951
5952 flush_scheduled_work();
5953
5954 unregister_netdev(dev);
5955
5956 if (bp->regview)
5957 iounmap(bp->regview);
5958
5959 free_netdev(dev);
5960 pci_release_regions(pdev);
5961 pci_disable_device(pdev);
5962 pci_set_drvdata(pdev, NULL);
5963 }
5964
5965 static int
5966 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5967 {
5968 struct net_device *dev = pci_get_drvdata(pdev);
5969 struct bnx2 *bp = netdev_priv(dev);
5970 u32 reset_code;
5971
5972 if (!netif_running(dev))
5973 return 0;
5974
5975 flush_scheduled_work();
5976 bnx2_netif_stop(bp);
5977 netif_device_detach(dev);
5978 del_timer_sync(&bp->timer);
5979 if (bp->flags & NO_WOL_FLAG)
5980 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5981 else if (bp->wol)
5982 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5983 else
5984 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5985 bnx2_reset_chip(bp, reset_code);
5986 bnx2_free_skbs(bp);
5987 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
5988 return 0;
5989 }
5990
5991 static int
5992 bnx2_resume(struct pci_dev *pdev)
5993 {
5994 struct net_device *dev = pci_get_drvdata(pdev);
5995 struct bnx2 *bp = netdev_priv(dev);
5996
5997 if (!netif_running(dev))
5998 return 0;
5999
6000 bnx2_set_power_state(bp, PCI_D0);
6001 netif_device_attach(dev);
6002 bnx2_init_nic(bp);
6003 bnx2_netif_start(bp);
6004 return 0;
6005 }
6006
6007 static struct pci_driver bnx2_pci_driver = {
6008 .name = DRV_MODULE_NAME,
6009 .id_table = bnx2_pci_tbl,
6010 .probe = bnx2_init_one,
6011 .remove = __devexit_p(bnx2_remove_one),
6012 .suspend = bnx2_suspend,
6013 .resume = bnx2_resume,
6014 };
6015
6016 static int __init bnx2_init(void)
6017 {
6018 return pci_module_init(&bnx2_pci_driver);
6019 }
6020
6021 static void __exit bnx2_cleanup(void)
6022 {
6023 pci_unregister_driver(&bnx2_pci_driver);
6024 }
6025
6026 module_init(bnx2_init);
6027 module_exit(bnx2_cleanup);
6028
6029
6030
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree