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ARM: 6310/1: mmci: support different FIFO sizes
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / mmc / host / mmci.c
blob1932e9cc8f52e7d394ee9c9f28c4a957e7a08538
1 /*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson AB.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/highmem.h>
20 #include <linux/log2.h>
21 #include <linux/mmc/host.h>
22 #include <linux/amba/bus.h>
23 #include <linux/clk.h>
24 #include <linux/scatterlist.h>
25 #include <linux/gpio.h>
26 #include <linux/amba/mmci.h>
27 #include <linux/regulator/consumer.h>
28
29 #include <asm/div64.h>
30 #include <asm/io.h>
31 #include <asm/sizes.h>
32
33 #include "mmci.h"
34
35 #define DRIVER_NAME "mmci-pl18x"
36
37 static unsigned int fmax = 515633;
38
39 /**
40 * struct variant_data - MMCI variant-specific quirks
41 * @clkreg: default value for MCICLOCK register
42 * @clkreg_enable: enable value for MMCICLOCK register
43 * @datalength_bits: number of bits in the MMCIDATALENGTH register
44 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
45 * is asserted (likewise for RX)
46 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
47 * is asserted (likewise for RX)
48 */
49 struct variant_data {
50 unsigned int clkreg;
51 unsigned int clkreg_enable;
52 unsigned int datalength_bits;
53 unsigned int fifosize;
54 unsigned int fifohalfsize;
55 };
56
57 static struct variant_data variant_arm = {
58 .fifosize = 16 * 4,
59 .fifohalfsize = 8 * 4,
60 .datalength_bits = 16,
61 };
62
63 static struct variant_data variant_u300 = {
64 .fifosize = 16 * 4,
65 .fifohalfsize = 8 * 4,
66 .clkreg_enable = 1 << 13, /* HWFCEN */
67 .datalength_bits = 16,
68 };
69
70 static struct variant_data variant_ux500 = {
71 .fifosize = 30 * 4,
72 .fifohalfsize = 8 * 4,
73 .clkreg = MCI_CLK_ENABLE,
74 .clkreg_enable = 1 << 14, /* HWFCEN */
75 .datalength_bits = 24,
76 };
77 /*
78 * This must be called with host->lock held
79 */
80 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
81 {
82 struct variant_data *variant = host->variant;
83 u32 clk = variant->clkreg;
84
85 if (desired) {
86 if (desired >= host->mclk) {
87 clk = MCI_CLK_BYPASS;
88 host->cclk = host->mclk;
89 } else {
90 clk = host->mclk / (2 * desired) - 1;
91 if (clk >= 256)
92 clk = 255;
93 host->cclk = host->mclk / (2 * (clk + 1));
94 }
95
96 clk |= variant->clkreg_enable;
97 clk |= MCI_CLK_ENABLE;
98 /* This hasn't proven to be worthwhile */
99 /* clk |= MCI_CLK_PWRSAVE; */
100 }
101
102 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
103 clk |= MCI_4BIT_BUS;
104 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
105 clk |= MCI_ST_8BIT_BUS;
106
107 writel(clk, host->base + MMCICLOCK);
108 }
109
110 static void
111 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
112 {
113 writel(0, host->base + MMCICOMMAND);
114
115 BUG_ON(host->data);
116
117 host->mrq = NULL;
118 host->cmd = NULL;
119
120 if (mrq->data)
121 mrq->data->bytes_xfered = host->data_xfered;
122
123 /*
124 * Need to drop the host lock here; mmc_request_done may call
125 * back into the driver...
126 */
127 spin_unlock(&host->lock);
128 mmc_request_done(host->mmc, mrq);
129 spin_lock(&host->lock);
130 }
131
132 static void mmci_stop_data(struct mmci_host *host)
133 {
134 writel(0, host->base + MMCIDATACTRL);
135 writel(0, host->base + MMCIMASK1);
136 host->data = NULL;
137 }
138
139 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
140 {
141 unsigned int flags = SG_MITER_ATOMIC;
142
143 if (data->flags & MMC_DATA_READ)
144 flags |= SG_MITER_TO_SG;
145 else
146 flags |= SG_MITER_FROM_SG;
147
148 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
149 }
150
151 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
152 {
153 struct variant_data *variant = host->variant;
154 unsigned int datactrl, timeout, irqmask;
155 unsigned long long clks;
156 void __iomem *base;
157 int blksz_bits;
158
159 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
160 data->blksz, data->blocks, data->flags);
161
162 host->data = data;
163 host->size = data->blksz * data->blocks;
164 host->data_xfered = 0;
165
166 mmci_init_sg(host, data);
167
168 clks = (unsigned long long)data->timeout_ns * host->cclk;
169 do_div(clks, 1000000000UL);
170
171 timeout = data->timeout_clks + (unsigned int)clks;
172
173 base = host->base;
174 writel(timeout, base + MMCIDATATIMER);
175 writel(host->size, base + MMCIDATALENGTH);
176
177 blksz_bits = ffs(data->blksz) - 1;
178 BUG_ON(1 << blksz_bits != data->blksz);
179
180 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
181 if (data->flags & MMC_DATA_READ) {
182 datactrl |= MCI_DPSM_DIRECTION;
183 irqmask = MCI_RXFIFOHALFFULLMASK;
184
185 /*
186 * If we have less than a FIFOSIZE of bytes to transfer,
187 * trigger a PIO interrupt as soon as any data is available.
188 */
189 if (host->size < variant->fifosize)
190 irqmask |= MCI_RXDATAAVLBLMASK;
191 } else {
192 /*
193 * We don't actually need to include "FIFO empty" here
194 * since its implicit in "FIFO half empty".
195 */
196 irqmask = MCI_TXFIFOHALFEMPTYMASK;
197 }
198
199 writel(datactrl, base + MMCIDATACTRL);
200 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
201 writel(irqmask, base + MMCIMASK1);
202 }
203
204 static void
205 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
206 {
207 void __iomem *base = host->base;
208
209 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
210 cmd->opcode, cmd->arg, cmd->flags);
211
212 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
213 writel(0, base + MMCICOMMAND);
214 udelay(1);
215 }
216
217 c |= cmd->opcode | MCI_CPSM_ENABLE;
218 if (cmd->flags & MMC_RSP_PRESENT) {
219 if (cmd->flags & MMC_RSP_136)
220 c |= MCI_CPSM_LONGRSP;
221 c |= MCI_CPSM_RESPONSE;
222 }
223 if (/*interrupt*/0)
224 c |= MCI_CPSM_INTERRUPT;
225
226 host->cmd = cmd;
227
228 writel(cmd->arg, base + MMCIARGUMENT);
229 writel(c, base + MMCICOMMAND);
230 }
231
232 static void
233 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
234 unsigned int status)
235 {
236 if (status & MCI_DATABLOCKEND) {
237 host->data_xfered += data->blksz;
238 #ifdef CONFIG_ARCH_U300
239 /*
240 * On the U300 some signal or other is
241 * badly routed so that a data write does
242 * not properly terminate with a MCI_DATAEND
243 * status flag. This quirk will make writes
244 * work again.
245 */
246 if (data->flags & MMC_DATA_WRITE)
247 status |= MCI_DATAEND;
248 #endif
249 }
250 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
251 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status);
252 if (status & MCI_DATACRCFAIL)
253 data->error = -EILSEQ;
254 else if (status & MCI_DATATIMEOUT)
255 data->error = -ETIMEDOUT;
256 else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
257 data->error = -EIO;
258 status |= MCI_DATAEND;
259
260 /*
261 * We hit an error condition. Ensure that any data
262 * partially written to a page is properly coherent.
263 */
264 if (data->flags & MMC_DATA_READ) {
265 struct sg_mapping_iter *sg_miter = &host->sg_miter;
266 unsigned long flags;
267
268 local_irq_save(flags);
269 if (sg_miter_next(sg_miter)) {
270 flush_dcache_page(sg_miter->page);
271 sg_miter_stop(sg_miter);
272 }
273 local_irq_restore(flags);
274 }
275 }
276 if (status & MCI_DATAEND) {
277 mmci_stop_data(host);
278
279 if (!data->stop) {
280 mmci_request_end(host, data->mrq);
281 } else {
282 mmci_start_command(host, data->stop, 0);
283 }
284 }
285 }
286
287 static void
288 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
289 unsigned int status)
290 {
291 void __iomem *base = host->base;
292
293 host->cmd = NULL;
294
295 cmd->resp[0] = readl(base + MMCIRESPONSE0);
296 cmd->resp[1] = readl(base + MMCIRESPONSE1);
297 cmd->resp[2] = readl(base + MMCIRESPONSE2);
298 cmd->resp[3] = readl(base + MMCIRESPONSE3);
299
300 if (status & MCI_CMDTIMEOUT) {
301 cmd->error = -ETIMEDOUT;
302 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
303 cmd->error = -EILSEQ;
304 }
305
306 if (!cmd->data || cmd->error) {
307 if (host->data)
308 mmci_stop_data(host);
309 mmci_request_end(host, cmd->mrq);
310 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
311 mmci_start_data(host, cmd->data);
312 }
313 }
314
315 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
316 {
317 void __iomem *base = host->base;
318 char *ptr = buffer;
319 u32 status;
320 int host_remain = host->size;
321
322 do {
323 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
324
325 if (count > remain)
326 count = remain;
327
328 if (count <= 0)
329 break;
330
331 readsl(base + MMCIFIFO, ptr, count >> 2);
332
333 ptr += count;
334 remain -= count;
335 host_remain -= count;
336
337 if (remain == 0)
338 break;
339
340 status = readl(base + MMCISTATUS);
341 } while (status & MCI_RXDATAAVLBL);
342
343 return ptr - buffer;
344 }
345
346 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
347 {
348 struct variant_data *variant = host->variant;
349 void __iomem *base = host->base;
350 char *ptr = buffer;
351
352 do {
353 unsigned int count, maxcnt;
354
355 maxcnt = status & MCI_TXFIFOEMPTY ?
356 variant->fifosize : variant->fifohalfsize;
357 count = min(remain, maxcnt);
358
359 writesl(base + MMCIFIFO, ptr, count >> 2);
360
361 ptr += count;
362 remain -= count;
363
364 if (remain == 0)
365 break;
366
367 status = readl(base + MMCISTATUS);
368 } while (status & MCI_TXFIFOHALFEMPTY);
369
370 return ptr - buffer;
371 }
372
373 /*
374 * PIO data transfer IRQ handler.
375 */
376 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
377 {
378 struct mmci_host *host = dev_id;
379 struct sg_mapping_iter *sg_miter = &host->sg_miter;
380 struct variant_data *variant = host->variant;
381 void __iomem *base = host->base;
382 unsigned long flags;
383 u32 status;
384
385 status = readl(base + MMCISTATUS);
386
387 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
388
389 local_irq_save(flags);
390
391 do {
392 unsigned int remain, len;
393 char *buffer;
394
395 /*
396 * For write, we only need to test the half-empty flag
397 * here - if the FIFO is completely empty, then by
398 * definition it is more than half empty.
399 *
400 * For read, check for data available.
401 */
402 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
403 break;
404
405 if (!sg_miter_next(sg_miter))
406 break;
407
408 buffer = sg_miter->addr;
409 remain = sg_miter->length;
410
411 len = 0;
412 if (status & MCI_RXACTIVE)
413 len = mmci_pio_read(host, buffer, remain);
414 if (status & MCI_TXACTIVE)
415 len = mmci_pio_write(host, buffer, remain, status);
416
417 sg_miter->consumed = len;
418
419 host->size -= len;
420 remain -= len;
421
422 if (remain)
423 break;
424
425 if (status & MCI_RXACTIVE)
426 flush_dcache_page(sg_miter->page);
427
428 status = readl(base + MMCISTATUS);
429 } while (1);
430
431 sg_miter_stop(sg_miter);
432
433 local_irq_restore(flags);
434
435 /*
436 * If we're nearing the end of the read, switch to
437 * "any data available" mode.
438 */
439 if (status & MCI_RXACTIVE && host->size < variant->fifosize)
440 writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
441
442 /*
443 * If we run out of data, disable the data IRQs; this
444 * prevents a race where the FIFO becomes empty before
445 * the chip itself has disabled the data path, and
446 * stops us racing with our data end IRQ.
447 */
448 if (host->size == 0) {
449 writel(0, base + MMCIMASK1);
450 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
451 }
452
453 return IRQ_HANDLED;
454 }
455
456 /*
457 * Handle completion of command and data transfers.
458 */
459 static irqreturn_t mmci_irq(int irq, void *dev_id)
460 {
461 struct mmci_host *host = dev_id;
462 u32 status;
463 int ret = 0;
464
465 spin_lock(&host->lock);
466
467 do {
468 struct mmc_command *cmd;
469 struct mmc_data *data;
470
471 status = readl(host->base + MMCISTATUS);
472 status &= readl(host->base + MMCIMASK0);
473 writel(status, host->base + MMCICLEAR);
474
475 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
476
477 data = host->data;
478 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
479 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
480 mmci_data_irq(host, data, status);
481
482 cmd = host->cmd;
483 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
484 mmci_cmd_irq(host, cmd, status);
485
486 ret = 1;
487 } while (status);
488
489 spin_unlock(&host->lock);
490
491 return IRQ_RETVAL(ret);
492 }
493
494 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
495 {
496 struct mmci_host *host = mmc_priv(mmc);
497 unsigned long flags;
498
499 WARN_ON(host->mrq != NULL);
500
501 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
502 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
503 mrq->data->blksz);
504 mrq->cmd->error = -EINVAL;
505 mmc_request_done(mmc, mrq);
506 return;
507 }
508
509 spin_lock_irqsave(&host->lock, flags);
510
511 host->mrq = mrq;
512
513 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
514 mmci_start_data(host, mrq->data);
515
516 mmci_start_command(host, mrq->cmd, 0);
517
518 spin_unlock_irqrestore(&host->lock, flags);
519 }
520
521 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
522 {
523 struct mmci_host *host = mmc_priv(mmc);
524 u32 pwr = 0;
525 unsigned long flags;
526
527 switch (ios->power_mode) {
528 case MMC_POWER_OFF:
529 if(host->vcc &&
530 regulator_is_enabled(host->vcc))
531 regulator_disable(host->vcc);
532 break;
533 case MMC_POWER_UP:
534 #ifdef CONFIG_REGULATOR
535 if (host->vcc)
536 /* This implicitly enables the regulator */
537 mmc_regulator_set_ocr(host->vcc, ios->vdd);
538 #endif
539 if (host->plat->vdd_handler)
540 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
541 ios->power_mode);
542 /* The ST version does not have this, fall through to POWER_ON */
543 if (host->hw_designer != AMBA_VENDOR_ST) {
544 pwr |= MCI_PWR_UP;
545 break;
546 }
547 case MMC_POWER_ON:
548 pwr |= MCI_PWR_ON;
549 break;
550 }
551
552 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
553 if (host->hw_designer != AMBA_VENDOR_ST)
554 pwr |= MCI_ROD;
555 else {
556 /*
557 * The ST Micro variant use the ROD bit for something
558 * else and only has OD (Open Drain).
559 */
560 pwr |= MCI_OD;
561 }
562 }
563
564 spin_lock_irqsave(&host->lock, flags);
565
566 mmci_set_clkreg(host, ios->clock);
567
568 if (host->pwr != pwr) {
569 host->pwr = pwr;
570 writel(pwr, host->base + MMCIPOWER);
571 }
572
573 spin_unlock_irqrestore(&host->lock, flags);
574 }
575
576 static int mmci_get_ro(struct mmc_host *mmc)
577 {
578 struct mmci_host *host = mmc_priv(mmc);
579
580 if (host->gpio_wp == -ENOSYS)
581 return -ENOSYS;
582
583 return gpio_get_value(host->gpio_wp);
584 }
585
586 static int mmci_get_cd(struct mmc_host *mmc)
587 {
588 struct mmci_host *host = mmc_priv(mmc);
589 struct mmci_platform_data *plat = host->plat;
590 unsigned int status;
591
592 if (host->gpio_cd == -ENOSYS)
593 status = plat->status(mmc_dev(host->mmc));
594 else
595 status = !!gpio_get_value(host->gpio_cd) ^ plat->cd_invert;
596
597 /*
598 * Use positive logic throughout - status is zero for no card,
599 * non-zero for card inserted.
600 */
601 return status;
602 }
603
604 static const struct mmc_host_ops mmci_ops = {
605 .request = mmci_request,
606 .set_ios = mmci_set_ios,
607 .get_ro = mmci_get_ro,
608 .get_cd = mmci_get_cd,
609 };
610
611 static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
612 {
613 struct mmci_platform_data *plat = dev->dev.platform_data;
614 struct variant_data *variant = id->data;
615 struct mmci_host *host;
616 struct mmc_host *mmc;
617 int ret;
618
619 /* must have platform data */
620 if (!plat) {
621 ret = -EINVAL;
622 goto out;
623 }
624
625 ret = amba_request_regions(dev, DRIVER_NAME);
626 if (ret)
627 goto out;
628
629 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
630 if (!mmc) {
631 ret = -ENOMEM;
632 goto rel_regions;
633 }
634
635 host = mmc_priv(mmc);
636 host->mmc = mmc;
637
638 host->gpio_wp = -ENOSYS;
639 host->gpio_cd = -ENOSYS;
640
641 host->hw_designer = amba_manf(dev);
642 host->hw_revision = amba_rev(dev);
643 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
644 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
645
646 host->clk = clk_get(&dev->dev, NULL);
647 if (IS_ERR(host->clk)) {
648 ret = PTR_ERR(host->clk);
649 host->clk = NULL;
650 goto host_free;
651 }
652
653 ret = clk_enable(host->clk);
654 if (ret)
655 goto clk_free;
656
657 host->plat = plat;
658 host->variant = variant;
659 host->mclk = clk_get_rate(host->clk);
660 /*
661 * According to the spec, mclk is max 100 MHz,
662 * so we try to adjust the clock down to this,
663 * (if possible).
664 */
665 if (host->mclk > 100000000) {
666 ret = clk_set_rate(host->clk, 100000000);
667 if (ret < 0)
668 goto clk_disable;
669 host->mclk = clk_get_rate(host->clk);
670 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
671 host->mclk);
672 }
673 host->base = ioremap(dev->res.start, resource_size(&dev->res));
674 if (!host->base) {
675 ret = -ENOMEM;
676 goto clk_disable;
677 }
678
679 mmc->ops = &mmci_ops;
680 mmc->f_min = (host->mclk + 511) / 512;
681 /*
682 * If the platform data supplies a maximum operating
683 * frequency, this takes precedence. Else, we fall back
684 * to using the module parameter, which has a (low)
685 * default value in case it is not specified. Either
686 * value must not exceed the clock rate into the block,
687 * of course.
688 */
689 if (plat->f_max)
690 mmc->f_max = min(host->mclk, plat->f_max);
691 else
692 mmc->f_max = min(host->mclk, fmax);
693 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
694
695 #ifdef CONFIG_REGULATOR
696 /* If we're using the regulator framework, try to fetch a regulator */
697 host->vcc = regulator_get(&dev->dev, "vmmc");
698 if (IS_ERR(host->vcc))
699 host->vcc = NULL;
700 else {
701 int mask = mmc_regulator_get_ocrmask(host->vcc);
702
703 if (mask < 0)
704 dev_err(&dev->dev, "error getting OCR mask (%d)\n",
705 mask);
706 else {
707 host->mmc->ocr_avail = (u32) mask;
708 if (plat->ocr_mask)
709 dev_warn(&dev->dev,
710 "Provided ocr_mask/setpower will not be used "
711 "(using regulator instead)\n");
712 }
713 }
714 #endif
715 /* Fall back to platform data if no regulator is found */
716 if (host->vcc == NULL)
717 mmc->ocr_avail = plat->ocr_mask;
718 mmc->caps = plat->capabilities;
719 mmc->caps |= MMC_CAP_NEEDS_POLL;
720
721 /*
722 * We can do SGIO
723 */
724 mmc->max_hw_segs = 16;
725 mmc->max_phys_segs = NR_SG;
726
727 /*
728 * Since only a certain number of bits are valid in the data length
729 * register, we must ensure that we don't exceed 2^num-1 bytes in a
730 * single request.
731 */
732 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
733
734 /*
735 * Set the maximum segment size. Since we aren't doing DMA
736 * (yet) we are only limited by the data length register.
737 */
738 mmc->max_seg_size = mmc->max_req_size;
739
740 /*
741 * Block size can be up to 2048 bytes, but must be a power of two.
742 */
743 mmc->max_blk_size = 2048;
744
745 /*
746 * No limit on the number of blocks transferred.
747 */
748 mmc->max_blk_count = mmc->max_req_size;
749
750 spin_lock_init(&host->lock);
751
752 writel(0, host->base + MMCIMASK0);
753 writel(0, host->base + MMCIMASK1);
754 writel(0xfff, host->base + MMCICLEAR);
755
756 if (gpio_is_valid(plat->gpio_cd)) {
757 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
758 if (ret == 0)
759 ret = gpio_direction_input(plat->gpio_cd);
760 if (ret == 0)
761 host->gpio_cd = plat->gpio_cd;
762 else if (ret != -ENOSYS)
763 goto err_gpio_cd;
764 }
765 if (gpio_is_valid(plat->gpio_wp)) {
766 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
767 if (ret == 0)
768 ret = gpio_direction_input(plat->gpio_wp);
769 if (ret == 0)
770 host->gpio_wp = plat->gpio_wp;
771 else if (ret != -ENOSYS)
772 goto err_gpio_wp;
773 }
774
775 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
776 if (ret)
777 goto unmap;
778
779 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host);
780 if (ret)
781 goto irq0_free;
782
783 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
784
785 amba_set_drvdata(dev, mmc);
786
787 mmc_add_host(mmc);
788
789 dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
790 mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
791 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
792
793 return 0;
794
795 irq0_free:
796 free_irq(dev->irq[0], host);
797 unmap:
798 if (host->gpio_wp != -ENOSYS)
799 gpio_free(host->gpio_wp);
800 err_gpio_wp:
801 if (host->gpio_cd != -ENOSYS)
802 gpio_free(host->gpio_cd);
803 err_gpio_cd:
804 iounmap(host->base);
805 clk_disable:
806 clk_disable(host->clk);
807 clk_free:
808 clk_put(host->clk);
809 host_free:
810 mmc_free_host(mmc);
811 rel_regions:
812 amba_release_regions(dev);
813 out:
814 return ret;
815 }
816
817 static int __devexit mmci_remove(struct amba_device *dev)
818 {
819 struct mmc_host *mmc = amba_get_drvdata(dev);
820
821 amba_set_drvdata(dev, NULL);
822
823 if (mmc) {
824 struct mmci_host *host = mmc_priv(mmc);
825
826 mmc_remove_host(mmc);
827
828 writel(0, host->base + MMCIMASK0);
829 writel(0, host->base + MMCIMASK1);
830
831 writel(0, host->base + MMCICOMMAND);
832 writel(0, host->base + MMCIDATACTRL);
833
834 free_irq(dev->irq[0], host);
835 free_irq(dev->irq[1], host);
836
837 if (host->gpio_wp != -ENOSYS)
838 gpio_free(host->gpio_wp);
839 if (host->gpio_cd != -ENOSYS)
840 gpio_free(host->gpio_cd);
841
842 iounmap(host->base);
843 clk_disable(host->clk);
844 clk_put(host->clk);
845
846 if (regulator_is_enabled(host->vcc))
847 regulator_disable(host->vcc);
848 regulator_put(host->vcc);
849
850 mmc_free_host(mmc);
851
852 amba_release_regions(dev);
853 }
854
855 return 0;
856 }
857
858 #ifdef CONFIG_PM
859 static int mmci_suspend(struct amba_device *dev, pm_message_t state)
860 {
861 struct mmc_host *mmc = amba_get_drvdata(dev);
862 int ret = 0;
863
864 if (mmc) {
865 struct mmci_host *host = mmc_priv(mmc);
866
867 ret = mmc_suspend_host(mmc);
868 if (ret == 0)
869 writel(0, host->base + MMCIMASK0);
870 }
871
872 return ret;
873 }
874
875 static int mmci_resume(struct amba_device *dev)
876 {
877 struct mmc_host *mmc = amba_get_drvdata(dev);
878 int ret = 0;
879
880 if (mmc) {
881 struct mmci_host *host = mmc_priv(mmc);
882
883 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
884
885 ret = mmc_resume_host(mmc);
886 }
887
888 return ret;
889 }
890 #else
891 #define mmci_suspend NULL
892 #define mmci_resume NULL
893 #endif
894
895 static struct amba_id mmci_ids[] = {
896 {
897 .id = 0x00041180,
898 .mask = 0x000fffff,
899 .data = &variant_arm,
900 },
901 {
902 .id = 0x00041181,
903 .mask = 0x000fffff,
904 .data = &variant_arm,
905 },
906 /* ST Micro variants */
907 {
908 .id = 0x00180180,
909 .mask = 0x00ffffff,
910 .data = &variant_u300,
911 },
912 {
913 .id = 0x00280180,
914 .mask = 0x00ffffff,
915 .data = &variant_u300,
916 },
917 {
918 .id = 0x00480180,
919 .mask = 0x00ffffff,
920 .data = &variant_ux500,
921 },
922 { 0, 0 },
923 };
924
925 static struct amba_driver mmci_driver = {
926 .drv = {
927 .name = DRIVER_NAME,
928 },
929 .probe = mmci_probe,
930 .remove = __devexit_p(mmci_remove),
931 .suspend = mmci_suspend,
932 .resume = mmci_resume,
933 .id_table = mmci_ids,
934 };
935
936 static int __init mmci_init(void)
937 {
938 return amba_driver_register(&mmci_driver);
939 }
940
941 static void __exit mmci_exit(void)
942 {
943 amba_driver_unregister(&mmci_driver);
944 }
945
946 module_init(mmci_init);
947 module_exit(mmci_exit);
948 module_param(fmax, uint, 0444);
949
950 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
951 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree