drivers/net/8390.h

   1 /* Generic NS8390 register definitions. */
   2 /* This file is part of Donald Becker's 8390 drivers, and is distributed
   3    under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
   4    Some of these names and comments originated from the Crynwr
   5    packet drivers, which are distributed under the GPL. */
   6
   7 #ifndef _8390_h
   8 #define _8390_h
   9
  10 #include <linux/if_ether.h>
  11 #include <linux/ioport.h>
  12 #include <linux/skbuff.h>
  13
  14 #define TX_PAGES 12     /* Two Tx slots */
  15
  16 #define ETHER_ADDR_LEN 6
  17
  18 /* The 8390 specific per-packet-header format. */
  19 struct e8390_pkt_hdr {
  20   unsigned char status; /* status */
  21   unsigned char next;   /* pointer to next packet. */
  22   unsigned short count; /* header + packet length in bytes */
  23 };
  24
  25 #ifdef notdef
  26 extern int ei_debug;
  27 #else
  28 #define ei_debug 1
  29 #endif
  30
  31 #ifdef CONFIG_NET_POLL_CONTROLLER
  32 extern void ei_poll(struct net_device *dev);
  33 #endif
  34
  35 extern void NS8390_init(struct net_device *dev, int startp);
  36 extern int ei_open(struct net_device *dev);
  37 extern int ei_close(struct net_device *dev);
  38 extern irqreturn_t ei_interrupt(int irq, void *dev_id);
  39 extern struct net_device *__alloc_ei_netdev(int size);
  40 static inline struct net_device *alloc_ei_netdev(void)
  41 {
  42         return __alloc_ei_netdev(0);
  43 }
  44
  45 /* You have one of these per-board */
  46 struct ei_device {
  47         const char *name;
  48         void (*reset_8390)(struct net_device *);
  49         void (*get_8390_hdr)(struct net_device *, struct e8390_pkt_hdr *, int);
  50         void (*block_output)(struct net_device *, int, const unsigned char *, int);
  51         void (*block_input)(struct net_device *, int, struct sk_buff *, int);
  52         unsigned long rmem_start;
  53         unsigned long rmem_end;
  54         void __iomem *mem;
  55         unsigned char mcfilter[8];
  56         unsigned open:1;
  57         unsigned word16:1;              /* We have the 16-bit (vs 8-bit) version of the card. */
  58         unsigned bigendian:1;           /* 16-bit big endian mode. Do NOT */
  59                                         /* set this on random 8390 clones! */
  60         unsigned txing:1;               /* Transmit Active */
  61         unsigned irqlock:1;             /* 8390's intrs disabled when '1'. */
  62         unsigned dmaing:1;              /* Remote DMA Active */
  63         unsigned char tx_start_page, rx_start_page, stop_page;
  64         unsigned char current_page;     /* Read pointer in buffer  */
  65         unsigned char interface_num;    /* Net port (AUI, 10bT.) to use. */
  66         unsigned char txqueue;          /* Tx Packet buffer queue length. */
  67         short tx1, tx2;                 /* Packet lengths for ping-pong tx. */
  68         short lasttx;                   /* Alpha version consistency check. */
  69         unsigned char reg0;             /* Register '0' in a WD8013 */
  70         unsigned char reg5;             /* Register '5' in a WD8013 */
  71         unsigned char saved_irq;        /* Original dev->irq value. */
  72         struct net_device_stats stat;   /* The new statistics table. */
  73         u32 *reg_offset;                /* Register mapping table */
  74         spinlock_t page_lock;           /* Page register locks */
  75         unsigned long priv;             /* Private field to store bus IDs etc. */
  76 };
  77
  78 /* The maximum number of 8390 interrupt service routines called per IRQ. */
  79 #define MAX_SERVICE 12
  80
  81 /* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
  82 #define TX_TIMEOUT (20*HZ/100)
  83
  84 #define ei_status (*(struct ei_device *)netdev_priv(dev))
  85
  86 /* Some generic ethernet register configurations. */
  87 #define E8390_TX_IRQ_MASK       0xa     /* For register EN0_ISR */
  88 #define E8390_RX_IRQ_MASK       0x5
  89 #define E8390_RXCONFIG          0x4     /* EN0_RXCR: broadcasts, no multicast,errors */
  90 #define E8390_RXOFF             0x20    /* EN0_RXCR: Accept no packets */
  91 #define E8390_TXCONFIG          0x00    /* EN0_TXCR: Normal transmit mode */
  92 #define E8390_TXOFF             0x02    /* EN0_TXCR: Transmitter off */
  93
  94 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  95 #define E8390_STOP      0x01    /* Stop and reset the chip */
  96 #define E8390_START     0x02    /* Start the chip, clear reset */
  97 #define E8390_TRANS     0x04    /* Transmit a frame */
  98 #define E8390_RREAD     0x08    /* Remote read */
  99 #define E8390_RWRITE    0x10    /* Remote write  */
 100 #define E8390_NODMA     0x20    /* Remote DMA */
 101 #define E8390_PAGE0     0x00    /* Select page chip registers */
 102 #define E8390_PAGE1     0x40    /* using the two high-order bits */
 103 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
 104
 105 /*
 106  *      Only generate indirect loads given a machine that needs them.
 107  *      - removed AMIGA_PCMCIA from this list, handled as ISA io now
 108  */
 109
 110 #ifndef ei_inb
 111 #define ei_inb(_p)      inb(_p)
 112 #define ei_outb(_v,_p)  outb(_v,_p)
 113 #define ei_inb_p(_p)    inb_p(_p)
 114 #define ei_outb_p(_v,_p) outb_p(_v,_p)
 115 #endif
 116
 117 #ifndef EI_SHIFT
 118 #define EI_SHIFT(x)     (x)
 119 #endif
 120
 121 #define E8390_CMD       EI_SHIFT(0x00)  /* The command register (for all pages) */
 122 /* Page 0 register offsets. */
 123 #define EN0_CLDALO      EI_SHIFT(0x01)  /* Low byte of current local dma addr  RD */
 124 #define EN0_STARTPG     EI_SHIFT(0x01)  /* Starting page of ring bfr WR */
 125 #define EN0_CLDAHI      EI_SHIFT(0x02)  /* High byte of current local dma addr  RD */
 126 #define EN0_STOPPG      EI_SHIFT(0x02)  /* Ending page +1 of ring bfr WR */
 127 #define EN0_BOUNDARY    EI_SHIFT(0x03)  /* Boundary page of ring bfr RD WR */
 128 #define EN0_TSR         EI_SHIFT(0x04)  /* Transmit status reg RD */
 129 #define EN0_TPSR        EI_SHIFT(0x04)  /* Transmit starting page WR */
 130 #define EN0_NCR         EI_SHIFT(0x05)  /* Number of collision reg RD */
 131 #define EN0_TCNTLO      EI_SHIFT(0x05)  /* Low  byte of tx byte count WR */
 132 #define EN0_FIFO        EI_SHIFT(0x06)  /* FIFO RD */
 133 #define EN0_TCNTHI      EI_SHIFT(0x06)  /* High byte of tx byte count WR */
 134 #define EN0_ISR         EI_SHIFT(0x07)  /* Interrupt status reg RD WR */
 135 #define EN0_CRDALO      EI_SHIFT(0x08)  /* low byte of current remote dma address RD */
 136 #define EN0_RSARLO      EI_SHIFT(0x08)  /* Remote start address reg 0 */
 137 #define EN0_CRDAHI      EI_SHIFT(0x09)  /* high byte, current remote dma address RD */
 138 #define EN0_RSARHI      EI_SHIFT(0x09)  /* Remote start address reg 1 */
 139 #define EN0_RCNTLO      EI_SHIFT(0x0a)  /* Remote byte count reg WR */
 140 #define EN0_RCNTHI      EI_SHIFT(0x0b)  /* Remote byte count reg WR */
 141 #define EN0_RSR         EI_SHIFT(0x0c)  /* rx status reg RD */
 142 #define EN0_RXCR        EI_SHIFT(0x0c)  /* RX configuration reg WR */
 143 #define EN0_TXCR        EI_SHIFT(0x0d)  /* TX configuration reg WR */
 144 #define EN0_COUNTER0    EI_SHIFT(0x0d)  /* Rcv alignment error counter RD */
 145 #define EN0_DCFG        EI_SHIFT(0x0e)  /* Data configuration reg WR */
 146 #define EN0_COUNTER1    EI_SHIFT(0x0e)  /* Rcv CRC error counter RD */
 147 #define EN0_IMR         EI_SHIFT(0x0f)  /* Interrupt mask reg WR */
 148 #define EN0_COUNTER2    EI_SHIFT(0x0f)  /* Rcv missed frame error counter RD */
 149
 150 /* Bits in EN0_ISR - Interrupt status register */
 151 #define ENISR_RX        0x01    /* Receiver, no error */
 152 #define ENISR_TX        0x02    /* Transmitter, no error */
 153 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
 154 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
 155 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
 156 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
 157 #define ENISR_RDC       0x40    /* remote dma complete */
 158 #define ENISR_RESET     0x80    /* Reset completed */
 159 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
 160
 161 /* Bits in EN0_DCFG - Data config register */
 162 #define ENDCFG_WTS      0x01    /* word transfer mode selection */
 163 #define ENDCFG_BOS      0x02    /* byte order selection */
 164
 165 /* Page 1 register offsets. */
 166 #define EN1_PHYS   EI_SHIFT(0x01)       /* This board's physical enet addr RD WR */
 167 #define EN1_PHYS_SHIFT(i)  EI_SHIFT(i+1) /* Get and set mac address */
 168 #define EN1_CURPAG EI_SHIFT(0x07)       /* Current memory page RD WR */
 169 #define EN1_MULT   EI_SHIFT(0x08)       /* Multicast filter mask array (8 bytes) RD WR */
 170 #define EN1_MULT_SHIFT(i)  EI_SHIFT(8+i) /* Get and set multicast filter */
 171
 172 /* Bits in received packet status byte and EN0_RSR*/
 173 #define ENRSR_RXOK      0x01    /* Received a good packet */
 174 #define ENRSR_CRC       0x02    /* CRC error */
 175 #define ENRSR_FAE       0x04    /* frame alignment error */
 176 #define ENRSR_FO        0x08    /* FIFO overrun */
 177 #define ENRSR_MPA       0x10    /* missed pkt */
 178 #define ENRSR_PHY       0x20    /* physical/multicast address */
 179 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
 180 #define ENRSR_DEF       0x80    /* deferring */
 181
 182 /* Transmitted packet status, EN0_TSR. */
 183 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
 184 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
 185 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 186 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 187 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 188 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 189 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 190 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 191
 192 #endif /* _8390_h */