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[media] v4l2-ctrls: queryctrl shouldn't attempt to replace V4L2_CID_PRIVATE_BASE IDs
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / rtl8712 / rtl871x_mp.c
blob427467cb10bde866f449cc6c2d53dfadc7204241
1 /******************************************************************************
2 * rtl871x_mp.c
3 *
4 * Description :
5 *
6 * Author :
7 *
8 * History :
9 *
10 * Copyright 2007, Realtek Corp.
11 *
12 * The contents of this file is the sole property of Realtek Corp. It can not be
13 * be used, copied or modified without written permission from Realtek Corp.
14 *
15 *******************************************************************************/
16 #define _RTL871X_MP_C_
17
18 #include "osdep_service.h"
19 #include "drv_types.h"
20 #include "rtl871x_mp_phy_regdef.h"
21 #include "rtl8712_cmd.h"
22
23 static void _init_mp_priv_(struct mp_priv *pmp_priv)
24 {
25 pmp_priv->mode = _LOOPBOOK_MODE_;
26 pmp_priv->curr_ch = 1;
27 pmp_priv->curr_modem = MIXED_PHY;
28 pmp_priv->curr_rateidx = 0;
29 pmp_priv->curr_txpoweridx = 0x14;
30 pmp_priv->antenna_tx = ANTENNA_A;
31 pmp_priv->antenna_rx = ANTENNA_AB;
32 pmp_priv->check_mp_pkt = 0;
33 pmp_priv->tx_pktcount = 0;
34 pmp_priv->rx_pktcount = 0;
35 pmp_priv->rx_crcerrpktcount = 0;
36 }
37
38 static int init_mp_priv(struct mp_priv *pmp_priv)
39 {
40 int i, res;
41 struct mp_xmit_frame *pmp_xmitframe;
42
43 _init_mp_priv_(pmp_priv);
44 _init_queue(&pmp_priv->free_mp_xmitqueue);
45 pmp_priv->pallocated_mp_xmitframe_buf = NULL;
46 pmp_priv->pallocated_mp_xmitframe_buf = _malloc(NR_MP_XMITFRAME *
47 sizeof(struct mp_xmit_frame) + 4);
48 if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) {
49 res = _FAIL;
50 goto _exit_init_mp_priv;
51 }
52 pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf +
53 4 -
54 ((addr_t)(pmp_priv->pallocated_mp_xmitframe_buf) & 3);
55 pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf;
56 for (i = 0; i < NR_MP_XMITFRAME; i++) {
57 _init_listhead(&(pmp_xmitframe->list));
58 list_insert_tail(&(pmp_xmitframe->list),
59 &(pmp_priv->free_mp_xmitqueue.queue));
60 pmp_xmitframe->pkt = NULL;
61 pmp_xmitframe->frame_tag = MP_FRAMETAG;
62 pmp_xmitframe->padapter = pmp_priv->papdater;
63 pmp_xmitframe++;
64 }
65 pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
66 res = _SUCCESS;
67 _exit_init_mp_priv:
68 return res;
69 }
70
71 static int free_mp_priv(struct mp_priv *pmp_priv)
72 {
73 int res = 0;
74 kfree(pmp_priv->pallocated_mp_xmitframe_buf);
75 return res;
76 }
77
78 void mp871xinit(struct _adapter *padapter)
79 {
80 struct mp_priv *pmppriv = &padapter->mppriv;
81
82 pmppriv->papdater = padapter;
83 init_mp_priv(pmppriv);
84 }
85
86 void mp871xdeinit(struct _adapter *padapter)
87 {
88 struct mp_priv *pmppriv = &padapter->mppriv;
89
90 free_mp_priv(pmppriv);
91 }
92
93 /*
94 * Special for bb and rf reg read/write
95 */
96 static u32 fw_iocmd_read(struct _adapter *pAdapter, struct IOCMD_STRUCT iocmd)
97 {
98 u32 cmd32 = 0, val32 = 0;
99 u8 iocmd_class = iocmd.cmdclass;
100 u16 iocmd_value = iocmd.value;
101 u8 iocmd_idx = iocmd.index;
102
103 cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx ;
104 if (r8712_fw_cmd(pAdapter, cmd32))
105 r8712_fw_cmd_data(pAdapter, &val32, 1);
106 else
107 val32 = 0;
108 return val32;
109 }
110
111 static u8 fw_iocmd_write(struct _adapter *pAdapter,
112 struct IOCMD_STRUCT iocmd, u32 value)
113 {
114 u32 cmd32 = 0;
115 u8 iocmd_class = iocmd.cmdclass;
116 u32 iocmd_value = iocmd.value;
117 u8 iocmd_idx = iocmd.index;
118
119 r8712_fw_cmd_data(pAdapter, &value, 0);
120 msleep(100);
121 cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx ;
122 return r8712_fw_cmd(pAdapter, cmd32);
123 }
124
125 /* offset : 0X800~0XFFF */
126 u32 r8712_bb_reg_read(struct _adapter *pAdapter, u16 offset)
127 {
128 u8 shift = offset & 0x0003; /* 4 byte access */
129 u16 bb_addr = offset & 0x0FFC; /* 4 byte access */
130 u32 bb_val = 0;
131 struct IOCMD_STRUCT iocmd;
132
133 iocmd.cmdclass = IOCMD_CLASS_BB_RF;
134 iocmd.value = bb_addr;
135 iocmd.index = IOCMD_BB_READ_IDX;
136 bb_val = fw_iocmd_read(pAdapter, iocmd);
137 if (shift != 0) {
138 u32 bb_val2 = 0;
139 bb_val >>= (shift * 8);
140 iocmd.value += 4;
141 bb_val2 = fw_iocmd_read(pAdapter, iocmd);
142 bb_val2 <<= ((4 - shift) * 8);
143 bb_val |= bb_val2;
144 }
145 return bb_val;
146 }
147
148 /* offset : 0X800~0XFFF */
149 u8 r8712_bb_reg_write(struct _adapter *pAdapter, u16 offset, u32 value)
150 {
151 u8 shift = offset & 0x0003; /* 4 byte access */
152 u16 bb_addr = offset & 0x0FFC; /* 4 byte access */
153 struct IOCMD_STRUCT iocmd;
154
155 iocmd.cmdclass = IOCMD_CLASS_BB_RF;
156 iocmd.value = bb_addr;
157 iocmd.index = IOCMD_BB_WRITE_IDX;
158 if (shift != 0) {
159 u32 oldValue = 0;
160 u32 newValue = value;
161
162 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
163 oldValue &= (0xFFFFFFFF >> ((4 - shift) * 8));
164 value = oldValue | (newValue << (shift * 8));
165 if (fw_iocmd_write(pAdapter, iocmd, value) == false)
166 return false;
167 iocmd.value += 4;
168 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
169 oldValue &= (0xFFFFFFFF << (shift * 8));
170 value = oldValue | (newValue >> ((4 - shift) * 8));
171 }
172 return fw_iocmd_write(pAdapter, iocmd, value);
173 }
174
175 /* offset : 0x00 ~ 0xFF */
176 u32 r8712_rf_reg_read(struct _adapter *pAdapter, u8 path, u8 offset)
177 {
178 u16 rf_addr = (path << 8) | offset;
179 u32 rf_data;
180 struct IOCMD_STRUCT iocmd;
181
182 iocmd.cmdclass = IOCMD_CLASS_BB_RF ;
183 iocmd.value = rf_addr ;
184 iocmd.index = IOCMD_RF_READ_IDX;
185 rf_data = fw_iocmd_read(pAdapter, iocmd);
186 return rf_data;
187 }
188
189 u8 r8712_rf_reg_write(struct _adapter *pAdapter, u8 path, u8 offset, u32 value)
190 {
191 u16 rf_addr = (path << 8) | offset;
192 struct IOCMD_STRUCT iocmd;
193
194 iocmd.cmdclass = IOCMD_CLASS_BB_RF;
195 iocmd.value = rf_addr;
196 iocmd.index = IOCMD_RF_WRIT_IDX;
197 return fw_iocmd_write(pAdapter, iocmd, value);
198 }
199
200 static u32 bitshift(u32 bitmask)
201 {
202 u32 i;
203
204 for (i = 0; i <= 31; i++)
205 if (((bitmask>>i) & 0x1) == 1)
206 break;
207 return i;
208 }
209
210 static u32 get_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask)
211 {
212 u32 org_value, bit_shift, new_value;
213
214 org_value = r8712_bb_reg_read(pAdapter, offset);
215 bit_shift = bitshift(bitmask);
216 new_value = (org_value & bitmask) >> bit_shift;
217 return new_value;
218 }
219
220 static u8 set_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask, u32 value)
221 {
222 u32 org_value, bit_shift, new_value;
223
224 if (bitmask != bMaskDWord) {
225 org_value = r8712_bb_reg_read(pAdapter, offset);
226 bit_shift = bitshift(bitmask);
227 new_value = ((org_value & (~bitmask)) | (value << bit_shift));
228 } else
229 new_value = value;
230 return r8712_bb_reg_write(pAdapter, offset, new_value);
231 }
232
233 static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset,
234 u32 bitmask)
235 {
236 u32 org_value, bit_shift, new_value;
237
238 org_value = r8712_rf_reg_read(pAdapter, path, offset);
239 bit_shift = bitshift(bitmask);
240 new_value = (org_value & bitmask) >> bit_shift;
241 return new_value;
242 }
243
244 static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask,
245 u32 value)
246 {
247 u32 org_value, bit_shift, new_value;
248
249 if (bitmask != bMaskDWord) {
250 org_value = r8712_rf_reg_read(pAdapter, path, offset);
251 bit_shift = bitshift(bitmask);
252 new_value = ((org_value & (~bitmask)) | (value << bit_shift));
253 } else
254 new_value = value;
255 return r8712_rf_reg_write(pAdapter, path, offset, new_value);
256 }
257
258 /*
259 * SetChannel
260 * Description
261 * Use H2C command to change channel,
262 * not only modify rf register, but also other setting need to be done.
263 */
264 void r8712_SetChannel(struct _adapter *pAdapter)
265 {
266 struct cmd_priv *pcmdpriv = &pAdapter->cmdpriv;
267 struct cmd_obj *pcmd = NULL;
268 struct SetChannel_parm *pparm = NULL;
269 u16 code = GEN_CMD_CODE(_SetChannel);
270
271 pcmd = (struct cmd_obj *)_malloc(sizeof(struct cmd_obj));
272 if (pcmd == NULL)
273 return;
274 pparm = (struct SetChannel_parm *)_malloc(sizeof(struct
275 SetChannel_parm));
276 if (pparm == NULL) {
277 if (pcmd != NULL)
278 kfree((u8 *)pcmd);
279 return;
280 }
281 pparm->curr_ch = pAdapter->mppriv.curr_ch;
282 init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code);
283 r8712_enqueue_cmd(pcmdpriv, pcmd);
284 }
285
286 static void SetCCKTxPower(struct _adapter *pAdapter, u8 TxPower)
287 {
288 u16 TxAGC = 0;
289
290 TxAGC = TxPower;
291 set_bb_reg(pAdapter, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
292 }
293
294 static void SetOFDMTxPower(struct _adapter *pAdapter, u8 TxPower)
295 {
296 u32 TxAGC = 0;
297
298 TxAGC |= ((TxPower<<24)|(TxPower<<16)|(TxPower<<8)|TxPower);
299 set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC);
300 set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC);
301 set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC);
302 set_bb_reg(pAdapter, rTxAGC_Mcs07_Mcs04, bTxAGCRateMCS7_MCS4, TxAGC);
303 set_bb_reg(pAdapter, rTxAGC_Mcs11_Mcs08, bTxAGCRateMCS11_MCS8, TxAGC);
304 set_bb_reg(pAdapter, rTxAGC_Mcs15_Mcs12, bTxAGCRateMCS15_MCS12, TxAGC);
305 }
306
307 void r8712_SetTxPower(struct _adapter *pAdapter)
308 {
309 u8 TxPower = pAdapter->mppriv.curr_txpoweridx;
310 SetCCKTxPower(pAdapter, TxPower);
311 SetOFDMTxPower(pAdapter, TxPower);
312 }
313
314 void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset)
315 {
316 u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
317
318 TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);
319 TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);
320 TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);
321 tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);
322 set_bb_reg(pAdapter, rFPGA0_TxGainStage,
323 (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);
324 }
325
326 void r8712_SetDataRate(struct _adapter *pAdapter)
327 {
328 u8 path = RF_PATH_A;
329 u8 offset = RF_SYN_G2;
330 u32 value;
331
332 value = (pAdapter->mppriv.curr_rateidx < 4) ? 0x4440 : 0xF200;
333 r8712_rf_reg_write(pAdapter, path, offset, value);
334 }
335
336 void r8712_SwitchBandwidth(struct _adapter *pAdapter)
337 {
338 /* 3 1.Set MAC register : BWOPMODE bit2:1 20MhzBW */
339 u8 regBwOpMode = 0;
340 u8 Bandwidth = pAdapter->mppriv.curr_bandwidth;
341
342 regBwOpMode = r8712_read8(pAdapter, 0x10250203);
343 if (Bandwidth == HT_CHANNEL_WIDTH_20)
344 regBwOpMode |= BIT(2);
345 else
346 regBwOpMode &= ~(BIT(2));
347 r8712_write8(pAdapter, 0x10250203, regBwOpMode);
348 /* 3 2.Set PHY related register */
349 switch (Bandwidth) {
350 /* 20 MHz channel*/
351 case HT_CHANNEL_WIDTH_20:
352 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0);
353 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x0);
354 /* Use PHY_REG.txt default value. Do not need to change.
355 * Correct the tx power for CCK rate in 40M.
356 * It is set in Tx descriptor for 8192x series
357 */
358 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x58);
359 break;
360 /* 40 MHz channel*/
361 case HT_CHANNEL_WIDTH_40:
362 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1);
363 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x1);
364 /* Use PHY_REG.txt default value. Do not need to change.
365 * Correct the tx power for CCK rate in 40M.
366 * Set Control channel to upper or lower. These settings are
367 * required only for 40MHz */
368 set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand,
369 (HAL_PRIME_CHNL_OFFSET_DONT_CARE>>1));
370 set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00,
371 HAL_PRIME_CHNL_OFFSET_DONT_CARE);
372 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18);
373 break;
374 default:
375 break;
376 }
377
378 /* 3 3.Set RF related register */
379 switch (Bandwidth) {
380 case HT_CHANNEL_WIDTH_20:
381 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
382 BIT(10) | BIT(11), 0x01);
383 break;
384 case HT_CHANNEL_WIDTH_40:
385 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
386 BIT(10) | BIT(11), 0x00);
387 break;
388 default:
389 break;
390 }
391 }
392 /*------------------------------Define structure----------------------------*/
393 struct R_ANTENNA_SELECT_OFDM {
394 u32 r_tx_antenna:4;
395 u32 r_ant_l:4;
396 u32 r_ant_non_ht:4;
397 u32 r_ant_ht1:4;
398 u32 r_ant_ht2:4;
399 u32 r_ant_ht_s1:4;
400 u32 r_ant_non_ht_s1:4;
401 u32 OFDM_TXSC:2;
402 u32 Reserved:2;
403 };
404
405 struct R_ANTENNA_SELECT_CCK {
406 u8 r_cckrx_enable_2:2;
407 u8 r_cckrx_enable:2;
408 u8 r_ccktx_enable:4;
409 };
410
411 void r8712_SwitchAntenna(struct _adapter *pAdapter)
412 {
413 u32 ofdm_tx_en_val = 0, ofdm_tx_ant_sel_val = 0;
414 u8 ofdm_rx_ant_sel_val = 0;
415 u8 cck_ant_select_val = 0;
416 u32 cck_ant_sel_val = 0;
417 struct R_ANTENNA_SELECT_CCK *p_cck_txrx;
418
419 p_cck_txrx = (struct R_ANTENNA_SELECT_CCK *)&cck_ant_select_val;
420
421 switch (pAdapter->mppriv.antenna_tx) {
422 case ANTENNA_A:
423 /* From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
424 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
425 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
426 ofdm_tx_en_val = 0x3;
427 ofdm_tx_ant_sel_val = 0x11111111;/* Power save */
428 p_cck_txrx->r_ccktx_enable = 0x8;
429 break;
430 case ANTENNA_B:
431 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
432 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
433 ofdm_tx_en_val = 0x3;
434 ofdm_tx_ant_sel_val = 0x22222222;/* Power save */
435 p_cck_txrx->r_ccktx_enable = 0x4;
436 break;
437 case ANTENNA_AB: /* For 8192S */
438 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
439 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
440 ofdm_tx_en_val = 0x3;
441 ofdm_tx_ant_sel_val = 0x3321333; /* Disable Power save */
442 p_cck_txrx->r_ccktx_enable = 0xC;
443 break;
444 default:
445 break;
446 }
447 /*OFDM Tx*/
448 set_bb_reg(pAdapter, rFPGA1_TxInfo, 0xffffffff, ofdm_tx_ant_sel_val);
449 /*OFDM Tx*/
450 set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, ofdm_tx_en_val);
451 switch (pAdapter->mppriv.antenna_rx) {
452 case ANTENNA_A:
453 ofdm_rx_ant_sel_val = 0x1; /* A */
454 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
455 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
456 break;
457 case ANTENNA_B:
458 ofdm_rx_ant_sel_val = 0x2; /* B */
459 p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
460 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
461 break;
462 case ANTENNA_AB:
463 ofdm_rx_ant_sel_val = 0x3; /* AB */
464 p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
465 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
466 break;
467 default:
468 break;
469 }
470 /*OFDM Rx*/
471 set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f,
472 ofdm_rx_ant_sel_val);
473 /*OFDM Rx*/
474 set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f,
475 ofdm_rx_ant_sel_val);
476
477 cck_ant_sel_val = cck_ant_select_val;
478 /*CCK TxRx*/
479 set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val);
480 }
481
482 void r8712_SetCrystalCap(struct _adapter *pAdapter)
483 {
484 set_bb_reg(pAdapter, rFPGA0_AnalogParameter1, bXtalCap,
485 pAdapter->mppriv.curr_crystalcap);
486 }
487
488 static void TriggerRFThermalMeter(struct _adapter *pAdapter)
489 {
490 /* 0x24: RF Reg[6:5] */
491 set_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
492 }
493
494 static u32 ReadRFThermalMeter(struct _adapter *pAdapter)
495 {
496 u32 ThermalValue = 0;
497
498 /* 0x24: RF Reg[4:0] */
499 ThermalValue = get_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F);
500 return ThermalValue;
501 }
502
503 void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value)
504 {
505 TriggerRFThermalMeter(pAdapter);
506 msleep(1000);
507 *value = ReadRFThermalMeter(pAdapter);
508 }
509
510 void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart)
511 {
512 if (bStart) { /* Start Single Carrier. */
513 /* 1. if OFDM block on? */
514 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
515 /*set OFDM block on*/
516 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
517 /* 2. set CCK test mode off, set to CCK normal mode */
518 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
519 /* 3. turn on scramble setting */
520 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
521 /* 4. Turn On Single Carrier Tx and off the other test modes. */
522 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
523 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
524 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
525 } else { /* Stop Single Carrier.*/
526 /* Turn off all test modes.*/
527 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
528 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
529 bDisable);
530 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
531 msleep(20);
532 /*BB Reset*/
533 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
534 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
535 }
536 }
537
538 void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart)
539 {
540 u8 rfPath = pAdapter->mppriv.curr_rfpath;
541 switch (pAdapter->mppriv.antenna_tx) {
542 case ANTENNA_B:
543 rfPath = RF_PATH_B;
544 break;
545 case ANTENNA_A:
546 default:
547 rfPath = RF_PATH_A;
548 break;
549 }
550 if (bStart) { /* Start Single Tone.*/
551 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable);
552 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable);
553 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
554 0xd4000);
555 msleep(100);
556 /* PAD all on.*/
557 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x2001f);
558 msleep(100);
559 } else { /* Stop Single Tone.*/
560 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
561 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
562 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
563 0x54000);
564 msleep(100);
565 /* PAD all on.*/
566 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x30000);
567 msleep(100);
568 }
569 }
570
571 void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart)
572 {
573 if (bStart) { /* Start Carrier Suppression.*/
574 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
575 /* 1. if CCK block on? */
576 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
577 /*set CCK block on*/
578 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn,
579 bEnable);
580 }
581 /* Turn Off All Test Mode */
582 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx,
583 bDisable);
584 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
585 bDisable);
586 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone,
587 bDisable);
588 /*transmit mode*/
589 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
590 /*turn off scramble setting*/
591 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
592 bDisable);
593 /*Set CCK Tx Test Rate*/
594 /*Set FTxRate to 1Mbps*/
595 set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);
596 }
597 } else { /* Stop Carrier Suppression. */
598 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
599 /*normal mode*/
600 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
601 /*turn on scramble setting*/
602 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
603 bEnable);
604 /*BB Reset*/
605 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
606 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
607 }
608 }
609 }
610
611 static void SetCCKContinuousTx(struct _adapter *pAdapter, u8 bStart)
612 {
613 u32 cckrate;
614
615 if (bStart) {
616 /* 1. if CCK block on? */
617 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
618 /*set CCK block on*/
619 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
620 }
621 /* Turn Off All Test Mode */
622 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
623 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
624 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
625 /*Set CCK Tx Test Rate*/
626 cckrate = pAdapter->mppriv.curr_rateidx;
627 set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
628 /*transmit mode*/
629 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
630 /*turn on scramble setting*/
631 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
632 } else {
633 /*normal mode*/
634 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
635 /*turn on scramble setting*/
636 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
637 /*BB Reset*/
638 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
639 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
640 }
641 } /* mpt_StartCckContTx */
642
643 static void SetOFDMContinuousTx(struct _adapter *pAdapter, u8 bStart)
644 {
645 if (bStart) {
646 /* 1. if OFDM block on? */
647 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) {
648 /*set OFDM block on*/
649 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
650 }
651 /* 2. set CCK test mode off, set to CCK normal mode*/
652 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
653 /* 3. turn on scramble setting */
654 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
655 /* 4. Turn On Continue Tx and turn off the other test modes.*/
656 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
657 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
658 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
659 } else {
660 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
661 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
662 bDisable);
663 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
664 msleep(20);
665 /*BB Reset*/
666 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
667 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
668 }
669 } /* mpt_StartOfdmContTx */
670
671 void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart)
672 {
673 /* ADC turn off [bit24-21] adc port0 ~ port1 */
674 if (bStart) {
675 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
676 r8712_bb_reg_read(pAdapter,
677 rRx_Wait_CCCA) & 0xFE1FFFFF);
678 msleep(100);
679 }
680 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M)
681 SetCCKContinuousTx(pAdapter, bStart);
682 else if ((pAdapter->mppriv.curr_rateidx >= MPT_RATE_6M) &&
683 (pAdapter->mppriv.curr_rateidx <= MPT_RATE_MCS15))
684 SetOFDMContinuousTx(pAdapter, bStart);
685 /* ADC turn on [bit24-21] adc port0 ~ port1 */
686 if (!bStart)
687 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
688 r8712_bb_reg_read(pAdapter,
689 rRx_Wait_CCCA) | 0x01E00000);
690 }
691
692 void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter)
693 {
694 u32 i, phyrx_set = 0;
695
696 for (i = OFDM_PPDU_BIT; i <= HT_MPDU_FAIL_BIT; i++) {
697 phyrx_set = 0;
698 phyrx_set |= (i << 28); /*select*/
699 phyrx_set |= 0x08000000; /* set counter to zero*/
700 r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
701 }
702 }
703
704 static u32 GetPhyRxPktCounts(struct _adapter *pAdapter, u32 selbit)
705 {
706 /*selection*/
707 u32 phyrx_set = 0, count = 0;
708 u32 SelectBit;
709
710 SelectBit = selbit << 28;
711 phyrx_set |= (SelectBit & 0xF0000000);
712 r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
713 /*Read packet count*/
714 count = r8712_read32(pAdapter, RXERR_RPT) & RPTMaxCount;
715 return count;
716 }
717
718 u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter)
719 {
720 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
721
722 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_OK_BIT);
723 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_OK_BIT);
724 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_OK_BIT);
725 return OFDM_cnt + CCK_cnt + HT_cnt;
726 }
727
728 u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter)
729 {
730 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
731
732 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_FAIL_BIT);
733 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_FAIL_BIT);
734 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_FAIL_BIT);
735 return OFDM_cnt + CCK_cnt + HT_cnt;
736 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree