arch/arm/mach-mx3/mach-pcm043.c

   1 /*
   2  *  Copyright (C) 2009 Sascha Hauer, Pengutronix
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/types.h>
  16 #include <linux/init.h>
  17
  18 #include <linux/platform_device.h>
  19 #include <linux/mtd/physmap.h>
  20 #include <linux/mtd/plat-ram.h>
  21 #include <linux/memory.h>
  22 #include <linux/gpio.h>
  23 #include <linux/smc911x.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/i2c.h>
  27 #include <linux/i2c/at24.h>
  28 #include <linux/usb/otg.h>
  29 #include <linux/usb/ulpi.h>
  30
  31 #include <asm/mach-types.h>
  32 #include <asm/mach/arch.h>
  33 #include <asm/mach/time.h>
  34 #include <asm/mach/map.h>
  35
  36 #include <mach/hardware.h>
  37 #include <mach/common.h>
  38 #include <mach/iomux-mx35.h>
  39 #include <mach/ipu.h>
  40 #include <mach/mx3fb.h>
  41 #include <mach/ulpi.h>
  42 #include <mach/audmux.h>
  43 #include <mach/esdhc.h>
  44
  45 #include "devices-imx35.h"
  46 #include "devices.h"
  47
  48 static const struct fb_videomode fb_modedb[] = {
  49         {
  50                 /* 240x320 @ 60 Hz */
  51                 .name           = "Sharp-LQ035Q7",
  52                 .refresh        = 60,
  53                 .xres           = 240,
  54                 .yres           = 320,
  55                 .pixclock       = 185925,
  56                 .left_margin    = 9,
  57                 .right_margin   = 16,
  58                 .upper_margin   = 7,
  59                 .lower_margin   = 9,
  60                 .hsync_len      = 1,
  61                 .vsync_len      = 1,
  62                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
  63                 .vmode          = FB_VMODE_NONINTERLACED,
  64                 .flag           = 0,
  65         }, {
  66                 /* 240x320 @ 60 Hz */
  67                 .name           = "TX090",
  68                 .refresh        = 60,
  69                 .xres           = 240,
  70                 .yres           = 320,
  71                 .pixclock       = 38255,
  72                 .left_margin    = 144,
  73                 .right_margin   = 0,
  74                 .upper_margin   = 7,
  75                 .lower_margin   = 40,
  76                 .hsync_len      = 96,
  77                 .vsync_len      = 1,
  78                 .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
  79                 .vmode          = FB_VMODE_NONINTERLACED,
  80                 .flag           = 0,
  81         },
  82 };
  83
  84 static struct ipu_platform_data mx3_ipu_data = {
  85         .irq_base = MXC_IPU_IRQ_START,
  86 };
  87
  88 static struct mx3fb_platform_data mx3fb_pdata = {
  89         .dma_dev        = &mx3_ipu.dev,
  90         .name           = "Sharp-LQ035Q7",
  91         .mode           = fb_modedb,
  92         .num_modes      = ARRAY_SIZE(fb_modedb),
  93 };
  94
  95 static struct physmap_flash_data pcm043_flash_data = {
  96         .width  = 2,
  97 };
  98
  99 static struct resource pcm043_flash_resource = {
 100         .start  = 0xa0000000,
 101         .end    = 0xa1ffffff,
 102         .flags  = IORESOURCE_MEM,
 103 };
 104
 105 static struct platform_device pcm043_flash = {
 106         .name   = "physmap-flash",
 107         .id     = 0,
 108         .dev    = {
 109                 .platform_data  = &pcm043_flash_data,
 110         },
 111         .resource = &pcm043_flash_resource,
 112         .num_resources = 1,
 113 };
 114
 115 static const struct imxuart_platform_data uart_pdata __initconst = {
 116         .flags = IMXUART_HAVE_RTSCTS,
 117 };
 118
 119 static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
 120         .bitrate = 50000,
 121 };
 122
 123 static struct at24_platform_data board_eeprom = {
 124         .byte_len = 4096,
 125         .page_size = 32,
 126         .flags = AT24_FLAG_ADDR16,
 127 };
 128
 129 static struct i2c_board_info pcm043_i2c_devices[] = {
 130        {
 131                 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
 132                 .platform_data = &board_eeprom,
 133         }, {
 134                 I2C_BOARD_INFO("pcf8563", 0x51),
 135         }
 136 };
 137
 138 static struct platform_device *devices[] __initdata = {
 139         &pcm043_flash,
 140 };
 141
 142 static iomux_v3_cfg_t pcm043_pads[] = {
 143         /* UART1 */
 144         MX35_PAD_CTS1__UART1_CTS,
 145         MX35_PAD_RTS1__UART1_RTS,
 146         MX35_PAD_TXD1__UART1_TXD_MUX,
 147         MX35_PAD_RXD1__UART1_RXD_MUX,
 148         /* UART2 */
 149         MX35_PAD_CTS2__UART2_CTS,
 150         MX35_PAD_RTS2__UART2_RTS,
 151         MX35_PAD_TXD2__UART2_TXD_MUX,
 152         MX35_PAD_RXD2__UART2_RXD_MUX,
 153         /* FEC */
 154         MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
 155         MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
 156         MX35_PAD_FEC_RX_DV__FEC_RX_DV,
 157         MX35_PAD_FEC_COL__FEC_COL,
 158         MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
 159         MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
 160         MX35_PAD_FEC_TX_EN__FEC_TX_EN,
 161         MX35_PAD_FEC_MDC__FEC_MDC,
 162         MX35_PAD_FEC_MDIO__FEC_MDIO,
 163         MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
 164         MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
 165         MX35_PAD_FEC_CRS__FEC_CRS,
 166         MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
 167         MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
 168         MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
 169         MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
 170         MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
 171         MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
 172         /* I2C1 */
 173         MX35_PAD_I2C1_CLK__I2C1_SCL,
 174         MX35_PAD_I2C1_DAT__I2C1_SDA,
 175         /* Display */
 176         MX35_PAD_LD0__IPU_DISPB_DAT_0,
 177         MX35_PAD_LD1__IPU_DISPB_DAT_1,
 178         MX35_PAD_LD2__IPU_DISPB_DAT_2,
 179         MX35_PAD_LD3__IPU_DISPB_DAT_3,
 180         MX35_PAD_LD4__IPU_DISPB_DAT_4,
 181         MX35_PAD_LD5__IPU_DISPB_DAT_5,
 182         MX35_PAD_LD6__IPU_DISPB_DAT_6,
 183         MX35_PAD_LD7__IPU_DISPB_DAT_7,
 184         MX35_PAD_LD8__IPU_DISPB_DAT_8,
 185         MX35_PAD_LD9__IPU_DISPB_DAT_9,
 186         MX35_PAD_LD10__IPU_DISPB_DAT_10,
 187         MX35_PAD_LD11__IPU_DISPB_DAT_11,
 188         MX35_PAD_LD12__IPU_DISPB_DAT_12,
 189         MX35_PAD_LD13__IPU_DISPB_DAT_13,
 190         MX35_PAD_LD14__IPU_DISPB_DAT_14,
 191         MX35_PAD_LD15__IPU_DISPB_DAT_15,
 192         MX35_PAD_LD16__IPU_DISPB_DAT_16,
 193         MX35_PAD_LD17__IPU_DISPB_DAT_17,
 194         MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
 195         MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
 196         MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
 197         MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
 198         MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
 199         MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
 200         MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
 201         /* gpio */
 202         MX35_PAD_ATA_CS0__GPIO2_6,
 203         /* USB host */
 204         MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
 205         MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
 206         /* SSI */
 207         MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
 208         MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
 209         MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
 210         MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
 211         /* CAN2 */
 212         MX35_PAD_TX5_RX0__CAN2_TXCAN,
 213         MX35_PAD_TX4_RX1__CAN2_RXCAN,
 214         /* esdhc */
 215         MX35_PAD_SD1_CMD__ESDHC1_CMD,
 216         MX35_PAD_SD1_CLK__ESDHC1_CLK,
 217         MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
 218         MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
 219         MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
 220         MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 221         MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */
 222         MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */
 223 };
 224
 225 #define AC97_GPIO_TXFS  IMX_GPIO_NR(2, 31)
 226 #define AC97_GPIO_TXD   IMX_GPIO_NR(2, 28)
 227 #define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
 228 #define SD1_GPIO_WP     IMX_GPIO_NR(2, 23)
 229 #define SD1_GPIO_CD     IMX_GPIO_NR(2, 24)
 230
 231 static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
 232 {
 233         iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
 234         iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
 235         int ret;
 236
 237         ret = gpio_request(AC97_GPIO_TXFS, "SSI");
 238         if (ret) {
 239                 printk("failed to get GPIO_TXFS: %d\n", ret);
 240                 return;
 241         }
 242
 243         mxc_iomux_v3_setup_pad(txfs_gpio);
 244
 245         /* warm reset */
 246         gpio_direction_output(AC97_GPIO_TXFS, 1);
 247         udelay(2);
 248         gpio_set_value(AC97_GPIO_TXFS, 0);
 249
 250         gpio_free(AC97_GPIO_TXFS);
 251         mxc_iomux_v3_setup_pad(txfs);
 252 }
 253
 254 static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
 255 {
 256         iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
 257         iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
 258         iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
 259         iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
 260         iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
 261         int ret;
 262
 263         ret = gpio_request(AC97_GPIO_TXFS, "SSI");
 264         if (ret)
 265                 goto err1;
 266
 267         ret = gpio_request(AC97_GPIO_TXD, "SSI");
 268         if (ret)
 269                 goto err2;
 270
 271         ret = gpio_request(AC97_GPIO_RESET, "SSI");
 272         if (ret)
 273                 goto err3;
 274
 275         mxc_iomux_v3_setup_pad(txfs_gpio);
 276         mxc_iomux_v3_setup_pad(txd_gpio);
 277         mxc_iomux_v3_setup_pad(reset_gpio);
 278
 279         gpio_direction_output(AC97_GPIO_TXFS, 0);
 280         gpio_direction_output(AC97_GPIO_TXD, 0);
 281
 282         /* cold reset */
 283         gpio_direction_output(AC97_GPIO_RESET, 0);
 284         udelay(10);
 285         gpio_direction_output(AC97_GPIO_RESET, 1);
 286
 287         mxc_iomux_v3_setup_pad(txd);
 288         mxc_iomux_v3_setup_pad(txfs);
 289
 290         gpio_free(AC97_GPIO_RESET);
 291 err3:
 292         gpio_free(AC97_GPIO_TXD);
 293 err2:
 294         gpio_free(AC97_GPIO_TXFS);
 295 err1:
 296         if (ret)
 297                 printk("%s failed with %d\n", __func__, ret);
 298         mdelay(1);
 299 }
 300
 301 static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
 302         .ac97_reset = pcm043_ac97_cold_reset,
 303         .ac97_warm_reset = pcm043_ac97_warm_reset,
 304         .flags = IMX_SSI_USE_AC97,
 305 };
 306
 307 static const struct mxc_nand_platform_data
 308 pcm037_nand_board_info __initconst = {
 309         .width = 1,
 310         .hw_ecc = 1,
 311 };
 312
 313 static int pcm043_otg_init(struct platform_device *pdev)
 314 {
 315         return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
 316 }
 317
 318 static struct mxc_usbh_platform_data otg_pdata __initdata = {
 319         .init   = pcm043_otg_init,
 320         .portsc = MXC_EHCI_MODE_UTMI,
 321 };
 322
 323 static int pcm043_usbh1_init(struct platform_device *pdev)
 324 {
 325         return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
 326                         MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
 327 }
 328
 329 static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
 330         .init   = pcm043_usbh1_init,
 331         .portsc = MXC_EHCI_MODE_SERIAL,
 332 };
 333
 334 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
 335         .operating_mode = FSL_USB2_DR_DEVICE,
 336         .phy_mode       = FSL_USB2_PHY_UTMI,
 337 };
 338
 339 static int otg_mode_host;
 340
 341 static int __init pcm043_otg_mode(char *options)
 342 {
 343         if (!strcmp(options, "host"))
 344                 otg_mode_host = 1;
 345         else if (!strcmp(options, "device"))
 346                 otg_mode_host = 0;
 347         else
 348                 pr_info("otg_mode neither \"host\" nor \"device\". "
 349                         "Defaulting to device\n");
 350         return 0;
 351 }
 352 __setup("otg_mode=", pcm043_otg_mode);
 353
 354 static struct esdhc_platform_data sd1_pdata = {
 355         .wp_gpio = SD1_GPIO_WP,
 356         .cd_gpio = SD1_GPIO_CD,
 357 };
 358
 359 /*
 360  * Board specific initialization.
 361  */
 362 static void __init pcm043_init(void)
 363 {
 364         mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
 365
 366         mxc_audmux_v2_configure_port(3,
 367                         MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
 368                         MXC_AUDMUX_V2_PTCR_TFSEL(0) |
 369                         MXC_AUDMUX_V2_PTCR_TFSDIR,
 370                         MXC_AUDMUX_V2_PDCR_RXDSEL(0));
 371
 372         mxc_audmux_v2_configure_port(0,
 373                         MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
 374                         MXC_AUDMUX_V2_PTCR_TCSEL(3) |
 375                         MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
 376                         MXC_AUDMUX_V2_PDCR_RXDSEL(3));
 377
 378         imx35_add_fec(NULL);
 379         platform_add_devices(devices, ARRAY_SIZE(devices));
 380         imx35_add_imx2_wdt(NULL);
 381
 382         imx35_add_imx_uart0(&uart_pdata);
 383         imx35_add_mxc_nand(&pcm037_nand_board_info);
 384         imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
 385
 386         imx35_add_imx_uart1(&uart_pdata);
 387
 388         i2c_register_board_info(0, pcm043_i2c_devices,
 389                         ARRAY_SIZE(pcm043_i2c_devices));
 390
 391         imx35_add_imx_i2c0(&pcm043_i2c0_data);
 392
 393         mxc_register_device(&mx3_ipu, &mx3_ipu_data);
 394         mxc_register_device(&mx3_fb, &mx3fb_pdata);
 395
 396         if (otg_mode_host) {
 397                 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
 398                                 ULPI_OTG_DRVVBUS_EXT);
 399                 if (otg_pdata.otg)
 400                         imx35_add_mxc_ehci_otg(&otg_pdata);
 401         }
 402         imx35_add_mxc_ehci_hs(&usbh1_pdata);
 403
 404         if (!otg_mode_host)
 405                 imx35_add_fsl_usb2_udc(&otg_device_pdata);
 406
 407         imx35_add_flexcan1(NULL);
 408         imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
 409 }
 410
 411 static void __init pcm043_timer_init(void)
 412 {
 413         mx35_clocks_init();
 414 }
 415
 416 struct sys_timer pcm043_timer = {
 417         .init   = pcm043_timer_init,
 418 };
 419
 420 MACHINE_START(PCM043, "Phytec Phycore pcm043")
 421         /* Maintainer: Pengutronix */
 422         .boot_params = MX3x_PHYS_OFFSET + 0x100,
 423         .map_io = mx35_map_io,
 424         .init_early = imx35_init_early,
 425         .init_irq = mx35_init_irq,
 426         .timer = &pcm043_timer,
 427         .init_machine = pcm043_init,
 428 MACHINE_END