arch/arm/include/asm/cacheflush.h

   1 /*
   2  *  arch/arm/include/asm/cacheflush.h
   3  *
   4  *  Copyright (C) 1999-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef _ASMARM_CACHEFLUSH_H
  11 #define _ASMARM_CACHEFLUSH_H
  12
  13 #include <linux/mm.h>
  14
  15 #include <asm/glue.h>
  16 #include <asm/shmparam.h>
  17 #include <asm/cachetype.h>
  18 #include <asm/outercache.h>
  19
  20 #define CACHE_COLOUR(vaddr)     ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
  21
  22 /*
  23  *      Cache Model
  24  *      ===========
  25  */
  26 #undef _CACHE
  27 #undef MULTI_CACHE
  28
  29 #if defined(CONFIG_CPU_CACHE_V3)
  30 # ifdef _CACHE
  31 #  define MULTI_CACHE 1
  32 # else
  33 #  define _CACHE v3
  34 # endif
  35 #endif
  36
  37 #if defined(CONFIG_CPU_CACHE_V4)
  38 # ifdef _CACHE
  39 #  define MULTI_CACHE 1
  40 # else
  41 #  define _CACHE v4
  42 # endif
  43 #endif
  44
  45 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
  46     defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \
  47     defined(CONFIG_CPU_ARM1026)
  48 # define MULTI_CACHE 1
  49 #endif
  50
  51 #if defined(CONFIG_CPU_FA526)
  52 # ifdef _CACHE
  53 #  define MULTI_CACHE 1
  54 # else
  55 #  define _CACHE fa
  56 # endif
  57 #endif
  58
  59 #if defined(CONFIG_CPU_ARM926T)
  60 # ifdef _CACHE
  61 #  define MULTI_CACHE 1
  62 # else
  63 #  define _CACHE arm926
  64 # endif
  65 #endif
  66
  67 #if defined(CONFIG_CPU_ARM940T)
  68 # ifdef _CACHE
  69 #  define MULTI_CACHE 1
  70 # else
  71 #  define _CACHE arm940
  72 # endif
  73 #endif
  74
  75 #if defined(CONFIG_CPU_ARM946E)
  76 # ifdef _CACHE
  77 #  define MULTI_CACHE 1
  78 # else
  79 #  define _CACHE arm946
  80 # endif
  81 #endif
  82
  83 #if defined(CONFIG_CPU_CACHE_V4WB)
  84 # ifdef _CACHE
  85 #  define MULTI_CACHE 1
  86 # else
  87 #  define _CACHE v4wb
  88 # endif
  89 #endif
  90
  91 #if defined(CONFIG_CPU_XSCALE)
  92 # ifdef _CACHE
  93 #  define MULTI_CACHE 1
  94 # else
  95 #  define _CACHE xscale
  96 # endif
  97 #endif
  98
  99 #if defined(CONFIG_CPU_XSC3)
 100 # ifdef _CACHE
 101 #  define MULTI_CACHE 1
 102 # else
 103 #  define _CACHE xsc3
 104 # endif
 105 #endif
 106
 107 #if defined(CONFIG_CPU_MOHAWK)
 108 # ifdef _CACHE
 109 #  define MULTI_CACHE 1
 110 # else
 111 #  define _CACHE mohawk
 112 # endif
 113 #endif
 114
 115 #if defined(CONFIG_CPU_FEROCEON)
 116 # define MULTI_CACHE 1
 117 #endif
 118
 119 #if defined(CONFIG_CPU_V6)
 120 //# ifdef _CACHE
 121 #  define MULTI_CACHE 1
 122 //# else
 123 //#  define _CACHE v6
 124 //# endif
 125 #endif
 126
 127 #if defined(CONFIG_CPU_V7)
 128 //# ifdef _CACHE
 129 #  define MULTI_CACHE 1
 130 //# else
 131 //#  define _CACHE v7
 132 //# endif
 133 #endif
 134
 135 #if !defined(_CACHE) && !defined(MULTI_CACHE)
 136 #error Unknown cache maintainence model
 137 #endif
 138
 139 /*
 140  * This flag is used to indicate that the page pointed to by a pte
 141  * is dirty and requires cleaning before returning it to the user.
 142  */
 143 #define PG_dcache_dirty PG_arch_1
 144
 145 /*
 146  *      MM Cache Management
 147  *      ===================
 148  *
 149  *      The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
 150  *      implement these methods.
 151  *
 152  *      Start addresses are inclusive and end addresses are exclusive;
 153  *      start addresses should be rounded down, end addresses up.
 154  *
 155  *      See Documentation/cachetlb.txt for more information.
 156  *      Please note that the implementation of these, and the required
 157  *      effects are cache-type (VIVT/VIPT/PIPT) specific.
 158  *
 159  *      flush_icache_all()
 160  *
 161  *              Unconditionally clean and invalidate the entire icache.
 162  *              Currently only needed for cache-v6.S and cache-v7.S, see
 163  *              __flush_icache_all for the generic implementation.
 164  *
 165  *      flush_kern_all()
 166  *
 167  *              Unconditionally clean and invalidate the entire cache.
 168  *
 169  *      flush_user_all()
 170  *
 171  *              Clean and invalidate all user space cache entries
 172  *              before a change of page tables.
 173  *
 174  *      flush_user_range(start, end, flags)
 175  *
 176  *              Clean and invalidate a range of cache entries in the
 177  *              specified address space before a change of page tables.
 178  *              - start - user start address (inclusive, page aligned)
 179  *              - end   - user end address   (exclusive, page aligned)
 180  *              - flags - vma->vm_flags field
 181  *
 182  *      coherent_kern_range(start, end)
 183  *
 184  *              Ensure coherency between the Icache and the Dcache in the
 185  *              region described by start, end.  If you have non-snooping
 186  *              Harvard caches, you need to implement this function.
 187  *              - start  - virtual start address
 188  *              - end    - virtual end address
 189  *
 190  *      coherent_user_range(start, end)
 191  *
 192  *              Ensure coherency between the Icache and the Dcache in the
 193  *              region described by start, end.  If you have non-snooping
 194  *              Harvard caches, you need to implement this function.
 195  *              - start  - virtual start address
 196  *              - end    - virtual end address
 197  *
 198  *      flush_kern_dcache_area(kaddr, size)
 199  *
 200  *              Ensure that the data held in page is written back.
 201  *              - kaddr  - page address
 202  *              - size   - region size
 203  *
 204  *      DMA Cache Coherency
 205  *      ===================
 206  *
 207  *      dma_flush_range(start, end)
 208  *
 209  *              Clean and invalidate the specified virtual address range.
 210  *              - start  - virtual start address
 211  *              - end    - virtual end address
 212  */
 213
 214 struct cpu_cache_fns {
 215         void (*flush_icache_all)(void);
 216         void (*flush_kern_all)(void);
 217         void (*flush_user_all)(void);
 218         void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
 219
 220         void (*coherent_kern_range)(unsigned long, unsigned long);
 221         void (*coherent_user_range)(unsigned long, unsigned long);
 222         void (*flush_kern_dcache_area)(void *, size_t);
 223
 224         void (*dma_map_area)(const void *, size_t, int);
 225         void (*dma_unmap_area)(const void *, size_t, int);
 226
 227         void (*dma_flush_range)(const void *, const void *);
 228 };
 229
 230 /*
 231  * Select the calling method
 232  */
 233 #ifdef MULTI_CACHE
 234
 235 extern struct cpu_cache_fns cpu_cache;
 236
 237 #define __cpuc_flush_icache_all         cpu_cache.flush_icache_all
 238 #define __cpuc_flush_kern_all           cpu_cache.flush_kern_all
 239 #define __cpuc_flush_user_all           cpu_cache.flush_user_all
 240 #define __cpuc_flush_user_range         cpu_cache.flush_user_range
 241 #define __cpuc_coherent_kern_range      cpu_cache.coherent_kern_range
 242 #define __cpuc_coherent_user_range      cpu_cache.coherent_user_range
 243 #define __cpuc_flush_dcache_area        cpu_cache.flush_kern_dcache_area
 244
 245 /*
 246  * These are private to the dma-mapping API.  Do not use directly.
 247  * Their sole purpose is to ensure that data held in the cache
 248  * is visible to DMA, or data written by DMA to system memory is
 249  * visible to the CPU.
 250  */
 251 #define dmac_map_area                   cpu_cache.dma_map_area
 252 #define dmac_unmap_area         cpu_cache.dma_unmap_area
 253 #define dmac_flush_range                cpu_cache.dma_flush_range
 254
 255 #else
 256
 257 #define __cpuc_flush_icache_all         __glue(_CACHE,_flush_icache_all)
 258 #define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
 259 #define __cpuc_flush_user_all           __glue(_CACHE,_flush_user_cache_all)
 260 #define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
 261 #define __cpuc_coherent_kern_range      __glue(_CACHE,_coherent_kern_range)
 262 #define __cpuc_coherent_user_range      __glue(_CACHE,_coherent_user_range)
 263 #define __cpuc_flush_dcache_area        __glue(_CACHE,_flush_kern_dcache_area)
 264
 265 extern void __cpuc_flush_icache_all(void);
 266 extern void __cpuc_flush_kern_all(void);
 267 extern void __cpuc_flush_user_all(void);
 268 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
 269 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
 270 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
 271 extern void __cpuc_flush_dcache_area(void *, size_t);
 272
 273 /*
 274  * These are private to the dma-mapping API.  Do not use directly.
 275  * Their sole purpose is to ensure that data held in the cache
 276  * is visible to DMA, or data written by DMA to system memory is
 277  * visible to the CPU.
 278  */
 279 #define dmac_map_area                   __glue(_CACHE,_dma_map_area)
 280 #define dmac_unmap_area         __glue(_CACHE,_dma_unmap_area)
 281 #define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
 282
 283 extern void dmac_map_area(const void *, size_t, int);
 284 extern void dmac_unmap_area(const void *, size_t, int);
 285 extern void dmac_flush_range(const void *, const void *);
 286
 287 #endif
 288
 289 /*
 290  * Copy user data from/to a page which is mapped into a different
 291  * processes address space.  Really, we want to allow our "user
 292  * space" model to handle this.
 293  */
 294 extern void copy_to_user_page(struct vm_area_struct *, struct page *,
 295         unsigned long, void *, const void *, unsigned long);
 296 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
 297         do {                                                    \
 298                 memcpy(dst, src, len);                          \
 299         } while (0)
 300
 301 /*
 302  * Convert calls to our calling convention.
 303  */
 304
 305 /* Invalidate I-cache */
 306 #define __flush_icache_all_generic()                                    \
 307         asm("mcr        p15, 0, %0, c7, c5, 0"                          \
 308             : : "r" (0));
 309
 310 /* Invalidate I-cache inner shareable */
 311 #define __flush_icache_all_v7_smp()                                     \
 312         asm("mcr        p15, 0, %0, c7, c1, 0"                          \
 313             : : "r" (0));
 314
 315 /*
 316  * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
 317  * will fall through to use __flush_icache_all_generic.
 318  */
 319 #if (defined(CONFIG_CPU_V7) && defined(CONFIG_CPU_V6)) ||               \
 320         defined(CONFIG_SMP_ON_UP)
 321 #define __flush_icache_preferred        __cpuc_flush_icache_all
 322 #elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
 323 #define __flush_icache_preferred        __flush_icache_all_v7_smp
 324 #elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920)
 325 #define __flush_icache_preferred        __cpuc_flush_icache_all
 326 #else
 327 #define __flush_icache_preferred        __flush_icache_all_generic
 328 #endif
 329
 330 static inline void __flush_icache_all(void)
 331 {
 332         __flush_icache_preferred();
 333 }
 334
 335 #define flush_cache_all()               __cpuc_flush_kern_all()
 336
 337 static inline void vivt_flush_cache_mm(struct mm_struct *mm)
 338 {
 339         if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
 340                 __cpuc_flush_user_all();
 341 }
 342
 343 static inline void
 344 vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 345 {
 346         if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
 347                 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
 348                                         vma->vm_flags);
 349 }
 350
 351 static inline void
 352 vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
 353 {
 354         if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
 355                 unsigned long addr = user_addr & PAGE_MASK;
 356                 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
 357         }
 358 }
 359
 360 #ifndef CONFIG_CPU_CACHE_VIPT
 361 #define flush_cache_mm(mm) \
 362                 vivt_flush_cache_mm(mm)
 363 #define flush_cache_range(vma,start,end) \
 364                 vivt_flush_cache_range(vma,start,end)
 365 #define flush_cache_page(vma,addr,pfn) \
 366                 vivt_flush_cache_page(vma,addr,pfn)
 367 #else
 368 extern void flush_cache_mm(struct mm_struct *mm);
 369 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 370 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
 371 #endif
 372
 373 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
 374
 375 /*
 376  * flush_cache_user_range is used when we want to ensure that the
 377  * Harvard caches are synchronised for the user space address range.
 378  * This is used for the ARM private sys_cacheflush system call.
 379  */
 380 #define flush_cache_user_range(vma,start,end) \
 381         __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
 382
 383 /*
 384  * Perform necessary cache operations to ensure that data previously
 385  * stored within this range of addresses can be executed by the CPU.
 386  */
 387 #define flush_icache_range(s,e)         __cpuc_coherent_kern_range(s,e)
 388
 389 /*
 390  * Perform necessary cache operations to ensure that the TLB will
 391  * see data written in the specified area.
 392  */
 393 #define clean_dcache_area(start,size)   cpu_dcache_clean_area(start, size)
 394
 395 /*
 396  * flush_dcache_page is used when the kernel has written to the page
 397  * cache page at virtual address page->virtual.
 398  *
 399  * If this page isn't mapped (ie, page_mapping == NULL), or it might
 400  * have userspace mappings, then we _must_ always clean + invalidate
 401  * the dcache entries associated with the kernel mapping.
 402  *
 403  * Otherwise we can defer the operation, and clean the cache when we are
 404  * about to change to user space.  This is the same method as used on SPARC64.
 405  * See update_mmu_cache for the user space part.
 406  */
 407 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
 408 extern void flush_dcache_page(struct page *);
 409
 410 static inline void flush_kernel_vmap_range(void *addr, int size)
 411 {
 412         if ((cache_is_vivt() || cache_is_vipt_aliasing()))
 413           __cpuc_flush_dcache_area(addr, (size_t)size);
 414 }
 415 static inline void invalidate_kernel_vmap_range(void *addr, int size)
 416 {
 417         if ((cache_is_vivt() || cache_is_vipt_aliasing()))
 418           __cpuc_flush_dcache_area(addr, (size_t)size);
 419 }
 420
 421 #define ARCH_HAS_FLUSH_ANON_PAGE
 422 static inline void flush_anon_page(struct vm_area_struct *vma,
 423                          struct page *page, unsigned long vmaddr)
 424 {
 425         extern void __flush_anon_page(struct vm_area_struct *vma,
 426                                 struct page *, unsigned long);
 427         if (PageAnon(page))
 428                 __flush_anon_page(vma, page, vmaddr);
 429 }
 430
 431 #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
 432 static inline void flush_kernel_dcache_page(struct page *page)
 433 {
 434         /* highmem pages are always flushed upon kunmap already */
 435         if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
 436                 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 437 }
 438
 439 #define flush_dcache_mmap_lock(mapping) \
 440         spin_lock_irq(&(mapping)->tree_lock)
 441 #define flush_dcache_mmap_unlock(mapping) \
 442         spin_unlock_irq(&(mapping)->tree_lock)
 443
 444 #define flush_icache_user_range(vma,page,addr,len) \
 445         flush_dcache_page(page)
 446
 447 /*
 448  * We don't appear to need to do anything here.  In fact, if we did, we'd
 449  * duplicate cache flushing elsewhere performed by flush_dcache_page().
 450  */
 451 #define flush_icache_page(vma,page)     do { } while (0)
 452
 453 /*
 454  * flush_cache_vmap() is used when creating mappings (eg, via vmap,
 455  * vmalloc, ioremap etc) in kernel space for pages.  On non-VIPT
 456  * caches, since the direct-mappings of these pages may contain cached
 457  * data, we need to do a full cache flush to ensure that writebacks
 458  * don't corrupt data placed into these pages via the new mappings.
 459  */
 460 static inline void flush_cache_vmap(unsigned long start, unsigned long end)
 461 {
 462         if (!cache_is_vipt_nonaliasing())
 463                 flush_cache_all();
 464         else
 465                 /*
 466                  * set_pte_at() called from vmap_pte_range() does not
 467                  * have a DSB after cleaning the cache line.
 468                  */
 469                 dsb();
 470 }
 471
 472 static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
 473 {
 474         if (!cache_is_vipt_nonaliasing())
 475                 flush_cache_all();
 476 }
 477
 478 #endif