2 * Samsung S5P Multi Format Codec v 5.1
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
24 #include <media/videobuf2-core.h>
26 #include "s5p_mfc_ctrl.h"
27 #include "s5p_mfc_debug.h"
28 #include "s5p_mfc_dec.h"
29 #include "s5p_mfc_enc.h"
30 #include "s5p_mfc_intr.h"
31 #include "s5p_mfc_opr.h"
32 #include "s5p_mfc_pm.h"
33 #include "s5p_mfc_shm.h"
35 #define S5P_MFC_NAME "s5p-mfc"
36 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
37 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
40 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
41 MODULE_PARM_DESC(debug
, "Debug level - higher value produces more verbose messages");
43 /* Helper functions for interrupt processing */
45 /* Remove from hw execution round robin */
46 void clear_work_bit(struct s5p_mfc_ctx
*ctx
)
48 struct s5p_mfc_dev
*dev
= ctx
->dev
;
50 spin_lock(&dev
->condlock
);
51 __clear_bit(ctx
->num
, &dev
->ctx_work_bits
);
52 spin_unlock(&dev
->condlock
);
55 /* Add to hw execution round robin */
56 void set_work_bit(struct s5p_mfc_ctx
*ctx
)
58 struct s5p_mfc_dev
*dev
= ctx
->dev
;
60 spin_lock(&dev
->condlock
);
61 __set_bit(ctx
->num
, &dev
->ctx_work_bits
);
62 spin_unlock(&dev
->condlock
);
65 /* Remove from hw execution round robin */
66 void clear_work_bit_irqsave(struct s5p_mfc_ctx
*ctx
)
68 struct s5p_mfc_dev
*dev
= ctx
->dev
;
71 spin_lock_irqsave(&dev
->condlock
, flags
);
72 __clear_bit(ctx
->num
, &dev
->ctx_work_bits
);
73 spin_unlock_irqrestore(&dev
->condlock
, flags
);
76 /* Add to hw execution round robin */
77 void set_work_bit_irqsave(struct s5p_mfc_ctx
*ctx
)
79 struct s5p_mfc_dev
*dev
= ctx
->dev
;
82 spin_lock_irqsave(&dev
->condlock
, flags
);
83 __set_bit(ctx
->num
, &dev
->ctx_work_bits
);
84 spin_unlock_irqrestore(&dev
->condlock
, flags
);
87 /* Wake up context wait_queue */
88 static void wake_up_ctx(struct s5p_mfc_ctx
*ctx
, unsigned int reason
,
92 ctx
->int_type
= reason
;
97 /* Wake up device wait_queue */
98 static void wake_up_dev(struct s5p_mfc_dev
*dev
, unsigned int reason
,
102 dev
->int_type
= reason
;
104 wake_up(&dev
->queue
);
107 static void s5p_mfc_watchdog(unsigned long arg
)
109 struct s5p_mfc_dev
*dev
= (struct s5p_mfc_dev
*)arg
;
111 if (test_bit(0, &dev
->hw_lock
))
112 atomic_inc(&dev
->watchdog_cnt
);
113 if (atomic_read(&dev
->watchdog_cnt
) >= MFC_WATCHDOG_CNT
) {
114 /* This means that hw is busy and no interrupts were
115 * generated by hw for the Nth time of running this
116 * watchdog timer. This usually means a serious hw
117 * error. Now it is time to kill all instances and
119 mfc_err("Time out during waiting for HW\n");
120 queue_work(dev
->watchdog_workqueue
, &dev
->watchdog_work
);
122 dev
->watchdog_timer
.expires
= jiffies
+
123 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL
);
124 add_timer(&dev
->watchdog_timer
);
127 static void s5p_mfc_watchdog_worker(struct work_struct
*work
)
129 struct s5p_mfc_dev
*dev
;
130 struct s5p_mfc_ctx
*ctx
;
135 dev
= container_of(work
, struct s5p_mfc_dev
, watchdog_work
);
137 mfc_err("Driver timeout error handling\n");
138 /* Lock the mutex that protects open and release.
139 * This is necessary as they may load and unload firmware. */
140 mutex_locked
= mutex_trylock(&dev
->mfc_mutex
);
142 mfc_err("Error: some instance may be closing/opening\n");
143 spin_lock_irqsave(&dev
->irqlock
, flags
);
147 for (i
= 0; i
< MFC_NUM_CONTEXTS
; i
++) {
151 ctx
->state
= MFCINST_ERROR
;
152 s5p_mfc_cleanup_queue(&ctx
->dst_queue
, &ctx
->vq_dst
);
153 s5p_mfc_cleanup_queue(&ctx
->src_queue
, &ctx
->vq_src
);
155 wake_up_ctx(ctx
, S5P_FIMV_R2H_CMD_ERR_RET
, 0);
157 clear_bit(0, &dev
->hw_lock
);
158 spin_unlock_irqrestore(&dev
->irqlock
, flags
);
159 /* Double check if there is at least one instance running.
160 * If no instance is in memory than no firmware should be present */
161 if (dev
->num_inst
> 0) {
162 ret
= s5p_mfc_reload_firmware(dev
);
164 mfc_err("Failed to reload FW\n");
168 ret
= s5p_mfc_init_hw(dev
);
170 mfc_err("Failed to reinit FW\n");
174 mutex_unlock(&dev
->mfc_mutex
);
177 static enum s5p_mfc_node_type
s5p_mfc_get_node_type(struct file
*file
)
179 struct video_device
*vdev
= video_devdata(file
);
182 mfc_err("failed to get video_device");
183 return MFCNODE_INVALID
;
185 if (vdev
->index
== 0)
186 return MFCNODE_DECODER
;
187 else if (vdev
->index
== 1)
188 return MFCNODE_ENCODER
;
189 return MFCNODE_INVALID
;
192 static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev
*dev
)
194 mfc_write(dev
, 0, S5P_FIMV_RISC_HOST_INT
);
195 mfc_write(dev
, 0, S5P_FIMV_RISC2HOST_CMD
);
196 mfc_write(dev
, 0xffff, S5P_FIMV_SI_RTN_CHID
);
199 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx
*ctx
)
201 struct s5p_mfc_buf
*dst_buf
;
203 ctx
->state
= MFCINST_FINISHED
;
205 while (!list_empty(&ctx
->dst_queue
)) {
206 dst_buf
= list_entry(ctx
->dst_queue
.next
,
207 struct s5p_mfc_buf
, list
);
208 mfc_debug(2, "Cleaning up buffer: %d\n",
209 dst_buf
->b
->v4l2_buf
.index
);
210 vb2_set_plane_payload(dst_buf
->b
, 0, 0);
211 vb2_set_plane_payload(dst_buf
->b
, 1, 0);
212 list_del(&dst_buf
->list
);
213 ctx
->dst_queue_cnt
--;
214 dst_buf
->b
->v4l2_buf
.sequence
= (ctx
->sequence
++);
216 if (s5p_mfc_read_shm(ctx
, PIC_TIME_TOP
) ==
217 s5p_mfc_read_shm(ctx
, PIC_TIME_BOT
))
218 dst_buf
->b
->v4l2_buf
.field
= V4L2_FIELD_NONE
;
220 dst_buf
->b
->v4l2_buf
.field
= V4L2_FIELD_INTERLACED
;
222 ctx
->dec_dst_flag
&= ~(1 << dst_buf
->b
->v4l2_buf
.index
);
223 vb2_buffer_done(dst_buf
->b
, VB2_BUF_STATE_DONE
);
227 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx
*ctx
)
229 struct s5p_mfc_dev
*dev
= ctx
->dev
;
230 struct s5p_mfc_buf
*dst_buf
, *src_buf
;
231 size_t dec_y_addr
= s5p_mfc_get_dec_y_adr();
232 unsigned int frame_type
= s5p_mfc_get_frame_type();
234 /* Copy timestamp / timecode from decoded src to dst and set
236 src_buf
= list_entry(ctx
->src_queue
.next
, struct s5p_mfc_buf
, list
);
237 list_for_each_entry(dst_buf
, &ctx
->dst_queue
, list
) {
238 if (vb2_dma_contig_plane_dma_addr(dst_buf
->b
, 0) == dec_y_addr
) {
239 memcpy(&dst_buf
->b
->v4l2_buf
.timecode
,
240 &src_buf
->b
->v4l2_buf
.timecode
,
241 sizeof(struct v4l2_timecode
));
242 memcpy(&dst_buf
->b
->v4l2_buf
.timestamp
,
243 &src_buf
->b
->v4l2_buf
.timestamp
,
244 sizeof(struct timeval
));
245 switch (frame_type
) {
246 case S5P_FIMV_DECODE_FRAME_I_FRAME
:
247 dst_buf
->b
->v4l2_buf
.flags
|=
248 V4L2_BUF_FLAG_KEYFRAME
;
250 case S5P_FIMV_DECODE_FRAME_P_FRAME
:
251 dst_buf
->b
->v4l2_buf
.flags
|=
252 V4L2_BUF_FLAG_PFRAME
;
254 case S5P_FIMV_DECODE_FRAME_B_FRAME
:
255 dst_buf
->b
->v4l2_buf
.flags
|=
256 V4L2_BUF_FLAG_BFRAME
;
264 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx
*ctx
, unsigned int err
)
266 struct s5p_mfc_dev
*dev
= ctx
->dev
;
267 struct s5p_mfc_buf
*dst_buf
;
268 size_t dspl_y_addr
= s5p_mfc_get_dspl_y_adr();
269 unsigned int frame_type
= s5p_mfc_get_frame_type();
272 /* If frame is same as previous then skip and do not dequeue */
273 if (frame_type
== S5P_FIMV_DECODE_FRAME_SKIPPED
) {
274 if (!ctx
->after_packed_pb
)
276 ctx
->after_packed_pb
= 0;
280 /* The MFC returns address of the buffer, now we have to
281 * check which videobuf does it correspond to */
282 list_for_each_entry(dst_buf
, &ctx
->dst_queue
, list
) {
283 /* Check if this is the buffer we're looking for */
284 if (vb2_dma_contig_plane_dma_addr(dst_buf
->b
, 0) == dspl_y_addr
) {
285 list_del(&dst_buf
->list
);
286 ctx
->dst_queue_cnt
--;
287 dst_buf
->b
->v4l2_buf
.sequence
= ctx
->sequence
;
288 if (s5p_mfc_read_shm(ctx
, PIC_TIME_TOP
) ==
289 s5p_mfc_read_shm(ctx
, PIC_TIME_BOT
))
290 dst_buf
->b
->v4l2_buf
.field
= V4L2_FIELD_NONE
;
292 dst_buf
->b
->v4l2_buf
.field
=
293 V4L2_FIELD_INTERLACED
;
294 vb2_set_plane_payload(dst_buf
->b
, 0, ctx
->luma_size
);
295 vb2_set_plane_payload(dst_buf
->b
, 1, ctx
->chroma_size
);
296 clear_bit(dst_buf
->b
->v4l2_buf
.index
,
299 vb2_buffer_done(dst_buf
->b
,
300 err
? VB2_BUF_STATE_ERROR
: VB2_BUF_STATE_DONE
);
302 index
= dst_buf
->b
->v4l2_buf
.index
;
308 /* Handle frame decoding interrupt */
309 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx
*ctx
,
310 unsigned int reason
, unsigned int err
)
312 struct s5p_mfc_dev
*dev
= ctx
->dev
;
313 unsigned int dst_frame_status
;
314 struct s5p_mfc_buf
*src_buf
;
316 unsigned int res_change
;
320 dst_frame_status
= s5p_mfc_get_dspl_status()
321 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK
;
322 res_change
= s5p_mfc_get_dspl_status()
323 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK
;
324 mfc_debug(2, "Frame Status: %x\n", dst_frame_status
);
325 if (ctx
->state
== MFCINST_RES_CHANGE_INIT
)
326 ctx
->state
= MFCINST_RES_CHANGE_FLUSH
;
328 ctx
->state
= MFCINST_RES_CHANGE_INIT
;
329 s5p_mfc_clear_int_flags(dev
);
330 wake_up_ctx(ctx
, reason
, err
);
331 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
334 s5p_mfc_try_run(dev
);
337 if (ctx
->dpb_flush_flag
)
338 ctx
->dpb_flush_flag
= 0;
340 spin_lock_irqsave(&dev
->irqlock
, flags
);
341 /* All frames remaining in the buffer have been extracted */
342 if (dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_EMPTY
) {
343 if (ctx
->state
== MFCINST_RES_CHANGE_FLUSH
) {
344 s5p_mfc_handle_frame_all_extracted(ctx
);
345 ctx
->state
= MFCINST_RES_CHANGE_END
;
346 goto leave_handle_frame
;
348 s5p_mfc_handle_frame_all_extracted(ctx
);
352 if (dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_DISPLAY
||
353 dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_ONLY
)
354 s5p_mfc_handle_frame_copy_time(ctx
);
356 /* A frame has been decoded and is in the buffer */
357 if (dst_frame_status
== S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
||
358 dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_DISPLAY
) {
359 s5p_mfc_handle_frame_new(ctx
, err
);
361 mfc_debug(2, "No frame decode\n");
363 /* Mark source buffer as complete */
364 if (dst_frame_status
!= S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
365 && !list_empty(&ctx
->src_queue
)) {
366 src_buf
= list_entry(ctx
->src_queue
.next
, struct s5p_mfc_buf
,
368 ctx
->consumed_stream
+= s5p_mfc_get_consumed_stream();
369 if (ctx
->codec_mode
!= S5P_FIMV_CODEC_H264_DEC
&&
370 s5p_mfc_get_frame_type() == S5P_FIMV_DECODE_FRAME_P_FRAME
371 && ctx
->consumed_stream
+ STUFF_BYTE
<
372 src_buf
->b
->v4l2_planes
[0].bytesused
) {
373 /* Run MFC again on the same buffer */
374 mfc_debug(2, "Running again the same buffer\n");
375 ctx
->after_packed_pb
= 1;
377 index
= src_buf
->b
->v4l2_buf
.index
;
378 mfc_debug(2, "MFC needs next buffer\n");
379 ctx
->consumed_stream
= 0;
380 list_del(&src_buf
->list
);
381 ctx
->src_queue_cnt
--;
382 if (s5p_mfc_err_dec(err
) > 0)
383 vb2_buffer_done(src_buf
->b
, VB2_BUF_STATE_ERROR
);
385 vb2_buffer_done(src_buf
->b
, VB2_BUF_STATE_DONE
);
389 spin_unlock_irqrestore(&dev
->irqlock
, flags
);
390 if ((ctx
->src_queue_cnt
== 0 && ctx
->state
!= MFCINST_FINISHING
)
391 || ctx
->dst_queue_cnt
< ctx
->dpb_count
)
393 s5p_mfc_clear_int_flags(dev
);
394 wake_up_ctx(ctx
, reason
, err
);
395 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
398 s5p_mfc_try_run(dev
);
401 /* Error handling for interrupt */
402 static void s5p_mfc_handle_error(struct s5p_mfc_ctx
*ctx
,
403 unsigned int reason
, unsigned int err
)
405 struct s5p_mfc_dev
*dev
;
408 /* If no context is available then all necessary
409 * processing has been done. */
414 mfc_err("Interrupt Error: %08x\n", err
);
415 s5p_mfc_clear_int_flags(dev
);
416 wake_up_dev(dev
, reason
, err
);
418 /* Error recovery is dependent on the state of context */
419 switch (ctx
->state
) {
421 /* This error had to happen while acquireing instance */
422 case MFCINST_GOT_INST
:
423 /* This error had to happen while parsing the header */
424 case MFCINST_HEAD_PARSED
:
425 /* This error had to happen while setting dst buffers */
426 case MFCINST_RETURN_INST
:
427 /* This error had to happen while releasing instance */
429 wake_up_ctx(ctx
, reason
, err
);
430 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
433 ctx
->state
= MFCINST_ERROR
;
435 case MFCINST_FINISHING
:
436 case MFCINST_FINISHED
:
437 case MFCINST_RUNNING
:
438 /* It is higly probable that an error occured
439 * while decoding a frame */
441 ctx
->state
= MFCINST_ERROR
;
442 /* Mark all dst buffers as having an error */
443 spin_lock_irqsave(&dev
->irqlock
, flags
);
444 s5p_mfc_cleanup_queue(&ctx
->dst_queue
, &ctx
->vq_dst
);
445 /* Mark all src buffers as having an error */
446 s5p_mfc_cleanup_queue(&ctx
->src_queue
, &ctx
->vq_src
);
447 spin_unlock_irqrestore(&dev
->irqlock
, flags
);
448 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
453 mfc_err("Encountered an error interrupt which had not been handled\n");
459 /* Header parsing interrupt handling */
460 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx
*ctx
,
461 unsigned int reason
, unsigned int err
)
463 struct s5p_mfc_dev
*dev
;
464 unsigned int guard_width
, guard_height
;
469 if (ctx
->c_ops
->post_seq_start
) {
470 if (ctx
->c_ops
->post_seq_start(ctx
))
471 mfc_err("post_seq_start() failed\n");
473 ctx
->img_width
= s5p_mfc_get_img_width();
474 ctx
->img_height
= s5p_mfc_get_img_height();
476 ctx
->buf_width
= ALIGN(ctx
->img_width
,
477 S5P_FIMV_NV12MT_HALIGN
);
478 ctx
->buf_height
= ALIGN(ctx
->img_height
,
479 S5P_FIMV_NV12MT_VALIGN
);
480 mfc_debug(2, "SEQ Done: Movie dimensions %dx%d, "
481 "buffer dimensions: %dx%d\n", ctx
->img_width
,
482 ctx
->img_height
, ctx
->buf_width
,
484 if (ctx
->codec_mode
== S5P_FIMV_CODEC_H264_DEC
) {
485 ctx
->luma_size
= ALIGN(ctx
->buf_width
*
486 ctx
->buf_height
, S5P_FIMV_DEC_BUF_ALIGN
);
487 ctx
->chroma_size
= ALIGN(ctx
->buf_width
*
488 ALIGN((ctx
->img_height
>> 1),
489 S5P_FIMV_NV12MT_VALIGN
),
490 S5P_FIMV_DEC_BUF_ALIGN
);
491 ctx
->mv_size
= ALIGN(ctx
->buf_width
*
492 ALIGN((ctx
->buf_height
>> 2),
493 S5P_FIMV_NV12MT_VALIGN
),
494 S5P_FIMV_DEC_BUF_ALIGN
);
496 guard_width
= ALIGN(ctx
->img_width
+ 24,
497 S5P_FIMV_NV12MT_HALIGN
);
498 guard_height
= ALIGN(ctx
->img_height
+ 16,
499 S5P_FIMV_NV12MT_VALIGN
);
500 ctx
->luma_size
= ALIGN(guard_width
*
501 guard_height
, S5P_FIMV_DEC_BUF_ALIGN
);
502 guard_width
= ALIGN(ctx
->img_width
+ 16,
503 S5P_FIMV_NV12MT_HALIGN
);
504 guard_height
= ALIGN((ctx
->img_height
>> 1) + 4,
505 S5P_FIMV_NV12MT_VALIGN
);
506 ctx
->chroma_size
= ALIGN(guard_width
*
507 guard_height
, S5P_FIMV_DEC_BUF_ALIGN
);
510 ctx
->dpb_count
= s5p_mfc_get_dpb_count();
511 if (ctx
->img_width
== 0 || ctx
->img_height
== 0)
512 ctx
->state
= MFCINST_ERROR
;
514 ctx
->state
= MFCINST_HEAD_PARSED
;
516 s5p_mfc_clear_int_flags(dev
);
518 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
521 s5p_mfc_try_run(dev
);
522 wake_up_ctx(ctx
, reason
, err
);
525 /* Header parsing interrupt handling */
526 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx
*ctx
,
527 unsigned int reason
, unsigned int err
)
529 struct s5p_mfc_buf
*src_buf
;
530 struct s5p_mfc_dev
*dev
;
536 s5p_mfc_clear_int_flags(dev
);
537 ctx
->int_type
= reason
;
542 ctx
->state
= MFCINST_RUNNING
;
543 if (!ctx
->dpb_flush_flag
) {
544 spin_lock_irqsave(&dev
->irqlock
, flags
);
545 if (!list_empty(&ctx
->src_queue
)) {
546 src_buf
= list_entry(ctx
->src_queue
.next
,
547 struct s5p_mfc_buf
, list
);
548 list_del(&src_buf
->list
);
549 ctx
->src_queue_cnt
--;
550 vb2_buffer_done(src_buf
->b
,
553 spin_unlock_irqrestore(&dev
->irqlock
, flags
);
555 ctx
->dpb_flush_flag
= 0;
557 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
562 wake_up(&ctx
->queue
);
563 s5p_mfc_try_run(dev
);
565 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
570 wake_up(&ctx
->queue
);
574 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx
*ctx
,
575 unsigned int reason
, unsigned int err
)
577 struct s5p_mfc_dev
*dev
= ctx
->dev
;
578 struct s5p_mfc_buf
*mb_entry
;
580 mfc_debug(2, "Stream completed");
582 s5p_mfc_clear_int_flags(dev
);
583 ctx
->int_type
= reason
;
585 ctx
->state
= MFCINST_FINISHED
;
587 spin_lock(&dev
->irqlock
);
588 if (!list_empty(&ctx
->dst_queue
)) {
589 mb_entry
= list_entry(ctx
->dst_queue
.next
, struct s5p_mfc_buf
,
591 list_del(&mb_entry
->list
);
592 ctx
->dst_queue_cnt
--;
593 vb2_set_plane_payload(mb_entry
->b
, 0, 0);
594 vb2_buffer_done(mb_entry
->b
, VB2_BUF_STATE_DONE
);
596 spin_unlock(&dev
->irqlock
);
600 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
604 wake_up(&ctx
->queue
);
605 s5p_mfc_try_run(dev
);
608 /* Interrupt processing */
609 static irqreturn_t
s5p_mfc_irq(int irq
, void *priv
)
611 struct s5p_mfc_dev
*dev
= priv
;
612 struct s5p_mfc_ctx
*ctx
;
617 /* Reset the timeout watchdog */
618 atomic_set(&dev
->watchdog_cnt
, 0);
619 ctx
= dev
->ctx
[dev
->curr_ctx
];
620 /* Get the reason of interrupt and the error code */
621 reason
= s5p_mfc_get_int_reason();
622 err
= s5p_mfc_get_int_err();
623 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason
, err
);
625 case S5P_FIMV_R2H_CMD_ERR_RET
:
626 /* An error has occured */
627 if (ctx
->state
== MFCINST_RUNNING
&&
628 s5p_mfc_err_dec(err
) >= S5P_FIMV_ERR_WARNINGS_START
)
629 s5p_mfc_handle_frame(ctx
, reason
, err
);
631 s5p_mfc_handle_error(ctx
, reason
, err
);
632 clear_bit(0, &dev
->enter_suspend
);
635 case S5P_FIMV_R2H_CMD_SLICE_DONE_RET
:
636 case S5P_FIMV_R2H_CMD_FRAME_DONE_RET
:
637 if (ctx
->c_ops
->post_frame_start
) {
638 if (ctx
->c_ops
->post_frame_start(ctx
))
639 mfc_err("post_frame_start() failed\n");
640 s5p_mfc_clear_int_flags(dev
);
641 wake_up_ctx(ctx
, reason
, err
);
642 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
645 s5p_mfc_try_run(dev
);
647 s5p_mfc_handle_frame(ctx
, reason
, err
);
651 case S5P_FIMV_R2H_CMD_SEQ_DONE_RET
:
652 s5p_mfc_handle_seq_done(ctx
, reason
, err
);
655 case S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET
:
656 ctx
->inst_no
= s5p_mfc_get_inst_no();
657 ctx
->state
= MFCINST_GOT_INST
;
659 wake_up(&ctx
->queue
);
662 case S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET
:
664 ctx
->state
= MFCINST_FREE
;
665 wake_up(&ctx
->queue
);
668 case S5P_FIMV_R2H_CMD_SYS_INIT_RET
:
669 case S5P_FIMV_R2H_CMD_FW_STATUS_RET
:
670 case S5P_FIMV_R2H_CMD_SLEEP_RET
:
671 case S5P_FIMV_R2H_CMD_WAKEUP_RET
:
674 s5p_mfc_clear_int_flags(dev
);
675 wake_up_dev(dev
, reason
, err
);
676 clear_bit(0, &dev
->hw_lock
);
677 clear_bit(0, &dev
->enter_suspend
);
680 case S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET
:
681 s5p_mfc_handle_init_buffers(ctx
, reason
, err
);
684 case S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET
:
685 s5p_mfc_handle_stream_complete(ctx
, reason
, err
);
689 mfc_debug(2, "Unknown int reason\n");
690 s5p_mfc_clear_int_flags(dev
);
695 s5p_mfc_clear_int_flags(dev
);
696 ctx
->int_type
= reason
;
699 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
700 mfc_err("Failed to unlock hw\n");
704 s5p_mfc_try_run(dev
);
705 mfc_debug(2, "Exit via irq_cleanup_hw\n");
709 /* Open an MFC node */
710 static int s5p_mfc_open(struct file
*file
)
712 struct s5p_mfc_dev
*dev
= video_drvdata(file
);
713 struct s5p_mfc_ctx
*ctx
= NULL
;
718 if (mutex_lock_interruptible(&dev
->mfc_mutex
))
720 dev
->num_inst
++; /* It is guarded by mfc_mutex in vfd */
721 /* Allocate memory for context */
722 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
724 mfc_err("Not enough memory\n");
728 v4l2_fh_init(&ctx
->fh
, video_devdata(file
));
729 file
->private_data
= &ctx
->fh
;
730 v4l2_fh_add(&ctx
->fh
);
732 INIT_LIST_HEAD(&ctx
->src_queue
);
733 INIT_LIST_HEAD(&ctx
->dst_queue
);
734 ctx
->src_queue_cnt
= 0;
735 ctx
->dst_queue_cnt
= 0;
736 /* Get context number */
738 while (dev
->ctx
[ctx
->num
]) {
740 if (ctx
->num
>= MFC_NUM_CONTEXTS
) {
741 mfc_err("Too many open contexts\n");
746 /* Mark context as idle */
747 clear_work_bit_irqsave(ctx
);
748 dev
->ctx
[ctx
->num
] = ctx
;
749 if (s5p_mfc_get_node_type(file
) == MFCNODE_DECODER
) {
750 ctx
->type
= MFCINST_DECODER
;
751 ctx
->c_ops
= get_dec_codec_ops();
752 /* Setup ctrl handler */
753 ret
= s5p_mfc_dec_ctrls_setup(ctx
);
755 mfc_err("Failed to setup mfc controls\n");
756 goto err_ctrls_setup
;
758 } else if (s5p_mfc_get_node_type(file
) == MFCNODE_ENCODER
) {
759 ctx
->type
= MFCINST_ENCODER
;
760 ctx
->c_ops
= get_enc_codec_ops();
761 /* only for encoder */
762 INIT_LIST_HEAD(&ctx
->ref_queue
);
763 ctx
->ref_queue_cnt
= 0;
764 /* Setup ctrl handler */
765 ret
= s5p_mfc_enc_ctrls_setup(ctx
);
767 mfc_err("Failed to setup mfc controls\n");
768 goto err_ctrls_setup
;
774 ctx
->fh
.ctrl_handler
= &ctx
->ctrl_handler
;
776 /* Load firmware if this is the first instance */
777 if (dev
->num_inst
== 1) {
778 dev
->watchdog_timer
.expires
= jiffies
+
779 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL
);
780 add_timer(&dev
->watchdog_timer
);
781 ret
= s5p_mfc_power_on();
783 mfc_err("power on failed\n");
787 ret
= s5p_mfc_alloc_and_load_firmware(dev
);
791 ret
= s5p_mfc_init_hw(dev
);
796 /* Init videobuf2 queue for CAPTURE */
798 q
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
;
799 q
->drv_priv
= &ctx
->fh
;
800 if (s5p_mfc_get_node_type(file
) == MFCNODE_DECODER
) {
801 q
->io_modes
= VB2_MMAP
;
802 q
->ops
= get_dec_queue_ops();
803 } else if (s5p_mfc_get_node_type(file
) == MFCNODE_ENCODER
) {
804 q
->io_modes
= VB2_MMAP
| VB2_USERPTR
;
805 q
->ops
= get_enc_queue_ops();
810 q
->mem_ops
= (struct vb2_mem_ops
*)&vb2_dma_contig_memops
;
811 ret
= vb2_queue_init(q
);
813 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
816 /* Init videobuf2 queue for OUTPUT */
818 q
->type
= V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
;
819 q
->io_modes
= VB2_MMAP
;
820 q
->drv_priv
= &ctx
->fh
;
821 if (s5p_mfc_get_node_type(file
) == MFCNODE_DECODER
) {
822 q
->io_modes
= VB2_MMAP
;
823 q
->ops
= get_dec_queue_ops();
824 } else if (s5p_mfc_get_node_type(file
) == MFCNODE_ENCODER
) {
825 q
->io_modes
= VB2_MMAP
| VB2_USERPTR
;
826 q
->ops
= get_enc_queue_ops();
831 q
->mem_ops
= (struct vb2_mem_ops
*)&vb2_dma_contig_memops
;
832 ret
= vb2_queue_init(q
);
834 mfc_err("Failed to initialize videobuf2 queue(output)\n");
837 init_waitqueue_head(&ctx
->queue
);
838 mutex_unlock(&dev
->mfc_mutex
);
841 /* Deinit when failure occured */
844 s5p_mfc_release_firmware(dev
);
846 dev
->ctx
[ctx
->num
] = NULL
;
847 del_timer_sync(&dev
->watchdog_timer
);
850 if (dev
->num_inst
== 1) {
851 if (s5p_mfc_power_off() < 0)
852 mfc_err("power off failed\n");
853 s5p_mfc_release_firmware(dev
);
856 s5p_mfc_dec_ctrls_delete(ctx
);
859 v4l2_fh_del(&ctx
->fh
);
860 v4l2_fh_exit(&ctx
->fh
);
864 mutex_unlock(&dev
->mfc_mutex
);
869 /* Release MFC context */
870 static int s5p_mfc_release(struct file
*file
)
872 struct s5p_mfc_ctx
*ctx
= fh_to_ctx(file
->private_data
);
873 struct s5p_mfc_dev
*dev
= ctx
->dev
;
876 mutex_lock(&dev
->mfc_mutex
);
878 vb2_queue_release(&ctx
->vq_src
);
879 vb2_queue_release(&ctx
->vq_dst
);
880 /* Mark context as idle */
881 clear_work_bit_irqsave(ctx
);
882 /* If instance was initialised then
883 * return instance and free reosurces */
884 if (ctx
->inst_no
!= MFC_NO_INSTANCE_SET
) {
885 mfc_debug(2, "Has to free instance\n");
886 ctx
->state
= MFCINST_RETURN_INST
;
887 set_work_bit_irqsave(ctx
);
888 s5p_mfc_clean_ctx_int_flags(ctx
);
889 s5p_mfc_try_run(dev
);
890 /* Wait until instance is returned or timeout occured */
891 if (s5p_mfc_wait_for_done_ctx
892 (ctx
, S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET
, 0)) {
894 mfc_err("Err returning instance\n");
896 mfc_debug(2, "After free instance\n");
898 s5p_mfc_release_codec_buffers(ctx
);
899 s5p_mfc_release_instance_buffer(ctx
);
900 if (ctx
->type
== MFCINST_DECODER
)
901 s5p_mfc_release_dec_desc_buffer(ctx
);
903 ctx
->inst_no
= MFC_NO_INSTANCE_SET
;
905 /* hardware locking scheme */
906 if (dev
->curr_ctx
== ctx
->num
)
907 clear_bit(0, &dev
->hw_lock
);
909 if (dev
->num_inst
== 0) {
910 mfc_debug(2, "Last instance - release firmware\n");
911 /* reset <-> F/W release */
913 s5p_mfc_release_firmware(dev
);
914 del_timer_sync(&dev
->watchdog_timer
);
915 if (s5p_mfc_power_off() < 0)
916 mfc_err("Power off failed\n");
918 mfc_debug(2, "Shutting down clock\n");
920 dev
->ctx
[ctx
->num
] = NULL
;
921 s5p_mfc_dec_ctrls_delete(ctx
);
922 v4l2_fh_del(&ctx
->fh
);
923 v4l2_fh_exit(&ctx
->fh
);
926 mutex_unlock(&dev
->mfc_mutex
);
931 static unsigned int s5p_mfc_poll(struct file
*file
,
932 struct poll_table_struct
*wait
)
934 struct s5p_mfc_ctx
*ctx
= fh_to_ctx(file
->private_data
);
935 struct s5p_mfc_dev
*dev
= ctx
->dev
;
936 struct vb2_queue
*src_q
, *dst_q
;
937 struct vb2_buffer
*src_vb
= NULL
, *dst_vb
= NULL
;
941 mutex_lock(&dev
->mfc_mutex
);
942 src_q
= &ctx
->vq_src
;
943 dst_q
= &ctx
->vq_dst
;
945 * There has to be at least one buffer queued on each queued_list, which
946 * means either in driver already or waiting for driver to claim it
947 * and start processing.
949 if ((!src_q
->streaming
|| list_empty(&src_q
->queued_list
))
950 && (!dst_q
->streaming
|| list_empty(&dst_q
->queued_list
))) {
954 mutex_unlock(&dev
->mfc_mutex
);
955 poll_wait(file
, &ctx
->fh
.wait
, wait
);
956 poll_wait(file
, &src_q
->done_wq
, wait
);
957 poll_wait(file
, &dst_q
->done_wq
, wait
);
958 mutex_lock(&dev
->mfc_mutex
);
959 if (v4l2_event_pending(&ctx
->fh
))
961 spin_lock_irqsave(&src_q
->done_lock
, flags
);
962 if (!list_empty(&src_q
->done_list
))
963 src_vb
= list_first_entry(&src_q
->done_list
, struct vb2_buffer
,
965 if (src_vb
&& (src_vb
->state
== VB2_BUF_STATE_DONE
966 || src_vb
->state
== VB2_BUF_STATE_ERROR
))
967 rc
|= POLLOUT
| POLLWRNORM
;
968 spin_unlock_irqrestore(&src_q
->done_lock
, flags
);
969 spin_lock_irqsave(&dst_q
->done_lock
, flags
);
970 if (!list_empty(&dst_q
->done_list
))
971 dst_vb
= list_first_entry(&dst_q
->done_list
, struct vb2_buffer
,
973 if (dst_vb
&& (dst_vb
->state
== VB2_BUF_STATE_DONE
974 || dst_vb
->state
== VB2_BUF_STATE_ERROR
))
975 rc
|= POLLIN
| POLLRDNORM
;
976 spin_unlock_irqrestore(&dst_q
->done_lock
, flags
);
978 mutex_unlock(&dev
->mfc_mutex
);
983 static int s5p_mfc_mmap(struct file
*file
, struct vm_area_struct
*vma
)
985 struct s5p_mfc_ctx
*ctx
= fh_to_ctx(file
->private_data
);
986 struct s5p_mfc_dev
*dev
= ctx
->dev
;
987 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
990 if (mutex_lock_interruptible(&dev
->mfc_mutex
))
992 if (offset
< DST_QUEUE_OFF_BASE
) {
993 mfc_debug(2, "mmaping source\n");
994 ret
= vb2_mmap(&ctx
->vq_src
, vma
);
995 } else { /* capture */
996 mfc_debug(2, "mmaping destination\n");
997 vma
->vm_pgoff
-= (DST_QUEUE_OFF_BASE
>> PAGE_SHIFT
);
998 ret
= vb2_mmap(&ctx
->vq_dst
, vma
);
1000 mutex_unlock(&dev
->mfc_mutex
);
1005 static const struct v4l2_file_operations s5p_mfc_fops
= {
1006 .owner
= THIS_MODULE
,
1007 .open
= s5p_mfc_open
,
1008 .release
= s5p_mfc_release
,
1009 .poll
= s5p_mfc_poll
,
1010 .unlocked_ioctl
= video_ioctl2
,
1011 .mmap
= s5p_mfc_mmap
,
1014 static int match_child(struct device
*dev
, void *data
)
1018 return !strcmp(dev_name(dev
), (char *)data
);
1021 /* MFC probe function */
1022 static int s5p_mfc_probe(struct platform_device
*pdev
)
1024 struct s5p_mfc_dev
*dev
;
1025 struct video_device
*vfd
;
1026 struct resource
*res
;
1029 pr_debug("%s++\n", __func__
);
1030 dev
= devm_kzalloc(&pdev
->dev
, sizeof(*dev
), GFP_KERNEL
);
1032 dev_err(&pdev
->dev
, "Not enough memory for MFC device\n");
1036 spin_lock_init(&dev
->irqlock
);
1037 spin_lock_init(&dev
->condlock
);
1038 dev
->plat_dev
= pdev
;
1039 if (!dev
->plat_dev
) {
1040 dev_err(&pdev
->dev
, "No platform data specified\n");
1044 ret
= s5p_mfc_init_pm(dev
);
1046 dev_err(&pdev
->dev
, "failed to get mfc clock source\n");
1050 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1052 dev
->regs_base
= devm_request_and_ioremap(&pdev
->dev
, res
);
1053 if (dev
->regs_base
== NULL
) {
1054 dev_err(&pdev
->dev
, "Failed to obtain io memory\n");
1058 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1060 dev_err(&pdev
->dev
, "failed to get irq resource\n");
1064 dev
->irq
= res
->start
;
1065 ret
= devm_request_irq(&pdev
->dev
, dev
->irq
, s5p_mfc_irq
,
1066 IRQF_DISABLED
, pdev
->name
, dev
);
1068 dev_err(&pdev
->dev
, "Failed to install irq (%d)\n", ret
);
1072 dev
->mem_dev_l
= device_find_child(&dev
->plat_dev
->dev
, "s5p-mfc-l",
1074 if (!dev
->mem_dev_l
) {
1075 mfc_err("Mem child (L) device get failed\n");
1079 dev
->mem_dev_r
= device_find_child(&dev
->plat_dev
->dev
, "s5p-mfc-r",
1081 if (!dev
->mem_dev_r
) {
1082 mfc_err("Mem child (R) device get failed\n");
1087 dev
->alloc_ctx
[0] = vb2_dma_contig_init_ctx(dev
->mem_dev_l
);
1088 if (IS_ERR_OR_NULL(dev
->alloc_ctx
[0])) {
1089 ret
= PTR_ERR(dev
->alloc_ctx
[0]);
1092 dev
->alloc_ctx
[1] = vb2_dma_contig_init_ctx(dev
->mem_dev_r
);
1093 if (IS_ERR_OR_NULL(dev
->alloc_ctx
[1])) {
1094 ret
= PTR_ERR(dev
->alloc_ctx
[1]);
1095 goto err_mem_init_ctx_1
;
1098 mutex_init(&dev
->mfc_mutex
);
1100 ret
= v4l2_device_register(&pdev
->dev
, &dev
->v4l2_dev
);
1102 goto err_v4l2_dev_reg
;
1103 init_waitqueue_head(&dev
->queue
);
1106 vfd
= video_device_alloc();
1108 v4l2_err(&dev
->v4l2_dev
, "Failed to allocate video device\n");
1112 vfd
->fops
= &s5p_mfc_fops
,
1113 vfd
->ioctl_ops
= get_dec_v4l2_ioctl_ops();
1114 vfd
->release
= video_device_release
,
1115 vfd
->lock
= &dev
->mfc_mutex
;
1116 vfd
->v4l2_dev
= &dev
->v4l2_dev
;
1117 vfd
->vfl_dir
= VFL_DIR_M2M
;
1118 snprintf(vfd
->name
, sizeof(vfd
->name
), "%s", S5P_MFC_DEC_NAME
);
1120 ret
= video_register_device(vfd
, VFL_TYPE_GRABBER
, 0);
1122 v4l2_err(&dev
->v4l2_dev
, "Failed to register video device\n");
1123 video_device_release(vfd
);
1126 v4l2_info(&dev
->v4l2_dev
,
1127 "decoder registered as /dev/video%d\n", vfd
->num
);
1128 video_set_drvdata(vfd
, dev
);
1131 vfd
= video_device_alloc();
1133 v4l2_err(&dev
->v4l2_dev
, "Failed to allocate video device\n");
1137 vfd
->fops
= &s5p_mfc_fops
,
1138 vfd
->ioctl_ops
= get_enc_v4l2_ioctl_ops();
1139 vfd
->release
= video_device_release
,
1140 vfd
->lock
= &dev
->mfc_mutex
;
1141 vfd
->v4l2_dev
= &dev
->v4l2_dev
;
1142 snprintf(vfd
->name
, sizeof(vfd
->name
), "%s", S5P_MFC_ENC_NAME
);
1144 ret
= video_register_device(vfd
, VFL_TYPE_GRABBER
, 0);
1146 v4l2_err(&dev
->v4l2_dev
, "Failed to register video device\n");
1147 video_device_release(vfd
);
1150 v4l2_info(&dev
->v4l2_dev
,
1151 "encoder registered as /dev/video%d\n", vfd
->num
);
1152 video_set_drvdata(vfd
, dev
);
1153 platform_set_drvdata(pdev
, dev
);
1156 dev
->watchdog_workqueue
= create_singlethread_workqueue(S5P_MFC_NAME
);
1157 INIT_WORK(&dev
->watchdog_work
, s5p_mfc_watchdog_worker
);
1158 atomic_set(&dev
->watchdog_cnt
, 0);
1159 init_timer(&dev
->watchdog_timer
);
1160 dev
->watchdog_timer
.data
= (unsigned long)dev
;
1161 dev
->watchdog_timer
.function
= s5p_mfc_watchdog
;
1163 pr_debug("%s--\n", __func__
);
1166 /* Deinit MFC if probe had failed */
1168 video_device_release(dev
->vfd_enc
);
1170 video_unregister_device(dev
->vfd_dec
);
1172 video_device_release(dev
->vfd_dec
);
1174 v4l2_device_unregister(&dev
->v4l2_dev
);
1176 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
[1]);
1178 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
[0]);
1180 s5p_mfc_final_pm(dev
);
1182 pr_debug("%s-- with error\n", __func__
);
1187 /* Remove the driver */
1188 static int __devexit
s5p_mfc_remove(struct platform_device
*pdev
)
1190 struct s5p_mfc_dev
*dev
= platform_get_drvdata(pdev
);
1192 v4l2_info(&dev
->v4l2_dev
, "Removing %s\n", pdev
->name
);
1194 del_timer_sync(&dev
->watchdog_timer
);
1195 flush_workqueue(dev
->watchdog_workqueue
);
1196 destroy_workqueue(dev
->watchdog_workqueue
);
1198 video_unregister_device(dev
->vfd_enc
);
1199 video_unregister_device(dev
->vfd_dec
);
1200 v4l2_device_unregister(&dev
->v4l2_dev
);
1201 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
[0]);
1202 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
[1]);
1204 s5p_mfc_final_pm(dev
);
1208 #ifdef CONFIG_PM_SLEEP
1210 static int s5p_mfc_suspend(struct device
*dev
)
1212 struct platform_device
*pdev
= to_platform_device(dev
);
1213 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1216 if (m_dev
->num_inst
== 0)
1219 if (test_and_set_bit(0, &m_dev
->enter_suspend
) != 0) {
1220 mfc_err("Error: going to suspend for a second time\n");
1224 /* Check if we're processing then wait if it necessary. */
1225 while (test_and_set_bit(0, &m_dev
->hw_lock
) != 0) {
1226 /* Try and lock the HW */
1227 /* Wait on the interrupt waitqueue */
1228 ret
= wait_event_interruptible_timeout(m_dev
->queue
,
1229 m_dev
->int_cond
|| m_dev
->ctx
[m_dev
->curr_ctx
]->int_cond
,
1230 msecs_to_jiffies(MFC_INT_TIMEOUT
));
1233 mfc_err("Waiting for hardware to finish timed out\n");
1238 return s5p_mfc_sleep(m_dev
);
1241 static int s5p_mfc_resume(struct device
*dev
)
1243 struct platform_device
*pdev
= to_platform_device(dev
);
1244 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1246 if (m_dev
->num_inst
== 0)
1248 return s5p_mfc_wakeup(m_dev
);
1252 #ifdef CONFIG_PM_RUNTIME
1253 static int s5p_mfc_runtime_suspend(struct device
*dev
)
1255 struct platform_device
*pdev
= to_platform_device(dev
);
1256 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1258 atomic_set(&m_dev
->pm
.power
, 0);
1262 static int s5p_mfc_runtime_resume(struct device
*dev
)
1264 struct platform_device
*pdev
= to_platform_device(dev
);
1265 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1268 if (!m_dev
->alloc_ctx
)
1270 pre_power
= atomic_read(&m_dev
->pm
.power
);
1271 atomic_set(&m_dev
->pm
.power
, 1);
1276 /* Power management */
1277 static const struct dev_pm_ops s5p_mfc_pm_ops
= {
1278 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend
, s5p_mfc_resume
)
1279 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend
, s5p_mfc_runtime_resume
,
1283 static struct platform_driver s5p_mfc_driver
= {
1284 .probe
= s5p_mfc_probe
,
1285 .remove
= __devexit_p(s5p_mfc_remove
),
1287 .name
= S5P_MFC_NAME
,
1288 .owner
= THIS_MODULE
,
1289 .pm
= &s5p_mfc_pm_ops
1293 module_platform_driver(s5p_mfc_driver
);
1295 MODULE_LICENSE("GPL");
1296 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1297 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");