1 /* linux/arch/arm/plat-s3c64xx/clock.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX Base clock support
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
23 #include <mach/hardware.h>
26 #include <mach/regs-sys.h>
27 #include <mach/regs-clock.h>
31 #include <plat/devs.h>
32 #include <plat/cpu-freq.h>
33 #include <plat/clock.h>
34 #include <plat/clock-clksrc.h>
36 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
37 * ext_xtal_mux for want of an actual name from the manual.
40 static struct clk clk_ext_xtal_mux
= {
45 #define clk_fin_apll clk_ext_xtal_mux
46 #define clk_fin_mpll clk_ext_xtal_mux
47 #define clk_fin_epll clk_ext_xtal_mux
49 #define clk_fout_mpll clk_mpll
50 #define clk_fout_epll clk_epll
58 struct clk clk_27m
= {
64 static int clk_48m_ctrl(struct clk
*clk
, int enable
)
69 /* can't rely on clock lock, this register has other usages */
70 local_irq_save(flags
);
72 val
= __raw_readl(S3C64XX_OTHERS
);
74 val
|= S3C64XX_OTHERS_USBMASK
;
76 val
&= ~S3C64XX_OTHERS_USBMASK
;
78 __raw_writel(val
, S3C64XX_OTHERS
);
79 local_irq_restore(flags
);
84 struct clk clk_48m
= {
88 .enable
= clk_48m_ctrl
,
91 struct clk clk_xusbxti
= {
97 static int inline s3c64xx_gate(void __iomem
*reg
,
101 unsigned int ctrlbit
= clk
->ctrlbit
;
104 con
= __raw_readl(reg
);
111 __raw_writel(con
, reg
);
115 static int s3c64xx_pclk_ctrl(struct clk
*clk
, int enable
)
117 return s3c64xx_gate(S3C_PCLK_GATE
, clk
, enable
);
120 static int s3c64xx_hclk_ctrl(struct clk
*clk
, int enable
)
122 return s3c64xx_gate(S3C_HCLK_GATE
, clk
, enable
);
125 int s3c64xx_sclk_ctrl(struct clk
*clk
, int enable
)
127 return s3c64xx_gate(S3C_SCLK_GATE
, clk
, enable
);
130 static struct clk init_clocks_disable
[] = {
139 .enable
= s3c64xx_pclk_ctrl
,
140 .ctrlbit
= S3C_CLKCON_PCLK_TSADC
,
145 .enable
= s3c64xx_pclk_ctrl
,
146 .ctrlbit
= S3C_CLKCON_PCLK_IIC
,
151 .enable
= s3c64xx_pclk_ctrl
,
152 .ctrlbit
= S3C_CLKCON_PCLK_IIS0
,
157 .enable
= s3c64xx_pclk_ctrl
,
158 .ctrlbit
= S3C_CLKCON_PCLK_IIS1
,
160 #ifdef CONFIG_CPU_S3C6410
162 .id
= -1, /* There's only one IISv4 port */
164 .enable
= s3c64xx_pclk_ctrl
,
165 .ctrlbit
= S3C6410_CLKCON_PCLK_IIS2
,
171 .enable
= s3c64xx_pclk_ctrl
,
172 .ctrlbit
= S3C_CLKCON_PCLK_SPI0
,
177 .enable
= s3c64xx_pclk_ctrl
,
178 .ctrlbit
= S3C_CLKCON_PCLK_SPI1
,
183 .enable
= s3c64xx_sclk_ctrl
,
184 .ctrlbit
= S3C_CLKCON_SCLK_SPI0_48
,
189 .enable
= s3c64xx_sclk_ctrl
,
190 .ctrlbit
= S3C_CLKCON_SCLK_SPI1_48
,
195 .enable
= s3c64xx_sclk_ctrl
,
196 .ctrlbit
= S3C_CLKCON_SCLK_MMC0_48
,
201 .enable
= s3c64xx_sclk_ctrl
,
202 .ctrlbit
= S3C_CLKCON_SCLK_MMC1_48
,
207 .enable
= s3c64xx_sclk_ctrl
,
208 .ctrlbit
= S3C_CLKCON_SCLK_MMC2_48
,
213 .enable
= s3c64xx_hclk_ctrl
,
214 .ctrlbit
= S3C_CLKCON_HCLK_DMA0
,
219 .enable
= s3c64xx_hclk_ctrl
,
220 .ctrlbit
= S3C_CLKCON_HCLK_DMA1
,
224 static struct clk init_clocks
[] = {
229 .enable
= s3c64xx_hclk_ctrl
,
230 .ctrlbit
= S3C_CLKCON_HCLK_LCD
,
235 .enable
= s3c64xx_pclk_ctrl
,
236 .ctrlbit
= S3C_CLKCON_PCLK_GPIO
,
241 .enable
= s3c64xx_hclk_ctrl
,
242 .ctrlbit
= S3C_CLKCON_HCLK_UHOST
,
247 .enable
= s3c64xx_hclk_ctrl
,
248 .ctrlbit
= S3C_CLKCON_HCLK_HSMMC0
,
253 .enable
= s3c64xx_hclk_ctrl
,
254 .ctrlbit
= S3C_CLKCON_HCLK_HSMMC1
,
259 .enable
= s3c64xx_hclk_ctrl
,
260 .ctrlbit
= S3C_CLKCON_HCLK_HSMMC2
,
265 .enable
= s3c64xx_pclk_ctrl
,
266 .ctrlbit
= S3C_CLKCON_PCLK_PWM
,
271 .enable
= s3c64xx_pclk_ctrl
,
272 .ctrlbit
= S3C_CLKCON_PCLK_UART0
,
277 .enable
= s3c64xx_pclk_ctrl
,
278 .ctrlbit
= S3C_CLKCON_PCLK_UART1
,
283 .enable
= s3c64xx_pclk_ctrl
,
284 .ctrlbit
= S3C_CLKCON_PCLK_UART2
,
289 .enable
= s3c64xx_pclk_ctrl
,
290 .ctrlbit
= S3C_CLKCON_PCLK_UART3
,
295 .enable
= s3c64xx_pclk_ctrl
,
296 .ctrlbit
= S3C_CLKCON_PCLK_RTC
,
301 .ctrlbit
= S3C_CLKCON_PCLK_WDT
,
306 .ctrlbit
= S3C_CLKCON_PCLK_AC97
,
311 static struct clk clk_fout_apll
= {
316 static struct clk
*clk_src_apll_list
[] = {
318 [1] = &clk_fout_apll
,
321 static struct clksrc_sources clk_src_apll
= {
322 .sources
= clk_src_apll_list
,
323 .nr_sources
= ARRAY_SIZE(clk_src_apll_list
),
326 static struct clksrc_clk clk_mout_apll
= {
331 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 0, .size
= 1 },
332 .sources
= &clk_src_apll
,
335 static struct clk
*clk_src_epll_list
[] = {
337 [1] = &clk_fout_epll
,
340 static struct clksrc_sources clk_src_epll
= {
341 .sources
= clk_src_epll_list
,
342 .nr_sources
= ARRAY_SIZE(clk_src_epll_list
),
345 static struct clksrc_clk clk_mout_epll
= {
350 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 2, .size
= 1 },
351 .sources
= &clk_src_epll
,
354 static struct clk
*clk_src_mpll_list
[] = {
356 [1] = &clk_fout_mpll
,
359 static struct clksrc_sources clk_src_mpll
= {
360 .sources
= clk_src_mpll_list
,
361 .nr_sources
= ARRAY_SIZE(clk_src_mpll_list
),
364 static struct clksrc_clk clk_mout_mpll
= {
369 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 1, .size
= 1 },
370 .sources
= &clk_src_mpll
,
373 static unsigned int armclk_mask
;
375 static unsigned long s3c64xx_clk_arm_get_rate(struct clk
*clk
)
377 unsigned long rate
= clk_get_rate(clk
->parent
);
380 /* divisor mask starts at bit0, so no need to shift */
381 clkdiv
= __raw_readl(S3C_CLK_DIV0
) & armclk_mask
;
383 return rate
/ (clkdiv
+ 1);
386 static unsigned long s3c64xx_clk_arm_round_rate(struct clk
*clk
,
389 unsigned long parent
= clk_get_rate(clk
->parent
);
395 div
= (parent
/ rate
) - 1;
396 if (div
> armclk_mask
)
399 return parent
/ (div
+ 1);
402 static int s3c64xx_clk_arm_set_rate(struct clk
*clk
, unsigned long rate
)
404 unsigned long parent
= clk_get_rate(clk
->parent
);
408 if (rate
< parent
/ (armclk_mask
+ 1))
411 rate
= clk_round_rate(clk
, rate
);
412 div
= clk_get_rate(clk
->parent
) / rate
;
414 val
= __raw_readl(S3C_CLK_DIV0
);
417 __raw_writel(val
, S3C_CLK_DIV0
);
423 static struct clk clk_arm
= {
426 .parent
= &clk_mout_apll
.clk
,
427 .ops
= &(struct clk_ops
) {
428 .get_rate
= s3c64xx_clk_arm_get_rate
,
429 .set_rate
= s3c64xx_clk_arm_set_rate
,
430 .round_rate
= s3c64xx_clk_arm_round_rate
,
434 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk
*clk
)
436 unsigned long rate
= clk_get_rate(clk
->parent
);
438 printk(KERN_DEBUG
"%s: parent is %ld\n", __func__
, rate
);
440 if (__raw_readl(S3C_CLK_DIV0
) & S3C6400_CLKDIV0_MPLL_MASK
)
446 static struct clk_ops clk_dout_ops
= {
447 .get_rate
= s3c64xx_clk_doutmpll_get_rate
,
450 static struct clk clk_dout_mpll
= {
453 .parent
= &clk_mout_mpll
.clk
,
454 .ops
= &clk_dout_ops
,
457 static struct clk
*clkset_spi_mmc_list
[] = {
464 static struct clksrc_sources clkset_spi_mmc
= {
465 .sources
= clkset_spi_mmc_list
,
466 .nr_sources
= ARRAY_SIZE(clkset_spi_mmc_list
),
469 static struct clk
*clkset_irda_list
[] = {
476 static struct clksrc_sources clkset_irda
= {
477 .sources
= clkset_irda_list
,
478 .nr_sources
= ARRAY_SIZE(clkset_irda_list
),
481 static struct clk
*clkset_uart_list
[] = {
488 static struct clksrc_sources clkset_uart
= {
489 .sources
= clkset_uart_list
,
490 .nr_sources
= ARRAY_SIZE(clkset_uart_list
),
493 static struct clk
*clkset_uhost_list
[] = {
500 static struct clksrc_sources clkset_uhost
= {
501 .sources
= clkset_uhost_list
,
502 .nr_sources
= ARRAY_SIZE(clkset_uhost_list
),
505 /* The peripheral clocks are all controlled via clocksource followed
506 * by an optional divider and gate stage. We currently roll this into
507 * one clock which hides the intermediate clock from the mux.
509 * Note, the JPEG clock can only be an even divider...
511 * The scaler and LCD clocks depend on the S3C64XX version, and also
512 * have a common parent divisor so are not included here.
515 /* clocks that feed other parts of the clock source tree */
517 static struct clk clk_iis_cd0
= {
518 .name
= "iis_cdclk0",
522 static struct clk clk_iis_cd1
= {
523 .name
= "iis_cdclk1",
527 static struct clk clk_iisv4_cd
= {
528 .name
= "iis_cdclk_v4",
532 static struct clk clk_pcm_cd
= {
537 static struct clk
*clkset_audio0_list
[] = {
538 [0] = &clk_mout_epll
.clk
,
539 [1] = &clk_dout_mpll
,
545 static struct clksrc_sources clkset_audio0
= {
546 .sources
= clkset_audio0_list
,
547 .nr_sources
= ARRAY_SIZE(clkset_audio0_list
),
550 static struct clk
*clkset_audio1_list
[] = {
551 [0] = &clk_mout_epll
.clk
,
552 [1] = &clk_dout_mpll
,
558 static struct clksrc_sources clkset_audio1
= {
559 .sources
= clkset_audio1_list
,
560 .nr_sources
= ARRAY_SIZE(clkset_audio1_list
),
563 static struct clk
*clkset_audio2_list
[] = {
564 [0] = &clk_mout_epll
.clk
,
565 [1] = &clk_dout_mpll
,
571 static struct clksrc_sources clkset_audio2
= {
572 .sources
= clkset_audio2_list
,
573 .nr_sources
= ARRAY_SIZE(clkset_audio2_list
),
576 static struct clk
*clkset_camif_list
[] = {
580 static struct clksrc_sources clkset_camif
= {
581 .sources
= clkset_camif_list
,
582 .nr_sources
= ARRAY_SIZE(clkset_camif_list
),
585 static struct clksrc_clk clksrcs
[] = {
590 .ctrlbit
= S3C_CLKCON_SCLK_MMC0
,
591 .enable
= s3c64xx_sclk_ctrl
,
593 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 18, .size
= 2 },
594 .reg_div
= { .reg
= S3C_CLK_DIV1
, .shift
= 0, .size
= 4 },
595 .sources
= &clkset_spi_mmc
,
600 .ctrlbit
= S3C_CLKCON_SCLK_MMC1
,
601 .enable
= s3c64xx_sclk_ctrl
,
603 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 20, .size
= 2 },
604 .reg_div
= { .reg
= S3C_CLK_DIV1
, .shift
= 4, .size
= 4 },
605 .sources
= &clkset_spi_mmc
,
610 .ctrlbit
= S3C_CLKCON_SCLK_MMC2
,
611 .enable
= s3c64xx_sclk_ctrl
,
613 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 22, .size
= 2 },
614 .reg_div
= { .reg
= S3C_CLK_DIV1
, .shift
= 8, .size
= 4 },
615 .sources
= &clkset_spi_mmc
,
618 .name
= "usb-bus-host",
620 .ctrlbit
= S3C_CLKCON_SCLK_UHOST
,
621 .enable
= s3c64xx_sclk_ctrl
,
623 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 5, .size
= 2 },
624 .reg_div
= { .reg
= S3C_CLK_DIV1
, .shift
= 20, .size
= 4 },
625 .sources
= &clkset_uhost
,
630 .ctrlbit
= S3C_CLKCON_SCLK_UART
,
631 .enable
= s3c64xx_sclk_ctrl
,
633 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 13, .size
= 1 },
634 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 16, .size
= 4 },
635 .sources
= &clkset_uart
,
637 /* Where does UCLK0 come from? */
641 .ctrlbit
= S3C_CLKCON_SCLK_SPI0
,
642 .enable
= s3c64xx_sclk_ctrl
,
644 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 14, .size
= 2 },
645 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 0, .size
= 4 },
646 .sources
= &clkset_spi_mmc
,
651 .ctrlbit
= S3C_CLKCON_SCLK_SPI1
,
652 .enable
= s3c64xx_sclk_ctrl
,
654 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 16, .size
= 2 },
655 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 4, .size
= 4 },
656 .sources
= &clkset_spi_mmc
,
661 .ctrlbit
= S3C_CLKCON_SCLK_AUDIO0
,
662 .enable
= s3c64xx_sclk_ctrl
,
664 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 7, .size
= 3 },
665 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 8, .size
= 4 },
666 .sources
= &clkset_audio0
,
671 .ctrlbit
= S3C_CLKCON_SCLK_AUDIO1
,
672 .enable
= s3c64xx_sclk_ctrl
,
674 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 10, .size
= 3 },
675 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 12, .size
= 4 },
676 .sources
= &clkset_audio1
,
680 .id
= -1, /* There's only one IISv4 port */
681 .ctrlbit
= S3C6410_CLKCON_SCLK_AUDIO2
,
682 .enable
= s3c64xx_sclk_ctrl
,
684 .reg_src
= { .reg
= S3C6410_CLK_SRC2
, .shift
= 0, .size
= 3 },
685 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 24, .size
= 4 },
686 .sources
= &clkset_audio2
,
691 .ctrlbit
= S3C_CLKCON_SCLK_IRDA
,
692 .enable
= s3c64xx_sclk_ctrl
,
694 .reg_src
= { .reg
= S3C_CLK_SRC
, .shift
= 24, .size
= 2 },
695 .reg_div
= { .reg
= S3C_CLK_DIV2
, .shift
= 20, .size
= 4 },
696 .sources
= &clkset_irda
,
701 .ctrlbit
= S3C_CLKCON_SCLK_CAM
,
702 .enable
= s3c64xx_sclk_ctrl
,
704 .reg_div
= { .reg
= S3C_CLK_DIV0
, .shift
= 20, .size
= 4 },
705 .reg_src
= { .reg
= NULL
, .shift
= 0, .size
= 0 },
706 .sources
= &clkset_camif
,
710 /* Clock initialisation code */
712 static struct clksrc_clk
*init_parents
[] = {
718 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
720 void __init_or_cpufreq
s3c6400_setup_clocks(void)
722 struct clk
*xtal_clk
;
734 printk(KERN_DEBUG
"%s: registering clocks\n", __func__
);
736 clkdiv0
= __raw_readl(S3C_CLK_DIV0
);
737 printk(KERN_DEBUG
"%s: clkdiv0 = %08x\n", __func__
, clkdiv0
);
739 xtal_clk
= clk_get(NULL
, "xtal");
740 BUG_ON(IS_ERR(xtal_clk
));
742 xtal
= clk_get_rate(xtal_clk
);
745 printk(KERN_DEBUG
"%s: xtal is %ld\n", __func__
, xtal
);
747 /* For now assume the mux always selects the crystal */
748 clk_ext_xtal_mux
.parent
= xtal_clk
;
750 epll
= s3c6400_get_epll(xtal
);
751 mpll
= s3c6400_get_pll(xtal
, __raw_readl(S3C_MPLL_CON
));
752 apll
= s3c6400_get_pll(xtal
, __raw_readl(S3C_APLL_CON
));
756 printk(KERN_INFO
"S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
759 hclk2
= mpll
/ GET_DIV(clkdiv0
, S3C6400_CLKDIV0_HCLK2
);
760 hclk
= hclk2
/ GET_DIV(clkdiv0
, S3C6400_CLKDIV0_HCLK
);
761 pclk
= hclk2
/ GET_DIV(clkdiv0
, S3C6400_CLKDIV0_PCLK
);
763 printk(KERN_INFO
"S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
766 clk_fout_mpll
.rate
= mpll
;
767 clk_fout_epll
.rate
= epll
;
768 clk_fout_apll
.rate
= apll
;
775 for (ptr
= 0; ptr
< ARRAY_SIZE(init_parents
); ptr
++)
776 s3c_set_clksrc(init_parents
[ptr
], true);
778 for (ptr
= 0; ptr
< ARRAY_SIZE(clksrcs
); ptr
++)
779 s3c_set_clksrc(&clksrcs
[ptr
], true);
782 static struct clk
*clks1
[] __initdata
= {
794 static struct clk
*clks
[] __initdata
= {
804 * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
805 * @xtal: The rate for the clock crystal feeding the PLLs.
806 * @armclk_divlimit: Divisor mask for ARMCLK.
808 * Register the clocks for the S3C6400 and S3C6410 SoC range, such
809 * as ARMCLK as well as the necessary parent clocks.
811 * This call does not setup the clocks, which is left to the
812 * s3c6400_setup_clocks() call which may be needed by the cpufreq
813 * or resume code to re-set the clocks if the bootloader has changed
816 void __init
s3c64xx_register_clocks(unsigned long xtal
,
817 unsigned armclk_divlimit
)
823 armclk_mask
= armclk_divlimit
;
825 s3c24xx_register_baseclocks(xtal
);
826 s3c24xx_register_clocks(clks
, ARRAY_SIZE(clks
));
828 s3c_register_clocks(init_clocks
, ARRAY_SIZE(init_clocks
));
830 clkp
= init_clocks_disable
;
831 for (ptr
= 0; ptr
< ARRAY_SIZE(init_clocks_disable
); ptr
++, clkp
++) {
833 ret
= s3c24xx_register_clock(clkp
);
835 printk(KERN_ERR
"Failed to register clock %s (%d)\n",
839 (clkp
->enable
)(clkp
, 0);
842 s3c24xx_register_clocks(clks1
, ARRAY_SIZE(clks1
));
843 s3c_register_clksrc(clksrcs
, ARRAY_SIZE(clksrcs
));