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USB: cp210x: call generic open last in open
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / tty / serial / 8250.c
blobeeadf1b8e093202234b30c688490da2de10a3c04
1 /*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #define SUPPORT_SYSRQ
21 #endif
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
41
42 #include <asm/io.h>
43 #include <asm/irq.h>
44
45 #include "8250.h"
46
47 #ifdef CONFIG_SPARC
48 #include "suncore.h"
49 #endif
50
51 /*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60 static struct uart_driver serial8250_reg;
61
62 static int serial_index(struct uart_port *port)
63 {
64 return (serial8250_reg.minor - 64) + port->line;
65 }
66
67 static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
69 /*
70 * Debugging.
71 */
72 #if 0
73 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
74 #else
75 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
76 #endif
77
78 #if 0
79 #define DEBUG_INTR(fmt...) printk(fmt)
80 #else
81 #define DEBUG_INTR(fmt...) do { } while (0)
82 #endif
83
84 #define PASS_LIMIT 512
85
86 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
89 /*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94 #define is_real_interrupt(irq) ((irq) != 0)
95
96 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97 #define CONFIG_SERIAL_DETECT_IRQ 1
98 #endif
99 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
100 #define CONFIG_SERIAL_MANY_PORTS 1
101 #endif
102
103 /*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107 #define CONFIG_HUB6 1
108
109 #include <asm/serial.h>
110 /*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115 #ifndef SERIAL_PORT_DFNS
116 #define SERIAL_PORT_DFNS
117 #endif
118
119 static const struct old_serial_port old_serial_port[] = {
120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121 };
122
123 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
124
125 #ifdef CONFIG_SERIAL_8250_RSA
126
127 #define PORT_RSA_MAX 4
128 static unsigned long probe_rsa[PORT_RSA_MAX];
129 static unsigned int probe_rsa_count;
130 #endif /* CONFIG_SERIAL_8250_RSA */
131
132 struct uart_8250_port {
133 struct uart_port port;
134 struct timer_list timer; /* "no irq" timer */
135 struct list_head list; /* ports on this IRQ */
136 unsigned short capabilities; /* port capabilities */
137 unsigned short bugs; /* port bugs */
138 unsigned int tx_loadsz; /* transmit fifo load size */
139 unsigned char acr;
140 unsigned char ier;
141 unsigned char lcr;
142 unsigned char mcr;
143 unsigned char mcr_mask; /* mask of user bits */
144 unsigned char mcr_force; /* mask of forced bits */
145 unsigned char cur_iotype; /* Running I/O type */
146
147 /*
148 * Some bits in registers are cleared on a read, so they must
149 * be saved whenever the register is read but the bits will not
150 * be immediately processed.
151 */
152 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 unsigned char lsr_saved_flags;
154 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 unsigned char msr_saved_flags;
156 };
157
158 struct irq_info {
159 struct hlist_node node;
160 int irq;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
163 };
164
165 #define NR_IRQ_HASH 32 /* Can be adjusted later */
166 static struct hlist_head irq_lists[NR_IRQ_HASH];
167 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
168
169 /*
170 * Here we define the default xmit fifo size used for each type of UART.
171 */
172 static const struct serial8250_config uart_config[] = {
173 [PORT_UNKNOWN] = {
174 .name = "unknown",
175 .fifo_size = 1,
176 .tx_loadsz = 1,
177 },
178 [PORT_8250] = {
179 .name = "8250",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16450] = {
184 .name = "16450",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16550] = {
189 .name = "16550",
190 .fifo_size = 1,
191 .tx_loadsz = 1,
192 },
193 [PORT_16550A] = {
194 .name = "16550A",
195 .fifo_size = 16,
196 .tx_loadsz = 16,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
199 },
200 [PORT_CIRRUS] = {
201 .name = "Cirrus",
202 .fifo_size = 1,
203 .tx_loadsz = 1,
204 },
205 [PORT_16650] = {
206 .name = "ST16650",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
210 },
211 [PORT_16650V2] = {
212 .name = "ST16650V2",
213 .fifo_size = 32,
214 .tx_loadsz = 16,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
216 UART_FCR_T_TRIG_00,
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 },
219 [PORT_16750] = {
220 .name = "TI16750",
221 .fifo_size = 64,
222 .tx_loadsz = 64,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
224 UART_FCR7_64BYTE,
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
226 },
227 [PORT_STARTECH] = {
228 .name = "Startech",
229 .fifo_size = 1,
230 .tx_loadsz = 1,
231 },
232 [PORT_16C950] = {
233 .name = "16C950/954",
234 .fifo_size = 128,
235 .tx_loadsz = 128,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
238 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
239 },
240 [PORT_16654] = {
241 .name = "ST16654",
242 .fifo_size = 64,
243 .tx_loadsz = 32,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
245 UART_FCR_T_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
247 },
248 [PORT_16850] = {
249 .name = "XR16850",
250 .fifo_size = 128,
251 .tx_loadsz = 128,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
254 },
255 [PORT_RSA] = {
256 .name = "RSA",
257 .fifo_size = 2048,
258 .tx_loadsz = 2048,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
261 },
262 [PORT_NS16550A] = {
263 .name = "NS16550A",
264 .fifo_size = 16,
265 .tx_loadsz = 16,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
268 },
269 [PORT_XSCALE] = {
270 .name = "XScale",
271 .fifo_size = 32,
272 .tx_loadsz = 32,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
275 },
276 [PORT_RM9000] = {
277 .name = "RM9000",
278 .fifo_size = 16,
279 .tx_loadsz = 16,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO,
282 },
283 [PORT_OCTEON] = {
284 .name = "OCTEON",
285 .fifo_size = 64,
286 .tx_loadsz = 64,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .flags = UART_CAP_FIFO,
289 },
290 [PORT_AR7] = {
291 .name = "AR7",
292 .fifo_size = 16,
293 .tx_loadsz = 16,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
296 },
297 [PORT_U6_16550A] = {
298 .name = "U6_16550A",
299 .fifo_size = 64,
300 .tx_loadsz = 64,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
303 },
304 [PORT_TEGRA] = {
305 .name = "Tegra",
306 .fifo_size = 32,
307 .tx_loadsz = 8,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
309 UART_FCR_T_TRIG_01,
310 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
311 },
312 [PORT_XR17D15X] = {
313 .name = "XR17D15X",
314 .fifo_size = 64,
315 .tx_loadsz = 64,
316 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
317 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
318 },
319 };
320
321 #if defined(CONFIG_MIPS_ALCHEMY)
322
323 /* Au1x00 UART hardware has a weird register layout */
324 static const u8 au_io_in_map[] = {
325 [UART_RX] = 0,
326 [UART_IER] = 2,
327 [UART_IIR] = 3,
328 [UART_LCR] = 5,
329 [UART_MCR] = 6,
330 [UART_LSR] = 7,
331 [UART_MSR] = 8,
332 };
333
334 static const u8 au_io_out_map[] = {
335 [UART_TX] = 1,
336 [UART_IER] = 2,
337 [UART_FCR] = 4,
338 [UART_LCR] = 5,
339 [UART_MCR] = 6,
340 };
341
342 /* sane hardware needs no mapping */
343 static inline int map_8250_in_reg(struct uart_port *p, int offset)
344 {
345 if (p->iotype != UPIO_AU)
346 return offset;
347 return au_io_in_map[offset];
348 }
349
350 static inline int map_8250_out_reg(struct uart_port *p, int offset)
351 {
352 if (p->iotype != UPIO_AU)
353 return offset;
354 return au_io_out_map[offset];
355 }
356
357 #elif defined(CONFIG_SERIAL_8250_RM9K)
358
359 static const u8
360 regmap_in[8] = {
361 [UART_RX] = 0x00,
362 [UART_IER] = 0x0c,
363 [UART_IIR] = 0x14,
364 [UART_LCR] = 0x1c,
365 [UART_MCR] = 0x20,
366 [UART_LSR] = 0x24,
367 [UART_MSR] = 0x28,
368 [UART_SCR] = 0x2c
369 },
370 regmap_out[8] = {
371 [UART_TX] = 0x04,
372 [UART_IER] = 0x0c,
373 [UART_FCR] = 0x18,
374 [UART_LCR] = 0x1c,
375 [UART_MCR] = 0x20,
376 [UART_LSR] = 0x24,
377 [UART_MSR] = 0x28,
378 [UART_SCR] = 0x2c
379 };
380
381 static inline int map_8250_in_reg(struct uart_port *p, int offset)
382 {
383 if (p->iotype != UPIO_RM9000)
384 return offset;
385 return regmap_in[offset];
386 }
387
388 static inline int map_8250_out_reg(struct uart_port *p, int offset)
389 {
390 if (p->iotype != UPIO_RM9000)
391 return offset;
392 return regmap_out[offset];
393 }
394
395 #else
396
397 /* sane hardware needs no mapping */
398 #define map_8250_in_reg(up, offset) (offset)
399 #define map_8250_out_reg(up, offset) (offset)
400
401 #endif
402
403 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
404 {
405 offset = map_8250_in_reg(p, offset) << p->regshift;
406 outb(p->hub6 - 1 + offset, p->iobase);
407 return inb(p->iobase + 1);
408 }
409
410 static void hub6_serial_out(struct uart_port *p, int offset, int value)
411 {
412 offset = map_8250_out_reg(p, offset) << p->regshift;
413 outb(p->hub6 - 1 + offset, p->iobase);
414 outb(value, p->iobase + 1);
415 }
416
417 static unsigned int mem_serial_in(struct uart_port *p, int offset)
418 {
419 offset = map_8250_in_reg(p, offset) << p->regshift;
420 return readb(p->membase + offset);
421 }
422
423 static void mem_serial_out(struct uart_port *p, int offset, int value)
424 {
425 offset = map_8250_out_reg(p, offset) << p->regshift;
426 writeb(value, p->membase + offset);
427 }
428
429 static void mem32_serial_out(struct uart_port *p, int offset, int value)
430 {
431 offset = map_8250_out_reg(p, offset) << p->regshift;
432 writel(value, p->membase + offset);
433 }
434
435 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
436 {
437 offset = map_8250_in_reg(p, offset) << p->regshift;
438 return readl(p->membase + offset);
439 }
440
441 static unsigned int au_serial_in(struct uart_port *p, int offset)
442 {
443 offset = map_8250_in_reg(p, offset) << p->regshift;
444 return __raw_readl(p->membase + offset);
445 }
446
447 static void au_serial_out(struct uart_port *p, int offset, int value)
448 {
449 offset = map_8250_out_reg(p, offset) << p->regshift;
450 __raw_writel(value, p->membase + offset);
451 }
452
453 static unsigned int io_serial_in(struct uart_port *p, int offset)
454 {
455 offset = map_8250_in_reg(p, offset) << p->regshift;
456 return inb(p->iobase + offset);
457 }
458
459 static void io_serial_out(struct uart_port *p, int offset, int value)
460 {
461 offset = map_8250_out_reg(p, offset) << p->regshift;
462 outb(value, p->iobase + offset);
463 }
464
465 static int serial8250_default_handle_irq(struct uart_port *port);
466
467 static void set_io_from_upio(struct uart_port *p)
468 {
469 struct uart_8250_port *up =
470 container_of(p, struct uart_8250_port, port);
471 switch (p->iotype) {
472 case UPIO_HUB6:
473 p->serial_in = hub6_serial_in;
474 p->serial_out = hub6_serial_out;
475 break;
476
477 case UPIO_MEM:
478 p->serial_in = mem_serial_in;
479 p->serial_out = mem_serial_out;
480 break;
481
482 case UPIO_RM9000:
483 case UPIO_MEM32:
484 p->serial_in = mem32_serial_in;
485 p->serial_out = mem32_serial_out;
486 break;
487
488 case UPIO_AU:
489 p->serial_in = au_serial_in;
490 p->serial_out = au_serial_out;
491 break;
492
493 default:
494 p->serial_in = io_serial_in;
495 p->serial_out = io_serial_out;
496 break;
497 }
498 /* Remember loaded iotype */
499 up->cur_iotype = p->iotype;
500 p->handle_irq = serial8250_default_handle_irq;
501 }
502
503 static void
504 serial_out_sync(struct uart_8250_port *up, int offset, int value)
505 {
506 struct uart_port *p = &up->port;
507 switch (p->iotype) {
508 case UPIO_MEM:
509 case UPIO_MEM32:
510 case UPIO_AU:
511 p->serial_out(p, offset, value);
512 p->serial_in(p, UART_LCR); /* safe, no side-effects */
513 break;
514 default:
515 p->serial_out(p, offset, value);
516 }
517 }
518
519 #define serial_in(up, offset) \
520 (up->port.serial_in(&(up)->port, (offset)))
521 #define serial_out(up, offset, value) \
522 (up->port.serial_out(&(up)->port, (offset), (value)))
523 /*
524 * We used to support using pause I/O for certain machines. We
525 * haven't supported this for a while, but just in case it's badly
526 * needed for certain old 386 machines, I've left these #define's
527 * in....
528 */
529 #define serial_inp(up, offset) serial_in(up, offset)
530 #define serial_outp(up, offset, value) serial_out(up, offset, value)
531
532 /* Uart divisor latch read */
533 static inline int _serial_dl_read(struct uart_8250_port *up)
534 {
535 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
536 }
537
538 /* Uart divisor latch write */
539 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
540 {
541 serial_outp(up, UART_DLL, value & 0xff);
542 serial_outp(up, UART_DLM, value >> 8 & 0xff);
543 }
544
545 #if defined(CONFIG_MIPS_ALCHEMY)
546 /* Au1x00 haven't got a standard divisor latch */
547 static int serial_dl_read(struct uart_8250_port *up)
548 {
549 if (up->port.iotype == UPIO_AU)
550 return __raw_readl(up->port.membase + 0x28);
551 else
552 return _serial_dl_read(up);
553 }
554
555 static void serial_dl_write(struct uart_8250_port *up, int value)
556 {
557 if (up->port.iotype == UPIO_AU)
558 __raw_writel(value, up->port.membase + 0x28);
559 else
560 _serial_dl_write(up, value);
561 }
562 #elif defined(CONFIG_SERIAL_8250_RM9K)
563 static int serial_dl_read(struct uart_8250_port *up)
564 {
565 return (up->port.iotype == UPIO_RM9000) ?
566 (((__raw_readl(up->port.membase + 0x10) << 8) |
567 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
568 _serial_dl_read(up);
569 }
570
571 static void serial_dl_write(struct uart_8250_port *up, int value)
572 {
573 if (up->port.iotype == UPIO_RM9000) {
574 __raw_writel(value, up->port.membase + 0x08);
575 __raw_writel(value >> 8, up->port.membase + 0x10);
576 } else {
577 _serial_dl_write(up, value);
578 }
579 }
580 #else
581 #define serial_dl_read(up) _serial_dl_read(up)
582 #define serial_dl_write(up, value) _serial_dl_write(up, value)
583 #endif
584
585 /*
586 * For the 16C950
587 */
588 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
589 {
590 serial_out(up, UART_SCR, offset);
591 serial_out(up, UART_ICR, value);
592 }
593
594 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
595 {
596 unsigned int value;
597
598 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
599 serial_out(up, UART_SCR, offset);
600 value = serial_in(up, UART_ICR);
601 serial_icr_write(up, UART_ACR, up->acr);
602
603 return value;
604 }
605
606 /*
607 * FIFO support.
608 */
609 static void serial8250_clear_fifos(struct uart_8250_port *p)
610 {
611 if (p->capabilities & UART_CAP_FIFO) {
612 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
613 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
614 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
615 serial_outp(p, UART_FCR, 0);
616 }
617 }
618
619 /*
620 * IER sleep support. UARTs which have EFRs need the "extended
621 * capability" bit enabled. Note that on XR16C850s, we need to
622 * reset LCR to write to IER.
623 */
624 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
625 {
626 if (p->capabilities & UART_CAP_SLEEP) {
627 if (p->capabilities & UART_CAP_EFR) {
628 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
629 serial_outp(p, UART_EFR, UART_EFR_ECB);
630 serial_outp(p, UART_LCR, 0);
631 }
632 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
633 if (p->capabilities & UART_CAP_EFR) {
634 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
635 serial_outp(p, UART_EFR, 0);
636 serial_outp(p, UART_LCR, 0);
637 }
638 }
639 }
640
641 #ifdef CONFIG_SERIAL_8250_RSA
642 /*
643 * Attempts to turn on the RSA FIFO. Returns zero on failure.
644 * We set the port uart clock rate if we succeed.
645 */
646 static int __enable_rsa(struct uart_8250_port *up)
647 {
648 unsigned char mode;
649 int result;
650
651 mode = serial_inp(up, UART_RSA_MSR);
652 result = mode & UART_RSA_MSR_FIFO;
653
654 if (!result) {
655 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
656 mode = serial_inp(up, UART_RSA_MSR);
657 result = mode & UART_RSA_MSR_FIFO;
658 }
659
660 if (result)
661 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
662
663 return result;
664 }
665
666 static void enable_rsa(struct uart_8250_port *up)
667 {
668 if (up->port.type == PORT_RSA) {
669 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
670 spin_lock_irq(&up->port.lock);
671 __enable_rsa(up);
672 spin_unlock_irq(&up->port.lock);
673 }
674 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
675 serial_outp(up, UART_RSA_FRR, 0);
676 }
677 }
678
679 /*
680 * Attempts to turn off the RSA FIFO. Returns zero on failure.
681 * It is unknown why interrupts were disabled in here. However,
682 * the caller is expected to preserve this behaviour by grabbing
683 * the spinlock before calling this function.
684 */
685 static void disable_rsa(struct uart_8250_port *up)
686 {
687 unsigned char mode;
688 int result;
689
690 if (up->port.type == PORT_RSA &&
691 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
692 spin_lock_irq(&up->port.lock);
693
694 mode = serial_inp(up, UART_RSA_MSR);
695 result = !(mode & UART_RSA_MSR_FIFO);
696
697 if (!result) {
698 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
699 mode = serial_inp(up, UART_RSA_MSR);
700 result = !(mode & UART_RSA_MSR_FIFO);
701 }
702
703 if (result)
704 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
705 spin_unlock_irq(&up->port.lock);
706 }
707 }
708 #endif /* CONFIG_SERIAL_8250_RSA */
709
710 /*
711 * This is a quickie test to see how big the FIFO is.
712 * It doesn't work at all the time, more's the pity.
713 */
714 static int size_fifo(struct uart_8250_port *up)
715 {
716 unsigned char old_fcr, old_mcr, old_lcr;
717 unsigned short old_dl;
718 int count;
719
720 old_lcr = serial_inp(up, UART_LCR);
721 serial_outp(up, UART_LCR, 0);
722 old_fcr = serial_inp(up, UART_FCR);
723 old_mcr = serial_inp(up, UART_MCR);
724 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
725 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
726 serial_outp(up, UART_MCR, UART_MCR_LOOP);
727 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
728 old_dl = serial_dl_read(up);
729 serial_dl_write(up, 0x0001);
730 serial_outp(up, UART_LCR, 0x03);
731 for (count = 0; count < 256; count++)
732 serial_outp(up, UART_TX, count);
733 mdelay(20);/* FIXME - schedule_timeout */
734 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
735 (count < 256); count++)
736 serial_inp(up, UART_RX);
737 serial_outp(up, UART_FCR, old_fcr);
738 serial_outp(up, UART_MCR, old_mcr);
739 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
740 serial_dl_write(up, old_dl);
741 serial_outp(up, UART_LCR, old_lcr);
742
743 return count;
744 }
745
746 /*
747 * Read UART ID using the divisor method - set DLL and DLM to zero
748 * and the revision will be in DLL and device type in DLM. We
749 * preserve the device state across this.
750 */
751 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
752 {
753 unsigned char old_dll, old_dlm, old_lcr;
754 unsigned int id;
755
756 old_lcr = serial_inp(p, UART_LCR);
757 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
758
759 old_dll = serial_inp(p, UART_DLL);
760 old_dlm = serial_inp(p, UART_DLM);
761
762 serial_outp(p, UART_DLL, 0);
763 serial_outp(p, UART_DLM, 0);
764
765 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
766
767 serial_outp(p, UART_DLL, old_dll);
768 serial_outp(p, UART_DLM, old_dlm);
769 serial_outp(p, UART_LCR, old_lcr);
770
771 return id;
772 }
773
774 /*
775 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
776 * When this function is called we know it is at least a StarTech
777 * 16650 V2, but it might be one of several StarTech UARTs, or one of
778 * its clones. (We treat the broken original StarTech 16650 V1 as a
779 * 16550, and why not? Startech doesn't seem to even acknowledge its
780 * existence.)
781 *
782 * What evil have men's minds wrought...
783 */
784 static void autoconfig_has_efr(struct uart_8250_port *up)
785 {
786 unsigned int id1, id2, id3, rev;
787
788 /*
789 * Everything with an EFR has SLEEP
790 */
791 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
792
793 /*
794 * First we check to see if it's an Oxford Semiconductor UART.
795 *
796 * If we have to do this here because some non-National
797 * Semiconductor clone chips lock up if you try writing to the
798 * LSR register (which serial_icr_read does)
799 */
800
801 /*
802 * Check for Oxford Semiconductor 16C950.
803 *
804 * EFR [4] must be set else this test fails.
805 *
806 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
807 * claims that it's needed for 952 dual UART's (which are not
808 * recommended for new designs).
809 */
810 up->acr = 0;
811 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
812 serial_out(up, UART_EFR, UART_EFR_ECB);
813 serial_out(up, UART_LCR, 0x00);
814 id1 = serial_icr_read(up, UART_ID1);
815 id2 = serial_icr_read(up, UART_ID2);
816 id3 = serial_icr_read(up, UART_ID3);
817 rev = serial_icr_read(up, UART_REV);
818
819 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
820
821 if (id1 == 0x16 && id2 == 0xC9 &&
822 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
823 up->port.type = PORT_16C950;
824
825 /*
826 * Enable work around for the Oxford Semiconductor 952 rev B
827 * chip which causes it to seriously miscalculate baud rates
828 * when DLL is 0.
829 */
830 if (id3 == 0x52 && rev == 0x01)
831 up->bugs |= UART_BUG_QUOT;
832 return;
833 }
834
835 /*
836 * We check for a XR16C850 by setting DLL and DLM to 0, and then
837 * reading back DLL and DLM. The chip type depends on the DLM
838 * value read back:
839 * 0x10 - XR16C850 and the DLL contains the chip revision.
840 * 0x12 - XR16C2850.
841 * 0x14 - XR16C854.
842 */
843 id1 = autoconfig_read_divisor_id(up);
844 DEBUG_AUTOCONF("850id=%04x ", id1);
845
846 id2 = id1 >> 8;
847 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
848 up->port.type = PORT_16850;
849 return;
850 }
851
852 /*
853 * It wasn't an XR16C850.
854 *
855 * We distinguish between the '654 and the '650 by counting
856 * how many bytes are in the FIFO. I'm using this for now,
857 * since that's the technique that was sent to me in the
858 * serial driver update, but I'm not convinced this works.
859 * I've had problems doing this in the past. -TYT
860 */
861 if (size_fifo(up) == 64)
862 up->port.type = PORT_16654;
863 else
864 up->port.type = PORT_16650V2;
865 }
866
867 /*
868 * We detected a chip without a FIFO. Only two fall into
869 * this category - the original 8250 and the 16450. The
870 * 16450 has a scratch register (accessible with LCR=0)
871 */
872 static void autoconfig_8250(struct uart_8250_port *up)
873 {
874 unsigned char scratch, status1, status2;
875
876 up->port.type = PORT_8250;
877
878 scratch = serial_in(up, UART_SCR);
879 serial_outp(up, UART_SCR, 0xa5);
880 status1 = serial_in(up, UART_SCR);
881 serial_outp(up, UART_SCR, 0x5a);
882 status2 = serial_in(up, UART_SCR);
883 serial_outp(up, UART_SCR, scratch);
884
885 if (status1 == 0xa5 && status2 == 0x5a)
886 up->port.type = PORT_16450;
887 }
888
889 static int broken_efr(struct uart_8250_port *up)
890 {
891 /*
892 * Exar ST16C2550 "A2" devices incorrectly detect as
893 * having an EFR, and report an ID of 0x0201. See
894 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
895 */
896 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
897 return 1;
898
899 return 0;
900 }
901
902 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
903 {
904 unsigned char status;
905
906 status = serial_in(up, 0x04); /* EXCR2 */
907 #define PRESL(x) ((x) & 0x30)
908 if (PRESL(status) == 0x10) {
909 /* already in high speed mode */
910 return 0;
911 } else {
912 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
913 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
914 serial_outp(up, 0x04, status);
915 }
916 return 1;
917 }
918
919 /*
920 * We know that the chip has FIFOs. Does it have an EFR? The
921 * EFR is located in the same register position as the IIR and
922 * we know the top two bits of the IIR are currently set. The
923 * EFR should contain zero. Try to read the EFR.
924 */
925 static void autoconfig_16550a(struct uart_8250_port *up)
926 {
927 unsigned char status1, status2;
928 unsigned int iersave;
929
930 up->port.type = PORT_16550A;
931 up->capabilities |= UART_CAP_FIFO;
932
933 /*
934 * Check for presence of the EFR when DLAB is set.
935 * Only ST16C650V1 UARTs pass this test.
936 */
937 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
938 if (serial_in(up, UART_EFR) == 0) {
939 serial_outp(up, UART_EFR, 0xA8);
940 if (serial_in(up, UART_EFR) != 0) {
941 DEBUG_AUTOCONF("EFRv1 ");
942 up->port.type = PORT_16650;
943 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
944 } else {
945 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
946 }
947 serial_outp(up, UART_EFR, 0);
948 return;
949 }
950
951 /*
952 * Maybe it requires 0xbf to be written to the LCR.
953 * (other ST16C650V2 UARTs, TI16C752A, etc)
954 */
955 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
956 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
957 DEBUG_AUTOCONF("EFRv2 ");
958 autoconfig_has_efr(up);
959 return;
960 }
961
962 /*
963 * Check for a National Semiconductor SuperIO chip.
964 * Attempt to switch to bank 2, read the value of the LOOP bit
965 * from EXCR1. Switch back to bank 0, change it in MCR. Then
966 * switch back to bank 2, read it from EXCR1 again and check
967 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
968 */
969 serial_outp(up, UART_LCR, 0);
970 status1 = serial_in(up, UART_MCR);
971 serial_outp(up, UART_LCR, 0xE0);
972 status2 = serial_in(up, 0x02); /* EXCR1 */
973
974 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
975 serial_outp(up, UART_LCR, 0);
976 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
977 serial_outp(up, UART_LCR, 0xE0);
978 status2 = serial_in(up, 0x02); /* EXCR1 */
979 serial_outp(up, UART_LCR, 0);
980 serial_outp(up, UART_MCR, status1);
981
982 if ((status2 ^ status1) & UART_MCR_LOOP) {
983 unsigned short quot;
984
985 serial_outp(up, UART_LCR, 0xE0);
986
987 quot = serial_dl_read(up);
988 quot <<= 3;
989
990 if (ns16550a_goto_highspeed(up))
991 serial_dl_write(up, quot);
992
993 serial_outp(up, UART_LCR, 0);
994
995 up->port.uartclk = 921600*16;
996 up->port.type = PORT_NS16550A;
997 up->capabilities |= UART_NATSEMI;
998 return;
999 }
1000 }
1001
1002 /*
1003 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1004 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1005 * Try setting it with and without DLAB set. Cheap clones
1006 * set bit 5 without DLAB set.
1007 */
1008 serial_outp(up, UART_LCR, 0);
1009 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1010 status1 = serial_in(up, UART_IIR) >> 5;
1011 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1012 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1013 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1014 status2 = serial_in(up, UART_IIR) >> 5;
1015 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1016 serial_outp(up, UART_LCR, 0);
1017
1018 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1019
1020 if (status1 == 6 && status2 == 7) {
1021 up->port.type = PORT_16750;
1022 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1023 return;
1024 }
1025
1026 /*
1027 * Try writing and reading the UART_IER_UUE bit (b6).
1028 * If it works, this is probably one of the Xscale platform's
1029 * internal UARTs.
1030 * We're going to explicitly set the UUE bit to 0 before
1031 * trying to write and read a 1 just to make sure it's not
1032 * already a 1 and maybe locked there before we even start start.
1033 */
1034 iersave = serial_in(up, UART_IER);
1035 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1036 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1037 /*
1038 * OK it's in a known zero state, try writing and reading
1039 * without disturbing the current state of the other bits.
1040 */
1041 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1042 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1043 /*
1044 * It's an Xscale.
1045 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1046 */
1047 DEBUG_AUTOCONF("Xscale ");
1048 up->port.type = PORT_XSCALE;
1049 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1050 return;
1051 }
1052 } else {
1053 /*
1054 * If we got here we couldn't force the IER_UUE bit to 0.
1055 * Log it and continue.
1056 */
1057 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1058 }
1059 serial_outp(up, UART_IER, iersave);
1060
1061 /*
1062 * Exar uarts have EFR in a weird location
1063 */
1064 if (up->port.flags & UPF_EXAR_EFR) {
1065 up->port.type = PORT_XR17D15X;
1066 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1067 }
1068
1069 /*
1070 * We distinguish between 16550A and U6 16550A by counting
1071 * how many bytes are in the FIFO.
1072 */
1073 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1074 up->port.type = PORT_U6_16550A;
1075 up->capabilities |= UART_CAP_AFE;
1076 }
1077 }
1078
1079 /*
1080 * This routine is called by rs_init() to initialize a specific serial
1081 * port. It determines what type of UART chip this serial port is
1082 * using: 8250, 16450, 16550, 16550A. The important question is
1083 * whether or not this UART is a 16550A or not, since this will
1084 * determine whether or not we can use its FIFO features or not.
1085 */
1086 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1087 {
1088 unsigned char status1, scratch, scratch2, scratch3;
1089 unsigned char save_lcr, save_mcr;
1090 unsigned long flags;
1091
1092 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1093 return;
1094
1095 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1096 serial_index(&up->port), up->port.iobase, up->port.membase);
1097
1098 /*
1099 * We really do need global IRQs disabled here - we're going to
1100 * be frobbing the chips IRQ enable register to see if it exists.
1101 */
1102 spin_lock_irqsave(&up->port.lock, flags);
1103
1104 up->capabilities = 0;
1105 up->bugs = 0;
1106
1107 if (!(up->port.flags & UPF_BUGGY_UART)) {
1108 /*
1109 * Do a simple existence test first; if we fail this,
1110 * there's no point trying anything else.
1111 *
1112 * 0x80 is used as a nonsense port to prevent against
1113 * false positives due to ISA bus float. The
1114 * assumption is that 0x80 is a non-existent port;
1115 * which should be safe since include/asm/io.h also
1116 * makes this assumption.
1117 *
1118 * Note: this is safe as long as MCR bit 4 is clear
1119 * and the device is in "PC" mode.
1120 */
1121 scratch = serial_inp(up, UART_IER);
1122 serial_outp(up, UART_IER, 0);
1123 #ifdef __i386__
1124 outb(0xff, 0x080);
1125 #endif
1126 /*
1127 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1128 * 16C754B) allow only to modify them if an EFR bit is set.
1129 */
1130 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1131 serial_outp(up, UART_IER, 0x0F);
1132 #ifdef __i386__
1133 outb(0, 0x080);
1134 #endif
1135 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1136 serial_outp(up, UART_IER, scratch);
1137 if (scratch2 != 0 || scratch3 != 0x0F) {
1138 /*
1139 * We failed; there's nothing here
1140 */
1141 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1142 scratch2, scratch3);
1143 goto out;
1144 }
1145 }
1146
1147 save_mcr = serial_in(up, UART_MCR);
1148 save_lcr = serial_in(up, UART_LCR);
1149
1150 /*
1151 * Check to see if a UART is really there. Certain broken
1152 * internal modems based on the Rockwell chipset fail this
1153 * test, because they apparently don't implement the loopback
1154 * test mode. So this test is skipped on the COM 1 through
1155 * COM 4 ports. This *should* be safe, since no board
1156 * manufacturer would be stupid enough to design a board
1157 * that conflicts with COM 1-4 --- we hope!
1158 */
1159 if (!(up->port.flags & UPF_SKIP_TEST)) {
1160 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1161 status1 = serial_inp(up, UART_MSR) & 0xF0;
1162 serial_outp(up, UART_MCR, save_mcr);
1163 if (status1 != 0x90) {
1164 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1165 status1);
1166 goto out;
1167 }
1168 }
1169
1170 /*
1171 * We're pretty sure there's a port here. Lets find out what
1172 * type of port it is. The IIR top two bits allows us to find
1173 * out if it's 8250 or 16450, 16550, 16550A or later. This
1174 * determines what we test for next.
1175 *
1176 * We also initialise the EFR (if any) to zero for later. The
1177 * EFR occupies the same register location as the FCR and IIR.
1178 */
1179 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1180 serial_outp(up, UART_EFR, 0);
1181 serial_outp(up, UART_LCR, 0);
1182
1183 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1184 scratch = serial_in(up, UART_IIR) >> 6;
1185
1186 DEBUG_AUTOCONF("iir=%d ", scratch);
1187
1188 switch (scratch) {
1189 case 0:
1190 autoconfig_8250(up);
1191 break;
1192 case 1:
1193 up->port.type = PORT_UNKNOWN;
1194 break;
1195 case 2:
1196 up->port.type = PORT_16550;
1197 break;
1198 case 3:
1199 autoconfig_16550a(up);
1200 break;
1201 }
1202
1203 #ifdef CONFIG_SERIAL_8250_RSA
1204 /*
1205 * Only probe for RSA ports if we got the region.
1206 */
1207 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1208 int i;
1209
1210 for (i = 0 ; i < probe_rsa_count; ++i) {
1211 if (probe_rsa[i] == up->port.iobase &&
1212 __enable_rsa(up)) {
1213 up->port.type = PORT_RSA;
1214 break;
1215 }
1216 }
1217 }
1218 #endif
1219
1220 serial_outp(up, UART_LCR, save_lcr);
1221
1222 if (up->capabilities != uart_config[up->port.type].flags) {
1223 printk(KERN_WARNING
1224 "ttyS%d: detected caps %08x should be %08x\n",
1225 serial_index(&up->port), up->capabilities,
1226 uart_config[up->port.type].flags);
1227 }
1228
1229 up->port.fifosize = uart_config[up->port.type].fifo_size;
1230 up->capabilities = uart_config[up->port.type].flags;
1231 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1232
1233 if (up->port.type == PORT_UNKNOWN)
1234 goto out;
1235
1236 /*
1237 * Reset the UART.
1238 */
1239 #ifdef CONFIG_SERIAL_8250_RSA
1240 if (up->port.type == PORT_RSA)
1241 serial_outp(up, UART_RSA_FRR, 0);
1242 #endif
1243 serial_outp(up, UART_MCR, save_mcr);
1244 serial8250_clear_fifos(up);
1245 serial_in(up, UART_RX);
1246 if (up->capabilities & UART_CAP_UUE)
1247 serial_outp(up, UART_IER, UART_IER_UUE);
1248 else
1249 serial_outp(up, UART_IER, 0);
1250
1251 out:
1252 spin_unlock_irqrestore(&up->port.lock, flags);
1253 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1254 }
1255
1256 static void autoconfig_irq(struct uart_8250_port *up)
1257 {
1258 unsigned char save_mcr, save_ier;
1259 unsigned char save_ICP = 0;
1260 unsigned int ICP = 0;
1261 unsigned long irqs;
1262 int irq;
1263
1264 if (up->port.flags & UPF_FOURPORT) {
1265 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1266 save_ICP = inb_p(ICP);
1267 outb_p(0x80, ICP);
1268 (void) inb_p(ICP);
1269 }
1270
1271 /* forget possible initially masked and pending IRQ */
1272 probe_irq_off(probe_irq_on());
1273 save_mcr = serial_inp(up, UART_MCR);
1274 save_ier = serial_inp(up, UART_IER);
1275 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1276
1277 irqs = probe_irq_on();
1278 serial_outp(up, UART_MCR, 0);
1279 udelay(10);
1280 if (up->port.flags & UPF_FOURPORT) {
1281 serial_outp(up, UART_MCR,
1282 UART_MCR_DTR | UART_MCR_RTS);
1283 } else {
1284 serial_outp(up, UART_MCR,
1285 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1286 }
1287 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1288 (void)serial_inp(up, UART_LSR);
1289 (void)serial_inp(up, UART_RX);
1290 (void)serial_inp(up, UART_IIR);
1291 (void)serial_inp(up, UART_MSR);
1292 serial_outp(up, UART_TX, 0xFF);
1293 udelay(20);
1294 irq = probe_irq_off(irqs);
1295
1296 serial_outp(up, UART_MCR, save_mcr);
1297 serial_outp(up, UART_IER, save_ier);
1298
1299 if (up->port.flags & UPF_FOURPORT)
1300 outb_p(save_ICP, ICP);
1301
1302 up->port.irq = (irq > 0) ? irq : 0;
1303 }
1304
1305 static inline void __stop_tx(struct uart_8250_port *p)
1306 {
1307 if (p->ier & UART_IER_THRI) {
1308 p->ier &= ~UART_IER_THRI;
1309 serial_out(p, UART_IER, p->ier);
1310 }
1311 }
1312
1313 static void serial8250_stop_tx(struct uart_port *port)
1314 {
1315 struct uart_8250_port *up =
1316 container_of(port, struct uart_8250_port, port);
1317
1318 __stop_tx(up);
1319
1320 /*
1321 * We really want to stop the transmitter from sending.
1322 */
1323 if (up->port.type == PORT_16C950) {
1324 up->acr |= UART_ACR_TXDIS;
1325 serial_icr_write(up, UART_ACR, up->acr);
1326 }
1327 }
1328
1329 static void transmit_chars(struct uart_8250_port *up);
1330
1331 static void serial8250_start_tx(struct uart_port *port)
1332 {
1333 struct uart_8250_port *up =
1334 container_of(port, struct uart_8250_port, port);
1335
1336 if (!(up->ier & UART_IER_THRI)) {
1337 up->ier |= UART_IER_THRI;
1338 serial_out(up, UART_IER, up->ier);
1339
1340 if (up->bugs & UART_BUG_TXEN) {
1341 unsigned char lsr;
1342 lsr = serial_in(up, UART_LSR);
1343 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1344 if ((up->port.type == PORT_RM9000) ?
1345 (lsr & UART_LSR_THRE) :
1346 (lsr & UART_LSR_TEMT))
1347 transmit_chars(up);
1348 }
1349 }
1350
1351 /*
1352 * Re-enable the transmitter if we disabled it.
1353 */
1354 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1355 up->acr &= ~UART_ACR_TXDIS;
1356 serial_icr_write(up, UART_ACR, up->acr);
1357 }
1358 }
1359
1360 static void serial8250_stop_rx(struct uart_port *port)
1361 {
1362 struct uart_8250_port *up =
1363 container_of(port, struct uart_8250_port, port);
1364
1365 up->ier &= ~UART_IER_RLSI;
1366 up->port.read_status_mask &= ~UART_LSR_DR;
1367 serial_out(up, UART_IER, up->ier);
1368 }
1369
1370 static void serial8250_enable_ms(struct uart_port *port)
1371 {
1372 struct uart_8250_port *up =
1373 container_of(port, struct uart_8250_port, port);
1374
1375 /* no MSR capabilities */
1376 if (up->bugs & UART_BUG_NOMSR)
1377 return;
1378
1379 up->ier |= UART_IER_MSI;
1380 serial_out(up, UART_IER, up->ier);
1381 }
1382
1383 /*
1384 * Clear the Tegra rx fifo after a break
1385 *
1386 * FIXME: This needs to become a port specific callback once we have a
1387 * framework for this
1388 */
1389 static void clear_rx_fifo(struct uart_8250_port *up)
1390 {
1391 unsigned int status, tmout = 10000;
1392 do {
1393 status = serial_in(up, UART_LSR);
1394 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1395 status = serial_in(up, UART_RX);
1396 else
1397 break;
1398 if (--tmout == 0)
1399 break;
1400 udelay(1);
1401 } while (1);
1402 }
1403
1404 static void
1405 receive_chars(struct uart_8250_port *up, unsigned int *status)
1406 {
1407 struct tty_struct *tty = up->port.state->port.tty;
1408 unsigned char ch, lsr = *status;
1409 int max_count = 256;
1410 char flag;
1411
1412 do {
1413 if (likely(lsr & UART_LSR_DR))
1414 ch = serial_inp(up, UART_RX);
1415 else
1416 /*
1417 * Intel 82571 has a Serial Over Lan device that will
1418 * set UART_LSR_BI without setting UART_LSR_DR when
1419 * it receives a break. To avoid reading from the
1420 * receive buffer without UART_LSR_DR bit set, we
1421 * just force the read character to be 0
1422 */
1423 ch = 0;
1424
1425 flag = TTY_NORMAL;
1426 up->port.icount.rx++;
1427
1428 lsr |= up->lsr_saved_flags;
1429 up->lsr_saved_flags = 0;
1430
1431 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1432 /*
1433 * For statistics only
1434 */
1435 if (lsr & UART_LSR_BI) {
1436 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1437 up->port.icount.brk++;
1438 /*
1439 * If tegra port then clear the rx fifo to
1440 * accept another break/character.
1441 */
1442 if (up->port.type == PORT_TEGRA)
1443 clear_rx_fifo(up);
1444
1445 /*
1446 * We do the SysRQ and SAK checking
1447 * here because otherwise the break
1448 * may get masked by ignore_status_mask
1449 * or read_status_mask.
1450 */
1451 if (uart_handle_break(&up->port))
1452 goto ignore_char;
1453 } else if (lsr & UART_LSR_PE)
1454 up->port.icount.parity++;
1455 else if (lsr & UART_LSR_FE)
1456 up->port.icount.frame++;
1457 if (lsr & UART_LSR_OE)
1458 up->port.icount.overrun++;
1459
1460 /*
1461 * Mask off conditions which should be ignored.
1462 */
1463 lsr &= up->port.read_status_mask;
1464
1465 if (lsr & UART_LSR_BI) {
1466 DEBUG_INTR("handling break....");
1467 flag = TTY_BREAK;
1468 } else if (lsr & UART_LSR_PE)
1469 flag = TTY_PARITY;
1470 else if (lsr & UART_LSR_FE)
1471 flag = TTY_FRAME;
1472 }
1473 if (uart_handle_sysrq_char(&up->port, ch))
1474 goto ignore_char;
1475
1476 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1477
1478 ignore_char:
1479 lsr = serial_inp(up, UART_LSR);
1480 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1481 spin_unlock(&up->port.lock);
1482 tty_flip_buffer_push(tty);
1483 spin_lock(&up->port.lock);
1484 *status = lsr;
1485 }
1486
1487 static void transmit_chars(struct uart_8250_port *up)
1488 {
1489 struct circ_buf *xmit = &up->port.state->xmit;
1490 int count;
1491
1492 if (up->port.x_char) {
1493 serial_outp(up, UART_TX, up->port.x_char);
1494 up->port.icount.tx++;
1495 up->port.x_char = 0;
1496 return;
1497 }
1498 if (uart_tx_stopped(&up->port)) {
1499 serial8250_stop_tx(&up->port);
1500 return;
1501 }
1502 if (uart_circ_empty(xmit)) {
1503 __stop_tx(up);
1504 return;
1505 }
1506
1507 count = up->tx_loadsz;
1508 do {
1509 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1510 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1511 up->port.icount.tx++;
1512 if (uart_circ_empty(xmit))
1513 break;
1514 } while (--count > 0);
1515
1516 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1517 uart_write_wakeup(&up->port);
1518
1519 DEBUG_INTR("THRE...");
1520
1521 if (uart_circ_empty(xmit))
1522 __stop_tx(up);
1523 }
1524
1525 static unsigned int check_modem_status(struct uart_8250_port *up)
1526 {
1527 unsigned int status = serial_in(up, UART_MSR);
1528
1529 status |= up->msr_saved_flags;
1530 up->msr_saved_flags = 0;
1531 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1532 up->port.state != NULL) {
1533 if (status & UART_MSR_TERI)
1534 up->port.icount.rng++;
1535 if (status & UART_MSR_DDSR)
1536 up->port.icount.dsr++;
1537 if (status & UART_MSR_DDCD)
1538 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1539 if (status & UART_MSR_DCTS)
1540 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1541
1542 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1543 }
1544
1545 return status;
1546 }
1547
1548 /*
1549 * This handles the interrupt from one port.
1550 */
1551 static void serial8250_handle_port(struct uart_8250_port *up)
1552 {
1553 unsigned int status;
1554 unsigned long flags;
1555
1556 spin_lock_irqsave(&up->port.lock, flags);
1557
1558 status = serial_inp(up, UART_LSR);
1559
1560 DEBUG_INTR("status = %x...", status);
1561
1562 if (status & (UART_LSR_DR | UART_LSR_BI))
1563 receive_chars(up, &status);
1564 check_modem_status(up);
1565 if (status & UART_LSR_THRE)
1566 transmit_chars(up);
1567
1568 spin_unlock_irqrestore(&up->port.lock, flags);
1569 }
1570
1571 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1572 {
1573 struct uart_8250_port *up =
1574 container_of(port, struct uart_8250_port, port);
1575
1576 if (!(iir & UART_IIR_NO_INT)) {
1577 serial8250_handle_port(up);
1578 return 1;
1579 }
1580
1581 return 0;
1582 }
1583 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1584
1585 static int serial8250_default_handle_irq(struct uart_port *port)
1586 {
1587 struct uart_8250_port *up =
1588 container_of(port, struct uart_8250_port, port);
1589 unsigned int iir = serial_in(up, UART_IIR);
1590
1591 return serial8250_handle_irq(port, iir);
1592 }
1593
1594 /*
1595 * This is the serial driver's interrupt routine.
1596 *
1597 * Arjan thinks the old way was overly complex, so it got simplified.
1598 * Alan disagrees, saying that need the complexity to handle the weird
1599 * nature of ISA shared interrupts. (This is a special exception.)
1600 *
1601 * In order to handle ISA shared interrupts properly, we need to check
1602 * that all ports have been serviced, and therefore the ISA interrupt
1603 * line has been de-asserted.
1604 *
1605 * This means we need to loop through all ports. checking that they
1606 * don't have an interrupt pending.
1607 */
1608 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1609 {
1610 struct irq_info *i = dev_id;
1611 struct list_head *l, *end = NULL;
1612 int pass_counter = 0, handled = 0;
1613
1614 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1615
1616 spin_lock(&i->lock);
1617
1618 l = i->head;
1619 do {
1620 struct uart_8250_port *up;
1621 struct uart_port *port;
1622
1623 up = list_entry(l, struct uart_8250_port, list);
1624 port = &up->port;
1625
1626 if (port->handle_irq(port)) {
1627 handled = 1;
1628 end = NULL;
1629 } else if (end == NULL)
1630 end = l;
1631
1632 l = l->next;
1633
1634 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1635 /* If we hit this, we're dead. */
1636 printk_ratelimited(KERN_ERR
1637 "serial8250: too much work for irq%d\n", irq);
1638 break;
1639 }
1640 } while (l != end);
1641
1642 spin_unlock(&i->lock);
1643
1644 DEBUG_INTR("end.\n");
1645
1646 return IRQ_RETVAL(handled);
1647 }
1648
1649 /*
1650 * To support ISA shared interrupts, we need to have one interrupt
1651 * handler that ensures that the IRQ line has been deasserted
1652 * before returning. Failing to do this will result in the IRQ
1653 * line being stuck active, and, since ISA irqs are edge triggered,
1654 * no more IRQs will be seen.
1655 */
1656 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1657 {
1658 spin_lock_irq(&i->lock);
1659
1660 if (!list_empty(i->head)) {
1661 if (i->head == &up->list)
1662 i->head = i->head->next;
1663 list_del(&up->list);
1664 } else {
1665 BUG_ON(i->head != &up->list);
1666 i->head = NULL;
1667 }
1668 spin_unlock_irq(&i->lock);
1669 /* List empty so throw away the hash node */
1670 if (i->head == NULL) {
1671 hlist_del(&i->node);
1672 kfree(i);
1673 }
1674 }
1675
1676 static int serial_link_irq_chain(struct uart_8250_port *up)
1677 {
1678 struct hlist_head *h;
1679 struct hlist_node *n;
1680 struct irq_info *i;
1681 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1682
1683 mutex_lock(&hash_mutex);
1684
1685 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1686
1687 hlist_for_each(n, h) {
1688 i = hlist_entry(n, struct irq_info, node);
1689 if (i->irq == up->port.irq)
1690 break;
1691 }
1692
1693 if (n == NULL) {
1694 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1695 if (i == NULL) {
1696 mutex_unlock(&hash_mutex);
1697 return -ENOMEM;
1698 }
1699 spin_lock_init(&i->lock);
1700 i->irq = up->port.irq;
1701 hlist_add_head(&i->node, h);
1702 }
1703 mutex_unlock(&hash_mutex);
1704
1705 spin_lock_irq(&i->lock);
1706
1707 if (i->head) {
1708 list_add(&up->list, i->head);
1709 spin_unlock_irq(&i->lock);
1710
1711 ret = 0;
1712 } else {
1713 INIT_LIST_HEAD(&up->list);
1714 i->head = &up->list;
1715 spin_unlock_irq(&i->lock);
1716 irq_flags |= up->port.irqflags;
1717 ret = request_irq(up->port.irq, serial8250_interrupt,
1718 irq_flags, "serial", i);
1719 if (ret < 0)
1720 serial_do_unlink(i, up);
1721 }
1722
1723 return ret;
1724 }
1725
1726 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1727 {
1728 struct irq_info *i;
1729 struct hlist_node *n;
1730 struct hlist_head *h;
1731
1732 mutex_lock(&hash_mutex);
1733
1734 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1735
1736 hlist_for_each(n, h) {
1737 i = hlist_entry(n, struct irq_info, node);
1738 if (i->irq == up->port.irq)
1739 break;
1740 }
1741
1742 BUG_ON(n == NULL);
1743 BUG_ON(i->head == NULL);
1744
1745 if (list_empty(i->head))
1746 free_irq(up->port.irq, i);
1747
1748 serial_do_unlink(i, up);
1749 mutex_unlock(&hash_mutex);
1750 }
1751
1752 /*
1753 * This function is used to handle ports that do not have an
1754 * interrupt. This doesn't work very well for 16450's, but gives
1755 * barely passable results for a 16550A. (Although at the expense
1756 * of much CPU overhead).
1757 */
1758 static void serial8250_timeout(unsigned long data)
1759 {
1760 struct uart_8250_port *up = (struct uart_8250_port *)data;
1761 unsigned int iir;
1762
1763 iir = serial_in(up, UART_IIR);
1764 if (!(iir & UART_IIR_NO_INT))
1765 serial8250_handle_port(up);
1766 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1767 }
1768
1769 static void serial8250_backup_timeout(unsigned long data)
1770 {
1771 struct uart_8250_port *up = (struct uart_8250_port *)data;
1772 unsigned int iir, ier = 0, lsr;
1773 unsigned long flags;
1774
1775 spin_lock_irqsave(&up->port.lock, flags);
1776
1777 /*
1778 * Must disable interrupts or else we risk racing with the interrupt
1779 * based handler.
1780 */
1781 if (is_real_interrupt(up->port.irq)) {
1782 ier = serial_in(up, UART_IER);
1783 serial_out(up, UART_IER, 0);
1784 }
1785
1786 iir = serial_in(up, UART_IIR);
1787
1788 /*
1789 * This should be a safe test for anyone who doesn't trust the
1790 * IIR bits on their UART, but it's specifically designed for
1791 * the "Diva" UART used on the management processor on many HP
1792 * ia64 and parisc boxes.
1793 */
1794 lsr = serial_in(up, UART_LSR);
1795 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1796 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1797 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1798 (lsr & UART_LSR_THRE)) {
1799 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1800 iir |= UART_IIR_THRI;
1801 }
1802
1803 if (!(iir & UART_IIR_NO_INT))
1804 transmit_chars(up);
1805
1806 if (is_real_interrupt(up->port.irq))
1807 serial_out(up, UART_IER, ier);
1808
1809 spin_unlock_irqrestore(&up->port.lock, flags);
1810
1811 /* Standard timer interval plus 0.2s to keep the port running */
1812 mod_timer(&up->timer,
1813 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1814 }
1815
1816 static unsigned int serial8250_tx_empty(struct uart_port *port)
1817 {
1818 struct uart_8250_port *up =
1819 container_of(port, struct uart_8250_port, port);
1820 unsigned long flags;
1821 unsigned int lsr;
1822
1823 spin_lock_irqsave(&up->port.lock, flags);
1824 lsr = serial_in(up, UART_LSR);
1825 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1826 spin_unlock_irqrestore(&up->port.lock, flags);
1827
1828 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1829 }
1830
1831 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1832 {
1833 struct uart_8250_port *up =
1834 container_of(port, struct uart_8250_port, port);
1835 unsigned int status;
1836 unsigned int ret;
1837
1838 status = check_modem_status(up);
1839
1840 ret = 0;
1841 if (status & UART_MSR_DCD)
1842 ret |= TIOCM_CAR;
1843 if (status & UART_MSR_RI)
1844 ret |= TIOCM_RNG;
1845 if (status & UART_MSR_DSR)
1846 ret |= TIOCM_DSR;
1847 if (status & UART_MSR_CTS)
1848 ret |= TIOCM_CTS;
1849 return ret;
1850 }
1851
1852 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1853 {
1854 struct uart_8250_port *up =
1855 container_of(port, struct uart_8250_port, port);
1856 unsigned char mcr = 0;
1857
1858 if (mctrl & TIOCM_RTS)
1859 mcr |= UART_MCR_RTS;
1860 if (mctrl & TIOCM_DTR)
1861 mcr |= UART_MCR_DTR;
1862 if (mctrl & TIOCM_OUT1)
1863 mcr |= UART_MCR_OUT1;
1864 if (mctrl & TIOCM_OUT2)
1865 mcr |= UART_MCR_OUT2;
1866 if (mctrl & TIOCM_LOOP)
1867 mcr |= UART_MCR_LOOP;
1868
1869 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1870
1871 serial_out(up, UART_MCR, mcr);
1872 }
1873
1874 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1875 {
1876 struct uart_8250_port *up =
1877 container_of(port, struct uart_8250_port, port);
1878 unsigned long flags;
1879
1880 spin_lock_irqsave(&up->port.lock, flags);
1881 if (break_state == -1)
1882 up->lcr |= UART_LCR_SBC;
1883 else
1884 up->lcr &= ~UART_LCR_SBC;
1885 serial_out(up, UART_LCR, up->lcr);
1886 spin_unlock_irqrestore(&up->port.lock, flags);
1887 }
1888
1889 /*
1890 * Wait for transmitter & holding register to empty
1891 */
1892 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1893 {
1894 unsigned int status, tmout = 10000;
1895
1896 /* Wait up to 10ms for the character(s) to be sent. */
1897 for (;;) {
1898 status = serial_in(up, UART_LSR);
1899
1900 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1901
1902 if ((status & bits) == bits)
1903 break;
1904 if (--tmout == 0)
1905 break;
1906 udelay(1);
1907 }
1908
1909 /* Wait up to 1s for flow control if necessary */
1910 if (up->port.flags & UPF_CONS_FLOW) {
1911 unsigned int tmout;
1912 for (tmout = 1000000; tmout; tmout--) {
1913 unsigned int msr = serial_in(up, UART_MSR);
1914 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1915 if (msr & UART_MSR_CTS)
1916 break;
1917 udelay(1);
1918 touch_nmi_watchdog();
1919 }
1920 }
1921 }
1922
1923 #ifdef CONFIG_CONSOLE_POLL
1924 /*
1925 * Console polling routines for writing and reading from the uart while
1926 * in an interrupt or debug context.
1927 */
1928
1929 static int serial8250_get_poll_char(struct uart_port *port)
1930 {
1931 struct uart_8250_port *up =
1932 container_of(port, struct uart_8250_port, port);
1933 unsigned char lsr = serial_inp(up, UART_LSR);
1934
1935 if (!(lsr & UART_LSR_DR))
1936 return NO_POLL_CHAR;
1937
1938 return serial_inp(up, UART_RX);
1939 }
1940
1941
1942 static void serial8250_put_poll_char(struct uart_port *port,
1943 unsigned char c)
1944 {
1945 unsigned int ier;
1946 struct uart_8250_port *up =
1947 container_of(port, struct uart_8250_port, port);
1948
1949 /*
1950 * First save the IER then disable the interrupts
1951 */
1952 ier = serial_in(up, UART_IER);
1953 if (up->capabilities & UART_CAP_UUE)
1954 serial_out(up, UART_IER, UART_IER_UUE);
1955 else
1956 serial_out(up, UART_IER, 0);
1957
1958 wait_for_xmitr(up, BOTH_EMPTY);
1959 /*
1960 * Send the character out.
1961 * If a LF, also do CR...
1962 */
1963 serial_out(up, UART_TX, c);
1964 if (c == 10) {
1965 wait_for_xmitr(up, BOTH_EMPTY);
1966 serial_out(up, UART_TX, 13);
1967 }
1968
1969 /*
1970 * Finally, wait for transmitter to become empty
1971 * and restore the IER
1972 */
1973 wait_for_xmitr(up, BOTH_EMPTY);
1974 serial_out(up, UART_IER, ier);
1975 }
1976
1977 #endif /* CONFIG_CONSOLE_POLL */
1978
1979 static int serial8250_startup(struct uart_port *port)
1980 {
1981 struct uart_8250_port *up =
1982 container_of(port, struct uart_8250_port, port);
1983 unsigned long flags;
1984 unsigned char lsr, iir;
1985 int retval;
1986
1987 up->port.fifosize = uart_config[up->port.type].fifo_size;
1988 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1989 up->capabilities = uart_config[up->port.type].flags;
1990 up->mcr = 0;
1991
1992 if (up->port.iotype != up->cur_iotype)
1993 set_io_from_upio(port);
1994
1995 if (up->port.type == PORT_16C950) {
1996 /* Wake up and initialize UART */
1997 up->acr = 0;
1998 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1999 serial_outp(up, UART_EFR, UART_EFR_ECB);
2000 serial_outp(up, UART_IER, 0);
2001 serial_outp(up, UART_LCR, 0);
2002 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2003 serial_outp(up, UART_LCR, 0xBF);
2004 serial_outp(up, UART_EFR, UART_EFR_ECB);
2005 serial_outp(up, UART_LCR, 0);
2006 }
2007
2008 #ifdef CONFIG_SERIAL_8250_RSA
2009 /*
2010 * If this is an RSA port, see if we can kick it up to the
2011 * higher speed clock.
2012 */
2013 enable_rsa(up);
2014 #endif
2015
2016 /*
2017 * Clear the FIFO buffers and disable them.
2018 * (they will be reenabled in set_termios())
2019 */
2020 serial8250_clear_fifos(up);
2021
2022 /*
2023 * Clear the interrupt registers.
2024 */
2025 (void) serial_inp(up, UART_LSR);
2026 (void) serial_inp(up, UART_RX);
2027 (void) serial_inp(up, UART_IIR);
2028 (void) serial_inp(up, UART_MSR);
2029
2030 /*
2031 * At this point, there's no way the LSR could still be 0xff;
2032 * if it is, then bail out, because there's likely no UART
2033 * here.
2034 */
2035 if (!(up->port.flags & UPF_BUGGY_UART) &&
2036 (serial_inp(up, UART_LSR) == 0xff)) {
2037 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2038 serial_index(&up->port));
2039 return -ENODEV;
2040 }
2041
2042 /*
2043 * For a XR16C850, we need to set the trigger levels
2044 */
2045 if (up->port.type == PORT_16850) {
2046 unsigned char fctr;
2047
2048 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2049
2050 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2051 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2052 serial_outp(up, UART_TRG, UART_TRG_96);
2053 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2054 serial_outp(up, UART_TRG, UART_TRG_96);
2055
2056 serial_outp(up, UART_LCR, 0);
2057 }
2058
2059 if (is_real_interrupt(up->port.irq)) {
2060 unsigned char iir1;
2061 /*
2062 * Test for UARTs that do not reassert THRE when the
2063 * transmitter is idle and the interrupt has already
2064 * been cleared. Real 16550s should always reassert
2065 * this interrupt whenever the transmitter is idle and
2066 * the interrupt is enabled. Delays are necessary to
2067 * allow register changes to become visible.
2068 */
2069 spin_lock_irqsave(&up->port.lock, flags);
2070 if (up->port.irqflags & IRQF_SHARED)
2071 disable_irq_nosync(up->port.irq);
2072
2073 wait_for_xmitr(up, UART_LSR_THRE);
2074 serial_out_sync(up, UART_IER, UART_IER_THRI);
2075 udelay(1); /* allow THRE to set */
2076 iir1 = serial_in(up, UART_IIR);
2077 serial_out(up, UART_IER, 0);
2078 serial_out_sync(up, UART_IER, UART_IER_THRI);
2079 udelay(1); /* allow a working UART time to re-assert THRE */
2080 iir = serial_in(up, UART_IIR);
2081 serial_out(up, UART_IER, 0);
2082
2083 if (up->port.irqflags & IRQF_SHARED)
2084 enable_irq(up->port.irq);
2085 spin_unlock_irqrestore(&up->port.lock, flags);
2086
2087 /*
2088 * If the interrupt is not reasserted, setup a timer to
2089 * kick the UART on a regular basis.
2090 */
2091 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2092 up->bugs |= UART_BUG_THRE;
2093 pr_debug("ttyS%d - using backup timer\n",
2094 serial_index(port));
2095 }
2096 }
2097
2098 /*
2099 * The above check will only give an accurate result the first time
2100 * the port is opened so this value needs to be preserved.
2101 */
2102 if (up->bugs & UART_BUG_THRE) {
2103 up->timer.function = serial8250_backup_timeout;
2104 up->timer.data = (unsigned long)up;
2105 mod_timer(&up->timer, jiffies +
2106 uart_poll_timeout(port) + HZ / 5);
2107 }
2108
2109 /*
2110 * If the "interrupt" for this port doesn't correspond with any
2111 * hardware interrupt, we use a timer-based system. The original
2112 * driver used to do this with IRQ0.
2113 */
2114 if (!is_real_interrupt(up->port.irq)) {
2115 up->timer.data = (unsigned long)up;
2116 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2117 } else {
2118 retval = serial_link_irq_chain(up);
2119 if (retval)
2120 return retval;
2121 }
2122
2123 /*
2124 * Now, initialize the UART
2125 */
2126 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2127
2128 spin_lock_irqsave(&up->port.lock, flags);
2129 if (up->port.flags & UPF_FOURPORT) {
2130 if (!is_real_interrupt(up->port.irq))
2131 up->port.mctrl |= TIOCM_OUT1;
2132 } else
2133 /*
2134 * Most PC uarts need OUT2 raised to enable interrupts.
2135 */
2136 if (is_real_interrupt(up->port.irq))
2137 up->port.mctrl |= TIOCM_OUT2;
2138
2139 serial8250_set_mctrl(&up->port, up->port.mctrl);
2140
2141 /* Serial over Lan (SoL) hack:
2142 Intel 8257x Gigabit ethernet chips have a
2143 16550 emulation, to be used for Serial Over Lan.
2144 Those chips take a longer time than a normal
2145 serial device to signalize that a transmission
2146 data was queued. Due to that, the above test generally
2147 fails. One solution would be to delay the reading of
2148 iir. However, this is not reliable, since the timeout
2149 is variable. So, let's just don't test if we receive
2150 TX irq. This way, we'll never enable UART_BUG_TXEN.
2151 */
2152 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2153 goto dont_test_tx_en;
2154
2155 /*
2156 * Do a quick test to see if we receive an
2157 * interrupt when we enable the TX irq.
2158 */
2159 serial_outp(up, UART_IER, UART_IER_THRI);
2160 lsr = serial_in(up, UART_LSR);
2161 iir = serial_in(up, UART_IIR);
2162 serial_outp(up, UART_IER, 0);
2163
2164 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2165 if (!(up->bugs & UART_BUG_TXEN)) {
2166 up->bugs |= UART_BUG_TXEN;
2167 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2168 serial_index(port));
2169 }
2170 } else {
2171 up->bugs &= ~UART_BUG_TXEN;
2172 }
2173
2174 dont_test_tx_en:
2175 spin_unlock_irqrestore(&up->port.lock, flags);
2176
2177 /*
2178 * Clear the interrupt registers again for luck, and clear the
2179 * saved flags to avoid getting false values from polling
2180 * routines or the previous session.
2181 */
2182 serial_inp(up, UART_LSR);
2183 serial_inp(up, UART_RX);
2184 serial_inp(up, UART_IIR);
2185 serial_inp(up, UART_MSR);
2186 up->lsr_saved_flags = 0;
2187 up->msr_saved_flags = 0;
2188
2189 /*
2190 * Finally, enable interrupts. Note: Modem status interrupts
2191 * are set via set_termios(), which will be occurring imminently
2192 * anyway, so we don't enable them here.
2193 */
2194 up->ier = UART_IER_RLSI | UART_IER_RDI;
2195 serial_outp(up, UART_IER, up->ier);
2196
2197 if (up->port.flags & UPF_FOURPORT) {
2198 unsigned int icp;
2199 /*
2200 * Enable interrupts on the AST Fourport board
2201 */
2202 icp = (up->port.iobase & 0xfe0) | 0x01f;
2203 outb_p(0x80, icp);
2204 (void) inb_p(icp);
2205 }
2206
2207 return 0;
2208 }
2209
2210 static void serial8250_shutdown(struct uart_port *port)
2211 {
2212 struct uart_8250_port *up =
2213 container_of(port, struct uart_8250_port, port);
2214 unsigned long flags;
2215
2216 /*
2217 * Disable interrupts from this port
2218 */
2219 up->ier = 0;
2220 serial_outp(up, UART_IER, 0);
2221
2222 spin_lock_irqsave(&up->port.lock, flags);
2223 if (up->port.flags & UPF_FOURPORT) {
2224 /* reset interrupts on the AST Fourport board */
2225 inb((up->port.iobase & 0xfe0) | 0x1f);
2226 up->port.mctrl |= TIOCM_OUT1;
2227 } else
2228 up->port.mctrl &= ~TIOCM_OUT2;
2229
2230 serial8250_set_mctrl(&up->port, up->port.mctrl);
2231 spin_unlock_irqrestore(&up->port.lock, flags);
2232
2233 /*
2234 * Disable break condition and FIFOs
2235 */
2236 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2237 serial8250_clear_fifos(up);
2238
2239 #ifdef CONFIG_SERIAL_8250_RSA
2240 /*
2241 * Reset the RSA board back to 115kbps compat mode.
2242 */
2243 disable_rsa(up);
2244 #endif
2245
2246 /*
2247 * Read data port to reset things, and then unlink from
2248 * the IRQ chain.
2249 */
2250 (void) serial_in(up, UART_RX);
2251
2252 del_timer_sync(&up->timer);
2253 up->timer.function = serial8250_timeout;
2254 if (is_real_interrupt(up->port.irq))
2255 serial_unlink_irq_chain(up);
2256 }
2257
2258 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2259 {
2260 unsigned int quot;
2261
2262 /*
2263 * Handle magic divisors for baud rates above baud_base on
2264 * SMSC SuperIO chips.
2265 */
2266 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2267 baud == (port->uartclk/4))
2268 quot = 0x8001;
2269 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2270 baud == (port->uartclk/8))
2271 quot = 0x8002;
2272 else
2273 quot = uart_get_divisor(port, baud);
2274
2275 return quot;
2276 }
2277
2278 void
2279 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2280 struct ktermios *old)
2281 {
2282 struct uart_8250_port *up =
2283 container_of(port, struct uart_8250_port, port);
2284 unsigned char cval, fcr = 0;
2285 unsigned long flags;
2286 unsigned int baud, quot;
2287
2288 switch (termios->c_cflag & CSIZE) {
2289 case CS5:
2290 cval = UART_LCR_WLEN5;
2291 break;
2292 case CS6:
2293 cval = UART_LCR_WLEN6;
2294 break;
2295 case CS7:
2296 cval = UART_LCR_WLEN7;
2297 break;
2298 default:
2299 case CS8:
2300 cval = UART_LCR_WLEN8;
2301 break;
2302 }
2303
2304 if (termios->c_cflag & CSTOPB)
2305 cval |= UART_LCR_STOP;
2306 if (termios->c_cflag & PARENB)
2307 cval |= UART_LCR_PARITY;
2308 if (!(termios->c_cflag & PARODD))
2309 cval |= UART_LCR_EPAR;
2310 #ifdef CMSPAR
2311 if (termios->c_cflag & CMSPAR)
2312 cval |= UART_LCR_SPAR;
2313 #endif
2314
2315 /*
2316 * Ask the core to calculate the divisor for us.
2317 */
2318 baud = uart_get_baud_rate(port, termios, old,
2319 port->uartclk / 16 / 0xffff,
2320 port->uartclk / 16);
2321 quot = serial8250_get_divisor(port, baud);
2322
2323 /*
2324 * Oxford Semi 952 rev B workaround
2325 */
2326 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2327 quot++;
2328
2329 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2330 if (baud < 2400)
2331 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2332 else
2333 fcr = uart_config[up->port.type].fcr;
2334 }
2335
2336 /*
2337 * MCR-based auto flow control. When AFE is enabled, RTS will be
2338 * deasserted when the receive FIFO contains more characters than
2339 * the trigger, or the MCR RTS bit is cleared. In the case where
2340 * the remote UART is not using CTS auto flow control, we must
2341 * have sufficient FIFO entries for the latency of the remote
2342 * UART to respond. IOW, at least 32 bytes of FIFO.
2343 */
2344 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2345 up->mcr &= ~UART_MCR_AFE;
2346 if (termios->c_cflag & CRTSCTS)
2347 up->mcr |= UART_MCR_AFE;
2348 }
2349
2350 /*
2351 * Ok, we're now changing the port state. Do it with
2352 * interrupts disabled.
2353 */
2354 spin_lock_irqsave(&up->port.lock, flags);
2355
2356 /*
2357 * Update the per-port timeout.
2358 */
2359 uart_update_timeout(port, termios->c_cflag, baud);
2360
2361 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2362 if (termios->c_iflag & INPCK)
2363 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2364 if (termios->c_iflag & (BRKINT | PARMRK))
2365 up->port.read_status_mask |= UART_LSR_BI;
2366
2367 /*
2368 * Characteres to ignore
2369 */
2370 up->port.ignore_status_mask = 0;
2371 if (termios->c_iflag & IGNPAR)
2372 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2373 if (termios->c_iflag & IGNBRK) {
2374 up->port.ignore_status_mask |= UART_LSR_BI;
2375 /*
2376 * If we're ignoring parity and break indicators,
2377 * ignore overruns too (for real raw support).
2378 */
2379 if (termios->c_iflag & IGNPAR)
2380 up->port.ignore_status_mask |= UART_LSR_OE;
2381 }
2382
2383 /*
2384 * ignore all characters if CREAD is not set
2385 */
2386 if ((termios->c_cflag & CREAD) == 0)
2387 up->port.ignore_status_mask |= UART_LSR_DR;
2388
2389 /*
2390 * CTS flow control flag and modem status interrupts
2391 */
2392 up->ier &= ~UART_IER_MSI;
2393 if (!(up->bugs & UART_BUG_NOMSR) &&
2394 UART_ENABLE_MS(&up->port, termios->c_cflag))
2395 up->ier |= UART_IER_MSI;
2396 if (up->capabilities & UART_CAP_UUE)
2397 up->ier |= UART_IER_UUE;
2398 if (up->capabilities & UART_CAP_RTOIE)
2399 up->ier |= UART_IER_RTOIE;
2400
2401 serial_out(up, UART_IER, up->ier);
2402
2403 if (up->capabilities & UART_CAP_EFR) {
2404 unsigned char efr = 0;
2405 /*
2406 * TI16C752/Startech hardware flow control. FIXME:
2407 * - TI16C752 requires control thresholds to be set.
2408 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2409 */
2410 if (termios->c_cflag & CRTSCTS)
2411 efr |= UART_EFR_CTS;
2412
2413 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2414 if (up->port.flags & UPF_EXAR_EFR)
2415 serial_outp(up, UART_XR_EFR, efr);
2416 else
2417 serial_outp(up, UART_EFR, efr);
2418 }
2419
2420 #ifdef CONFIG_ARCH_OMAP
2421 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2422 if (cpu_is_omap1510() && is_omap_port(up)) {
2423 if (baud == 115200) {
2424 quot = 1;
2425 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2426 } else
2427 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2428 }
2429 #endif
2430
2431 if (up->capabilities & UART_NATSEMI) {
2432 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2433 serial_outp(up, UART_LCR, 0xe0);
2434 } else {
2435 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2436 }
2437
2438 serial_dl_write(up, quot);
2439
2440 /*
2441 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2442 * is written without DLAB set, this mode will be disabled.
2443 */
2444 if (up->port.type == PORT_16750)
2445 serial_outp(up, UART_FCR, fcr);
2446
2447 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2448 up->lcr = cval; /* Save LCR */
2449 if (up->port.type != PORT_16750) {
2450 if (fcr & UART_FCR_ENABLE_FIFO) {
2451 /* emulated UARTs (Lucent Venus 167x) need two steps */
2452 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2453 }
2454 serial_outp(up, UART_FCR, fcr); /* set fcr */
2455 }
2456 serial8250_set_mctrl(&up->port, up->port.mctrl);
2457 spin_unlock_irqrestore(&up->port.lock, flags);
2458 /* Don't rewrite B0 */
2459 if (tty_termios_baud_rate(termios))
2460 tty_termios_encode_baud_rate(termios, baud, baud);
2461 }
2462 EXPORT_SYMBOL(serial8250_do_set_termios);
2463
2464 static void
2465 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2466 struct ktermios *old)
2467 {
2468 if (port->set_termios)
2469 port->set_termios(port, termios, old);
2470 else
2471 serial8250_do_set_termios(port, termios, old);
2472 }
2473
2474 static void
2475 serial8250_set_ldisc(struct uart_port *port, int new)
2476 {
2477 if (new == N_PPS) {
2478 port->flags |= UPF_HARDPPS_CD;
2479 serial8250_enable_ms(port);
2480 } else
2481 port->flags &= ~UPF_HARDPPS_CD;
2482 }
2483
2484
2485 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2486 unsigned int oldstate)
2487 {
2488 struct uart_8250_port *p =
2489 container_of(port, struct uart_8250_port, port);
2490
2491 serial8250_set_sleep(p, state != 0);
2492 }
2493 EXPORT_SYMBOL(serial8250_do_pm);
2494
2495 static void
2496 serial8250_pm(struct uart_port *port, unsigned int state,
2497 unsigned int oldstate)
2498 {
2499 if (port->pm)
2500 port->pm(port, state, oldstate);
2501 else
2502 serial8250_do_pm(port, state, oldstate);
2503 }
2504
2505 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2506 {
2507 if (pt->port.iotype == UPIO_AU)
2508 return 0x1000;
2509 #ifdef CONFIG_ARCH_OMAP
2510 if (is_omap_port(pt))
2511 return 0x16 << pt->port.regshift;
2512 #endif
2513 return 8 << pt->port.regshift;
2514 }
2515
2516 /*
2517 * Resource handling.
2518 */
2519 static int serial8250_request_std_resource(struct uart_8250_port *up)
2520 {
2521 unsigned int size = serial8250_port_size(up);
2522 int ret = 0;
2523
2524 switch (up->port.iotype) {
2525 case UPIO_AU:
2526 case UPIO_TSI:
2527 case UPIO_MEM32:
2528 case UPIO_MEM:
2529 if (!up->port.mapbase)
2530 break;
2531
2532 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2533 ret = -EBUSY;
2534 break;
2535 }
2536
2537 if (up->port.flags & UPF_IOREMAP) {
2538 up->port.membase = ioremap_nocache(up->port.mapbase,
2539 size);
2540 if (!up->port.membase) {
2541 release_mem_region(up->port.mapbase, size);
2542 ret = -ENOMEM;
2543 }
2544 }
2545 break;
2546
2547 case UPIO_HUB6:
2548 case UPIO_PORT:
2549 if (!request_region(up->port.iobase, size, "serial"))
2550 ret = -EBUSY;
2551 break;
2552 }
2553 return ret;
2554 }
2555
2556 static void serial8250_release_std_resource(struct uart_8250_port *up)
2557 {
2558 unsigned int size = serial8250_port_size(up);
2559
2560 switch (up->port.iotype) {
2561 case UPIO_AU:
2562 case UPIO_TSI:
2563 case UPIO_MEM32:
2564 case UPIO_MEM:
2565 if (!up->port.mapbase)
2566 break;
2567
2568 if (up->port.flags & UPF_IOREMAP) {
2569 iounmap(up->port.membase);
2570 up->port.membase = NULL;
2571 }
2572
2573 release_mem_region(up->port.mapbase, size);
2574 break;
2575
2576 case UPIO_HUB6:
2577 case UPIO_PORT:
2578 release_region(up->port.iobase, size);
2579 break;
2580 }
2581 }
2582
2583 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2584 {
2585 unsigned long start = UART_RSA_BASE << up->port.regshift;
2586 unsigned int size = 8 << up->port.regshift;
2587 int ret = -EINVAL;
2588
2589 switch (up->port.iotype) {
2590 case UPIO_HUB6:
2591 case UPIO_PORT:
2592 start += up->port.iobase;
2593 if (request_region(start, size, "serial-rsa"))
2594 ret = 0;
2595 else
2596 ret = -EBUSY;
2597 break;
2598 }
2599
2600 return ret;
2601 }
2602
2603 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2604 {
2605 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2606 unsigned int size = 8 << up->port.regshift;
2607
2608 switch (up->port.iotype) {
2609 case UPIO_HUB6:
2610 case UPIO_PORT:
2611 release_region(up->port.iobase + offset, size);
2612 break;
2613 }
2614 }
2615
2616 static void serial8250_release_port(struct uart_port *port)
2617 {
2618 struct uart_8250_port *up =
2619 container_of(port, struct uart_8250_port, port);
2620
2621 serial8250_release_std_resource(up);
2622 if (up->port.type == PORT_RSA)
2623 serial8250_release_rsa_resource(up);
2624 }
2625
2626 static int serial8250_request_port(struct uart_port *port)
2627 {
2628 struct uart_8250_port *up =
2629 container_of(port, struct uart_8250_port, port);
2630 int ret = 0;
2631
2632 ret = serial8250_request_std_resource(up);
2633 if (ret == 0 && up->port.type == PORT_RSA) {
2634 ret = serial8250_request_rsa_resource(up);
2635 if (ret < 0)
2636 serial8250_release_std_resource(up);
2637 }
2638
2639 return ret;
2640 }
2641
2642 static void serial8250_config_port(struct uart_port *port, int flags)
2643 {
2644 struct uart_8250_port *up =
2645 container_of(port, struct uart_8250_port, port);
2646 int probeflags = PROBE_ANY;
2647 int ret;
2648
2649 /*
2650 * Find the region that we can probe for. This in turn
2651 * tells us whether we can probe for the type of port.
2652 */
2653 ret = serial8250_request_std_resource(up);
2654 if (ret < 0)
2655 return;
2656
2657 ret = serial8250_request_rsa_resource(up);
2658 if (ret < 0)
2659 probeflags &= ~PROBE_RSA;
2660
2661 if (up->port.iotype != up->cur_iotype)
2662 set_io_from_upio(port);
2663
2664 if (flags & UART_CONFIG_TYPE)
2665 autoconfig(up, probeflags);
2666
2667 /* if access method is AU, it is a 16550 with a quirk */
2668 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2669 up->bugs |= UART_BUG_NOMSR;
2670
2671 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2672 autoconfig_irq(up);
2673
2674 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2675 serial8250_release_rsa_resource(up);
2676 if (up->port.type == PORT_UNKNOWN)
2677 serial8250_release_std_resource(up);
2678 }
2679
2680 static int
2681 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2682 {
2683 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2684 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2685 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2686 ser->type == PORT_STARTECH)
2687 return -EINVAL;
2688 return 0;
2689 }
2690
2691 static const char *
2692 serial8250_type(struct uart_port *port)
2693 {
2694 int type = port->type;
2695
2696 if (type >= ARRAY_SIZE(uart_config))
2697 type = 0;
2698 return uart_config[type].name;
2699 }
2700
2701 static struct uart_ops serial8250_pops = {
2702 .tx_empty = serial8250_tx_empty,
2703 .set_mctrl = serial8250_set_mctrl,
2704 .get_mctrl = serial8250_get_mctrl,
2705 .stop_tx = serial8250_stop_tx,
2706 .start_tx = serial8250_start_tx,
2707 .stop_rx = serial8250_stop_rx,
2708 .enable_ms = serial8250_enable_ms,
2709 .break_ctl = serial8250_break_ctl,
2710 .startup = serial8250_startup,
2711 .shutdown = serial8250_shutdown,
2712 .set_termios = serial8250_set_termios,
2713 .set_ldisc = serial8250_set_ldisc,
2714 .pm = serial8250_pm,
2715 .type = serial8250_type,
2716 .release_port = serial8250_release_port,
2717 .request_port = serial8250_request_port,
2718 .config_port = serial8250_config_port,
2719 .verify_port = serial8250_verify_port,
2720 #ifdef CONFIG_CONSOLE_POLL
2721 .poll_get_char = serial8250_get_poll_char,
2722 .poll_put_char = serial8250_put_poll_char,
2723 #endif
2724 };
2725
2726 static struct uart_8250_port serial8250_ports[UART_NR];
2727
2728 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2729 unsigned short *capabilities);
2730
2731 void serial8250_set_isa_configurator(
2732 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2733 {
2734 serial8250_isa_config = v;
2735 }
2736 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2737
2738 static void __init serial8250_isa_init_ports(void)
2739 {
2740 struct uart_8250_port *up;
2741 static int first = 1;
2742 int i, irqflag = 0;
2743
2744 if (!first)
2745 return;
2746 first = 0;
2747
2748 for (i = 0; i < nr_uarts; i++) {
2749 struct uart_8250_port *up = &serial8250_ports[i];
2750
2751 up->port.line = i;
2752 spin_lock_init(&up->port.lock);
2753
2754 init_timer(&up->timer);
2755 up->timer.function = serial8250_timeout;
2756
2757 /*
2758 * ALPHA_KLUDGE_MCR needs to be killed.
2759 */
2760 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2761 up->mcr_force = ALPHA_KLUDGE_MCR;
2762
2763 up->port.ops = &serial8250_pops;
2764 }
2765
2766 if (share_irqs)
2767 irqflag = IRQF_SHARED;
2768
2769 for (i = 0, up = serial8250_ports;
2770 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2771 i++, up++) {
2772 up->port.iobase = old_serial_port[i].port;
2773 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2774 up->port.irqflags = old_serial_port[i].irqflags;
2775 up->port.uartclk = old_serial_port[i].baud_base * 16;
2776 up->port.flags = old_serial_port[i].flags;
2777 up->port.hub6 = old_serial_port[i].hub6;
2778 up->port.membase = old_serial_port[i].iomem_base;
2779 up->port.iotype = old_serial_port[i].io_type;
2780 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2781 set_io_from_upio(&up->port);
2782 up->port.irqflags |= irqflag;
2783 if (serial8250_isa_config != NULL)
2784 serial8250_isa_config(i, &up->port, &up->capabilities);
2785
2786 }
2787 }
2788
2789 static void
2790 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2791 {
2792 up->port.type = type;
2793 up->port.fifosize = uart_config[type].fifo_size;
2794 up->capabilities = uart_config[type].flags;
2795 up->tx_loadsz = uart_config[type].tx_loadsz;
2796 }
2797
2798 static void __init
2799 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2800 {
2801 int i;
2802
2803 for (i = 0; i < nr_uarts; i++) {
2804 struct uart_8250_port *up = &serial8250_ports[i];
2805 up->cur_iotype = 0xFF;
2806 }
2807
2808 serial8250_isa_init_ports();
2809
2810 for (i = 0; i < nr_uarts; i++) {
2811 struct uart_8250_port *up = &serial8250_ports[i];
2812
2813 up->port.dev = dev;
2814
2815 if (up->port.flags & UPF_FIXED_TYPE)
2816 serial8250_init_fixed_type_port(up, up->port.type);
2817
2818 uart_add_one_port(drv, &up->port);
2819 }
2820 }
2821
2822 #ifdef CONFIG_SERIAL_8250_CONSOLE
2823
2824 static void serial8250_console_putchar(struct uart_port *port, int ch)
2825 {
2826 struct uart_8250_port *up =
2827 container_of(port, struct uart_8250_port, port);
2828
2829 wait_for_xmitr(up, UART_LSR_THRE);
2830 serial_out(up, UART_TX, ch);
2831 }
2832
2833 /*
2834 * Print a string to the serial port trying not to disturb
2835 * any possible real use of the port...
2836 *
2837 * The console_lock must be held when we get here.
2838 */
2839 static void
2840 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2841 {
2842 struct uart_8250_port *up = &serial8250_ports[co->index];
2843 unsigned long flags;
2844 unsigned int ier;
2845 int locked = 1;
2846
2847 touch_nmi_watchdog();
2848
2849 local_irq_save(flags);
2850 if (up->port.sysrq) {
2851 /* serial8250_handle_port() already took the lock */
2852 locked = 0;
2853 } else if (oops_in_progress) {
2854 locked = spin_trylock(&up->port.lock);
2855 } else
2856 spin_lock(&up->port.lock);
2857
2858 /*
2859 * First save the IER then disable the interrupts
2860 */
2861 ier = serial_in(up, UART_IER);
2862
2863 if (up->capabilities & UART_CAP_UUE)
2864 serial_out(up, UART_IER, UART_IER_UUE);
2865 else
2866 serial_out(up, UART_IER, 0);
2867
2868 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2869
2870 /*
2871 * Finally, wait for transmitter to become empty
2872 * and restore the IER
2873 */
2874 wait_for_xmitr(up, BOTH_EMPTY);
2875 serial_out(up, UART_IER, ier);
2876
2877 /*
2878 * The receive handling will happen properly because the
2879 * receive ready bit will still be set; it is not cleared
2880 * on read. However, modem control will not, we must
2881 * call it if we have saved something in the saved flags
2882 * while processing with interrupts off.
2883 */
2884 if (up->msr_saved_flags)
2885 check_modem_status(up);
2886
2887 if (locked)
2888 spin_unlock(&up->port.lock);
2889 local_irq_restore(flags);
2890 }
2891
2892 static int __init serial8250_console_setup(struct console *co, char *options)
2893 {
2894 struct uart_port *port;
2895 int baud = 9600;
2896 int bits = 8;
2897 int parity = 'n';
2898 int flow = 'n';
2899
2900 /*
2901 * Check whether an invalid uart number has been specified, and
2902 * if so, search for the first available port that does have
2903 * console support.
2904 */
2905 if (co->index >= nr_uarts)
2906 co->index = 0;
2907 port = &serial8250_ports[co->index].port;
2908 if (!port->iobase && !port->membase)
2909 return -ENODEV;
2910
2911 if (options)
2912 uart_parse_options(options, &baud, &parity, &bits, &flow);
2913
2914 return uart_set_options(port, co, baud, parity, bits, flow);
2915 }
2916
2917 static int serial8250_console_early_setup(void)
2918 {
2919 return serial8250_find_port_for_earlycon();
2920 }
2921
2922 static struct console serial8250_console = {
2923 .name = "ttyS",
2924 .write = serial8250_console_write,
2925 .device = uart_console_device,
2926 .setup = serial8250_console_setup,
2927 .early_setup = serial8250_console_early_setup,
2928 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2929 .index = -1,
2930 .data = &serial8250_reg,
2931 };
2932
2933 static int __init serial8250_console_init(void)
2934 {
2935 if (nr_uarts > UART_NR)
2936 nr_uarts = UART_NR;
2937
2938 serial8250_isa_init_ports();
2939 register_console(&serial8250_console);
2940 return 0;
2941 }
2942 console_initcall(serial8250_console_init);
2943
2944 int serial8250_find_port(struct uart_port *p)
2945 {
2946 int line;
2947 struct uart_port *port;
2948
2949 for (line = 0; line < nr_uarts; line++) {
2950 port = &serial8250_ports[line].port;
2951 if (uart_match_port(p, port))
2952 return line;
2953 }
2954 return -ENODEV;
2955 }
2956
2957 #define SERIAL8250_CONSOLE &serial8250_console
2958 #else
2959 #define SERIAL8250_CONSOLE NULL
2960 #endif
2961
2962 static struct uart_driver serial8250_reg = {
2963 .owner = THIS_MODULE,
2964 .driver_name = "serial",
2965 .dev_name = "ttyS",
2966 .major = TTY_MAJOR,
2967 .minor = 64,
2968 .cons = SERIAL8250_CONSOLE,
2969 };
2970
2971 /*
2972 * early_serial_setup - early registration for 8250 ports
2973 *
2974 * Setup an 8250 port structure prior to console initialisation. Use
2975 * after console initialisation will cause undefined behaviour.
2976 */
2977 int __init early_serial_setup(struct uart_port *port)
2978 {
2979 struct uart_port *p;
2980
2981 if (port->line >= ARRAY_SIZE(serial8250_ports))
2982 return -ENODEV;
2983
2984 serial8250_isa_init_ports();
2985 p = &serial8250_ports[port->line].port;
2986 p->iobase = port->iobase;
2987 p->membase = port->membase;
2988 p->irq = port->irq;
2989 p->irqflags = port->irqflags;
2990 p->uartclk = port->uartclk;
2991 p->fifosize = port->fifosize;
2992 p->regshift = port->regshift;
2993 p->iotype = port->iotype;
2994 p->flags = port->flags;
2995 p->mapbase = port->mapbase;
2996 p->private_data = port->private_data;
2997 p->type = port->type;
2998 p->line = port->line;
2999
3000 set_io_from_upio(p);
3001 if (port->serial_in)
3002 p->serial_in = port->serial_in;
3003 if (port->serial_out)
3004 p->serial_out = port->serial_out;
3005 if (port->handle_irq)
3006 p->handle_irq = port->handle_irq;
3007 else
3008 p->handle_irq = serial8250_default_handle_irq;
3009
3010 return 0;
3011 }
3012
3013 /**
3014 * serial8250_suspend_port - suspend one serial port
3015 * @line: serial line number
3016 *
3017 * Suspend one serial port.
3018 */
3019 void serial8250_suspend_port(int line)
3020 {
3021 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3022 }
3023
3024 /**
3025 * serial8250_resume_port - resume one serial port
3026 * @line: serial line number
3027 *
3028 * Resume one serial port.
3029 */
3030 void serial8250_resume_port(int line)
3031 {
3032 struct uart_8250_port *up = &serial8250_ports[line];
3033
3034 if (up->capabilities & UART_NATSEMI) {
3035 /* Ensure it's still in high speed mode */
3036 serial_outp(up, UART_LCR, 0xE0);
3037
3038 ns16550a_goto_highspeed(up);
3039
3040 serial_outp(up, UART_LCR, 0);
3041 up->port.uartclk = 921600*16;
3042 }
3043 uart_resume_port(&serial8250_reg, &up->port);
3044 }
3045
3046 /*
3047 * Register a set of serial devices attached to a platform device. The
3048 * list is terminated with a zero flags entry, which means we expect
3049 * all entries to have at least UPF_BOOT_AUTOCONF set.
3050 */
3051 static int __devinit serial8250_probe(struct platform_device *dev)
3052 {
3053 struct plat_serial8250_port *p = dev->dev.platform_data;
3054 struct uart_port port;
3055 int ret, i, irqflag = 0;
3056
3057 memset(&port, 0, sizeof(struct uart_port));
3058
3059 if (share_irqs)
3060 irqflag = IRQF_SHARED;
3061
3062 for (i = 0; p && p->flags != 0; p++, i++) {
3063 port.iobase = p->iobase;
3064 port.membase = p->membase;
3065 port.irq = p->irq;
3066 port.irqflags = p->irqflags;
3067 port.uartclk = p->uartclk;
3068 port.regshift = p->regshift;
3069 port.iotype = p->iotype;
3070 port.flags = p->flags;
3071 port.mapbase = p->mapbase;
3072 port.hub6 = p->hub6;
3073 port.private_data = p->private_data;
3074 port.type = p->type;
3075 port.serial_in = p->serial_in;
3076 port.serial_out = p->serial_out;
3077 port.handle_irq = p->handle_irq;
3078 port.set_termios = p->set_termios;
3079 port.pm = p->pm;
3080 port.dev = &dev->dev;
3081 port.irqflags |= irqflag;
3082 ret = serial8250_register_port(&port);
3083 if (ret < 0) {
3084 dev_err(&dev->dev, "unable to register port at index %d "
3085 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3086 p->iobase, (unsigned long long)p->mapbase,
3087 p->irq, ret);
3088 }
3089 }
3090 return 0;
3091 }
3092
3093 /*
3094 * Remove serial ports registered against a platform device.
3095 */
3096 static int __devexit serial8250_remove(struct platform_device *dev)
3097 {
3098 int i;
3099
3100 for (i = 0; i < nr_uarts; i++) {
3101 struct uart_8250_port *up = &serial8250_ports[i];
3102
3103 if (up->port.dev == &dev->dev)
3104 serial8250_unregister_port(i);
3105 }
3106 return 0;
3107 }
3108
3109 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3110 {
3111 int i;
3112
3113 for (i = 0; i < UART_NR; i++) {
3114 struct uart_8250_port *up = &serial8250_ports[i];
3115
3116 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3117 uart_suspend_port(&serial8250_reg, &up->port);
3118 }
3119
3120 return 0;
3121 }
3122
3123 static int serial8250_resume(struct platform_device *dev)
3124 {
3125 int i;
3126
3127 for (i = 0; i < UART_NR; i++) {
3128 struct uart_8250_port *up = &serial8250_ports[i];
3129
3130 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3131 serial8250_resume_port(i);
3132 }
3133
3134 return 0;
3135 }
3136
3137 static struct platform_driver serial8250_isa_driver = {
3138 .probe = serial8250_probe,
3139 .remove = __devexit_p(serial8250_remove),
3140 .suspend = serial8250_suspend,
3141 .resume = serial8250_resume,
3142 .driver = {
3143 .name = "serial8250",
3144 .owner = THIS_MODULE,
3145 },
3146 };
3147
3148 /*
3149 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3150 * in the table in include/asm/serial.h
3151 */
3152 static struct platform_device *serial8250_isa_devs;
3153
3154 /*
3155 * serial8250_register_port and serial8250_unregister_port allows for
3156 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3157 * modems and PCI multiport cards.
3158 */
3159 static DEFINE_MUTEX(serial_mutex);
3160
3161 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3162 {
3163 int i;
3164
3165 /*
3166 * First, find a port entry which matches.
3167 */
3168 for (i = 0; i < nr_uarts; i++)
3169 if (uart_match_port(&serial8250_ports[i].port, port))
3170 return &serial8250_ports[i];
3171
3172 /*
3173 * We didn't find a matching entry, so look for the first
3174 * free entry. We look for one which hasn't been previously
3175 * used (indicated by zero iobase).
3176 */
3177 for (i = 0; i < nr_uarts; i++)
3178 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3179 serial8250_ports[i].port.iobase == 0)
3180 return &serial8250_ports[i];
3181
3182 /*
3183 * That also failed. Last resort is to find any entry which
3184 * doesn't have a real port associated with it.
3185 */
3186 for (i = 0; i < nr_uarts; i++)
3187 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3188 return &serial8250_ports[i];
3189
3190 return NULL;
3191 }
3192
3193 /**
3194 * serial8250_register_port - register a serial port
3195 * @port: serial port template
3196 *
3197 * Configure the serial port specified by the request. If the
3198 * port exists and is in use, it is hung up and unregistered
3199 * first.
3200 *
3201 * The port is then probed and if necessary the IRQ is autodetected
3202 * If this fails an error is returned.
3203 *
3204 * On success the port is ready to use and the line number is returned.
3205 */
3206 int serial8250_register_port(struct uart_port *port)
3207 {
3208 struct uart_8250_port *uart;
3209 int ret = -ENOSPC;
3210
3211 if (port->uartclk == 0)
3212 return -EINVAL;
3213
3214 mutex_lock(&serial_mutex);
3215
3216 uart = serial8250_find_match_or_unused(port);
3217 if (uart) {
3218 uart_remove_one_port(&serial8250_reg, &uart->port);
3219
3220 uart->port.iobase = port->iobase;
3221 uart->port.membase = port->membase;
3222 uart->port.irq = port->irq;
3223 uart->port.irqflags = port->irqflags;
3224 uart->port.uartclk = port->uartclk;
3225 uart->port.fifosize = port->fifosize;
3226 uart->port.regshift = port->regshift;
3227 uart->port.iotype = port->iotype;
3228 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3229 uart->port.mapbase = port->mapbase;
3230 uart->port.private_data = port->private_data;
3231 if (port->dev)
3232 uart->port.dev = port->dev;
3233
3234 if (port->flags & UPF_FIXED_TYPE)
3235 serial8250_init_fixed_type_port(uart, port->type);
3236
3237 set_io_from_upio(&uart->port);
3238 /* Possibly override default I/O functions. */
3239 if (port->serial_in)
3240 uart->port.serial_in = port->serial_in;
3241 if (port->serial_out)
3242 uart->port.serial_out = port->serial_out;
3243 if (port->handle_irq)
3244 uart->port.handle_irq = port->handle_irq;
3245 /* Possibly override set_termios call */
3246 if (port->set_termios)
3247 uart->port.set_termios = port->set_termios;
3248 if (port->pm)
3249 uart->port.pm = port->pm;
3250
3251 if (serial8250_isa_config != NULL)
3252 serial8250_isa_config(0, &uart->port,
3253 &uart->capabilities);
3254
3255 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3256 if (ret == 0)
3257 ret = uart->port.line;
3258 }
3259 mutex_unlock(&serial_mutex);
3260
3261 return ret;
3262 }
3263 EXPORT_SYMBOL(serial8250_register_port);
3264
3265 /**
3266 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3267 * @line: serial line number
3268 *
3269 * Remove one serial port. This may not be called from interrupt
3270 * context. We hand the port back to the our control.
3271 */
3272 void serial8250_unregister_port(int line)
3273 {
3274 struct uart_8250_port *uart = &serial8250_ports[line];
3275
3276 mutex_lock(&serial_mutex);
3277 uart_remove_one_port(&serial8250_reg, &uart->port);
3278 if (serial8250_isa_devs) {
3279 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3280 uart->port.type = PORT_UNKNOWN;
3281 uart->port.dev = &serial8250_isa_devs->dev;
3282 uart->capabilities = uart_config[uart->port.type].flags;
3283 uart_add_one_port(&serial8250_reg, &uart->port);
3284 } else {
3285 uart->port.dev = NULL;
3286 }
3287 mutex_unlock(&serial_mutex);
3288 }
3289 EXPORT_SYMBOL(serial8250_unregister_port);
3290
3291 static int __init serial8250_init(void)
3292 {
3293 int ret;
3294
3295 if (nr_uarts > UART_NR)
3296 nr_uarts = UART_NR;
3297
3298 printk(KERN_INFO "Serial: 8250/16550 driver, "
3299 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3300 share_irqs ? "en" : "dis");
3301
3302 #ifdef CONFIG_SPARC
3303 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3304 #else
3305 serial8250_reg.nr = UART_NR;
3306 ret = uart_register_driver(&serial8250_reg);
3307 #endif
3308 if (ret)
3309 goto out;
3310
3311 serial8250_isa_devs = platform_device_alloc("serial8250",
3312 PLAT8250_DEV_LEGACY);
3313 if (!serial8250_isa_devs) {
3314 ret = -ENOMEM;
3315 goto unreg_uart_drv;
3316 }
3317
3318 ret = platform_device_add(serial8250_isa_devs);
3319 if (ret)
3320 goto put_dev;
3321
3322 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3323
3324 ret = platform_driver_register(&serial8250_isa_driver);
3325 if (ret == 0)
3326 goto out;
3327
3328 platform_device_del(serial8250_isa_devs);
3329 put_dev:
3330 platform_device_put(serial8250_isa_devs);
3331 unreg_uart_drv:
3332 #ifdef CONFIG_SPARC
3333 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3334 #else
3335 uart_unregister_driver(&serial8250_reg);
3336 #endif
3337 out:
3338 return ret;
3339 }
3340
3341 static void __exit serial8250_exit(void)
3342 {
3343 struct platform_device *isa_dev = serial8250_isa_devs;
3344
3345 /*
3346 * This tells serial8250_unregister_port() not to re-register
3347 * the ports (thereby making serial8250_isa_driver permanently
3348 * in use.)
3349 */
3350 serial8250_isa_devs = NULL;
3351
3352 platform_driver_unregister(&serial8250_isa_driver);
3353 platform_device_unregister(isa_dev);
3354
3355 #ifdef CONFIG_SPARC
3356 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3357 #else
3358 uart_unregister_driver(&serial8250_reg);
3359 #endif
3360 }
3361
3362 module_init(serial8250_init);
3363 module_exit(serial8250_exit);
3364
3365 EXPORT_SYMBOL(serial8250_suspend_port);
3366 EXPORT_SYMBOL(serial8250_resume_port);
3367
3368 MODULE_LICENSE("GPL");
3369 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3370
3371 module_param(share_irqs, uint, 0644);
3372 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3373 " (unsafe)");
3374
3375 module_param(nr_uarts, uint, 0644);
3376 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3377
3378 module_param(skip_txen_test, uint, 0644);
3379 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3380
3381 #ifdef CONFIG_SERIAL_8250_RSA
3382 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3383 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3384 #endif
3385 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree