2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/pci-aspm.h>
52 #include <linux/ethtool.h>
53 #include <linux/uaccess.h>
54 #include <linux/slab.h>
55 #include <linux/etherdevice.h>
57 #include <net/ieee80211_radiotap.h>
59 #include <asm/unaligned.h>
67 static int modparam_nohwcrypt
;
68 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
69 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
71 static int modparam_all_channels
;
72 module_param_named(all_channels
, modparam_all_channels
, bool, S_IRUGO
);
73 MODULE_PARM_DESC(all_channels
, "Expose all channels the device can use.");
76 MODULE_AUTHOR("Jiri Slaby");
77 MODULE_AUTHOR("Nick Kossifidis");
78 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
79 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
80 MODULE_LICENSE("Dual BSD/GPL");
81 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
83 static int ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
);
84 static int ath5k_beacon_update(struct ieee80211_hw
*hw
,
85 struct ieee80211_vif
*vif
);
86 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
89 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table
) = {
90 { PCI_VDEVICE(ATHEROS
, 0x0207) }, /* 5210 early */
91 { PCI_VDEVICE(ATHEROS
, 0x0007) }, /* 5210 */
92 { PCI_VDEVICE(ATHEROS
, 0x0011) }, /* 5311 - this is on AHB bus !*/
93 { PCI_VDEVICE(ATHEROS
, 0x0012) }, /* 5211 */
94 { PCI_VDEVICE(ATHEROS
, 0x0013) }, /* 5212 */
95 { PCI_VDEVICE(3COM_2
, 0x0013) }, /* 3com 5212 */
96 { PCI_VDEVICE(3COM
, 0x0013) }, /* 3com 3CRDAG675 5212 */
97 { PCI_VDEVICE(ATHEROS
, 0x1014) }, /* IBM minipci 5212 */
98 { PCI_VDEVICE(ATHEROS
, 0x0014) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS
, 0x0015) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS
, 0x0016) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS
, 0x0017) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS
, 0x0018) }, /* 5212 combatible */
103 { PCI_VDEVICE(ATHEROS
, 0x0019) }, /* 5212 combatible */
104 { PCI_VDEVICE(ATHEROS
, 0x001a) }, /* 2413 Griffin-lite */
105 { PCI_VDEVICE(ATHEROS
, 0x001b) }, /* 5413 Eagle */
106 { PCI_VDEVICE(ATHEROS
, 0x001c) }, /* PCI-E cards */
107 { PCI_VDEVICE(ATHEROS
, 0x001d) }, /* 2417 Nala */
110 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
113 static const struct ath5k_srev_name srev_names
[] = {
114 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
115 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
116 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
117 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
118 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
119 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
120 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
121 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
122 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
123 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
124 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
125 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
126 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
127 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
128 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
129 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
130 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
131 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
132 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
133 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
134 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
135 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
136 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
137 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
138 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
139 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
140 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
141 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
142 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
143 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
144 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
145 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
146 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
147 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
148 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
149 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
152 static const struct ieee80211_rate ath5k_rates
[] = {
154 .hw_value
= ATH5K_RATE_CODE_1M
, },
156 .hw_value
= ATH5K_RATE_CODE_2M
,
157 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
158 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
160 .hw_value
= ATH5K_RATE_CODE_5_5M
,
161 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
162 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
164 .hw_value
= ATH5K_RATE_CODE_11M
,
165 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
166 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
168 .hw_value
= ATH5K_RATE_CODE_6M
,
171 .hw_value
= ATH5K_RATE_CODE_9M
,
174 .hw_value
= ATH5K_RATE_CODE_12M
,
177 .hw_value
= ATH5K_RATE_CODE_18M
,
180 .hw_value
= ATH5K_RATE_CODE_24M
,
183 .hw_value
= ATH5K_RATE_CODE_36M
,
186 .hw_value
= ATH5K_RATE_CODE_48M
,
189 .hw_value
= ATH5K_RATE_CODE_54M
,
194 static inline void ath5k_txbuf_free_skb(struct ath5k_softc
*sc
,
195 struct ath5k_buf
*bf
)
200 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
202 dev_kfree_skb_any(bf
->skb
);
205 bf
->desc
->ds_data
= 0;
208 static inline void ath5k_rxbuf_free_skb(struct ath5k_softc
*sc
,
209 struct ath5k_buf
*bf
)
211 struct ath5k_hw
*ah
= sc
->ah
;
212 struct ath_common
*common
= ath5k_hw_common(ah
);
217 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, common
->rx_bufsize
,
219 dev_kfree_skb_any(bf
->skb
);
222 bf
->desc
->ds_data
= 0;
226 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
228 u64 tsf
= ath5k_hw_get_tsf64(ah
);
230 if ((tsf
& 0x7fff) < rstamp
)
233 return (tsf
& ~0x7fff) | rstamp
;
237 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
239 const char *name
= "xxxxx";
242 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
243 if (srev_names
[i
].sr_type
!= type
)
246 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
247 name
= srev_names
[i
].sr_name
;
249 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
250 name
= srev_names
[i
].sr_name
;
257 static unsigned int ath5k_ioread32(void *hw_priv
, u32 reg_offset
)
259 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
260 return ath5k_hw_reg_read(ah
, reg_offset
);
263 static void ath5k_iowrite32(void *hw_priv
, u32 val
, u32 reg_offset
)
265 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
266 ath5k_hw_reg_write(ah
, val
, reg_offset
);
269 static const struct ath_ops ath5k_common_ops
= {
270 .read
= ath5k_ioread32
,
271 .write
= ath5k_iowrite32
,
274 /***********************\
275 * Driver Initialization *
276 \***********************/
278 static int ath5k_reg_notifier(struct wiphy
*wiphy
, struct regulatory_request
*request
)
280 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
281 struct ath5k_softc
*sc
= hw
->priv
;
282 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(sc
->ah
);
284 return ath_reg_notifier_apply(wiphy
, request
, regulatory
);
287 /********************\
288 * Channel/mode setup *
289 \********************/
292 * Convert IEEE channel number to MHz frequency.
295 ath5k_ieee2mhz(short chan
)
297 if (chan
<= 14 || chan
>= 27)
298 return ieee80211chan2mhz(chan
);
300 return 2212 + chan
* 20;
304 * Returns true for the channel numbers used without all_channels modparam.
306 static bool ath5k_is_standard_channel(short chan
)
308 return ((chan
<= 14) ||
310 ((chan
& 3) == 0 && chan
>= 36 && chan
<= 64) ||
312 ((chan
& 3) == 0 && chan
>= 100 && chan
<= 140) ||
314 ((chan
& 3) == 1 && chan
>= 149 && chan
<= 165));
318 ath5k_copy_channels(struct ath5k_hw
*ah
,
319 struct ieee80211_channel
*channels
,
323 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
325 if (!test_bit(mode
, ah
->ah_modes
))
330 case AR5K_MODE_11A_TURBO
:
331 /* 1..220, but 2GHz frequencies are filtered by check_channel */
333 chfreq
= CHANNEL_5GHZ
;
337 case AR5K_MODE_11G_TURBO
:
339 chfreq
= CHANNEL_2GHZ
;
342 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
346 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
348 freq
= ath5k_ieee2mhz(ch
);
350 /* Check if channel is supported by the chipset */
351 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
354 if (!modparam_all_channels
&& !ath5k_is_standard_channel(ch
))
357 /* Write channel info and increment counter */
358 channels
[count
].center_freq
= freq
;
359 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
360 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
364 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
366 case AR5K_MODE_11A_TURBO
:
367 case AR5K_MODE_11G_TURBO
:
368 channels
[count
].hw_value
= chfreq
|
369 CHANNEL_OFDM
| CHANNEL_TURBO
;
372 channels
[count
].hw_value
= CHANNEL_B
;
383 ath5k_setup_rate_idx(struct ath5k_softc
*sc
, struct ieee80211_supported_band
*b
)
387 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
388 sc
->rate_idx
[b
->band
][i
] = -1;
390 for (i
= 0; i
< b
->n_bitrates
; i
++) {
391 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
392 if (b
->bitrates
[i
].hw_value_short
)
393 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
398 ath5k_setup_bands(struct ieee80211_hw
*hw
)
400 struct ath5k_softc
*sc
= hw
->priv
;
401 struct ath5k_hw
*ah
= sc
->ah
;
402 struct ieee80211_supported_band
*sband
;
403 int max_c
, count_c
= 0;
406 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
407 max_c
= ARRAY_SIZE(sc
->channels
);
410 sband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
411 sband
->band
= IEEE80211_BAND_2GHZ
;
412 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_2GHZ
][0];
414 if (test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
416 memcpy(sband
->bitrates
, &ath5k_rates
[0],
417 sizeof(struct ieee80211_rate
) * 12);
418 sband
->n_bitrates
= 12;
420 sband
->channels
= sc
->channels
;
421 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
422 AR5K_MODE_11G
, max_c
);
424 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
425 count_c
= sband
->n_channels
;
427 } else if (test_bit(AR5K_MODE_11B
, sc
->ah
->ah_capabilities
.cap_mode
)) {
429 memcpy(sband
->bitrates
, &ath5k_rates
[0],
430 sizeof(struct ieee80211_rate
) * 4);
431 sband
->n_bitrates
= 4;
433 /* 5211 only supports B rates and uses 4bit rate codes
434 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
437 if (ah
->ah_version
== AR5K_AR5211
) {
438 for (i
= 0; i
< 4; i
++) {
439 sband
->bitrates
[i
].hw_value
=
440 sband
->bitrates
[i
].hw_value
& 0xF;
441 sband
->bitrates
[i
].hw_value_short
=
442 sband
->bitrates
[i
].hw_value_short
& 0xF;
446 sband
->channels
= sc
->channels
;
447 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
448 AR5K_MODE_11B
, max_c
);
450 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
451 count_c
= sband
->n_channels
;
454 ath5k_setup_rate_idx(sc
, sband
);
456 /* 5GHz band, A mode */
457 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
458 sband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
459 sband
->band
= IEEE80211_BAND_5GHZ
;
460 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_5GHZ
][0];
462 memcpy(sband
->bitrates
, &ath5k_rates
[4],
463 sizeof(struct ieee80211_rate
) * 8);
464 sband
->n_bitrates
= 8;
466 sband
->channels
= &sc
->channels
[count_c
];
467 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
468 AR5K_MODE_11A
, max_c
);
470 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
472 ath5k_setup_rate_idx(sc
, sband
);
474 ath5k_debug_dump_bands(sc
);
480 * Set/change channels. We always reset the chip.
481 * To accomplish this we must first cleanup any pending DMA,
482 * then restart stuff after a la ath5k_init.
484 * Called with sc->lock.
487 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
489 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
490 "channel set, resetting (%u -> %u MHz)\n",
491 sc
->curchan
->center_freq
, chan
->center_freq
);
494 * To switch channels clear any pending DMA operations;
495 * wait long enough for the RX fifo to drain, reset the
496 * hardware at the new frequency, and then re-enable
497 * the relevant bits of the h/w.
499 return ath5k_reset(sc
, chan
);
503 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
507 if (mode
== AR5K_MODE_11A
) {
508 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
510 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
514 struct ath_vif_iter_data
{
515 const u8
*hw_macaddr
;
517 u8 active_mac
[ETH_ALEN
]; /* first active MAC */
518 bool need_set_hw_addr
;
521 enum nl80211_iftype opmode
;
524 static void ath_vif_iter(void *data
, u8
*mac
, struct ieee80211_vif
*vif
)
526 struct ath_vif_iter_data
*iter_data
= data
;
528 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
530 if (iter_data
->hw_macaddr
)
531 for (i
= 0; i
< ETH_ALEN
; i
++)
532 iter_data
->mask
[i
] &=
533 ~(iter_data
->hw_macaddr
[i
] ^ mac
[i
]);
535 if (!iter_data
->found_active
) {
536 iter_data
->found_active
= true;
537 memcpy(iter_data
->active_mac
, mac
, ETH_ALEN
);
540 if (iter_data
->need_set_hw_addr
&& iter_data
->hw_macaddr
)
541 if (compare_ether_addr(iter_data
->hw_macaddr
, mac
) == 0)
542 iter_data
->need_set_hw_addr
= false;
544 if (!iter_data
->any_assoc
) {
546 iter_data
->any_assoc
= true;
549 /* Calculate combined mode - when APs are active, operate in AP mode.
550 * Otherwise use the mode of the new interface. This can currently
551 * only deal with combinations of APs and STAs. Only one ad-hoc
552 * interfaces is allowed.
554 if (avf
->opmode
== NL80211_IFTYPE_AP
)
555 iter_data
->opmode
= NL80211_IFTYPE_AP
;
557 if (iter_data
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
558 iter_data
->opmode
= avf
->opmode
;
561 static void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc
*sc
,
562 struct ieee80211_vif
*vif
)
564 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
565 struct ath_vif_iter_data iter_data
;
568 * Use the hardware MAC address as reference, the hardware uses it
569 * together with the BSSID mask when matching addresses.
571 iter_data
.hw_macaddr
= common
->macaddr
;
572 memset(&iter_data
.mask
, 0xff, ETH_ALEN
);
573 iter_data
.found_active
= false;
574 iter_data
.need_set_hw_addr
= true;
575 iter_data
.opmode
= NL80211_IFTYPE_UNSPECIFIED
;
578 ath_vif_iter(&iter_data
, vif
->addr
, vif
);
580 /* Get list of all active MAC addresses */
581 ieee80211_iterate_active_interfaces_atomic(sc
->hw
, ath_vif_iter
,
583 memcpy(sc
->bssidmask
, iter_data
.mask
, ETH_ALEN
);
585 sc
->opmode
= iter_data
.opmode
;
586 if (sc
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
587 /* Nothing active, default to station mode */
588 sc
->opmode
= NL80211_IFTYPE_STATION
;
590 ath5k_hw_set_opmode(sc
->ah
, sc
->opmode
);
591 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "mode setup opmode %d (%s)\n",
592 sc
->opmode
, ath_opmode_to_string(sc
->opmode
));
594 if (iter_data
.need_set_hw_addr
&& iter_data
.found_active
)
595 ath5k_hw_set_lladdr(sc
->ah
, iter_data
.active_mac
);
597 if (ath5k_hw_hasbssidmask(sc
->ah
))
598 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
602 ath5k_mode_setup(struct ath5k_softc
*sc
, struct ieee80211_vif
*vif
)
604 struct ath5k_hw
*ah
= sc
->ah
;
607 /* configure rx filter */
608 rfilt
= sc
->filter_flags
;
609 ath5k_hw_set_rx_filter(ah
, rfilt
);
610 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
612 ath5k_update_bssid_mask_and_opmode(sc
, vif
);
616 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
)
620 /* return base rate on errors */
621 if (WARN(hw_rix
< 0 || hw_rix
>= AR5K_MAX_RATES
,
622 "hw_rix out of bounds: %x\n", hw_rix
))
625 rix
= sc
->rate_idx
[sc
->curband
->band
][hw_rix
];
626 if (WARN(rix
< 0, "invalid hw_rix: %x\n", hw_rix
))
637 struct sk_buff
*ath5k_rx_skb_alloc(struct ath5k_softc
*sc
, dma_addr_t
*skb_addr
)
639 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
643 * Allocate buffer with headroom_needed space for the
644 * fake physical layer header at the start.
646 skb
= ath_rxbuf_alloc(common
,
651 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
656 *skb_addr
= pci_map_single(sc
->pdev
,
657 skb
->data
, common
->rx_bufsize
,
659 if (unlikely(pci_dma_mapping_error(sc
->pdev
, *skb_addr
))) {
660 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
668 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
670 struct ath5k_hw
*ah
= sc
->ah
;
671 struct sk_buff
*skb
= bf
->skb
;
672 struct ath5k_desc
*ds
;
676 skb
= ath5k_rx_skb_alloc(sc
, &bf
->skbaddr
);
683 * Setup descriptors. For receive we always terminate
684 * the descriptor list with a self-linked entry so we'll
685 * not get overrun under high load (as can happen with a
686 * 5212 when ANI processing enables PHY error frames).
688 * To ensure the last descriptor is self-linked we create
689 * each descriptor as self-linked and add it to the end. As
690 * each additional descriptor is added the previous self-linked
691 * entry is "fixed" naturally. This should be safe even
692 * if DMA is happening. When processing RX interrupts we
693 * never remove/process the last, self-linked, entry on the
694 * descriptor list. This ensures the hardware always has
695 * someplace to write a new frame.
698 ds
->ds_link
= bf
->daddr
; /* link to self */
699 ds
->ds_data
= bf
->skbaddr
;
700 ret
= ath5k_hw_setup_rx_desc(ah
, ds
, ah
->common
.rx_bufsize
, 0);
702 ATH5K_ERR(sc
, "%s: could not setup RX desc\n", __func__
);
706 if (sc
->rxlink
!= NULL
)
707 *sc
->rxlink
= bf
->daddr
;
708 sc
->rxlink
= &ds
->ds_link
;
712 static enum ath5k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
714 struct ieee80211_hdr
*hdr
;
715 enum ath5k_pkt_type htype
;
718 hdr
= (struct ieee80211_hdr
*)skb
->data
;
719 fc
= hdr
->frame_control
;
721 if (ieee80211_is_beacon(fc
))
722 htype
= AR5K_PKT_TYPE_BEACON
;
723 else if (ieee80211_is_probe_resp(fc
))
724 htype
= AR5K_PKT_TYPE_PROBE_RESP
;
725 else if (ieee80211_is_atim(fc
))
726 htype
= AR5K_PKT_TYPE_ATIM
;
727 else if (ieee80211_is_pspoll(fc
))
728 htype
= AR5K_PKT_TYPE_PSPOLL
;
730 htype
= AR5K_PKT_TYPE_NORMAL
;
736 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
,
737 struct ath5k_txq
*txq
, int padsize
)
739 struct ath5k_hw
*ah
= sc
->ah
;
740 struct ath5k_desc
*ds
= bf
->desc
;
741 struct sk_buff
*skb
= bf
->skb
;
742 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
743 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
744 struct ieee80211_rate
*rate
;
745 unsigned int mrr_rate
[3], mrr_tries
[3];
752 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
755 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
758 rate
= ieee80211_get_tx_rate(sc
->hw
, info
);
764 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
765 flags
|= AR5K_TXDESC_NOACK
;
767 rc_flags
= info
->control
.rates
[0].flags
;
768 hw_rate
= (rc_flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
) ?
769 rate
->hw_value_short
: rate
->hw_value
;
773 /* FIXME: If we are in g mode and rate is a CCK rate
774 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
775 * from tx power (value is in dB units already) */
776 if (info
->control
.hw_key
) {
777 keyidx
= info
->control
.hw_key
->hw_key_idx
;
778 pktlen
+= info
->control
.hw_key
->icv_len
;
780 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
781 flags
|= AR5K_TXDESC_RTSENA
;
782 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
783 duration
= le16_to_cpu(ieee80211_rts_duration(sc
->hw
,
784 info
->control
.vif
, pktlen
, info
));
786 if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
787 flags
|= AR5K_TXDESC_CTSENA
;
788 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
789 duration
= le16_to_cpu(ieee80211_ctstoself_duration(sc
->hw
,
790 info
->control
.vif
, pktlen
, info
));
792 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
793 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
794 get_hw_packet_type(skb
),
795 (sc
->power_level
* 2),
797 info
->control
.rates
[0].count
, keyidx
, ah
->ah_tx_ant
, flags
,
802 memset(mrr_rate
, 0, sizeof(mrr_rate
));
803 memset(mrr_tries
, 0, sizeof(mrr_tries
));
804 for (i
= 0; i
< 3; i
++) {
805 rate
= ieee80211_get_alt_retry_rate(sc
->hw
, info
, i
);
809 mrr_rate
[i
] = rate
->hw_value
;
810 mrr_tries
[i
] = info
->control
.rates
[i
+ 1].count
;
813 ath5k_hw_setup_mrr_tx_desc(ah
, ds
,
814 mrr_rate
[0], mrr_tries
[0],
815 mrr_rate
[1], mrr_tries
[1],
816 mrr_rate
[2], mrr_tries
[2]);
819 ds
->ds_data
= bf
->skbaddr
;
821 spin_lock_bh(&txq
->lock
);
822 list_add_tail(&bf
->list
, &txq
->q
);
824 if (txq
->link
== NULL
) /* is this first packet? */
825 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
826 else /* no, so only link it */
827 *txq
->link
= bf
->daddr
;
829 txq
->link
= &ds
->ds_link
;
830 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
832 spin_unlock_bh(&txq
->lock
);
836 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
840 /*******************\
841 * Descriptors setup *
842 \*******************/
845 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
847 struct ath5k_desc
*ds
;
848 struct ath5k_buf
*bf
;
853 /* allocate descriptors */
854 sc
->desc_len
= sizeof(struct ath5k_desc
) *
855 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
856 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
857 if (sc
->desc
== NULL
) {
858 ATH5K_ERR(sc
, "can't allocate descriptors\n");
864 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
865 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
867 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
868 sizeof(struct ath5k_buf
), GFP_KERNEL
);
870 ATH5K_ERR(sc
, "can't allocate bufptr\n");
876 INIT_LIST_HEAD(&sc
->rxbuf
);
877 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
880 list_add_tail(&bf
->list
, &sc
->rxbuf
);
883 INIT_LIST_HEAD(&sc
->txbuf
);
884 sc
->txbuf_len
= ATH_TXBUF
;
885 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
889 list_add_tail(&bf
->list
, &sc
->txbuf
);
893 INIT_LIST_HEAD(&sc
->bcbuf
);
894 for (i
= 0; i
< ATH_BCBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
897 list_add_tail(&bf
->list
, &sc
->bcbuf
);
902 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
909 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
911 struct ath5k_buf
*bf
;
913 list_for_each_entry(bf
, &sc
->txbuf
, list
)
914 ath5k_txbuf_free_skb(sc
, bf
);
915 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
916 ath5k_rxbuf_free_skb(sc
, bf
);
917 list_for_each_entry(bf
, &sc
->bcbuf
, list
)
918 ath5k_txbuf_free_skb(sc
, bf
);
920 /* Free memory associated with all descriptors */
921 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
934 static struct ath5k_txq
*
935 ath5k_txq_setup(struct ath5k_softc
*sc
,
936 int qtype
, int subtype
)
938 struct ath5k_hw
*ah
= sc
->ah
;
939 struct ath5k_txq
*txq
;
940 struct ath5k_txq_info qi
= {
941 .tqi_subtype
= subtype
,
942 /* XXX: default values not correct for B and XR channels,
944 .tqi_aifs
= AR5K_TUNE_AIFS
,
945 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
946 .tqi_cw_max
= AR5K_TUNE_CWMAX
951 * Enable interrupts only for EOL and DESC conditions.
952 * We mark tx descriptors to receive a DESC interrupt
953 * when a tx queue gets deep; otherwise we wait for the
954 * EOL to reap descriptors. Note that this is done to
955 * reduce interrupt load and this only defers reaping
956 * descriptors, never transmitting frames. Aside from
957 * reducing interrupts this also permits more concurrency.
958 * The only potential downside is if the tx queue backs
959 * up in which case the top half of the kernel may backup
960 * due to a lack of tx descriptors.
962 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
963 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
964 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
967 * NB: don't print a message, this happens
968 * normally on parts with too few tx queues
970 return ERR_PTR(qnum
);
972 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
973 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
974 qnum
, ARRAY_SIZE(sc
->txqs
));
975 ath5k_hw_release_tx_queue(ah
, qnum
);
976 return ERR_PTR(-EINVAL
);
978 txq
= &sc
->txqs
[qnum
];
982 INIT_LIST_HEAD(&txq
->q
);
983 spin_lock_init(&txq
->lock
);
986 txq
->txq_poll_mark
= false;
989 return &sc
->txqs
[qnum
];
993 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
995 struct ath5k_txq_info qi
= {
996 /* XXX: default values not correct for B and XR channels,
998 .tqi_aifs
= AR5K_TUNE_AIFS
,
999 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
1000 .tqi_cw_max
= AR5K_TUNE_CWMAX
,
1001 /* NB: for dynamic turbo, don't enable any other interrupts */
1002 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1005 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1009 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1011 struct ath5k_hw
*ah
= sc
->ah
;
1012 struct ath5k_txq_info qi
;
1015 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1019 if (sc
->opmode
== NL80211_IFTYPE_AP
||
1020 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1022 * Always burst out beacon and CAB traffic
1023 * (aifs = cwmin = cwmax = 0)
1028 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
1030 * Adhoc mode; backoff between 0 and (2 * cw_min).
1034 qi
.tqi_cw_max
= 2 * AR5K_TUNE_CWMIN
;
1037 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1038 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1039 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1041 ret
= ath5k_hw_set_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1043 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1044 "hardware queue!\n", __func__
);
1047 ret
= ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */
1051 /* reconfigure cabq with ready time to 80% of beacon_interval */
1052 ret
= ath5k_hw_get_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1056 qi
.tqi_ready_time
= (sc
->bintval
* 80) / 100;
1057 ret
= ath5k_hw_set_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1061 ret
= ath5k_hw_reset_tx_queue(ah
, AR5K_TX_QUEUE_ID_CAB
);
1067 * ath5k_drain_tx_buffs - Empty tx buffers
1069 * @sc The &struct ath5k_softc
1071 * Empty tx buffers from all queues in preparation
1072 * of a reset or during shutdown.
1074 * NB: this assumes output has been stopped and
1075 * we do not need to block ath5k_tx_tasklet
1078 ath5k_drain_tx_buffs(struct ath5k_softc
*sc
)
1080 struct ath5k_txq
*txq
;
1081 struct ath5k_buf
*bf
, *bf0
;
1084 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++) {
1085 if (sc
->txqs
[i
].setup
) {
1087 spin_lock_bh(&txq
->lock
);
1088 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1089 ath5k_debug_printtxbuf(sc
, bf
);
1091 ath5k_txbuf_free_skb(sc
, bf
);
1093 spin_lock_bh(&sc
->txbuflock
);
1094 list_move_tail(&bf
->list
, &sc
->txbuf
);
1097 spin_unlock_bh(&sc
->txbuflock
);
1100 txq
->txq_poll_mark
= false;
1101 spin_unlock_bh(&txq
->lock
);
1107 ath5k_txq_release(struct ath5k_softc
*sc
)
1109 struct ath5k_txq
*txq
= sc
->txqs
;
1112 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1114 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1125 * Enable the receive h/w following a reset.
1128 ath5k_rx_start(struct ath5k_softc
*sc
)
1130 struct ath5k_hw
*ah
= sc
->ah
;
1131 struct ath_common
*common
= ath5k_hw_common(ah
);
1132 struct ath5k_buf
*bf
;
1135 common
->rx_bufsize
= roundup(IEEE80211_MAX_FRAME_LEN
, common
->cachelsz
);
1137 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rx_bufsize %u\n",
1138 common
->cachelsz
, common
->rx_bufsize
);
1140 spin_lock_bh(&sc
->rxbuflock
);
1142 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1143 ret
= ath5k_rxbuf_setup(sc
, bf
);
1145 spin_unlock_bh(&sc
->rxbuflock
);
1149 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1150 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1151 spin_unlock_bh(&sc
->rxbuflock
);
1153 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1154 ath5k_mode_setup(sc
, NULL
); /* set filters, etc. */
1155 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1163 * Disable the receive logic on PCU (DRU)
1164 * In preparation for a shutdown.
1166 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1170 ath5k_rx_stop(struct ath5k_softc
*sc
)
1172 struct ath5k_hw
*ah
= sc
->ah
;
1174 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1175 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1177 ath5k_debug_printrxbuffs(sc
, ah
);
1181 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1182 struct ath5k_rx_status
*rs
)
1184 struct ath5k_hw
*ah
= sc
->ah
;
1185 struct ath_common
*common
= ath5k_hw_common(ah
);
1186 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1187 unsigned int keyix
, hlen
;
1189 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1190 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1191 return RX_FLAG_DECRYPTED
;
1193 /* Apparently when a default key is used to decrypt the packet
1194 the hw does not set the index used to decrypt. In such cases
1195 get the index from the packet. */
1196 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1197 if (ieee80211_has_protected(hdr
->frame_control
) &&
1198 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1199 skb
->len
>= hlen
+ 4) {
1200 keyix
= skb
->data
[hlen
+ 3] >> 6;
1202 if (test_bit(keyix
, common
->keymap
))
1203 return RX_FLAG_DECRYPTED
;
1211 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1212 struct ieee80211_rx_status
*rxs
)
1214 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
1217 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1219 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1220 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1221 memcmp(mgmt
->bssid
, common
->curbssid
, ETH_ALEN
) == 0) {
1223 * Received an IBSS beacon with the same BSSID. Hardware *must*
1224 * have updated the local TSF. We have to work around various
1225 * hardware bugs, though...
1227 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1228 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1229 hw_tu
= TSF_TO_TU(tsf
);
1231 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1232 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1233 (unsigned long long)bc_tstamp
,
1234 (unsigned long long)rxs
->mactime
,
1235 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1236 (unsigned long long)tsf
);
1239 * Sometimes the HW will give us a wrong tstamp in the rx
1240 * status, causing the timestamp extension to go wrong.
1241 * (This seems to happen especially with beacon frames bigger
1242 * than 78 byte (incl. FCS))
1243 * But we know that the receive timestamp must be later than the
1244 * timestamp of the beacon since HW must have synced to that.
1246 * NOTE: here we assume mactime to be after the frame was
1247 * received, not like mac80211 which defines it at the start.
1249 if (bc_tstamp
> rxs
->mactime
) {
1250 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1251 "fixing mactime from %llx to %llx\n",
1252 (unsigned long long)rxs
->mactime
,
1253 (unsigned long long)tsf
);
1258 * Local TSF might have moved higher than our beacon timers,
1259 * in that case we have to update them to continue sending
1260 * beacons. This also takes care of synchronizing beacon sending
1261 * times with other stations.
1263 if (hw_tu
>= sc
->nexttbtt
)
1264 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1266 /* Check if the beacon timers are still correct, because a TSF
1267 * update might have created a window between them - for a
1268 * longer description see the comment of this function: */
1269 if (!ath5k_hw_check_beacon_timers(sc
->ah
, sc
->bintval
)) {
1270 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1271 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1272 "fixed beacon timers after beacon receive\n");
1278 ath5k_update_beacon_rssi(struct ath5k_softc
*sc
, struct sk_buff
*skb
, int rssi
)
1280 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1281 struct ath5k_hw
*ah
= sc
->ah
;
1282 struct ath_common
*common
= ath5k_hw_common(ah
);
1284 /* only beacons from our BSSID */
1285 if (!ieee80211_is_beacon(mgmt
->frame_control
) ||
1286 memcmp(mgmt
->bssid
, common
->curbssid
, ETH_ALEN
) != 0)
1289 ewma_add(&ah
->ah_beacon_rssi_avg
, rssi
);
1291 /* in IBSS mode we should keep RSSI statistics per neighbour */
1292 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1296 * Compute padding position. skb must contain an IEEE 802.11 frame
1298 static int ath5k_common_padpos(struct sk_buff
*skb
)
1300 struct ieee80211_hdr
* hdr
= (struct ieee80211_hdr
*)skb
->data
;
1301 __le16 frame_control
= hdr
->frame_control
;
1304 if (ieee80211_has_a4(frame_control
)) {
1307 if (ieee80211_is_data_qos(frame_control
)) {
1308 padpos
+= IEEE80211_QOS_CTL_LEN
;
1315 * This function expects an 802.11 frame and returns the number of
1316 * bytes added, or -1 if we don't have enough header room.
1318 static int ath5k_add_padding(struct sk_buff
*skb
)
1320 int padpos
= ath5k_common_padpos(skb
);
1321 int padsize
= padpos
& 3;
1323 if (padsize
&& skb
->len
>padpos
) {
1325 if (skb_headroom(skb
) < padsize
)
1328 skb_push(skb
, padsize
);
1329 memmove(skb
->data
, skb
->data
+padsize
, padpos
);
1337 * The MAC header is padded to have 32-bit boundary if the
1338 * packet payload is non-zero. The general calculation for
1339 * padsize would take into account odd header lengths:
1340 * padsize = 4 - (hdrlen & 3); however, since only
1341 * even-length headers are used, padding can only be 0 or 2
1342 * bytes and we can optimize this a bit. We must not try to
1343 * remove padding from short control frames that do not have a
1346 * This function expects an 802.11 frame and returns the number of
1349 static int ath5k_remove_padding(struct sk_buff
*skb
)
1351 int padpos
= ath5k_common_padpos(skb
);
1352 int padsize
= padpos
& 3;
1354 if (padsize
&& skb
->len
>=padpos
+padsize
) {
1355 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
1356 skb_pull(skb
, padsize
);
1364 ath5k_receive_frame(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1365 struct ath5k_rx_status
*rs
)
1367 struct ieee80211_rx_status
*rxs
;
1369 ath5k_remove_padding(skb
);
1371 rxs
= IEEE80211_SKB_RXCB(skb
);
1374 if (unlikely(rs
->rs_status
& AR5K_RXERR_MIC
))
1375 rxs
->flag
|= RX_FLAG_MMIC_ERROR
;
1378 * always extend the mac timestamp, since this information is
1379 * also needed for proper IBSS merging.
1381 * XXX: it might be too late to do it here, since rs_tstamp is
1382 * 15bit only. that means TSF extension has to be done within
1383 * 32768usec (about 32ms). it might be necessary to move this to
1384 * the interrupt handler, like it is done in madwifi.
1386 * Unfortunately we don't know when the hardware takes the rx
1387 * timestamp (beginning of phy frame, data frame, end of rx?).
1388 * The only thing we know is that it is hardware specific...
1389 * On AR5213 it seems the rx timestamp is at the end of the
1390 * frame, but i'm not sure.
1392 * NOTE: mac80211 defines mactime at the beginning of the first
1393 * data symbol. Since we don't have any time references it's
1394 * impossible to comply to that. This affects IBSS merge only
1395 * right now, so it's not too bad...
1397 rxs
->mactime
= ath5k_extend_tsf(sc
->ah
, rs
->rs_tstamp
);
1398 rxs
->flag
|= RX_FLAG_TSFT
;
1400 rxs
->freq
= sc
->curchan
->center_freq
;
1401 rxs
->band
= sc
->curband
->band
;
1403 rxs
->signal
= sc
->ah
->ah_noise_floor
+ rs
->rs_rssi
;
1405 rxs
->antenna
= rs
->rs_antenna
;
1407 if (rs
->rs_antenna
> 0 && rs
->rs_antenna
< 5)
1408 sc
->stats
.antenna_rx
[rs
->rs_antenna
]++;
1410 sc
->stats
.antenna_rx
[0]++; /* invalid */
1412 rxs
->rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
->rs_rate
);
1413 rxs
->flag
|= ath5k_rx_decrypted(sc
, skb
, rs
);
1415 if (rxs
->rate_idx
>= 0 && rs
->rs_rate
==
1416 sc
->curband
->bitrates
[rxs
->rate_idx
].hw_value_short
)
1417 rxs
->flag
|= RX_FLAG_SHORTPRE
;
1419 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1421 ath5k_update_beacon_rssi(sc
, skb
, rs
->rs_rssi
);
1423 /* check beacons in IBSS mode */
1424 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
1425 ath5k_check_ibss_tsf(sc
, skb
, rxs
);
1427 ieee80211_rx(sc
->hw
, skb
);
1430 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1432 * Check if we want to further process this frame or not. Also update
1433 * statistics. Return true if we want this frame, false if not.
1436 ath5k_receive_frame_ok(struct ath5k_softc
*sc
, struct ath5k_rx_status
*rs
)
1438 sc
->stats
.rx_all_count
++;
1439 sc
->stats
.rx_bytes_count
+= rs
->rs_datalen
;
1441 if (unlikely(rs
->rs_status
)) {
1442 if (rs
->rs_status
& AR5K_RXERR_CRC
)
1443 sc
->stats
.rxerr_crc
++;
1444 if (rs
->rs_status
& AR5K_RXERR_FIFO
)
1445 sc
->stats
.rxerr_fifo
++;
1446 if (rs
->rs_status
& AR5K_RXERR_PHY
) {
1447 sc
->stats
.rxerr_phy
++;
1448 if (rs
->rs_phyerr
> 0 && rs
->rs_phyerr
< 32)
1449 sc
->stats
.rxerr_phy_code
[rs
->rs_phyerr
]++;
1452 if (rs
->rs_status
& AR5K_RXERR_DECRYPT
) {
1454 * Decrypt error. If the error occurred
1455 * because there was no hardware key, then
1456 * let the frame through so the upper layers
1457 * can process it. This is necessary for 5210
1458 * parts which have no way to setup a ``clear''
1461 * XXX do key cache faulting
1463 sc
->stats
.rxerr_decrypt
++;
1464 if (rs
->rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1465 !(rs
->rs_status
& AR5K_RXERR_CRC
))
1468 if (rs
->rs_status
& AR5K_RXERR_MIC
) {
1469 sc
->stats
.rxerr_mic
++;
1473 /* reject any frames with non-crypto errors */
1474 if (rs
->rs_status
& ~(AR5K_RXERR_DECRYPT
))
1478 if (unlikely(rs
->rs_more
)) {
1479 sc
->stats
.rxerr_jumbo
++;
1486 ath5k_tasklet_rx(unsigned long data
)
1488 struct ath5k_rx_status rs
= {};
1489 struct sk_buff
*skb
, *next_skb
;
1490 dma_addr_t next_skb_addr
;
1491 struct ath5k_softc
*sc
= (void *)data
;
1492 struct ath5k_hw
*ah
= sc
->ah
;
1493 struct ath_common
*common
= ath5k_hw_common(ah
);
1494 struct ath5k_buf
*bf
;
1495 struct ath5k_desc
*ds
;
1498 spin_lock(&sc
->rxbuflock
);
1499 if (list_empty(&sc
->rxbuf
)) {
1500 ATH5K_WARN(sc
, "empty rx buf pool\n");
1504 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1505 BUG_ON(bf
->skb
== NULL
);
1509 /* bail if HW is still using self-linked descriptor */
1510 if (ath5k_hw_get_rxdp(sc
->ah
) == bf
->daddr
)
1513 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1514 if (unlikely(ret
== -EINPROGRESS
))
1516 else if (unlikely(ret
)) {
1517 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1518 sc
->stats
.rxerr_proc
++;
1522 if (ath5k_receive_frame_ok(sc
, &rs
)) {
1523 next_skb
= ath5k_rx_skb_alloc(sc
, &next_skb_addr
);
1526 * If we can't replace bf->skb with a new skb under
1527 * memory pressure, just skip this packet
1532 pci_unmap_single(sc
->pdev
, bf
->skbaddr
,
1534 PCI_DMA_FROMDEVICE
);
1536 skb_put(skb
, rs
.rs_datalen
);
1538 ath5k_receive_frame(sc
, skb
, &rs
);
1541 bf
->skbaddr
= next_skb_addr
;
1544 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1545 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1547 spin_unlock(&sc
->rxbuflock
);
1555 static int ath5k_tx_queue(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1556 struct ath5k_txq
*txq
)
1558 struct ath5k_softc
*sc
= hw
->priv
;
1559 struct ath5k_buf
*bf
;
1560 unsigned long flags
;
1563 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
1566 * The hardware expects the header padded to 4 byte boundaries.
1567 * If this is not the case, we add the padding after the header.
1569 padsize
= ath5k_add_padding(skb
);
1571 ATH5K_ERR(sc
, "tx hdrlen not %%4: not enough"
1572 " headroom to pad");
1576 if (txq
->txq_len
>= ATH5K_TXQ_LEN_MAX
)
1577 ieee80211_stop_queue(hw
, txq
->qnum
);
1579 spin_lock_irqsave(&sc
->txbuflock
, flags
);
1580 if (list_empty(&sc
->txbuf
)) {
1581 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
1582 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
1583 ieee80211_stop_queues(hw
);
1586 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
1587 list_del(&bf
->list
);
1589 if (list_empty(&sc
->txbuf
))
1590 ieee80211_stop_queues(hw
);
1591 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
1595 if (ath5k_txbuf_setup(sc
, bf
, txq
, padsize
)) {
1597 spin_lock_irqsave(&sc
->txbuflock
, flags
);
1598 list_add_tail(&bf
->list
, &sc
->txbuf
);
1600 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
1603 return NETDEV_TX_OK
;
1606 dev_kfree_skb_any(skb
);
1607 return NETDEV_TX_OK
;
1611 ath5k_tx_frame_completed(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1612 struct ath5k_tx_status
*ts
)
1614 struct ieee80211_tx_info
*info
;
1617 sc
->stats
.tx_all_count
++;
1618 sc
->stats
.tx_bytes_count
+= skb
->len
;
1619 info
= IEEE80211_SKB_CB(skb
);
1621 ieee80211_tx_info_clear_status(info
);
1622 for (i
= 0; i
< 4; i
++) {
1623 struct ieee80211_tx_rate
*r
=
1624 &info
->status
.rates
[i
];
1626 if (ts
->ts_rate
[i
]) {
1627 r
->idx
= ath5k_hw_to_driver_rix(sc
, ts
->ts_rate
[i
]);
1628 r
->count
= ts
->ts_retry
[i
];
1635 /* count the successful attempt as well */
1636 info
->status
.rates
[ts
->ts_final_idx
].count
++;
1638 if (unlikely(ts
->ts_status
)) {
1639 sc
->stats
.ack_fail
++;
1640 if (ts
->ts_status
& AR5K_TXERR_FILT
) {
1641 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1642 sc
->stats
.txerr_filt
++;
1644 if (ts
->ts_status
& AR5K_TXERR_XRETRY
)
1645 sc
->stats
.txerr_retry
++;
1646 if (ts
->ts_status
& AR5K_TXERR_FIFO
)
1647 sc
->stats
.txerr_fifo
++;
1649 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1650 info
->status
.ack_signal
= ts
->ts_rssi
;
1654 * Remove MAC header padding before giving the frame
1657 ath5k_remove_padding(skb
);
1659 if (ts
->ts_antenna
> 0 && ts
->ts_antenna
< 5)
1660 sc
->stats
.antenna_tx
[ts
->ts_antenna
]++;
1662 sc
->stats
.antenna_tx
[0]++; /* invalid */
1664 ieee80211_tx_status(sc
->hw
, skb
);
1668 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1670 struct ath5k_tx_status ts
= {};
1671 struct ath5k_buf
*bf
, *bf0
;
1672 struct ath5k_desc
*ds
;
1673 struct sk_buff
*skb
;
1676 spin_lock(&txq
->lock
);
1677 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1679 txq
->txq_poll_mark
= false;
1681 /* skb might already have been processed last time. */
1682 if (bf
->skb
!= NULL
) {
1685 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1686 if (unlikely(ret
== -EINPROGRESS
))
1688 else if (unlikely(ret
)) {
1690 "error %d while processing "
1691 "queue %u\n", ret
, txq
->qnum
);
1697 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
1699 ath5k_tx_frame_completed(sc
, skb
, &ts
);
1703 * It's possible that the hardware can say the buffer is
1704 * completed when it hasn't yet loaded the ds_link from
1705 * host memory and moved on.
1706 * Always keep the last descriptor to avoid HW races...
1708 if (ath5k_hw_get_txdp(sc
->ah
, txq
->qnum
) != bf
->daddr
) {
1709 spin_lock(&sc
->txbuflock
);
1710 list_move_tail(&bf
->list
, &sc
->txbuf
);
1713 spin_unlock(&sc
->txbuflock
);
1716 spin_unlock(&txq
->lock
);
1717 if (txq
->txq_len
< ATH5K_TXQ_LEN_LOW
&& txq
->qnum
< 4)
1718 ieee80211_wake_queue(sc
->hw
, txq
->qnum
);
1722 ath5k_tasklet_tx(unsigned long data
)
1725 struct ath5k_softc
*sc
= (void *)data
;
1727 for (i
=0; i
< AR5K_NUM_TX_QUEUES
; i
++)
1728 if (sc
->txqs
[i
].setup
&& (sc
->ah
->ah_txq_isr
& BIT(i
)))
1729 ath5k_tx_processq(sc
, &sc
->txqs
[i
]);
1738 * Setup the beacon frame for transmit.
1741 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1743 struct sk_buff
*skb
= bf
->skb
;
1744 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1745 struct ath5k_hw
*ah
= sc
->ah
;
1746 struct ath5k_desc
*ds
;
1750 const int padsize
= 0;
1752 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1754 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1755 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1756 (unsigned long long)bf
->skbaddr
);
1757 if (pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
)) {
1758 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
1763 antenna
= ah
->ah_tx_ant
;
1765 flags
= AR5K_TXDESC_NOACK
;
1766 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
1767 ds
->ds_link
= bf
->daddr
; /* self-linked */
1768 flags
|= AR5K_TXDESC_VEOL
;
1773 * If we use multiple antennas on AP and use
1774 * the Sectored AP scenario, switch antenna every
1775 * 4 beacons to make sure everybody hears our AP.
1776 * When a client tries to associate, hw will keep
1777 * track of the tx antenna to be used for this client
1778 * automaticaly, based on ACKed packets.
1780 * Note: AP still listens and transmits RTS on the
1781 * default antenna which is supposed to be an omni.
1783 * Note2: On sectored scenarios it's possible to have
1784 * multiple antennas (1 omni -- the default -- and 14
1785 * sectors), so if we choose to actually support this
1786 * mode, we need to allow the user to set how many antennas
1787 * we have and tweak the code below to send beacons
1790 if (ah
->ah_ant_mode
== AR5K_ANTMODE_SECTOR_AP
)
1791 antenna
= sc
->bsent
& 4 ? 2 : 1;
1794 /* FIXME: If we are in g mode and rate is a CCK rate
1795 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1796 * from tx power (value is in dB units already) */
1797 ds
->ds_data
= bf
->skbaddr
;
1798 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
1799 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
1800 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
1801 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1802 1, AR5K_TXKEYIX_INVALID
,
1803 antenna
, flags
, 0, 0);
1809 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1814 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1815 * this is called only once at config_bss time, for AP we do it every
1816 * SWBA interrupt so that the TIM will reflect buffered frames.
1818 * Called with the beacon lock.
1821 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
1824 struct ath5k_softc
*sc
= hw
->priv
;
1825 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
1826 struct sk_buff
*skb
;
1828 if (WARN_ON(!vif
)) {
1833 skb
= ieee80211_beacon_get(hw
, vif
);
1840 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
1842 ath5k_txbuf_free_skb(sc
, avf
->bbuf
);
1843 avf
->bbuf
->skb
= skb
;
1844 ret
= ath5k_beacon_setup(sc
, avf
->bbuf
);
1846 avf
->bbuf
->skb
= NULL
;
1852 * Transmit a beacon frame at SWBA. Dynamic updates to the
1853 * frame contents are done as needed and the slot time is
1854 * also adjusted based on current state.
1856 * This is called from software irq context (beacontq tasklets)
1857 * or user context from ath5k_beacon_config.
1860 ath5k_beacon_send(struct ath5k_softc
*sc
)
1862 struct ath5k_hw
*ah
= sc
->ah
;
1863 struct ieee80211_vif
*vif
;
1864 struct ath5k_vif
*avf
;
1865 struct ath5k_buf
*bf
;
1866 struct sk_buff
*skb
;
1868 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
1871 * Check if the previous beacon has gone out. If
1872 * not, don't don't try to post another: skip this
1873 * period and wait for the next. Missed beacons
1874 * indicate a problem and should not occur. If we
1875 * miss too many consecutive beacons reset the device.
1877 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
1879 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1880 "missed %u consecutive beacons\n", sc
->bmisscount
);
1881 if (sc
->bmisscount
> 10) { /* NB: 10 is a guess */
1882 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1883 "stuck beacon time (%u missed)\n",
1885 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
1886 "stuck beacon, resetting\n");
1887 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
1891 if (unlikely(sc
->bmisscount
!= 0)) {
1892 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1893 "resume beacon xmit after %u misses\n",
1898 if (sc
->opmode
== NL80211_IFTYPE_AP
&& sc
->num_ap_vifs
> 1) {
1899 u64 tsf
= ath5k_hw_get_tsf64(ah
);
1900 u32 tsftu
= TSF_TO_TU(tsf
);
1901 int slot
= ((tsftu
% sc
->bintval
) * ATH_BCBUF
) / sc
->bintval
;
1902 vif
= sc
->bslot
[(slot
+ 1) % ATH_BCBUF
];
1903 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1904 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1905 (unsigned long long)tsf
, tsftu
, sc
->bintval
, slot
, vif
);
1906 } else /* only one interface */
1912 avf
= (void *)vif
->drv_priv
;
1914 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== NL80211_IFTYPE_STATION
||
1915 sc
->opmode
== NL80211_IFTYPE_MONITOR
)) {
1916 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
1921 * Stop any current dma and put the new frame on the queue.
1922 * This should never fail since we check above that no frames
1923 * are still pending on the queue.
1925 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
1926 ATH5K_WARN(sc
, "beacon queue %u didn't start/stop ?\n", sc
->bhalq
);
1927 /* NB: hw still stops DMA, so proceed */
1930 /* refresh the beacon for AP mode */
1931 if (sc
->opmode
== NL80211_IFTYPE_AP
)
1932 ath5k_beacon_update(sc
->hw
, vif
);
1934 ath5k_hw_set_txdp(ah
, sc
->bhalq
, bf
->daddr
);
1935 ath5k_hw_start_tx_dma(ah
, sc
->bhalq
);
1936 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
1937 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
1939 skb
= ieee80211_get_buffered_bc(sc
->hw
, vif
);
1941 ath5k_tx_queue(sc
->hw
, skb
, sc
->cabq
);
1942 skb
= ieee80211_get_buffered_bc(sc
->hw
, vif
);
1949 * ath5k_beacon_update_timers - update beacon timers
1951 * @sc: struct ath5k_softc pointer we are operating on
1952 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1953 * beacon timer update based on the current HW TSF.
1955 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1956 * of a received beacon or the current local hardware TSF and write it to the
1957 * beacon timer registers.
1959 * This is called in a variety of situations, e.g. when a beacon is received,
1960 * when a TSF update has been detected, but also when an new IBSS is created or
1961 * when we otherwise know we have to update the timers, but we keep it in this
1962 * function to have it all together in one place.
1965 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
1967 struct ath5k_hw
*ah
= sc
->ah
;
1968 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
1971 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
1972 if (sc
->opmode
== NL80211_IFTYPE_AP
&& sc
->num_ap_vifs
> 1) {
1973 intval
/= ATH_BCBUF
; /* staggered multi-bss beacons */
1975 ATH5K_WARN(sc
, "intval %u is too low, min 15\n",
1978 if (WARN_ON(!intval
))
1981 /* beacon TSF converted to TU */
1982 bc_tu
= TSF_TO_TU(bc_tsf
);
1984 /* current TSF converted to TU */
1985 hw_tsf
= ath5k_hw_get_tsf64(ah
);
1986 hw_tu
= TSF_TO_TU(hw_tsf
);
1988 #define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1989 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1990 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1991 * configuration we need to make sure it is bigger than that. */
1995 * no beacons received, called internally.
1996 * just need to refresh timers based on HW TSF.
1998 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
1999 } else if (bc_tsf
== 0) {
2001 * no beacon received, probably called by ath5k_reset_tsf().
2002 * reset TSF to start with 0.
2005 intval
|= AR5K_BEACON_RESET_TSF
;
2006 } else if (bc_tsf
> hw_tsf
) {
2008 * beacon received, SW merge happend but HW TSF not yet updated.
2009 * not possible to reconfigure timers yet, but next time we
2010 * receive a beacon with the same BSSID, the hardware will
2011 * automatically update the TSF and then we need to reconfigure
2014 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2015 "need to wait for HW TSF sync\n");
2019 * most important case for beacon synchronization between STA.
2021 * beacon received and HW TSF has been already updated by HW.
2022 * update next TBTT based on the TSF of the beacon, but make
2023 * sure it is ahead of our local TSF timer.
2025 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2029 sc
->nexttbtt
= nexttbtt
;
2031 intval
|= AR5K_BEACON_ENA
;
2032 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2035 * debugging output last in order to preserve the time critical aspect
2039 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2040 "reconfigured timers based on HW TSF\n");
2041 else if (bc_tsf
== 0)
2042 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2043 "reset HW TSF and timers\n");
2045 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2046 "updated timers based on beacon TSF\n");
2048 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2049 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2050 (unsigned long long) bc_tsf
,
2051 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2052 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2053 intval
& AR5K_BEACON_PERIOD
,
2054 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2055 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2059 * ath5k_beacon_config - Configure the beacon queues and interrupts
2061 * @sc: struct ath5k_softc pointer we are operating on
2063 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2064 * interrupts to detect TSF updates only.
2067 ath5k_beacon_config(struct ath5k_softc
*sc
)
2069 struct ath5k_hw
*ah
= sc
->ah
;
2070 unsigned long flags
;
2072 spin_lock_irqsave(&sc
->block
, flags
);
2074 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2076 if (sc
->enable_beacon
) {
2078 * In IBSS mode we use a self-linked tx descriptor and let the
2079 * hardware send the beacons automatically. We have to load it
2081 * We use the SWBA interrupt only to keep track of the beacon
2082 * timers in order to detect automatic TSF updates.
2084 ath5k_beaconq_config(sc
);
2086 sc
->imask
|= AR5K_INT_SWBA
;
2088 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2089 if (ath5k_hw_hasveol(ah
))
2090 ath5k_beacon_send(sc
);
2092 ath5k_beacon_update_timers(sc
, -1);
2094 ath5k_hw_stop_tx_dma(sc
->ah
, sc
->bhalq
);
2097 ath5k_hw_set_imr(ah
, sc
->imask
);
2099 spin_unlock_irqrestore(&sc
->block
, flags
);
2102 static void ath5k_tasklet_beacon(unsigned long data
)
2104 struct ath5k_softc
*sc
= (struct ath5k_softc
*) data
;
2107 * Software beacon alert--time to send a beacon.
2109 * In IBSS mode we use this interrupt just to
2110 * keep track of the next TBTT (target beacon
2111 * transmission time) in order to detect wether
2112 * automatic TSF updates happened.
2114 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2115 /* XXX: only if VEOL suppported */
2116 u64 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
2117 sc
->nexttbtt
+= sc
->bintval
;
2118 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2119 "SWBA nexttbtt: %x hw_tu: %x "
2123 (unsigned long long) tsf
);
2125 spin_lock(&sc
->block
);
2126 ath5k_beacon_send(sc
);
2127 spin_unlock(&sc
->block
);
2132 /********************\
2133 * Interrupt handling *
2134 \********************/
2137 ath5k_intr_calibration_poll(struct ath5k_hw
*ah
)
2139 if (time_is_before_eq_jiffies(ah
->ah_cal_next_ani
) &&
2140 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
)) {
2141 /* run ANI only when full calibration is not active */
2142 ah
->ah_cal_next_ani
= jiffies
+
2143 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI
);
2144 tasklet_schedule(&ah
->ah_sc
->ani_tasklet
);
2146 } else if (time_is_before_eq_jiffies(ah
->ah_cal_next_full
)) {
2147 ah
->ah_cal_next_full
= jiffies
+
2148 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL
);
2149 tasklet_schedule(&ah
->ah_sc
->calib
);
2151 /* we could use SWI to generate enough interrupts to meet our
2152 * calibration interval requirements, if necessary:
2153 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2157 ath5k_intr(int irq
, void *dev_id
)
2159 struct ath5k_softc
*sc
= dev_id
;
2160 struct ath5k_hw
*ah
= sc
->ah
;
2161 enum ath5k_int status
;
2162 unsigned int counter
= 1000;
2164 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2165 !ath5k_hw_is_intr_pending(ah
)))
2169 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2170 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2172 if (unlikely(status
& AR5K_INT_FATAL
)) {
2174 * Fatal errors are unrecoverable.
2175 * Typically these are caused by DMA errors.
2177 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2178 "fatal int, resetting\n");
2179 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
2180 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2182 * Receive buffers are full. Either the bus is busy or
2183 * the CPU is not fast enough to process all received
2185 * Older chipsets need a reset to come out of this
2186 * condition, but we treat it as RX for newer chips.
2187 * We don't know exactly which versions need a reset -
2188 * this guess is copied from the HAL.
2190 sc
->stats
.rxorn_intr
++;
2191 if (ah
->ah_mac_srev
< AR5K_SREV_AR5212
) {
2192 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2193 "rx overrun, resetting\n");
2194 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
2197 tasklet_schedule(&sc
->rxtq
);
2199 if (status
& AR5K_INT_SWBA
) {
2200 tasklet_hi_schedule(&sc
->beacontq
);
2202 if (status
& AR5K_INT_RXEOL
) {
2204 * NB: the hardware should re-read the link when
2205 * RXE bit is written, but it doesn't work at
2206 * least on older hardware revs.
2208 sc
->stats
.rxeol_intr
++;
2210 if (status
& AR5K_INT_TXURN
) {
2211 /* bump tx trigger level */
2212 ath5k_hw_update_tx_triglevel(ah
, true);
2214 if (status
& (AR5K_INT_RXOK
| AR5K_INT_RXERR
))
2215 tasklet_schedule(&sc
->rxtq
);
2216 if (status
& (AR5K_INT_TXOK
| AR5K_INT_TXDESC
2217 | AR5K_INT_TXERR
| AR5K_INT_TXEOL
))
2218 tasklet_schedule(&sc
->txtq
);
2219 if (status
& AR5K_INT_BMISS
) {
2222 if (status
& AR5K_INT_MIB
) {
2223 sc
->stats
.mib_intr
++;
2224 ath5k_hw_update_mib_counters(ah
);
2225 ath5k_ani_mib_intr(ah
);
2227 if (status
& AR5K_INT_GPIO
)
2228 tasklet_schedule(&sc
->rf_kill
.toggleq
);
2231 } while (ath5k_hw_is_intr_pending(ah
) && --counter
> 0);
2233 if (unlikely(!counter
))
2234 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2236 ath5k_intr_calibration_poll(ah
);
2242 * Periodically recalibrate the PHY to account
2243 * for temperature/environment changes.
2246 ath5k_tasklet_calibrate(unsigned long data
)
2248 struct ath5k_softc
*sc
= (void *)data
;
2249 struct ath5k_hw
*ah
= sc
->ah
;
2251 /* Only full calibration for now */
2252 ah
->ah_cal_mask
|= AR5K_CALIBRATION_FULL
;
2254 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2255 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2256 sc
->curchan
->hw_value
);
2258 if (ath5k_hw_gainf_calibrate(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2260 * Rfgain is out of bounds, reset the chip
2261 * to load new gain values.
2263 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2264 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
2266 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2267 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2268 ieee80211_frequency_to_channel(
2269 sc
->curchan
->center_freq
));
2271 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2273 * TODO: We should stop TX here, so that it doesn't interfere.
2274 * Note that stopping the queues is not enough to stop TX! */
2275 if (time_is_before_eq_jiffies(ah
->ah_cal_next_nf
)) {
2276 ah
->ah_cal_next_nf
= jiffies
+
2277 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF
);
2278 ath5k_hw_update_noise_floor(ah
);
2281 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_FULL
;
2286 ath5k_tasklet_ani(unsigned long data
)
2288 struct ath5k_softc
*sc
= (void *)data
;
2289 struct ath5k_hw
*ah
= sc
->ah
;
2291 ah
->ah_cal_mask
|= AR5K_CALIBRATION_ANI
;
2292 ath5k_ani_calibration(ah
);
2293 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_ANI
;
2298 ath5k_tx_complete_poll_work(struct work_struct
*work
)
2300 struct ath5k_softc
*sc
= container_of(work
, struct ath5k_softc
,
2301 tx_complete_work
.work
);
2302 struct ath5k_txq
*txq
;
2304 bool needreset
= false;
2306 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++) {
2307 if (sc
->txqs
[i
].setup
) {
2309 spin_lock_bh(&txq
->lock
);
2310 if (txq
->txq_len
> 1) {
2311 if (txq
->txq_poll_mark
) {
2312 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
,
2313 "TX queue stuck %d\n",
2317 spin_unlock_bh(&txq
->lock
);
2320 txq
->txq_poll_mark
= true;
2323 spin_unlock_bh(&txq
->lock
);
2328 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2329 "TX queues stuck, resetting\n");
2330 ath5k_reset(sc
, sc
->curchan
);
2333 ieee80211_queue_delayed_work(sc
->hw
, &sc
->tx_complete_work
,
2334 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2338 /*************************\
2339 * Initialization routines *
2340 \*************************/
2343 ath5k_stop_locked(struct ath5k_softc
*sc
)
2345 struct ath5k_hw
*ah
= sc
->ah
;
2347 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2348 test_bit(ATH_STAT_INVALID
, sc
->status
));
2351 * Shutdown the hardware and driver:
2352 * stop output from above
2353 * disable interrupts
2355 * turn off the radio
2356 * clear transmit machinery
2357 * clear receive machinery
2358 * drain and release tx queues
2359 * reclaim beacon resources
2360 * power down hardware
2362 * Note that some of this work is not possible if the
2363 * hardware is gone (invalid).
2365 ieee80211_stop_queues(sc
->hw
);
2367 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2369 ath5k_hw_set_imr(ah
, 0);
2370 synchronize_irq(sc
->pdev
->irq
);
2372 ath5k_hw_dma_stop(ah
);
2373 ath5k_drain_tx_buffs(sc
);
2374 ath5k_hw_phy_disable(ah
);
2381 ath5k_init(struct ath5k_softc
*sc
)
2383 struct ath5k_hw
*ah
= sc
->ah
;
2384 struct ath_common
*common
= ath5k_hw_common(ah
);
2387 mutex_lock(&sc
->lock
);
2389 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2392 * Stop anything previously setup. This is safe
2393 * no matter this is the first time through or not.
2395 ath5k_stop_locked(sc
);
2398 * The basic interface to setting the hardware in a good
2399 * state is ``reset''. On return the hardware is known to
2400 * be powered up and with interrupts disabled. This must
2401 * be followed by initialization of the appropriate bits
2402 * and then setup of the interrupt mask.
2404 sc
->curchan
= sc
->hw
->conf
.channel
;
2405 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2406 sc
->imask
= AR5K_INT_RXOK
| AR5K_INT_RXERR
| AR5K_INT_RXEOL
|
2407 AR5K_INT_RXORN
| AR5K_INT_TXDESC
| AR5K_INT_TXEOL
|
2408 AR5K_INT_FATAL
| AR5K_INT_GLOBAL
| AR5K_INT_MIB
;
2410 ret
= ath5k_reset(sc
, NULL
);
2414 ath5k_rfkill_hw_start(ah
);
2417 * Reset the key cache since some parts do not reset the
2418 * contents on initial power up or resume from suspend.
2420 for (i
= 0; i
< common
->keymax
; i
++)
2421 ath_hw_keyreset(common
, (u16
) i
);
2423 ath5k_hw_set_ack_bitrate_high(ah
, true);
2425 for (i
= 0; i
< ARRAY_SIZE(sc
->bslot
); i
++)
2426 sc
->bslot
[i
] = NULL
;
2431 mutex_unlock(&sc
->lock
);
2433 ieee80211_queue_delayed_work(sc
->hw
, &sc
->tx_complete_work
,
2434 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2439 static void stop_tasklets(struct ath5k_softc
*sc
)
2441 tasklet_kill(&sc
->rxtq
);
2442 tasklet_kill(&sc
->txtq
);
2443 tasklet_kill(&sc
->calib
);
2444 tasklet_kill(&sc
->beacontq
);
2445 tasklet_kill(&sc
->ani_tasklet
);
2449 * Stop the device, grabbing the top-level lock to protect
2450 * against concurrent entry through ath5k_init (which can happen
2451 * if another thread does a system call and the thread doing the
2452 * stop is preempted).
2455 ath5k_stop_hw(struct ath5k_softc
*sc
)
2459 mutex_lock(&sc
->lock
);
2460 ret
= ath5k_stop_locked(sc
);
2461 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2463 * Don't set the card in full sleep mode!
2465 * a) When the device is in this state it must be carefully
2466 * woken up or references to registers in the PCI clock
2467 * domain may freeze the bus (and system). This varies
2468 * by chip and is mostly an issue with newer parts
2469 * (madwifi sources mentioned srev >= 0x78) that go to
2470 * sleep more quickly.
2472 * b) On older chips full sleep results a weird behaviour
2473 * during wakeup. I tested various cards with srev < 0x78
2474 * and they don't wake up after module reload, a second
2475 * module reload is needed to bring the card up again.
2477 * Until we figure out what's going on don't enable
2478 * full chip reset on any chip (this is what Legacy HAL
2479 * and Sam's HAL do anyway). Instead Perform a full reset
2480 * on the device (same as initial state after attach) and
2481 * leave it idle (keep MAC/BB on warm reset) */
2482 ret
= ath5k_hw_on_hold(sc
->ah
);
2484 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2485 "putting device to sleep\n");
2489 mutex_unlock(&sc
->lock
);
2493 cancel_delayed_work_sync(&sc
->tx_complete_work
);
2495 ath5k_rfkill_hw_stop(sc
->ah
);
2501 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2502 * and change to the given channel.
2504 * This should be called with sc->lock.
2507 ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
2509 struct ath5k_hw
*ah
= sc
->ah
;
2512 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2514 ath5k_hw_set_imr(ah
, 0);
2515 synchronize_irq(sc
->pdev
->irq
);
2519 ath5k_drain_tx_buffs(sc
);
2522 sc
->curband
= &sc
->sbands
[chan
->band
];
2524 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, chan
!= NULL
);
2526 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2530 ret
= ath5k_rx_start(sc
);
2532 ATH5K_ERR(sc
, "can't start recv logic\n");
2536 ath5k_ani_init(ah
, ah
->ah_sc
->ani_state
.ani_mode
);
2538 ah
->ah_cal_next_full
= jiffies
;
2539 ah
->ah_cal_next_ani
= jiffies
;
2540 ah
->ah_cal_next_nf
= jiffies
;
2541 ewma_init(&ah
->ah_beacon_rssi_avg
, 1000, 8);
2544 * Change channels and update the h/w rate map if we're switching;
2545 * e.g. 11a to 11b/g.
2547 * We may be doing a reset in response to an ioctl that changes the
2548 * channel so update any state that might change as a result.
2552 /* ath5k_chan_change(sc, c); */
2554 ath5k_beacon_config(sc
);
2555 /* intrs are enabled by ath5k_beacon_config */
2557 ieee80211_wake_queues(sc
->hw
);
2564 static void ath5k_reset_work(struct work_struct
*work
)
2566 struct ath5k_softc
*sc
= container_of(work
, struct ath5k_softc
,
2569 mutex_lock(&sc
->lock
);
2570 ath5k_reset(sc
, sc
->curchan
);
2571 mutex_unlock(&sc
->lock
);
2575 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
2577 struct ath5k_softc
*sc
= hw
->priv
;
2578 struct ath5k_hw
*ah
= sc
->ah
;
2579 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
2580 struct ath5k_txq
*txq
;
2581 u8 mac
[ETH_ALEN
] = {};
2584 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
2587 * Check if the MAC has multi-rate retry support.
2588 * We do this by trying to setup a fake extended
2589 * descriptor. MACs that don't have support will
2590 * return false w/o doing anything. MACs that do
2591 * support it will return true w/o doing anything.
2593 ret
= ath5k_hw_setup_mrr_tx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
2598 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
2601 * Collect the channel list. The 802.11 layer
2602 * is resposible for filtering this list based
2603 * on settings like the phy mode and regulatory
2604 * domain restrictions.
2606 ret
= ath5k_setup_bands(hw
);
2608 ATH5K_ERR(sc
, "can't get channels\n");
2612 /* NB: setup here so ath5k_rate_update is happy */
2613 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
2614 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
2616 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
2619 * Allocate tx+rx descriptors and populate the lists.
2621 ret
= ath5k_desc_alloc(sc
, pdev
);
2623 ATH5K_ERR(sc
, "can't allocate descriptors\n");
2628 * Allocate hardware transmit queues: one queue for
2629 * beacon frames and one data queue for each QoS
2630 * priority. Note that hw functions handle resetting
2631 * these queues at the needed time.
2633 ret
= ath5k_beaconq_setup(ah
);
2635 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
2639 sc
->cabq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_CAB
, 0);
2640 if (IS_ERR(sc
->cabq
)) {
2641 ATH5K_ERR(sc
, "can't setup cab queue\n");
2642 ret
= PTR_ERR(sc
->cabq
);
2646 /* This order matches mac80211's queue priority, so we can
2647 * directly use the mac80211 queue number without any mapping */
2648 txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VO
);
2650 ATH5K_ERR(sc
, "can't setup xmit queue\n");
2654 txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VI
);
2656 ATH5K_ERR(sc
, "can't setup xmit queue\n");
2660 txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BE
);
2662 ATH5K_ERR(sc
, "can't setup xmit queue\n");
2666 txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
2668 ATH5K_ERR(sc
, "can't setup xmit queue\n");
2674 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
2675 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
2676 tasklet_init(&sc
->calib
, ath5k_tasklet_calibrate
, (unsigned long)sc
);
2677 tasklet_init(&sc
->beacontq
, ath5k_tasklet_beacon
, (unsigned long)sc
);
2678 tasklet_init(&sc
->ani_tasklet
, ath5k_tasklet_ani
, (unsigned long)sc
);
2680 INIT_WORK(&sc
->reset_work
, ath5k_reset_work
);
2681 INIT_DELAYED_WORK(&sc
->tx_complete_work
, ath5k_tx_complete_poll_work
);
2683 ret
= ath5k_eeprom_read_mac(ah
, mac
);
2685 ATH5K_ERR(sc
, "unable to read address from EEPROM: 0x%04x\n",
2690 SET_IEEE80211_PERM_ADDR(hw
, mac
);
2691 memcpy(&sc
->lladdr
, mac
, ETH_ALEN
);
2692 /* All MAC address bits matter for ACKs */
2693 ath5k_update_bssid_mask_and_opmode(sc
, NULL
);
2695 regulatory
->current_rd
= ah
->ah_capabilities
.cap_eeprom
.ee_regdomain
;
2696 ret
= ath_regd_init(regulatory
, hw
->wiphy
, ath5k_reg_notifier
);
2698 ATH5K_ERR(sc
, "can't initialize regulatory system\n");
2702 ret
= ieee80211_register_hw(hw
);
2704 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
2708 if (!ath_is_world_regd(regulatory
))
2709 regulatory_hint(hw
->wiphy
, regulatory
->alpha2
);
2711 ath5k_init_leds(sc
);
2713 ath5k_sysfs_register(sc
);
2717 ath5k_txq_release(sc
);
2719 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
2721 ath5k_desc_free(sc
, pdev
);
2727 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
2729 struct ath5k_softc
*sc
= hw
->priv
;
2732 * NB: the order of these is important:
2733 * o call the 802.11 layer before detaching ath5k_hw to
2734 * ensure callbacks into the driver to delete global
2735 * key cache entries can be handled
2736 * o reclaim the tx queue data structures after calling
2737 * the 802.11 layer as we'll get called back to reclaim
2738 * node state and potentially want to use them
2739 * o to cleanup the tx queues the hal is called, so detach
2741 * XXX: ??? detach ath5k_hw ???
2742 * Other than that, it's straightforward...
2744 ieee80211_unregister_hw(hw
);
2745 ath5k_desc_free(sc
, pdev
);
2746 ath5k_txq_release(sc
);
2747 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
2748 ath5k_unregister_leds(sc
);
2750 ath5k_sysfs_unregister(sc
);
2752 * NB: can't reclaim these until after ieee80211_ifdetach
2753 * returns because we'll get called back to reclaim node
2754 * state and potentially want to use them.
2758 /********************\
2759 * Mac80211 functions *
2760 \********************/
2763 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2765 struct ath5k_softc
*sc
= hw
->priv
;
2766 u16 qnum
= skb_get_queue_mapping(skb
);
2768 if (WARN_ON(qnum
>= sc
->ah
->ah_capabilities
.cap_queues
.q_tx_num
)) {
2769 dev_kfree_skb_any(skb
);
2773 return ath5k_tx_queue(hw
, skb
, &sc
->txqs
[qnum
]);
2776 static int ath5k_start(struct ieee80211_hw
*hw
)
2778 return ath5k_init(hw
->priv
);
2781 static void ath5k_stop(struct ieee80211_hw
*hw
)
2783 ath5k_stop_hw(hw
->priv
);
2786 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2787 struct ieee80211_vif
*vif
)
2789 struct ath5k_softc
*sc
= hw
->priv
;
2791 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
2793 mutex_lock(&sc
->lock
);
2795 if ((vif
->type
== NL80211_IFTYPE_AP
||
2796 vif
->type
== NL80211_IFTYPE_ADHOC
)
2797 && (sc
->num_ap_vifs
+ sc
->num_adhoc_vifs
) >= ATH_BCBUF
) {
2802 /* Don't allow other interfaces if one ad-hoc is configured.
2803 * TODO: Fix the problems with ad-hoc and multiple other interfaces.
2804 * We would need to operate the HW in ad-hoc mode to allow TSF updates
2805 * for the IBSS, but this breaks with additional AP or STA interfaces
2807 if (sc
->num_adhoc_vifs
||
2808 (sc
->nvifs
&& vif
->type
== NL80211_IFTYPE_ADHOC
)) {
2809 ATH5K_ERR(sc
, "Only one single ad-hoc interface is allowed.\n");
2814 switch (vif
->type
) {
2815 case NL80211_IFTYPE_AP
:
2816 case NL80211_IFTYPE_STATION
:
2817 case NL80211_IFTYPE_ADHOC
:
2818 case NL80211_IFTYPE_MESH_POINT
:
2819 avf
->opmode
= vif
->type
;
2827 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "add interface mode %d\n", avf
->opmode
);
2829 /* Assign the vap/adhoc to a beacon xmit slot. */
2830 if ((avf
->opmode
== NL80211_IFTYPE_AP
) ||
2831 (avf
->opmode
== NL80211_IFTYPE_ADHOC
)) {
2834 WARN_ON(list_empty(&sc
->bcbuf
));
2835 avf
->bbuf
= list_first_entry(&sc
->bcbuf
, struct ath5k_buf
,
2837 list_del(&avf
->bbuf
->list
);
2840 for (slot
= 0; slot
< ATH_BCBUF
; slot
++) {
2841 if (!sc
->bslot
[slot
]) {
2846 BUG_ON(sc
->bslot
[avf
->bslot
] != NULL
);
2847 sc
->bslot
[avf
->bslot
] = vif
;
2848 if (avf
->opmode
== NL80211_IFTYPE_AP
)
2851 sc
->num_adhoc_vifs
++;
2854 /* Any MAC address is fine, all others are included through the
2857 memcpy(&sc
->lladdr
, vif
->addr
, ETH_ALEN
);
2858 ath5k_hw_set_lladdr(sc
->ah
, vif
->addr
);
2860 memcpy(&avf
->lladdr
, vif
->addr
, ETH_ALEN
);
2862 ath5k_mode_setup(sc
, vif
);
2866 mutex_unlock(&sc
->lock
);
2871 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2872 struct ieee80211_vif
*vif
)
2874 struct ath5k_softc
*sc
= hw
->priv
;
2875 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
2878 mutex_lock(&sc
->lock
);
2882 ath5k_txbuf_free_skb(sc
, avf
->bbuf
);
2883 list_add_tail(&avf
->bbuf
->list
, &sc
->bcbuf
);
2884 for (i
= 0; i
< ATH_BCBUF
; i
++) {
2885 if (sc
->bslot
[i
] == vif
) {
2886 sc
->bslot
[i
] = NULL
;
2892 if (avf
->opmode
== NL80211_IFTYPE_AP
)
2894 else if (avf
->opmode
== NL80211_IFTYPE_ADHOC
)
2895 sc
->num_adhoc_vifs
--;
2897 ath5k_update_bssid_mask_and_opmode(sc
, NULL
);
2898 mutex_unlock(&sc
->lock
);
2902 * TODO: Phy disable/diversity etc
2905 ath5k_config(struct ieee80211_hw
*hw
, u32 changed
)
2907 struct ath5k_softc
*sc
= hw
->priv
;
2908 struct ath5k_hw
*ah
= sc
->ah
;
2909 struct ieee80211_conf
*conf
= &hw
->conf
;
2912 mutex_lock(&sc
->lock
);
2914 if (changed
& IEEE80211_CONF_CHANGE_CHANNEL
) {
2915 ret
= ath5k_chan_set(sc
, conf
->channel
);
2920 if ((changed
& IEEE80211_CONF_CHANGE_POWER
) &&
2921 (sc
->power_level
!= conf
->power_level
)) {
2922 sc
->power_level
= conf
->power_level
;
2925 ath5k_hw_set_txpower_limit(ah
, (conf
->power_level
* 2));
2929 * 1) Move this on config_interface and handle each case
2930 * separately eg. when we have only one STA vif, use
2931 * AR5K_ANTMODE_SINGLE_AP
2933 * 2) Allow the user to change antenna mode eg. when only
2934 * one antenna is present
2936 * 3) Allow the user to set default/tx antenna when possible
2938 * 4) Default mode should handle 90% of the cases, together
2939 * with fixed a/b and single AP modes we should be able to
2940 * handle 99%. Sectored modes are extreme cases and i still
2941 * haven't found a usage for them. If we decide to support them,
2942 * then we must allow the user to set how many tx antennas we
2945 ath5k_hw_set_antenna_mode(ah
, ah
->ah_ant_mode
);
2948 mutex_unlock(&sc
->lock
);
2952 static u64
ath5k_prepare_multicast(struct ieee80211_hw
*hw
,
2953 struct netdev_hw_addr_list
*mc_list
)
2957 struct netdev_hw_addr
*ha
;
2962 netdev_hw_addr_list_for_each(ha
, mc_list
) {
2963 /* calculate XOR of eight 6-bit values */
2964 val
= get_unaligned_le32(ha
->addr
+ 0);
2965 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2966 val
= get_unaligned_le32(ha
->addr
+ 3);
2967 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2969 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2970 /* XXX: we might be able to just do this instead,
2971 * but not sure, needs testing, if we do use this we'd
2972 * neet to inform below to not reset the mcast */
2973 /* ath5k_hw_set_mcast_filterindex(ah,
2977 return ((u64
)(mfilt
[1]) << 32) | mfilt
[0];
2980 static bool ath_any_vif_assoc(struct ath5k_softc
*sc
)
2982 struct ath_vif_iter_data iter_data
;
2983 iter_data
.hw_macaddr
= NULL
;
2984 iter_data
.any_assoc
= false;
2985 iter_data
.need_set_hw_addr
= false;
2986 iter_data
.found_active
= true;
2988 ieee80211_iterate_active_interfaces_atomic(sc
->hw
, ath_vif_iter
,
2990 return iter_data
.any_assoc
;
2993 #define SUPPORTED_FIF_FLAGS \
2994 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2995 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2996 FIF_BCN_PRBRESP_PROMISC
2998 * o always accept unicast, broadcast, and multicast traffic
2999 * o multicast traffic for all BSSIDs will be enabled if mac80211
3001 * o maintain current state of phy ofdm or phy cck error reception.
3002 * If the hardware detects any of these type of errors then
3003 * ath5k_hw_get_rx_filter() will pass to us the respective
3004 * hardware filters to be able to receive these type of frames.
3005 * o probe request frames are accepted only when operating in
3006 * hostap, adhoc, or monitor modes
3007 * o enable promiscuous mode according to the interface state
3009 * - when operating in adhoc mode so the 802.11 layer creates
3010 * node table entries for peers,
3011 * - when operating in station mode for collecting rssi data when
3012 * the station is otherwise quiet, or
3015 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
3016 unsigned int changed_flags
,
3017 unsigned int *new_flags
,
3020 struct ath5k_softc
*sc
= hw
->priv
;
3021 struct ath5k_hw
*ah
= sc
->ah
;
3022 u32 mfilt
[2], rfilt
;
3024 mutex_lock(&sc
->lock
);
3026 mfilt
[0] = multicast
;
3027 mfilt
[1] = multicast
>> 32;
3029 /* Only deal with supported flags */
3030 changed_flags
&= SUPPORTED_FIF_FLAGS
;
3031 *new_flags
&= SUPPORTED_FIF_FLAGS
;
3033 /* If HW detects any phy or radar errors, leave those filters on.
3034 * Also, always enable Unicast, Broadcasts and Multicast
3035 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3036 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
3037 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
3038 AR5K_RX_FILTER_MCAST
);
3040 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
3041 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
3042 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
3044 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
3048 if (test_bit(ATH_STAT_PROMISC
, sc
->status
))
3049 rfilt
|= AR5K_RX_FILTER_PROM
;
3051 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3052 if (*new_flags
& FIF_ALLMULTI
) {
3057 /* This is the best we can do */
3058 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
3059 rfilt
|= AR5K_RX_FILTER_PHYERR
;
3061 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3062 * and probes for any BSSID */
3063 if ((*new_flags
& FIF_BCN_PRBRESP_PROMISC
) || (sc
->nvifs
> 1))
3064 rfilt
|= AR5K_RX_FILTER_BEACON
;
3066 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3067 * set we should only pass on control frames for this
3068 * station. This needs testing. I believe right now this
3069 * enables *all* control frames, which is OK.. but
3070 * but we should see if we can improve on granularity */
3071 if (*new_flags
& FIF_CONTROL
)
3072 rfilt
|= AR5K_RX_FILTER_CONTROL
;
3074 /* Additional settings per mode -- this is per ath5k */
3076 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3078 switch (sc
->opmode
) {
3079 case NL80211_IFTYPE_MESH_POINT
:
3080 rfilt
|= AR5K_RX_FILTER_CONTROL
|
3081 AR5K_RX_FILTER_BEACON
|
3082 AR5K_RX_FILTER_PROBEREQ
|
3083 AR5K_RX_FILTER_PROM
;
3085 case NL80211_IFTYPE_AP
:
3086 case NL80211_IFTYPE_ADHOC
:
3087 rfilt
|= AR5K_RX_FILTER_PROBEREQ
|
3088 AR5K_RX_FILTER_BEACON
;
3090 case NL80211_IFTYPE_STATION
:
3092 rfilt
|= AR5K_RX_FILTER_BEACON
;
3098 ath5k_hw_set_rx_filter(ah
, rfilt
);
3100 /* Set multicast bits */
3101 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
3102 /* Set the cached hw filter flags, this will later actually
3104 sc
->filter_flags
= rfilt
;
3106 mutex_unlock(&sc
->lock
);
3110 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
3111 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
3112 struct ieee80211_key_conf
*key
)
3114 struct ath5k_softc
*sc
= hw
->priv
;
3115 struct ath5k_hw
*ah
= sc
->ah
;
3116 struct ath_common
*common
= ath5k_hw_common(ah
);
3119 if (modparam_nohwcrypt
)
3122 switch (key
->cipher
) {
3123 case WLAN_CIPHER_SUITE_WEP40
:
3124 case WLAN_CIPHER_SUITE_WEP104
:
3125 case WLAN_CIPHER_SUITE_TKIP
:
3127 case WLAN_CIPHER_SUITE_CCMP
:
3128 if (common
->crypt_caps
& ATH_CRYPT_CAP_CIPHER_AESCCM
)
3136 mutex_lock(&sc
->lock
);
3140 ret
= ath_key_config(common
, vif
, sta
, key
);
3142 key
->hw_key_idx
= ret
;
3143 /* push IV and Michael MIC generation to stack */
3144 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
3145 if (key
->cipher
== WLAN_CIPHER_SUITE_TKIP
)
3146 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
3147 if (key
->cipher
== WLAN_CIPHER_SUITE_CCMP
)
3148 key
->flags
|= IEEE80211_KEY_FLAG_SW_MGMT
;
3153 ath_key_delete(common
, key
);
3160 mutex_unlock(&sc
->lock
);
3165 ath5k_get_stats(struct ieee80211_hw
*hw
,
3166 struct ieee80211_low_level_stats
*stats
)
3168 struct ath5k_softc
*sc
= hw
->priv
;
3171 ath5k_hw_update_mib_counters(sc
->ah
);
3173 stats
->dot11ACKFailureCount
= sc
->stats
.ack_fail
;
3174 stats
->dot11RTSFailureCount
= sc
->stats
.rts_fail
;
3175 stats
->dot11RTSSuccessCount
= sc
->stats
.rts_ok
;
3176 stats
->dot11FCSErrorCount
= sc
->stats
.fcs_error
;
3181 static int ath5k_get_survey(struct ieee80211_hw
*hw
, int idx
,
3182 struct survey_info
*survey
)
3184 struct ath5k_softc
*sc
= hw
->priv
;
3185 struct ieee80211_conf
*conf
= &hw
->conf
;
3186 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
3187 struct ath_cycle_counters
*cc
= &common
->cc_survey
;
3188 unsigned int div
= common
->clockrate
* 1000;
3193 survey
->channel
= conf
->channel
;
3194 survey
->filled
= SURVEY_INFO_NOISE_DBM
;
3195 survey
->noise
= sc
->ah
->ah_noise_floor
;
3197 spin_lock_bh(&common
->cc_lock
);
3198 ath_hw_cycle_counters_update(common
);
3199 if (cc
->cycles
> 0) {
3200 survey
->filled
|= SURVEY_INFO_CHANNEL_TIME
|
3201 SURVEY_INFO_CHANNEL_TIME_BUSY
|
3202 SURVEY_INFO_CHANNEL_TIME_RX
|
3203 SURVEY_INFO_CHANNEL_TIME_TX
;
3204 survey
->channel_time
+= cc
->cycles
/ div
;
3205 survey
->channel_time_busy
+= cc
->rx_busy
/ div
;
3206 survey
->channel_time_rx
+= cc
->rx_frame
/ div
;
3207 survey
->channel_time_tx
+= cc
->tx_frame
/ div
;
3209 memset(cc
, 0, sizeof(*cc
));
3210 spin_unlock_bh(&common
->cc_lock
);
3216 ath5k_get_tsf(struct ieee80211_hw
*hw
)
3218 struct ath5k_softc
*sc
= hw
->priv
;
3220 return ath5k_hw_get_tsf64(sc
->ah
);
3224 ath5k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
)
3226 struct ath5k_softc
*sc
= hw
->priv
;
3228 ath5k_hw_set_tsf64(sc
->ah
, tsf
);
3232 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3234 struct ath5k_softc
*sc
= hw
->priv
;
3237 * in IBSS mode we need to update the beacon timers too.
3238 * this will also reset the TSF if we call it with 0
3240 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
3241 ath5k_beacon_update_timers(sc
, 0);
3243 ath5k_hw_reset_tsf(sc
->ah
);
3247 set_beacon_filter(struct ieee80211_hw
*hw
, bool enable
)
3249 struct ath5k_softc
*sc
= hw
->priv
;
3250 struct ath5k_hw
*ah
= sc
->ah
;
3252 rfilt
= ath5k_hw_get_rx_filter(ah
);
3254 rfilt
|= AR5K_RX_FILTER_BEACON
;
3256 rfilt
&= ~AR5K_RX_FILTER_BEACON
;
3257 ath5k_hw_set_rx_filter(ah
, rfilt
);
3258 sc
->filter_flags
= rfilt
;
3261 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
3262 struct ieee80211_vif
*vif
,
3263 struct ieee80211_bss_conf
*bss_conf
,
3266 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
3267 struct ath5k_softc
*sc
= hw
->priv
;
3268 struct ath5k_hw
*ah
= sc
->ah
;
3269 struct ath_common
*common
= ath5k_hw_common(ah
);
3270 unsigned long flags
;
3272 mutex_lock(&sc
->lock
);
3274 if (changes
& BSS_CHANGED_BSSID
) {
3275 /* Cache for later use during resets */
3276 memcpy(common
->curbssid
, bss_conf
->bssid
, ETH_ALEN
);
3278 ath5k_hw_set_bssid(ah
);
3282 if (changes
& BSS_CHANGED_BEACON_INT
)
3283 sc
->bintval
= bss_conf
->beacon_int
;
3285 if (changes
& BSS_CHANGED_ASSOC
) {
3286 avf
->assoc
= bss_conf
->assoc
;
3287 if (bss_conf
->assoc
)
3288 sc
->assoc
= bss_conf
->assoc
;
3290 sc
->assoc
= ath_any_vif_assoc(sc
);
3292 if (sc
->opmode
== NL80211_IFTYPE_STATION
)
3293 set_beacon_filter(hw
, sc
->assoc
);
3294 ath5k_hw_set_ledstate(sc
->ah
, sc
->assoc
?
3295 AR5K_LED_ASSOC
: AR5K_LED_INIT
);
3296 if (bss_conf
->assoc
) {
3297 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
,
3298 "Bss Info ASSOC %d, bssid: %pM\n",
3299 bss_conf
->aid
, common
->curbssid
);
3300 common
->curaid
= bss_conf
->aid
;
3301 ath5k_hw_set_bssid(ah
);
3302 /* Once ANI is available you would start it here */
3306 if (changes
& BSS_CHANGED_BEACON
) {
3307 spin_lock_irqsave(&sc
->block
, flags
);
3308 ath5k_beacon_update(hw
, vif
);
3309 spin_unlock_irqrestore(&sc
->block
, flags
);
3312 if (changes
& BSS_CHANGED_BEACON_ENABLED
)
3313 sc
->enable_beacon
= bss_conf
->enable_beacon
;
3315 if (changes
& (BSS_CHANGED_BEACON
| BSS_CHANGED_BEACON_ENABLED
|
3316 BSS_CHANGED_BEACON_INT
))
3317 ath5k_beacon_config(sc
);
3319 mutex_unlock(&sc
->lock
);
3322 static void ath5k_sw_scan_start(struct ieee80211_hw
*hw
)
3324 struct ath5k_softc
*sc
= hw
->priv
;
3326 ath5k_hw_set_ledstate(sc
->ah
, AR5K_LED_SCAN
);
3329 static void ath5k_sw_scan_complete(struct ieee80211_hw
*hw
)
3331 struct ath5k_softc
*sc
= hw
->priv
;
3332 ath5k_hw_set_ledstate(sc
->ah
, sc
->assoc
?
3333 AR5K_LED_ASSOC
: AR5K_LED_INIT
);
3337 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3339 * @hw: struct ieee80211_hw pointer
3340 * @coverage_class: IEEE 802.11 coverage class number
3342 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3343 * coverage class. The values are persistent, they are restored after device
3346 static void ath5k_set_coverage_class(struct ieee80211_hw
*hw
, u8 coverage_class
)
3348 struct ath5k_softc
*sc
= hw
->priv
;
3350 mutex_lock(&sc
->lock
);
3351 ath5k_hw_set_coverage_class(sc
->ah
, coverage_class
);
3352 mutex_unlock(&sc
->lock
);
3355 static int ath5k_conf_tx(struct ieee80211_hw
*hw
, u16 queue
,
3356 const struct ieee80211_tx_queue_params
*params
)
3358 struct ath5k_softc
*sc
= hw
->priv
;
3359 struct ath5k_hw
*ah
= sc
->ah
;
3360 struct ath5k_txq_info qi
;
3363 if (queue
>= ah
->ah_capabilities
.cap_queues
.q_tx_num
)
3366 mutex_lock(&sc
->lock
);
3368 ath5k_hw_get_tx_queueprops(ah
, queue
, &qi
);
3370 qi
.tqi_aifs
= params
->aifs
;
3371 qi
.tqi_cw_min
= params
->cw_min
;
3372 qi
.tqi_cw_max
= params
->cw_max
;
3373 qi
.tqi_burst_time
= params
->txop
;
3375 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
,
3376 "Configure tx [queue %d], "
3377 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
3378 queue
, params
->aifs
, params
->cw_min
,
3379 params
->cw_max
, params
->txop
);
3381 if (ath5k_hw_set_tx_queueprops(ah
, queue
, &qi
)) {
3383 "Unable to update hardware queue %u!\n", queue
);
3386 ath5k_hw_reset_tx_queue(ah
, queue
);
3388 mutex_unlock(&sc
->lock
);
3393 static int ath5k_set_antenna(struct ieee80211_hw
*hw
, u32 tx_ant
, u32 rx_ant
)
3395 struct ath5k_softc
*sc
= hw
->priv
;
3397 if (tx_ant
== 1 && rx_ant
== 1)
3398 ath5k_hw_set_antenna_mode(sc
->ah
, AR5K_ANTMODE_FIXED_A
);
3399 else if (tx_ant
== 2 && rx_ant
== 2)
3400 ath5k_hw_set_antenna_mode(sc
->ah
, AR5K_ANTMODE_FIXED_B
);
3401 else if ((tx_ant
& 3) == 3 && (rx_ant
& 3) == 3)
3402 ath5k_hw_set_antenna_mode(sc
->ah
, AR5K_ANTMODE_DEFAULT
);
3408 static int ath5k_get_antenna(struct ieee80211_hw
*hw
, u32
*tx_ant
, u32
*rx_ant
)
3410 struct ath5k_softc
*sc
= hw
->priv
;
3412 switch (sc
->ah
->ah_ant_mode
) {
3413 case AR5K_ANTMODE_FIXED_A
:
3414 *tx_ant
= 1; *rx_ant
= 1; break;
3415 case AR5K_ANTMODE_FIXED_B
:
3416 *tx_ant
= 2; *rx_ant
= 2; break;
3417 case AR5K_ANTMODE_DEFAULT
:
3418 *tx_ant
= 3; *rx_ant
= 3; break;
3423 static const struct ieee80211_ops ath5k_hw_ops
= {
3425 .start
= ath5k_start
,
3427 .add_interface
= ath5k_add_interface
,
3428 .remove_interface
= ath5k_remove_interface
,
3429 .config
= ath5k_config
,
3430 .prepare_multicast
= ath5k_prepare_multicast
,
3431 .configure_filter
= ath5k_configure_filter
,
3432 .set_key
= ath5k_set_key
,
3433 .get_stats
= ath5k_get_stats
,
3434 .get_survey
= ath5k_get_survey
,
3435 .conf_tx
= ath5k_conf_tx
,
3436 .get_tsf
= ath5k_get_tsf
,
3437 .set_tsf
= ath5k_set_tsf
,
3438 .reset_tsf
= ath5k_reset_tsf
,
3439 .bss_info_changed
= ath5k_bss_info_changed
,
3440 .sw_scan_start
= ath5k_sw_scan_start
,
3441 .sw_scan_complete
= ath5k_sw_scan_complete
,
3442 .set_coverage_class
= ath5k_set_coverage_class
,
3443 .set_antenna
= ath5k_set_antenna
,
3444 .get_antenna
= ath5k_get_antenna
,
3447 /********************\
3448 * PCI Initialization *
3449 \********************/
3451 static int __devinit
3452 ath5k_pci_probe(struct pci_dev
*pdev
,
3453 const struct pci_device_id
*id
)
3456 struct ath5k_softc
*sc
;
3457 struct ath_common
*common
;
3458 struct ieee80211_hw
*hw
;
3463 * L0s needs to be disabled on all ath5k cards.
3465 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
3466 * by default in the future in 2.6.36) this will also mean both L1 and
3467 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
3468 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
3469 * though but cannot currently undue the effect of a blacklist, for
3470 * details you can read pcie_aspm_sanity_check() and see how it adjusts
3471 * the device link capability.
3473 * It may be possible in the future to implement some PCI API to allow
3474 * drivers to override blacklists for pre 1.1 PCIe but for now it is
3475 * best to accept that both L0s and L1 will be disabled completely for
3476 * distributions shipping with CONFIG_PCIEASPM rather than having this
3477 * issue present. Motivation for adding this new API will be to help
3478 * with power consumption for some of these devices.
3480 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
);
3482 ret
= pci_enable_device(pdev
);
3484 dev_err(&pdev
->dev
, "can't enable device\n");
3488 /* XXX 32-bit addressing only */
3489 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3491 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
3496 * Cache line size is used to size and align various
3497 * structures used to communicate with the hardware.
3499 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
3502 * Linux 2.4.18 (at least) writes the cache line size
3503 * register as a 16-bit wide register which is wrong.
3504 * We must have this setup properly for rx buffer
3505 * DMA to work so force a reasonable value here if it
3508 csz
= L1_CACHE_BYTES
>> 2;
3509 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
3512 * The default setting of latency timer yields poor results,
3513 * set it to the value used by other systems. It may be worth
3514 * tweaking this setting more.
3516 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
3518 /* Enable bus mastering */
3519 pci_set_master(pdev
);
3522 * Disable the RETRY_TIMEOUT register (0x41) to keep
3523 * PCI Tx retries from interfering with C3 CPU state.
3525 pci_write_config_byte(pdev
, 0x41, 0);
3527 ret
= pci_request_region(pdev
, 0, "ath5k");
3529 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
3533 mem
= pci_iomap(pdev
, 0, 0);
3535 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
3541 * Allocate hw (mac80211 main struct)
3542 * and hw->priv (driver private data)
3544 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
3546 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
3551 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
3553 /* Initialize driver private data */
3554 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
3555 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
3556 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
3557 IEEE80211_HW_SIGNAL_DBM
;
3559 hw
->wiphy
->interface_modes
=
3560 BIT(NL80211_IFTYPE_AP
) |
3561 BIT(NL80211_IFTYPE_STATION
) |
3562 BIT(NL80211_IFTYPE_ADHOC
) |
3563 BIT(NL80211_IFTYPE_MESH_POINT
);
3565 hw
->extra_tx_headroom
= 2;
3566 hw
->channel_change_time
= 5000;
3572 * Mark the device as detached to avoid processing
3573 * interrupts until setup is complete.
3575 __set_bit(ATH_STAT_INVALID
, sc
->status
);
3577 sc
->iobase
= mem
; /* So we can unmap it on detach */
3578 sc
->opmode
= NL80211_IFTYPE_STATION
;
3580 mutex_init(&sc
->lock
);
3581 spin_lock_init(&sc
->rxbuflock
);
3582 spin_lock_init(&sc
->txbuflock
);
3583 spin_lock_init(&sc
->block
);
3585 /* Set private data */
3586 pci_set_drvdata(pdev
, sc
);
3588 /* Setup interrupt handler */
3589 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
3591 ATH5K_ERR(sc
, "request_irq failed\n");
3595 /* If we passed the test, malloc an ath5k_hw struct */
3596 sc
->ah
= kzalloc(sizeof(struct ath5k_hw
), GFP_KERNEL
);
3599 ATH5K_ERR(sc
, "out of memory\n");
3604 sc
->ah
->ah_iobase
= sc
->iobase
;
3605 common
= ath5k_hw_common(sc
->ah
);
3606 common
->ops
= &ath5k_common_ops
;
3607 common
->ah
= sc
->ah
;
3609 common
->cachelsz
= csz
<< 2; /* convert to bytes */
3610 spin_lock_init(&common
->cc_lock
);
3612 /* Initialize device */
3613 ret
= ath5k_hw_attach(sc
);
3618 /* set up multi-rate retry capabilities */
3619 if (sc
->ah
->ah_version
== AR5K_AR5212
) {
3621 hw
->max_rate_tries
= 11;
3624 hw
->vif_data_size
= sizeof(struct ath5k_vif
);
3626 /* Finish private driver data initialization */
3627 ret
= ath5k_attach(pdev
, hw
);
3631 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
3632 ath5k_chip_name(AR5K_VERSION_MAC
, sc
->ah
->ah_mac_srev
),
3633 sc
->ah
->ah_mac_srev
,
3634 sc
->ah
->ah_phy_revision
);
3636 if (!sc
->ah
->ah_single_chip
) {
3637 /* Single chip radio (!RF5111) */
3638 if (sc
->ah
->ah_radio_5ghz_revision
&&
3639 !sc
->ah
->ah_radio_2ghz_revision
) {
3640 /* No 5GHz support -> report 2GHz radio */
3641 if (!test_bit(AR5K_MODE_11A
,
3642 sc
->ah
->ah_capabilities
.cap_mode
)) {
3643 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
3644 ath5k_chip_name(AR5K_VERSION_RAD
,
3645 sc
->ah
->ah_radio_5ghz_revision
),
3646 sc
->ah
->ah_radio_5ghz_revision
);
3647 /* No 2GHz support (5110 and some
3648 * 5Ghz only cards) -> report 5Ghz radio */
3649 } else if (!test_bit(AR5K_MODE_11B
,
3650 sc
->ah
->ah_capabilities
.cap_mode
)) {
3651 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
3652 ath5k_chip_name(AR5K_VERSION_RAD
,
3653 sc
->ah
->ah_radio_5ghz_revision
),
3654 sc
->ah
->ah_radio_5ghz_revision
);
3655 /* Multiband radio */
3657 ATH5K_INFO(sc
, "RF%s multiband radio found"
3659 ath5k_chip_name(AR5K_VERSION_RAD
,
3660 sc
->ah
->ah_radio_5ghz_revision
),
3661 sc
->ah
->ah_radio_5ghz_revision
);
3664 /* Multi chip radio (RF5111 - RF2111) ->
3665 * report both 2GHz/5GHz radios */
3666 else if (sc
->ah
->ah_radio_5ghz_revision
&&
3667 sc
->ah
->ah_radio_2ghz_revision
){
3668 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
3669 ath5k_chip_name(AR5K_VERSION_RAD
,
3670 sc
->ah
->ah_radio_5ghz_revision
),
3671 sc
->ah
->ah_radio_5ghz_revision
);
3672 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
3673 ath5k_chip_name(AR5K_VERSION_RAD
,
3674 sc
->ah
->ah_radio_2ghz_revision
),
3675 sc
->ah
->ah_radio_2ghz_revision
);
3679 ath5k_debug_init_device(sc
);
3681 /* ready to process interrupts */
3682 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
3686 ath5k_hw_detach(sc
->ah
);
3690 free_irq(pdev
->irq
, sc
);
3692 ieee80211_free_hw(hw
);
3694 pci_iounmap(pdev
, mem
);
3696 pci_release_region(pdev
, 0);
3698 pci_disable_device(pdev
);
3703 static void __devexit
3704 ath5k_pci_remove(struct pci_dev
*pdev
)
3706 struct ath5k_softc
*sc
= pci_get_drvdata(pdev
);
3708 ath5k_debug_finish_device(sc
);
3709 ath5k_detach(pdev
, sc
->hw
);
3710 ath5k_hw_detach(sc
->ah
);
3712 free_irq(pdev
->irq
, sc
);
3713 pci_iounmap(pdev
, sc
->iobase
);
3714 pci_release_region(pdev
, 0);
3715 pci_disable_device(pdev
);
3716 ieee80211_free_hw(sc
->hw
);
3719 #ifdef CONFIG_PM_SLEEP
3720 static int ath5k_pci_suspend(struct device
*dev
)
3722 struct ath5k_softc
*sc
= pci_get_drvdata(to_pci_dev(dev
));
3728 static int ath5k_pci_resume(struct device
*dev
)
3730 struct pci_dev
*pdev
= to_pci_dev(dev
);
3731 struct ath5k_softc
*sc
= pci_get_drvdata(pdev
);
3734 * Suspend/Resume resets the PCI configuration space, so we have to
3735 * re-disable the RETRY_TIMEOUT register (0x41) to keep
3736 * PCI Tx retries from interfering with C3 CPU state
3738 pci_write_config_byte(pdev
, 0x41, 0);
3740 ath5k_led_enable(sc
);
3744 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops
, ath5k_pci_suspend
, ath5k_pci_resume
);
3745 #define ATH5K_PM_OPS (&ath5k_pm_ops)
3747 #define ATH5K_PM_OPS NULL
3748 #endif /* CONFIG_PM_SLEEP */
3750 static struct pci_driver ath5k_pci_driver
= {
3751 .name
= KBUILD_MODNAME
,
3752 .id_table
= ath5k_pci_id_table
,
3753 .probe
= ath5k_pci_probe
,
3754 .remove
= __devexit_p(ath5k_pci_remove
),
3755 .driver
.pm
= ATH5K_PM_OPS
,
3759 * Module init/exit functions
3762 init_ath5k_pci(void)
3766 ret
= pci_register_driver(&ath5k_pci_driver
);
3768 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
3776 exit_ath5k_pci(void)
3778 pci_unregister_driver(&ath5k_pci_driver
);
3781 module_init(init_ath5k_pci
);
3782 module_exit(exit_ath5k_pci
);