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MMC: MMCI: allow GPIOs to be passed
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-versatile / core.c
blobafc0f87f3fa41c43fba36616dfec78aaa3f9bcbd
1 /*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29 #include <linux/amba/pl061.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/cnt32_to_63.h>
33 #include <linux/io.h>
34
35 #include <asm/clkdev.h>
36 #include <asm/system.h>
37 #include <mach/hardware.h>
38 #include <asm/irq.h>
39 #include <asm/leds.h>
40 #include <asm/hardware/arm_timer.h>
41 #include <asm/hardware/icst307.h>
42 #include <asm/hardware/vic.h>
43 #include <asm/mach-types.h>
44
45 #include <asm/mach/arch.h>
46 #include <asm/mach/flash.h>
47 #include <asm/mach/irq.h>
48 #include <asm/mach/time.h>
49 #include <asm/mach/map.h>
50 #include <asm/mach/mmc.h>
51
52 #include "core.h"
53 #include "clock.h"
54
55 /*
56 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
57 * is the (PA >> 12).
58 *
59 * Setup a VA for the Versatile Vectored Interrupt Controller.
60 */
61 #define __io_address(n) __io(IO_ADDRESS(n))
62 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
63 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
64
65 static void sic_mask_irq(unsigned int irq)
66 {
67 irq -= IRQ_SIC_START;
68 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
69 }
70
71 static void sic_unmask_irq(unsigned int irq)
72 {
73 irq -= IRQ_SIC_START;
74 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
75 }
76
77 static struct irq_chip sic_chip = {
78 .name = "SIC",
79 .ack = sic_mask_irq,
80 .mask = sic_mask_irq,
81 .unmask = sic_unmask_irq,
82 };
83
84 static void
85 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
86 {
87 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
88
89 if (status == 0) {
90 do_bad_IRQ(irq, desc);
91 return;
92 }
93
94 do {
95 irq = ffs(status) - 1;
96 status &= ~(1 << irq);
97
98 irq += IRQ_SIC_START;
99
100 generic_handle_irq(irq);
101 } while (status);
102 }
103
104 #if 1
105 #define IRQ_MMCI0A IRQ_VICSOURCE22
106 #define IRQ_AACI IRQ_VICSOURCE24
107 #define IRQ_ETH IRQ_VICSOURCE25
108 #define PIC_MASK 0xFFD00000
109 #else
110 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
111 #define IRQ_AACI IRQ_SIC_AACI
112 #define IRQ_ETH IRQ_SIC_ETH
113 #define PIC_MASK 0
114 #endif
115
116 void __init versatile_init_irq(void)
117 {
118 unsigned int i;
119
120 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
121
122 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
123
124 /* Do second interrupt controller */
125 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
126
127 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
128 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
129 set_irq_chip(i, &sic_chip);
130 set_irq_handler(i, handle_level_irq);
131 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
132 }
133 }
134
135 /*
136 * Interrupts on secondary controller from 0 to 8 are routed to
137 * source 31 on PIC.
138 * Interrupts from 21 to 31 are routed directly to the VIC on
139 * the corresponding number on primary controller. This is controlled
140 * by setting PIC_ENABLEx.
141 */
142 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
143 }
144
145 static struct map_desc versatile_io_desc[] __initdata = {
146 {
147 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
148 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
149 .length = SZ_4K,
150 .type = MT_DEVICE
151 }, {
152 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
153 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
154 .length = SZ_4K,
155 .type = MT_DEVICE
156 }, {
157 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
158 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
159 .length = SZ_4K,
160 .type = MT_DEVICE
161 }, {
162 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
163 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
164 .length = SZ_4K * 9,
165 .type = MT_DEVICE
166 },
167 #ifdef CONFIG_MACH_VERSATILE_AB
168 {
169 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
170 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
171 .length = SZ_4K,
172 .type = MT_DEVICE
173 }, {
174 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
175 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
176 .length = SZ_64M,
177 .type = MT_DEVICE
178 },
179 #endif
180 #ifdef CONFIG_DEBUG_LL
181 {
182 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
183 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
184 .length = SZ_4K,
185 .type = MT_DEVICE
186 },
187 #endif
188 #ifdef CONFIG_PCI
189 {
190 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
191 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
192 .length = SZ_4K,
193 .type = MT_DEVICE
194 }, {
195 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
196 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
197 .length = VERSATILE_PCI_BASE_SIZE,
198 .type = MT_DEVICE
199 }, {
200 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
201 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
202 .length = VERSATILE_PCI_CFG_BASE_SIZE,
203 .type = MT_DEVICE
204 },
205 #if 0
206 {
207 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
208 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
209 .length = SZ_16M,
210 .type = MT_DEVICE
211 }, {
212 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
213 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
214 .length = SZ_16M,
215 .type = MT_DEVICE
216 }, {
217 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
218 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
219 .length = SZ_16M,
220 .type = MT_DEVICE
221 },
222 #endif
223 #endif
224 };
225
226 void __init versatile_map_io(void)
227 {
228 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
229 }
230
231 #define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
232
233 /*
234 * This is the Versatile sched_clock implementation. This has
235 * a resolution of 41.7ns, and a maximum value of about 35583 days.
236 *
237 * The return value is guaranteed to be monotonic in that range as
238 * long as there is always less than 89 seconds between successive
239 * calls to this function.
240 */
241 unsigned long long sched_clock(void)
242 {
243 unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
244
245 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
246 v *= 125<<1;
247 do_div(v, 3<<1);
248
249 return v;
250 }
251
252
253 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
254
255 static int versatile_flash_init(void)
256 {
257 u32 val;
258
259 val = __raw_readl(VERSATILE_FLASHCTRL);
260 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
261 __raw_writel(val, VERSATILE_FLASHCTRL);
262
263 return 0;
264 }
265
266 static void versatile_flash_exit(void)
267 {
268 u32 val;
269
270 val = __raw_readl(VERSATILE_FLASHCTRL);
271 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
272 __raw_writel(val, VERSATILE_FLASHCTRL);
273 }
274
275 static void versatile_flash_set_vpp(int on)
276 {
277 u32 val;
278
279 val = __raw_readl(VERSATILE_FLASHCTRL);
280 if (on)
281 val |= VERSATILE_FLASHPROG_FLVPPEN;
282 else
283 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
284 __raw_writel(val, VERSATILE_FLASHCTRL);
285 }
286
287 static struct flash_platform_data versatile_flash_data = {
288 .map_name = "cfi_probe",
289 .width = 4,
290 .init = versatile_flash_init,
291 .exit = versatile_flash_exit,
292 .set_vpp = versatile_flash_set_vpp,
293 };
294
295 static struct resource versatile_flash_resource = {
296 .start = VERSATILE_FLASH_BASE,
297 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
298 .flags = IORESOURCE_MEM,
299 };
300
301 static struct platform_device versatile_flash_device = {
302 .name = "armflash",
303 .id = 0,
304 .dev = {
305 .platform_data = &versatile_flash_data,
306 },
307 .num_resources = 1,
308 .resource = &versatile_flash_resource,
309 };
310
311 static struct resource smc91x_resources[] = {
312 [0] = {
313 .start = VERSATILE_ETH_BASE,
314 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
315 .flags = IORESOURCE_MEM,
316 },
317 [1] = {
318 .start = IRQ_ETH,
319 .end = IRQ_ETH,
320 .flags = IORESOURCE_IRQ,
321 },
322 };
323
324 static struct platform_device smc91x_device = {
325 .name = "smc91x",
326 .id = 0,
327 .num_resources = ARRAY_SIZE(smc91x_resources),
328 .resource = smc91x_resources,
329 };
330
331 static struct resource versatile_i2c_resource = {
332 .start = VERSATILE_I2C_BASE,
333 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
334 .flags = IORESOURCE_MEM,
335 };
336
337 static struct platform_device versatile_i2c_device = {
338 .name = "versatile-i2c",
339 .id = 0,
340 .num_resources = 1,
341 .resource = &versatile_i2c_resource,
342 };
343
344 static struct i2c_board_info versatile_i2c_board_info[] = {
345 {
346 I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1),
347 .type = "ds1338",
348 },
349 };
350
351 static int __init versatile_i2c_init(void)
352 {
353 return i2c_register_board_info(0, versatile_i2c_board_info,
354 ARRAY_SIZE(versatile_i2c_board_info));
355 }
356 arch_initcall(versatile_i2c_init);
357
358 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
359
360 unsigned int mmc_status(struct device *dev)
361 {
362 struct amba_device *adev = container_of(dev, struct amba_device, dev);
363 u32 mask;
364
365 if (adev->res.start == VERSATILE_MMCI0_BASE)
366 mask = 1;
367 else
368 mask = 2;
369
370 return readl(VERSATILE_SYSMCI) & mask;
371 }
372
373 static struct mmc_platform_data mmc0_plat_data = {
374 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
375 .status = mmc_status,
376 .gpio_wp = -1,
377 .gpio_cd = -1,
378 };
379
380 /*
381 * Clock handling
382 */
383 static const struct icst307_params versatile_oscvco_params = {
384 .ref = 24000,
385 .vco_max = 200000,
386 .vd_min = 4 + 8,
387 .vd_max = 511 + 8,
388 .rd_min = 1 + 2,
389 .rd_max = 127 + 2,
390 };
391
392 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
393 {
394 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
395 void __iomem *sys_lock = sys + VERSATILE_SYS_LOCK_OFFSET;
396 u32 val;
397
398 val = readl(sys + clk->oscoff) & ~0x7ffff;
399 val |= vco.v | (vco.r << 9) | (vco.s << 16);
400
401 writel(0xa05f, sys_lock);
402 writel(val, sys + clk->oscoff);
403 writel(0, sys_lock);
404 }
405
406 static struct clk osc4_clk = {
407 .params = &versatile_oscvco_params,
408 .oscoff = VERSATILE_SYS_OSCCLCD_OFFSET,
409 .setvco = versatile_oscvco_set,
410 };
411
412 /*
413 * These are fixed clocks.
414 */
415 static struct clk ref24_clk = {
416 .rate = 24000000,
417 };
418
419 static struct clk_lookup lookups[] = {
420 { /* UART0 */
421 .dev_id = "dev:f1",
422 .clk = &ref24_clk,
423 }, { /* UART1 */
424 .dev_id = "dev:f2",
425 .clk = &ref24_clk,
426 }, { /* UART2 */
427 .dev_id = "dev:f3",
428 .clk = &ref24_clk,
429 }, { /* UART3 */
430 .dev_id = "fpga:09",
431 .clk = &ref24_clk,
432 }, { /* KMI0 */
433 .dev_id = "fpga:06",
434 .clk = &ref24_clk,
435 }, { /* KMI1 */
436 .dev_id = "fpga:07",
437 .clk = &ref24_clk,
438 }, { /* MMC0 */
439 .dev_id = "fpga:05",
440 .clk = &ref24_clk,
441 }, { /* MMC1 */
442 .dev_id = "fpga:0b",
443 .clk = &ref24_clk,
444 }, { /* CLCD */
445 .dev_id = "dev:20",
446 .clk = &osc4_clk,
447 }
448 };
449
450 /*
451 * CLCD support.
452 */
453 #define SYS_CLCD_MODE_MASK (3 << 0)
454 #define SYS_CLCD_MODE_888 (0 << 0)
455 #define SYS_CLCD_MODE_5551 (1 << 0)
456 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
457 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
458 #define SYS_CLCD_NLCDIOON (1 << 2)
459 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
460 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
461 #define SYS_CLCD_ID_MASK (0x1f << 8)
462 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
463 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
464 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
465 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
466 #define SYS_CLCD_ID_VGA (0x1f << 8)
467
468 static struct clcd_panel vga = {
469 .mode = {
470 .name = "VGA",
471 .refresh = 60,
472 .xres = 640,
473 .yres = 480,
474 .pixclock = 39721,
475 .left_margin = 40,
476 .right_margin = 24,
477 .upper_margin = 32,
478 .lower_margin = 11,
479 .hsync_len = 96,
480 .vsync_len = 2,
481 .sync = 0,
482 .vmode = FB_VMODE_NONINTERLACED,
483 },
484 .width = -1,
485 .height = -1,
486 .tim2 = TIM2_BCD | TIM2_IPC,
487 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
488 .bpp = 16,
489 };
490
491 static struct clcd_panel sanyo_3_8_in = {
492 .mode = {
493 .name = "Sanyo QVGA",
494 .refresh = 116,
495 .xres = 320,
496 .yres = 240,
497 .pixclock = 100000,
498 .left_margin = 6,
499 .right_margin = 6,
500 .upper_margin = 5,
501 .lower_margin = 5,
502 .hsync_len = 6,
503 .vsync_len = 6,
504 .sync = 0,
505 .vmode = FB_VMODE_NONINTERLACED,
506 },
507 .width = -1,
508 .height = -1,
509 .tim2 = TIM2_BCD,
510 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
511 .bpp = 16,
512 };
513
514 static struct clcd_panel sanyo_2_5_in = {
515 .mode = {
516 .name = "Sanyo QVGA Portrait",
517 .refresh = 116,
518 .xres = 240,
519 .yres = 320,
520 .pixclock = 100000,
521 .left_margin = 20,
522 .right_margin = 10,
523 .upper_margin = 2,
524 .lower_margin = 2,
525 .hsync_len = 10,
526 .vsync_len = 2,
527 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
528 .vmode = FB_VMODE_NONINTERLACED,
529 },
530 .width = -1,
531 .height = -1,
532 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
533 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
534 .bpp = 16,
535 };
536
537 static struct clcd_panel epson_2_2_in = {
538 .mode = {
539 .name = "Epson QCIF",
540 .refresh = 390,
541 .xres = 176,
542 .yres = 220,
543 .pixclock = 62500,
544 .left_margin = 3,
545 .right_margin = 2,
546 .upper_margin = 1,
547 .lower_margin = 0,
548 .hsync_len = 3,
549 .vsync_len = 2,
550 .sync = 0,
551 .vmode = FB_VMODE_NONINTERLACED,
552 },
553 .width = -1,
554 .height = -1,
555 .tim2 = TIM2_BCD | TIM2_IPC,
556 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
557 .bpp = 16,
558 };
559
560 /*
561 * Detect which LCD panel is connected, and return the appropriate
562 * clcd_panel structure. Note: we do not have any information on
563 * the required timings for the 8.4in panel, so we presently assume
564 * VGA timings.
565 */
566 static struct clcd_panel *versatile_clcd_panel(void)
567 {
568 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
569 struct clcd_panel *panel = &vga;
570 u32 val;
571
572 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
573 if (val == SYS_CLCD_ID_SANYO_3_8)
574 panel = &sanyo_3_8_in;
575 else if (val == SYS_CLCD_ID_SANYO_2_5)
576 panel = &sanyo_2_5_in;
577 else if (val == SYS_CLCD_ID_EPSON_2_2)
578 panel = &epson_2_2_in;
579 else if (val == SYS_CLCD_ID_VGA)
580 panel = &vga;
581 else {
582 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
583 val);
584 panel = &vga;
585 }
586
587 return panel;
588 }
589
590 /*
591 * Disable all display connectors on the interface module.
592 */
593 static void versatile_clcd_disable(struct clcd_fb *fb)
594 {
595 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
596 u32 val;
597
598 val = readl(sys_clcd);
599 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
600 writel(val, sys_clcd);
601
602 #ifdef CONFIG_MACH_VERSATILE_AB
603 /*
604 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
605 */
606 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
607 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
608 unsigned long ctrl;
609
610 ctrl = readl(versatile_ib2_ctrl);
611 ctrl &= ~0x01;
612 writel(ctrl, versatile_ib2_ctrl);
613 }
614 #endif
615 }
616
617 /*
618 * Enable the relevant connector on the interface module.
619 */
620 static void versatile_clcd_enable(struct clcd_fb *fb)
621 {
622 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
623 u32 val;
624
625 val = readl(sys_clcd);
626 val &= ~SYS_CLCD_MODE_MASK;
627
628 switch (fb->fb.var.green.length) {
629 case 5:
630 val |= SYS_CLCD_MODE_5551;
631 break;
632 case 6:
633 val |= SYS_CLCD_MODE_565_RLSB;
634 break;
635 case 8:
636 val |= SYS_CLCD_MODE_888;
637 break;
638 }
639
640 /*
641 * Set the MUX
642 */
643 writel(val, sys_clcd);
644
645 /*
646 * And now enable the PSUs
647 */
648 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
649 writel(val, sys_clcd);
650
651 #ifdef CONFIG_MACH_VERSATILE_AB
652 /*
653 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
654 */
655 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
656 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
657 unsigned long ctrl;
658
659 ctrl = readl(versatile_ib2_ctrl);
660 ctrl |= 0x01;
661 writel(ctrl, versatile_ib2_ctrl);
662 }
663 #endif
664 }
665
666 static unsigned long framesize = SZ_1M;
667
668 static int versatile_clcd_setup(struct clcd_fb *fb)
669 {
670 dma_addr_t dma;
671
672 fb->panel = versatile_clcd_panel();
673
674 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
675 &dma, GFP_KERNEL);
676 if (!fb->fb.screen_base) {
677 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
678 return -ENOMEM;
679 }
680
681 fb->fb.fix.smem_start = dma;
682 fb->fb.fix.smem_len = framesize;
683
684 return 0;
685 }
686
687 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
688 {
689 return dma_mmap_writecombine(&fb->dev->dev, vma,
690 fb->fb.screen_base,
691 fb->fb.fix.smem_start,
692 fb->fb.fix.smem_len);
693 }
694
695 static void versatile_clcd_remove(struct clcd_fb *fb)
696 {
697 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
698 fb->fb.screen_base, fb->fb.fix.smem_start);
699 }
700
701 static struct clcd_board clcd_plat_data = {
702 .name = "Versatile",
703 .check = clcdfb_check,
704 .decode = clcdfb_decode,
705 .disable = versatile_clcd_disable,
706 .enable = versatile_clcd_enable,
707 .setup = versatile_clcd_setup,
708 .mmap = versatile_clcd_mmap,
709 .remove = versatile_clcd_remove,
710 };
711
712 static struct pl061_platform_data gpio0_plat_data = {
713 .gpio_base = 0,
714 .irq_base = IRQ_GPIO0_START,
715 };
716
717 static struct pl061_platform_data gpio1_plat_data = {
718 .gpio_base = 8,
719 .irq_base = IRQ_GPIO1_START,
720 };
721
722 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
723 #define AACI_DMA { 0x80, 0x81 }
724 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
725 #define MMCI0_DMA { 0x84, 0 }
726 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
727 #define KMI0_DMA { 0, 0 }
728 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
729 #define KMI1_DMA { 0, 0 }
730
731 /*
732 * These devices are connected directly to the multi-layer AHB switch
733 */
734 #define SMC_IRQ { NO_IRQ, NO_IRQ }
735 #define SMC_DMA { 0, 0 }
736 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
737 #define MPMC_DMA { 0, 0 }
738 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
739 #define CLCD_DMA { 0, 0 }
740 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
741 #define DMAC_DMA { 0, 0 }
742
743 /*
744 * These devices are connected via the core APB bridge
745 */
746 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
747 #define SCTL_DMA { 0, 0 }
748 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
749 #define WATCHDOG_DMA { 0, 0 }
750 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
751 #define GPIO0_DMA { 0, 0 }
752 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
753 #define GPIO1_DMA { 0, 0 }
754 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
755 #define RTC_DMA { 0, 0 }
756
757 /*
758 * These devices are connected via the DMA APB bridge
759 */
760 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
761 #define SCI_DMA { 7, 6 }
762 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
763 #define UART0_DMA { 15, 14 }
764 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
765 #define UART1_DMA { 13, 12 }
766 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
767 #define UART2_DMA { 11, 10 }
768 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
769 #define SSP_DMA { 9, 8 }
770
771 /* FPGA Primecells */
772 AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
773 AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
774 AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
775 AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
776
777 /* DevChip Primecells */
778 AMBA_DEVICE(smc, "dev:00", SMC, NULL);
779 AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
780 AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
781 AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
782 AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
783 AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
784 AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
785 AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
786 AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
787 AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
788 AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
789 AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
790 AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
791 AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
792
793 static struct amba_device *amba_devs[] __initdata = {
794 &dmac_device,
795 &uart0_device,
796 &uart1_device,
797 &uart2_device,
798 &smc_device,
799 &mpmc_device,
800 &clcd_device,
801 &sctl_device,
802 &wdog_device,
803 &gpio0_device,
804 &gpio1_device,
805 &rtc_device,
806 &sci0_device,
807 &ssp0_device,
808 &aaci_device,
809 &mmc0_device,
810 &kmi0_device,
811 &kmi1_device,
812 };
813
814 #ifdef CONFIG_LEDS
815 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
816
817 static void versatile_leds_event(led_event_t ledevt)
818 {
819 unsigned long flags;
820 u32 val;
821
822 local_irq_save(flags);
823 val = readl(VA_LEDS_BASE);
824
825 switch (ledevt) {
826 case led_idle_start:
827 val = val & ~VERSATILE_SYS_LED0;
828 break;
829
830 case led_idle_end:
831 val = val | VERSATILE_SYS_LED0;
832 break;
833
834 case led_timer:
835 val = val ^ VERSATILE_SYS_LED1;
836 break;
837
838 case led_halted:
839 val = 0;
840 break;
841
842 default:
843 break;
844 }
845
846 writel(val, VA_LEDS_BASE);
847 local_irq_restore(flags);
848 }
849 #endif /* CONFIG_LEDS */
850
851 void __init versatile_init(void)
852 {
853 int i;
854
855 for (i = 0; i < ARRAY_SIZE(lookups); i++)
856 clkdev_add(&lookups[i]);
857
858 platform_device_register(&versatile_flash_device);
859 platform_device_register(&versatile_i2c_device);
860 platform_device_register(&smc91x_device);
861
862 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
863 struct amba_device *d = amba_devs[i];
864 amba_device_register(d, &iomem_resource);
865 }
866
867 #ifdef CONFIG_LEDS
868 leds_event = versatile_leds_event;
869 #endif
870 }
871
872 /*
873 * Where is the timer (VA)?
874 */
875 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
876 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
877 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
878 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
879 #define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
880
881 /*
882 * How long is the timer interval?
883 */
884 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
885 #if TIMER_INTERVAL >= 0x100000
886 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
887 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
888 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
889 #elif TIMER_INTERVAL >= 0x10000
890 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
891 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
892 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
893 #else
894 #define TIMER_RELOAD (TIMER_INTERVAL)
895 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
896 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
897 #endif
898
899 static void timer_set_mode(enum clock_event_mode mode,
900 struct clock_event_device *clk)
901 {
902 unsigned long ctrl;
903
904 switch(mode) {
905 case CLOCK_EVT_MODE_PERIODIC:
906 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
907
908 ctrl = TIMER_CTRL_PERIODIC;
909 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
910 break;
911 case CLOCK_EVT_MODE_ONESHOT:
912 /* period set, and timer enabled in 'next_event' hook */
913 ctrl = TIMER_CTRL_ONESHOT;
914 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
915 break;
916 case CLOCK_EVT_MODE_UNUSED:
917 case CLOCK_EVT_MODE_SHUTDOWN:
918 default:
919 ctrl = 0;
920 }
921
922 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
923 }
924
925 static int timer_set_next_event(unsigned long evt,
926 struct clock_event_device *unused)
927 {
928 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
929
930 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
931 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
932
933 return 0;
934 }
935
936 static struct clock_event_device timer0_clockevent = {
937 .name = "timer0",
938 .shift = 32,
939 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
940 .set_mode = timer_set_mode,
941 .set_next_event = timer_set_next_event,
942 };
943
944 /*
945 * IRQ handler for the timer
946 */
947 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
948 {
949 struct clock_event_device *evt = &timer0_clockevent;
950
951 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
952
953 evt->event_handler(evt);
954
955 return IRQ_HANDLED;
956 }
957
958 static struct irqaction versatile_timer_irq = {
959 .name = "Versatile Timer Tick",
960 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
961 .handler = versatile_timer_interrupt,
962 };
963
964 static cycle_t versatile_get_cycles(struct clocksource *cs)
965 {
966 return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
967 }
968
969 static struct clocksource clocksource_versatile = {
970 .name = "timer3",
971 .rating = 200,
972 .read = versatile_get_cycles,
973 .mask = CLOCKSOURCE_MASK(32),
974 .shift = 20,
975 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
976 };
977
978 static int __init versatile_clocksource_init(void)
979 {
980 /* setup timer3 as free-running clocksource */
981 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
982 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
983 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
984 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
985 TIMER3_VA_BASE + TIMER_CTRL);
986
987 clocksource_versatile.mult =
988 clocksource_khz2mult(1000, clocksource_versatile.shift);
989 clocksource_register(&clocksource_versatile);
990
991 return 0;
992 }
993
994 /*
995 * Set up timer interrupt, and return the current time in seconds.
996 */
997 static void __init versatile_timer_init(void)
998 {
999 u32 val;
1000
1001 /*
1002 * set clock frequency:
1003 * VERSATILE_REFCLK is 32KHz
1004 * VERSATILE_TIMCLK is 1MHz
1005 */
1006 val = readl(__io_address(VERSATILE_SCTL_BASE));
1007 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
1008 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
1009 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
1010 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
1011 __io_address(VERSATILE_SCTL_BASE));
1012
1013 /*
1014 * Initialise to a known state (all timers off)
1015 */
1016 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
1017 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
1018 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
1019 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
1020
1021 /*
1022 * Make irqs happen for the system timer
1023 */
1024 setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
1025
1026 versatile_clocksource_init();
1027
1028 timer0_clockevent.mult =
1029 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
1030 timer0_clockevent.max_delta_ns =
1031 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
1032 timer0_clockevent.min_delta_ns =
1033 clockevent_delta2ns(0xf, &timer0_clockevent);
1034
1035 timer0_clockevent.cpumask = cpumask_of(0);
1036 clockevents_register_device(&timer0_clockevent);
1037 }
1038
1039 struct sys_timer versatile_timer = {
1040 .init = versatile_timer_init,
1041 };
1042
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree