2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
43 static atomic_t pciehp_num_controllers
= ATOMIC_INIT(0);
61 } __attribute__ ((packed
));
63 /* offsets to the controller registers based on the above structure layout */
65 PCIECAPID
= offsetof(struct ctrl_reg
, cap_id
),
66 NXTCAPPTR
= offsetof(struct ctrl_reg
, nxt_ptr
),
67 CAPREG
= offsetof(struct ctrl_reg
, cap_reg
),
68 DEVCAP
= offsetof(struct ctrl_reg
, dev_cap
),
69 DEVCTRL
= offsetof(struct ctrl_reg
, dev_ctrl
),
70 DEVSTATUS
= offsetof(struct ctrl_reg
, dev_status
),
71 LNKCAP
= offsetof(struct ctrl_reg
, lnk_cap
),
72 LNKCTRL
= offsetof(struct ctrl_reg
, lnk_ctrl
),
73 LNKSTATUS
= offsetof(struct ctrl_reg
, lnk_status
),
74 SLOTCAP
= offsetof(struct ctrl_reg
, slot_cap
),
75 SLOTCTRL
= offsetof(struct ctrl_reg
, slot_ctrl
),
76 SLOTSTATUS
= offsetof(struct ctrl_reg
, slot_status
),
77 ROOTCTRL
= offsetof(struct ctrl_reg
, root_ctrl
),
78 ROOTSTATUS
= offsetof(struct ctrl_reg
, root_status
),
81 static inline int pciehp_readw(struct controller
*ctrl
, int reg
, u16
*value
)
83 struct pci_dev
*dev
= ctrl
->pci_dev
;
84 return pci_read_config_word(dev
, ctrl
->cap_base
+ reg
, value
);
87 static inline int pciehp_readl(struct controller
*ctrl
, int reg
, u32
*value
)
89 struct pci_dev
*dev
= ctrl
->pci_dev
;
90 return pci_read_config_dword(dev
, ctrl
->cap_base
+ reg
, value
);
93 static inline int pciehp_writew(struct controller
*ctrl
, int reg
, u16 value
)
95 struct pci_dev
*dev
= ctrl
->pci_dev
;
96 return pci_write_config_word(dev
, ctrl
->cap_base
+ reg
, value
);
99 static inline int pciehp_writel(struct controller
*ctrl
, int reg
, u32 value
)
101 struct pci_dev
*dev
= ctrl
->pci_dev
;
102 return pci_write_config_dword(dev
, ctrl
->cap_base
+ reg
, value
);
105 /* Field definitions in PCI Express Capabilities Register */
106 #define CAP_VER 0x000F
107 #define DEV_PORT_TYPE 0x00F0
108 #define SLOT_IMPL 0x0100
109 #define MSG_NUM 0x3E00
111 /* Device or Port Type */
112 #define NAT_ENDPT 0x00
113 #define LEG_ENDPT 0x01
114 #define ROOT_PORT 0x04
115 #define UP_STREAM 0x05
116 #define DN_STREAM 0x06
117 #define PCIE_PCI_BRDG 0x07
118 #define PCI_PCIE_BRDG 0x10
120 /* Field definitions in Device Capabilities Register */
121 #define DATTN_BUTTN_PRSN 0x1000
122 #define DATTN_LED_PRSN 0x2000
123 #define DPWR_LED_PRSN 0x4000
125 /* Field definitions in Link Capabilities Register */
126 #define MAX_LNK_SPEED 0x000F
127 #define MAX_LNK_WIDTH 0x03F0
129 /* Link Width Encoding */
138 /*Field definitions of Link Status Register */
139 #define LNK_SPEED 0x000F
140 #define NEG_LINK_WD 0x03F0
141 #define LNK_TRN_ERR 0x0400
142 #define LNK_TRN 0x0800
143 #define SLOT_CLK_CONF 0x1000
145 /* Field definitions in Slot Capabilities Register */
146 #define ATTN_BUTTN_PRSN 0x00000001
147 #define PWR_CTRL_PRSN 0x00000002
148 #define MRL_SENS_PRSN 0x00000004
149 #define ATTN_LED_PRSN 0x00000008
150 #define PWR_LED_PRSN 0x00000010
151 #define HP_SUPR_RM_SUP 0x00000020
152 #define HP_CAP 0x00000040
153 #define SLOT_PWR_VALUE 0x000003F8
154 #define SLOT_PWR_LIMIT 0x00000C00
155 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
157 /* Field definitions in Slot Control Register */
158 #define ATTN_BUTTN_ENABLE 0x0001
159 #define PWR_FAULT_DETECT_ENABLE 0x0002
160 #define MRL_DETECT_ENABLE 0x0004
161 #define PRSN_DETECT_ENABLE 0x0008
162 #define CMD_CMPL_INTR_ENABLE 0x0010
163 #define HP_INTR_ENABLE 0x0020
164 #define ATTN_LED_CTRL 0x00C0
165 #define PWR_LED_CTRL 0x0300
166 #define PWR_CTRL 0x0400
167 #define EMI_CTRL 0x0800
169 /* Attention indicator and Power indicator states */
171 #define LED_BLINK 0x10
174 /* Power Control Command */
176 #define POWER_OFF 0x0400
178 /* EMI Status defines */
179 #define EMI_DISENGAGED 0
180 #define EMI_ENGAGED 1
182 /* Field definitions in Slot Status Register */
183 #define ATTN_BUTTN_PRESSED 0x0001
184 #define PWR_FAULT_DETECTED 0x0002
185 #define MRL_SENS_CHANGED 0x0004
186 #define PRSN_DETECT_CHANGED 0x0008
187 #define CMD_COMPLETED 0x0010
188 #define MRL_STATE 0x0020
189 #define PRSN_STATE 0x0040
190 #define EMI_STATE 0x0080
191 #define EMI_STATUS_BIT 7
193 static irqreturn_t
pcie_isr(int irq
, void *dev_id
);
194 static void start_int_poll_timer(struct controller
*ctrl
, int sec
);
196 /* This is the interrupt polling timeout function. */
197 static void int_poll_timeout(unsigned long data
)
199 struct controller
*ctrl
= (struct controller
*)data
;
201 /* Poll for interrupt events. regs == NULL => polling */
204 init_timer(&ctrl
->poll_timer
);
205 if (!pciehp_poll_time
)
206 pciehp_poll_time
= 2; /* default polling interval is 2 sec */
208 start_int_poll_timer(ctrl
, pciehp_poll_time
);
211 /* This function starts the interrupt polling timer. */
212 static void start_int_poll_timer(struct controller
*ctrl
, int sec
)
214 /* Clamp to sane value */
215 if ((sec
<= 0) || (sec
> 60))
218 ctrl
->poll_timer
.function
= &int_poll_timeout
;
219 ctrl
->poll_timer
.data
= (unsigned long)ctrl
;
220 ctrl
->poll_timer
.expires
= jiffies
+ sec
* HZ
;
221 add_timer(&ctrl
->poll_timer
);
224 static inline int pciehp_request_irq(struct controller
*ctrl
)
226 int retval
, irq
= ctrl
->pcie
->irq
;
228 /* Install interrupt polling timer. Start with 10 sec delay */
229 if (pciehp_poll_mode
) {
230 init_timer(&ctrl
->poll_timer
);
231 start_int_poll_timer(ctrl
, 10);
235 /* Installs the interrupt handler */
236 retval
= request_irq(irq
, pcie_isr
, IRQF_SHARED
, MY_NAME
, ctrl
);
238 ctrl_err(ctrl
, "Cannot get irq %d for the hotplug controller\n",
243 static inline void pciehp_free_irq(struct controller
*ctrl
)
245 if (pciehp_poll_mode
)
246 del_timer_sync(&ctrl
->poll_timer
);
248 free_irq(ctrl
->pcie
->irq
, ctrl
);
251 static int pcie_poll_cmd(struct controller
*ctrl
)
256 if (!pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
)) {
257 if (slot_status
& CMD_COMPLETED
) {
258 pciehp_writew(ctrl
, SLOTSTATUS
, CMD_COMPLETED
);
262 while (timeout
> 0) {
265 if (!pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
)) {
266 if (slot_status
& CMD_COMPLETED
) {
267 pciehp_writew(ctrl
, SLOTSTATUS
, CMD_COMPLETED
);
272 return 0; /* timeout */
275 static void pcie_wait_cmd(struct controller
*ctrl
, int poll
)
277 unsigned int msecs
= pciehp_poll_mode
? 2500 : 1000;
278 unsigned long timeout
= msecs_to_jiffies(msecs
);
282 rc
= pcie_poll_cmd(ctrl
);
284 rc
= wait_event_timeout(ctrl
->queue
, !ctrl
->cmd_busy
, timeout
);
286 ctrl_dbg(ctrl
, "Command not completed in 1000 msec\n");
290 * pcie_write_cmd - Issue controller command
291 * @ctrl: controller to which the command is issued
292 * @cmd: command value written to slot control register
293 * @mask: bitmask of slot control register to be modified
295 static int pcie_write_cmd(struct controller
*ctrl
, u16 cmd
, u16 mask
)
301 mutex_lock(&ctrl
->ctrl_lock
);
303 retval
= pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
);
305 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS register\n",
310 if (slot_status
& CMD_COMPLETED
) {
311 if (!ctrl
->no_cmd_complete
) {
313 * After 1 sec and CMD_COMPLETED still not set, just
314 * proceed forward to issue the next command according
315 * to spec. Just print out the error message.
318 "%s: CMD_COMPLETED not clear after 1 sec.\n",
320 } else if (!NO_CMD_CMPL(ctrl
)) {
322 * This controller semms to notify of command completed
323 * event even though it supports none of power
324 * controller, attention led, power led and EMI.
326 ctrl_dbg(ctrl
, "%s: Unexpected CMD_COMPLETED. Need to "
327 "wait for command completed event.\n",
329 ctrl
->no_cmd_complete
= 0;
331 ctrl_dbg(ctrl
, "%s: Unexpected CMD_COMPLETED. Maybe "
332 "the controller is broken.\n", __func__
);
336 retval
= pciehp_readw(ctrl
, SLOTCTRL
, &slot_ctrl
);
338 ctrl_err(ctrl
, "%s: Cannot read SLOTCTRL register\n", __func__
);
343 slot_ctrl
|= (cmd
& mask
);
346 retval
= pciehp_writew(ctrl
, SLOTCTRL
, slot_ctrl
);
348 ctrl_err(ctrl
, "%s: Cannot write to SLOTCTRL register\n",
352 * Wait for command completion.
354 if (!retval
&& !ctrl
->no_cmd_complete
) {
357 * if hotplug interrupt is not enabled or command
358 * completed interrupt is not enabled, we need to poll
359 * command completed event.
361 if (!(slot_ctrl
& HP_INTR_ENABLE
) ||
362 !(slot_ctrl
& CMD_CMPL_INTR_ENABLE
))
364 pcie_wait_cmd(ctrl
, poll
);
367 mutex_unlock(&ctrl
->ctrl_lock
);
371 static int hpc_check_lnk_status(struct controller
*ctrl
)
376 retval
= pciehp_readw(ctrl
, LNKSTATUS
, &lnk_status
);
378 ctrl_err(ctrl
, "%s: Cannot read LNKSTATUS register\n",
383 ctrl_dbg(ctrl
, "%s: lnk_status = %x\n", __func__
, lnk_status
);
384 if ( (lnk_status
& LNK_TRN
) || (lnk_status
& LNK_TRN_ERR
) ||
385 !(lnk_status
& NEG_LINK_WD
)) {
386 ctrl_err(ctrl
, "%s : Link Training Error occurs \n", __func__
);
394 static int hpc_get_attention_status(struct slot
*slot
, u8
*status
)
396 struct controller
*ctrl
= slot
->ctrl
;
401 retval
= pciehp_readw(ctrl
, SLOTCTRL
, &slot_ctrl
);
403 ctrl_err(ctrl
, "%s: Cannot read SLOTCTRL register\n", __func__
);
407 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x, value read %x\n",
408 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_ctrl
);
410 atten_led_state
= (slot_ctrl
& ATTN_LED_CTRL
) >> 6;
412 switch (atten_led_state
) {
414 *status
= 0xFF; /* Reserved */
417 *status
= 1; /* On */
420 *status
= 2; /* Blink */
423 *status
= 0; /* Off */
433 static int hpc_get_power_status(struct slot
*slot
, u8
*status
)
435 struct controller
*ctrl
= slot
->ctrl
;
440 retval
= pciehp_readw(ctrl
, SLOTCTRL
, &slot_ctrl
);
442 ctrl_err(ctrl
, "%s: Cannot read SLOTCTRL register\n", __func__
);
445 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x value read %x\n",
446 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_ctrl
);
448 pwr_state
= (slot_ctrl
& PWR_CTRL
) >> 10;
465 static int hpc_get_latch_status(struct slot
*slot
, u8
*status
)
467 struct controller
*ctrl
= slot
->ctrl
;
471 retval
= pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
);
473 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS register\n",
478 *status
= (((slot_status
& MRL_STATE
) >> 5) == 0) ? 0 : 1;
483 static int hpc_get_adapter_status(struct slot
*slot
, u8
*status
)
485 struct controller
*ctrl
= slot
->ctrl
;
490 retval
= pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
);
492 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS register\n",
496 card_state
= (u8
)((slot_status
& PRSN_STATE
) >> 6);
497 *status
= (card_state
== 1) ? 1 : 0;
502 static int hpc_query_power_fault(struct slot
*slot
)
504 struct controller
*ctrl
= slot
->ctrl
;
509 retval
= pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
);
511 ctrl_err(ctrl
, "%s: Cannot check for power fault\n", __func__
);
514 pwr_fault
= (u8
)((slot_status
& PWR_FAULT_DETECTED
) >> 1);
519 static int hpc_get_emi_status(struct slot
*slot
, u8
*status
)
521 struct controller
*ctrl
= slot
->ctrl
;
525 retval
= pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
);
527 ctrl_err(ctrl
, "%s : Cannot check EMI status\n", __func__
);
530 *status
= (slot_status
& EMI_STATE
) >> EMI_STATUS_BIT
;
535 static int hpc_toggle_emi(struct slot
*slot
)
543 rc
= pcie_write_cmd(slot
->ctrl
, slot_cmd
, cmd_mask
);
544 slot
->last_emi_toggle
= get_seconds();
549 static int hpc_set_attention_status(struct slot
*slot
, u8 value
)
551 struct controller
*ctrl
= slot
->ctrl
;
556 cmd_mask
= ATTN_LED_CTRL
;
558 case 0 : /* turn off */
561 case 1: /* turn on */
564 case 2: /* turn blink */
570 rc
= pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
571 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n",
572 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_cmd
);
577 static void hpc_set_green_led_on(struct slot
*slot
)
579 struct controller
*ctrl
= slot
->ctrl
;
584 cmd_mask
= PWR_LED_CTRL
;
585 pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
586 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n",
587 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_cmd
);
590 static void hpc_set_green_led_off(struct slot
*slot
)
592 struct controller
*ctrl
= slot
->ctrl
;
597 cmd_mask
= PWR_LED_CTRL
;
598 pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
599 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n",
600 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_cmd
);
603 static void hpc_set_green_led_blink(struct slot
*slot
)
605 struct controller
*ctrl
= slot
->ctrl
;
610 cmd_mask
= PWR_LED_CTRL
;
611 pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
612 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n",
613 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_cmd
);
616 static int hpc_power_on_slot(struct slot
* slot
)
618 struct controller
*ctrl
= slot
->ctrl
;
624 ctrl_dbg(ctrl
, "%s: slot->hp_slot %x\n", __func__
, slot
->hp_slot
);
626 /* Clear sticky power-fault bit from previous power failures */
627 retval
= pciehp_readw(ctrl
, SLOTSTATUS
, &slot_status
);
629 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS register\n",
633 slot_status
&= PWR_FAULT_DETECTED
;
635 retval
= pciehp_writew(ctrl
, SLOTSTATUS
, slot_status
);
638 "%s: Cannot write to SLOTSTATUS register\n",
646 /* Enable detection that we turned off at slot power-off time */
647 if (!pciehp_poll_mode
) {
648 slot_cmd
|= (PWR_FAULT_DETECT_ENABLE
| MRL_DETECT_ENABLE
|
650 cmd_mask
|= (PWR_FAULT_DETECT_ENABLE
| MRL_DETECT_ENABLE
|
654 retval
= pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
657 ctrl_err(ctrl
, "%s: Write %x command failed!\n",
661 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n",
662 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_cmd
);
667 static inline int pcie_mask_bad_dllp(struct controller
*ctrl
)
669 struct pci_dev
*dev
= ctrl
->pci_dev
;
673 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ERR
);
676 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, ®
);
677 if (reg
& PCI_ERR_COR_BAD_DLLP
)
679 reg
|= PCI_ERR_COR_BAD_DLLP
;
680 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, reg
);
684 static inline void pcie_unmask_bad_dllp(struct controller
*ctrl
)
686 struct pci_dev
*dev
= ctrl
->pci_dev
;
690 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ERR
);
693 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, ®
);
694 if (!(reg
& PCI_ERR_COR_BAD_DLLP
))
696 reg
&= ~PCI_ERR_COR_BAD_DLLP
;
697 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, reg
);
700 static int hpc_power_off_slot(struct slot
* slot
)
702 struct controller
*ctrl
= slot
->ctrl
;
708 ctrl_dbg(ctrl
, "%s: slot->hp_slot %x\n", __func__
, slot
->hp_slot
);
711 * Set Bad DLLP Mask bit in Correctable Error Mask
712 * Register. This is the workaround against Bad DLLP error
713 * that sometimes happens during turning power off the slot
714 * which conforms to PCI Express 1.0a spec.
716 changed
= pcie_mask_bad_dllp(ctrl
);
718 slot_cmd
= POWER_OFF
;
721 * If we get MRL or presence detect interrupts now, the isr
722 * will notice the sticky power-fault bit too and issue power
723 * indicator change commands. This will lead to an endless loop
724 * of command completions, since the power-fault bit remains on
725 * till the slot is powered on again.
727 if (!pciehp_poll_mode
) {
728 slot_cmd
&= ~(PWR_FAULT_DETECT_ENABLE
| MRL_DETECT_ENABLE
|
730 cmd_mask
|= (PWR_FAULT_DETECT_ENABLE
| MRL_DETECT_ENABLE
|
734 retval
= pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
736 ctrl_err(ctrl
, "%s: Write command failed!\n", __func__
);
740 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n",
741 __func__
, ctrl
->cap_base
+ SLOTCTRL
, slot_cmd
);
744 pcie_unmask_bad_dllp(ctrl
);
749 static irqreturn_t
pcie_isr(int irq
, void *dev_id
)
751 struct controller
*ctrl
= (struct controller
*)dev_id
;
752 u16 detected
, intr_loc
;
756 * In order to guarantee that all interrupt events are
757 * serviced, we need to re-inspect Slot Status register after
758 * clearing what is presumed to be the last pending interrupt.
762 if (pciehp_readw(ctrl
, SLOTSTATUS
, &detected
)) {
763 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS\n",
768 detected
&= (ATTN_BUTTN_PRESSED
| PWR_FAULT_DETECTED
|
769 MRL_SENS_CHANGED
| PRSN_DETECT_CHANGED
|
771 intr_loc
|= detected
;
774 if (detected
&& pciehp_writew(ctrl
, SLOTSTATUS
, detected
)) {
775 ctrl_err(ctrl
, "%s: Cannot write to SLOTSTATUS\n",
781 ctrl_dbg(ctrl
, "%s: intr_loc %x\n", __func__
, intr_loc
);
783 /* Check Command Complete Interrupt Pending */
784 if (intr_loc
& CMD_COMPLETED
) {
787 wake_up(&ctrl
->queue
);
790 if (!(intr_loc
& ~CMD_COMPLETED
))
793 p_slot
= pciehp_find_slot(ctrl
, ctrl
->slot_device_offset
);
795 /* Check MRL Sensor Changed */
796 if (intr_loc
& MRL_SENS_CHANGED
)
797 pciehp_handle_switch_change(p_slot
);
799 /* Check Attention Button Pressed */
800 if (intr_loc
& ATTN_BUTTN_PRESSED
)
801 pciehp_handle_attention_button(p_slot
);
803 /* Check Presence Detect Changed */
804 if (intr_loc
& PRSN_DETECT_CHANGED
)
805 pciehp_handle_presence_change(p_slot
);
807 /* Check Power Fault Detected */
808 if (intr_loc
& PWR_FAULT_DETECTED
)
809 pciehp_handle_power_fault(p_slot
);
814 static int hpc_get_max_lnk_speed(struct slot
*slot
, enum pci_bus_speed
*value
)
816 struct controller
*ctrl
= slot
->ctrl
;
817 enum pcie_link_speed lnk_speed
;
821 retval
= pciehp_readl(ctrl
, LNKCAP
, &lnk_cap
);
823 ctrl_err(ctrl
, "%s: Cannot read LNKCAP register\n", __func__
);
827 switch (lnk_cap
& 0x000F) {
829 lnk_speed
= PCIE_2PT5GB
;
832 lnk_speed
= PCIE_LNK_SPEED_UNKNOWN
;
837 ctrl_dbg(ctrl
, "Max link speed = %d\n", lnk_speed
);
842 static int hpc_get_max_lnk_width(struct slot
*slot
,
843 enum pcie_link_width
*value
)
845 struct controller
*ctrl
= slot
->ctrl
;
846 enum pcie_link_width lnk_wdth
;
850 retval
= pciehp_readl(ctrl
, LNKCAP
, &lnk_cap
);
852 ctrl_err(ctrl
, "%s: Cannot read LNKCAP register\n", __func__
);
856 switch ((lnk_cap
& 0x03F0) >> 4){
858 lnk_wdth
= PCIE_LNK_WIDTH_RESRV
;
861 lnk_wdth
= PCIE_LNK_X1
;
864 lnk_wdth
= PCIE_LNK_X2
;
867 lnk_wdth
= PCIE_LNK_X4
;
870 lnk_wdth
= PCIE_LNK_X8
;
873 lnk_wdth
= PCIE_LNK_X12
;
876 lnk_wdth
= PCIE_LNK_X16
;
879 lnk_wdth
= PCIE_LNK_X32
;
882 lnk_wdth
= PCIE_LNK_WIDTH_UNKNOWN
;
887 ctrl_dbg(ctrl
, "Max link width = %d\n", lnk_wdth
);
892 static int hpc_get_cur_lnk_speed(struct slot
*slot
, enum pci_bus_speed
*value
)
894 struct controller
*ctrl
= slot
->ctrl
;
895 enum pcie_link_speed lnk_speed
= PCI_SPEED_UNKNOWN
;
899 retval
= pciehp_readw(ctrl
, LNKSTATUS
, &lnk_status
);
901 ctrl_err(ctrl
, "%s: Cannot read LNKSTATUS register\n",
906 switch (lnk_status
& 0x0F) {
908 lnk_speed
= PCIE_2PT5GB
;
911 lnk_speed
= PCIE_LNK_SPEED_UNKNOWN
;
916 ctrl_dbg(ctrl
, "Current link speed = %d\n", lnk_speed
);
921 static int hpc_get_cur_lnk_width(struct slot
*slot
,
922 enum pcie_link_width
*value
)
924 struct controller
*ctrl
= slot
->ctrl
;
925 enum pcie_link_width lnk_wdth
= PCIE_LNK_WIDTH_UNKNOWN
;
929 retval
= pciehp_readw(ctrl
, LNKSTATUS
, &lnk_status
);
931 ctrl_err(ctrl
, "%s: Cannot read LNKSTATUS register\n",
936 switch ((lnk_status
& 0x03F0) >> 4){
938 lnk_wdth
= PCIE_LNK_WIDTH_RESRV
;
941 lnk_wdth
= PCIE_LNK_X1
;
944 lnk_wdth
= PCIE_LNK_X2
;
947 lnk_wdth
= PCIE_LNK_X4
;
950 lnk_wdth
= PCIE_LNK_X8
;
953 lnk_wdth
= PCIE_LNK_X12
;
956 lnk_wdth
= PCIE_LNK_X16
;
959 lnk_wdth
= PCIE_LNK_X32
;
962 lnk_wdth
= PCIE_LNK_WIDTH_UNKNOWN
;
967 ctrl_dbg(ctrl
, "Current link width = %d\n", lnk_wdth
);
972 static void pcie_release_ctrl(struct controller
*ctrl
);
973 static struct hpc_ops pciehp_hpc_ops
= {
974 .power_on_slot
= hpc_power_on_slot
,
975 .power_off_slot
= hpc_power_off_slot
,
976 .set_attention_status
= hpc_set_attention_status
,
977 .get_power_status
= hpc_get_power_status
,
978 .get_attention_status
= hpc_get_attention_status
,
979 .get_latch_status
= hpc_get_latch_status
,
980 .get_adapter_status
= hpc_get_adapter_status
,
981 .get_emi_status
= hpc_get_emi_status
,
982 .toggle_emi
= hpc_toggle_emi
,
984 .get_max_bus_speed
= hpc_get_max_lnk_speed
,
985 .get_cur_bus_speed
= hpc_get_cur_lnk_speed
,
986 .get_max_lnk_width
= hpc_get_max_lnk_width
,
987 .get_cur_lnk_width
= hpc_get_cur_lnk_width
,
989 .query_power_fault
= hpc_query_power_fault
,
990 .green_led_on
= hpc_set_green_led_on
,
991 .green_led_off
= hpc_set_green_led_off
,
992 .green_led_blink
= hpc_set_green_led_blink
,
994 .release_ctlr
= pcie_release_ctrl
,
995 .check_lnk_status
= hpc_check_lnk_status
,
998 int pcie_enable_notification(struct controller
*ctrl
)
1002 cmd
= PRSN_DETECT_ENABLE
;
1003 if (ATTN_BUTTN(ctrl
))
1004 cmd
|= ATTN_BUTTN_ENABLE
;
1005 if (POWER_CTRL(ctrl
))
1006 cmd
|= PWR_FAULT_DETECT_ENABLE
;
1008 cmd
|= MRL_DETECT_ENABLE
;
1009 if (!pciehp_poll_mode
)
1010 cmd
|= HP_INTR_ENABLE
| CMD_CMPL_INTR_ENABLE
;
1012 mask
= PRSN_DETECT_ENABLE
| ATTN_BUTTN_ENABLE
| MRL_DETECT_ENABLE
|
1013 PWR_FAULT_DETECT_ENABLE
| HP_INTR_ENABLE
| CMD_CMPL_INTR_ENABLE
;
1015 if (pcie_write_cmd(ctrl
, cmd
, mask
)) {
1016 ctrl_err(ctrl
, "%s: Cannot enable software notification\n",
1023 static void pcie_disable_notification(struct controller
*ctrl
)
1026 mask
= PRSN_DETECT_ENABLE
| ATTN_BUTTN_ENABLE
| MRL_DETECT_ENABLE
|
1027 PWR_FAULT_DETECT_ENABLE
| HP_INTR_ENABLE
| CMD_CMPL_INTR_ENABLE
;
1028 if (pcie_write_cmd(ctrl
, 0, mask
))
1029 ctrl_warn(ctrl
, "%s: Cannot disable software notification\n",
1033 static int pcie_init_notification(struct controller
*ctrl
)
1035 if (pciehp_request_irq(ctrl
))
1037 if (pcie_enable_notification(ctrl
)) {
1038 pciehp_free_irq(ctrl
);
1044 static void pcie_shutdown_notification(struct controller
*ctrl
)
1046 pcie_disable_notification(ctrl
);
1047 pciehp_free_irq(ctrl
);
1050 static int pcie_init_slot(struct controller
*ctrl
)
1054 slot
= kzalloc(sizeof(*slot
), GFP_KERNEL
);
1060 slot
->bus
= ctrl
->pci_dev
->subordinate
->number
;
1061 slot
->device
= ctrl
->slot_device_offset
+ slot
->hp_slot
;
1062 slot
->hpc_ops
= ctrl
->hpc_ops
;
1063 slot
->number
= ctrl
->first_slot
;
1064 snprintf(slot
->name
, SLOT_NAME_SIZE
, "%d", slot
->number
);
1065 mutex_init(&slot
->lock
);
1066 INIT_DELAYED_WORK(&slot
->work
, pciehp_queue_pushbutton_work
);
1067 list_add(&slot
->slot_list
, &ctrl
->slot_list
);
1071 static void pcie_cleanup_slot(struct controller
*ctrl
)
1074 slot
= list_first_entry(&ctrl
->slot_list
, struct slot
, slot_list
);
1075 list_del(&slot
->slot_list
);
1076 cancel_delayed_work(&slot
->work
);
1077 flush_scheduled_work();
1078 flush_workqueue(pciehp_wq
);
1082 static inline void dbg_ctrl(struct controller
*ctrl
)
1086 struct pci_dev
*pdev
= ctrl
->pci_dev
;
1091 ctrl_info(ctrl
, "Hotplug Controller:\n");
1092 ctrl_info(ctrl
, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
1093 pci_name(pdev
), pdev
->irq
);
1094 ctrl_info(ctrl
, " Vendor ID : 0x%04x\n", pdev
->vendor
);
1095 ctrl_info(ctrl
, " Device ID : 0x%04x\n", pdev
->device
);
1096 ctrl_info(ctrl
, " Subsystem ID : 0x%04x\n",
1097 pdev
->subsystem_device
);
1098 ctrl_info(ctrl
, " Subsystem Vendor ID : 0x%04x\n",
1099 pdev
->subsystem_vendor
);
1100 ctrl_info(ctrl
, " PCIe Cap offset : 0x%02x\n", ctrl
->cap_base
);
1101 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1102 if (!pci_resource_len(pdev
, i
))
1104 ctrl_info(ctrl
, " PCI resource [%d] : 0x%llx@0x%llx\n",
1105 i
, (unsigned long long)pci_resource_len(pdev
, i
),
1106 (unsigned long long)pci_resource_start(pdev
, i
));
1108 ctrl_info(ctrl
, "Slot Capabilities : 0x%08x\n", ctrl
->slot_cap
);
1109 ctrl_info(ctrl
, " Physical Slot Number : %d\n", ctrl
->first_slot
);
1110 ctrl_info(ctrl
, " Attention Button : %3s\n",
1111 ATTN_BUTTN(ctrl
) ? "yes" : "no");
1112 ctrl_info(ctrl
, " Power Controller : %3s\n",
1113 POWER_CTRL(ctrl
) ? "yes" : "no");
1114 ctrl_info(ctrl
, " MRL Sensor : %3s\n",
1115 MRL_SENS(ctrl
) ? "yes" : "no");
1116 ctrl_info(ctrl
, " Attention Indicator : %3s\n",
1117 ATTN_LED(ctrl
) ? "yes" : "no");
1118 ctrl_info(ctrl
, " Power Indicator : %3s\n",
1119 PWR_LED(ctrl
) ? "yes" : "no");
1120 ctrl_info(ctrl
, " Hot-Plug Surprise : %3s\n",
1121 HP_SUPR_RM(ctrl
) ? "yes" : "no");
1122 ctrl_info(ctrl
, " EMI Present : %3s\n",
1123 EMI(ctrl
) ? "yes" : "no");
1124 ctrl_info(ctrl
, " Command Completed : %3s\n",
1125 NO_CMD_CMPL(ctrl
) ? "no" : "yes");
1126 pciehp_readw(ctrl
, SLOTSTATUS
, ®16
);
1127 ctrl_info(ctrl
, "Slot Status : 0x%04x\n", reg16
);
1128 pciehp_readw(ctrl
, SLOTCTRL
, ®16
);
1129 ctrl_info(ctrl
, "Slot Control : 0x%04x\n", reg16
);
1132 struct controller
*pcie_init(struct pcie_device
*dev
)
1134 struct controller
*ctrl
;
1136 struct pci_dev
*pdev
= dev
->port
;
1138 ctrl
= kzalloc(sizeof(*ctrl
), GFP_KERNEL
);
1140 dev_err(&dev
->device
, "%s : out of memory\n", __func__
);
1143 INIT_LIST_HEAD(&ctrl
->slot_list
);
1146 ctrl
->pci_dev
= pdev
;
1147 ctrl
->cap_base
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
1148 if (!ctrl
->cap_base
) {
1149 ctrl_err(ctrl
, "%s: Cannot find PCI Express capability\n",
1153 if (pciehp_readl(ctrl
, SLOTCAP
, &slot_cap
)) {
1154 ctrl_err(ctrl
, "%s: Cannot read SLOTCAP register\n", __func__
);
1158 ctrl
->slot_cap
= slot_cap
;
1159 ctrl
->first_slot
= slot_cap
>> 19;
1160 ctrl
->slot_device_offset
= 0;
1161 ctrl
->num_slots
= 1;
1162 ctrl
->hpc_ops
= &pciehp_hpc_ops
;
1163 mutex_init(&ctrl
->crit_sect
);
1164 mutex_init(&ctrl
->ctrl_lock
);
1165 init_waitqueue_head(&ctrl
->queue
);
1168 * Controller doesn't notify of command completion if the "No
1169 * Command Completed Support" bit is set in Slot Capability
1170 * register or the controller supports none of power
1171 * controller, attention led, power led and EMI.
1173 if (NO_CMD_CMPL(ctrl
) ||
1174 !(POWER_CTRL(ctrl
) | ATTN_LED(ctrl
) | PWR_LED(ctrl
) | EMI(ctrl
)))
1175 ctrl
->no_cmd_complete
= 1;
1177 /* Clear all remaining event bits in Slot Status register */
1178 if (pciehp_writew(ctrl
, SLOTSTATUS
, 0x1f))
1181 /* Disable sotfware notification */
1182 pcie_disable_notification(ctrl
);
1185 * If this is the first controller to be initialized,
1186 * initialize the pciehp work queue
1188 if (atomic_add_return(1, &pciehp_num_controllers
) == 1) {
1189 pciehp_wq
= create_singlethread_workqueue("pciehpd");
1194 ctrl_info(ctrl
, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1195 pdev
->vendor
, pdev
->device
, pdev
->subsystem_vendor
,
1196 pdev
->subsystem_device
);
1198 if (pcie_init_slot(ctrl
))
1201 if (pcie_init_notification(ctrl
))
1207 pcie_cleanup_slot(ctrl
);
1214 void pcie_release_ctrl(struct controller
*ctrl
)
1216 pcie_shutdown_notification(ctrl
);
1217 pcie_cleanup_slot(ctrl
);
1219 * If this is the last controller to be released, destroy the
1222 if (atomic_dec_and_test(&pciehp_num_controllers
))
1223 destroy_workqueue(pciehp_wq
);