include/linux/dmar.h

   1 /*
   2  * Copyright (c) 2006, Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  15  * Place - Suite 330, Boston, MA 02111-1307 USA.
  16  *
  17  * Copyright (C) Ashok Raj <ashok.raj@intel.com>
  18  * Copyright (C) Shaohua Li <shaohua.li@intel.com>
  19  */
  20
  21 #ifndef __DMAR_H__
  22 #define __DMAR_H__
  23
  24 #include <linux/acpi.h>
  25 #include <linux/types.h>
  26 #include <linux/msi.h>
  27
  28 #ifdef CONFIG_DMAR
  29 struct intel_iommu;
  30
  31 extern const char *dmar_get_fault_reason(u8 fault_reason);
  32
  33 /* Can't use the common MSI interrupt functions
  34  * since DMAR is not a pci device
  35  */
  36 extern void dmar_msi_unmask(unsigned int irq);
  37 extern void dmar_msi_mask(unsigned int irq);
  38 extern void dmar_msi_read(int irq, struct msi_msg *msg);
  39 extern void dmar_msi_write(int irq, struct msi_msg *msg);
  40 extern int dmar_set_interrupt(struct intel_iommu *iommu);
  41 extern int arch_setup_dmar_msi(unsigned int irq);
  42
  43 /* Intel IOMMU detection and initialization functions */
  44 extern void detect_intel_iommu(void);
  45 extern int intel_iommu_init(void);
  46
  47 extern int dmar_table_init(void);
  48 extern int early_dmar_detect(void);
  49
  50 extern struct list_head dmar_drhd_units;
  51 extern struct list_head dmar_rmrr_units;
  52
  53 struct dmar_drhd_unit {
  54         struct list_head list;          /* list of drhd units   */
  55         u64     reg_base_addr;          /* register base address*/
  56         struct  pci_dev **devices;      /* target device array  */
  57         int     devices_cnt;            /* target device count  */
  58         u8      ignored:1;              /* ignore drhd          */
  59         u8      include_all:1;
  60         struct intel_iommu *iommu;
  61 };
  62
  63 struct dmar_rmrr_unit {
  64         struct list_head list;          /* list of rmrr units   */
  65         u64     base_address;           /* reserved base address*/
  66         u64     end_address;            /* reserved end address */
  67         struct pci_dev **devices;       /* target devices */
  68         int     devices_cnt;            /* target device count */
  69 };
  70
  71 #define for_each_drhd_unit(drhd) \
  72         list_for_each_entry(drhd, &dmar_drhd_units, list)
  73 #define for_each_rmrr_units(rmrr) \
  74         list_for_each_entry(rmrr, &dmar_rmrr_units, list)
  75 #else
  76 static inline void detect_intel_iommu(void)
  77 {
  78         return;
  79 }
  80 static inline int intel_iommu_init(void)
  81 {
  82         return -ENODEV;
  83 }
  84
  85 #endif /* !CONFIG_DMAR */
  86 #endif /* __DMAR_H__ */