drivers/pci/hotplug/shpchprm_legacy.c

   1 /*
   2  * SHPCHPRM Legacy: PHP Resource Manager for Non-ACPI/Legacy platform
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/config.h>
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/types.h>
  34 #include <linux/pci.h>
  35 #include <linux/init.h>
  36 #include <asm/uaccess.h>
  37 #include "shpchp.h"
  38 #include "shpchprm.h"
  39
  40 void shpchprm_cleanup(void)
  41 {
  42 }
  43
  44 int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum)
  45 {
  46         int     offset = devnum - ctrl->slot_device_offset;
  47
  48         *sun = (u8) (ctrl->first_slot + ctrl->slot_num_inc * offset);
  49         return 0;
  50 }
  51
  52 int shpchprm_set_hpp(
  53         struct controller *ctrl,
  54         struct pci_func *func,
  55         u8      card_type)
  56 {
  57         u32 rc;
  58         u8 temp_byte;
  59         struct pci_bus lpci_bus, *pci_bus;
  60         unsigned int    devfn;
  61         memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
  62         pci_bus = &lpci_bus;
  63         pci_bus->number = func->bus;
  64         devfn = PCI_DEVFN(func->device, func->function);
  65
  66         temp_byte = 0x40;       /* hard coded value for LT */
  67         if (card_type == PCI_HEADER_TYPE_BRIDGE) {
  68                 /* set subordinate Latency Timer */
  69                 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, temp_byte);
  70                 if (rc) {
  71                         dbg("%s: set secondary LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus,
  72                                 func->device, func->function);
  73                         return rc;
  74                 }
  75         }
  76
  77         /* set base Latency Timer */
  78         rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
  79         if (rc) {
  80                 dbg("%s: set LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
  81                 return rc;
  82         }
  83
  84         /* set Cache Line size */
  85         temp_byte = 0x08;       /* hard coded value for CLS */
  86         rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
  87         if (rc) {
  88                 dbg("%s: set CLS error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
  89         }
  90
  91         /* set enable_perr */
  92         /* set enable_serr */
  93
  94         return rc;
  95 }
  96
  97 void shpchprm_enable_card(
  98         struct controller *ctrl,
  99         struct pci_func *func,
 100         u8 card_type)
 101 {
 102         u16 command, bcommand;
 103         struct pci_bus lpci_bus, *pci_bus;
 104         unsigned int devfn;
 105         int rc;
 106
 107         memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
 108         pci_bus = &lpci_bus;
 109         pci_bus->number = func->bus;
 110         devfn = PCI_DEVFN(func->device, func->function);
 111
 112         rc = pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &command);
 113         command |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR
 114                 | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
 115                 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 116         rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
 117
 118         if (card_type == PCI_HEADER_TYPE_BRIDGE) {
 119                 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, &bcommand);
 120                 bcommand |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR
 121                         | PCI_BRIDGE_CTL_NO_ISA;
 122                 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, bcommand);
 123         }
 124 }
 125
 126 static int legacy_shpchprm_init_pci(void)
 127 {
 128         return 0;
 129 }
 130
 131 int shpchprm_init(enum php_ctlr_type ctrl_type)
 132 {
 133         int retval;
 134
 135         switch (ctrl_type) {
 136         case PCI:
 137                 retval = legacy_shpchprm_init_pci();
 138                 break;
 139         default:
 140                 retval = -ENODEV;
 141                 break;
 142         }
 143
 144         return retval;
 145 }