2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
);
40 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
43 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
45 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
48 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
49 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
50 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
52 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
53 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
54 struct drm_i915_gem_pwrite
*args
,
55 struct drm_file
*file_priv
);
56 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
58 static LIST_HEAD(shrink_list
);
59 static DEFINE_SPINLOCK(shrink_list_lock
);
62 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
64 return obj_priv
->gtt_space
&&
66 obj_priv
->pin_count
== 0;
69 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
72 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
75 (start
& (PAGE_SIZE
- 1)) != 0 ||
76 (end
& (PAGE_SIZE
- 1)) != 0) {
80 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
83 dev
->gtt_total
= (uint32_t) (end
- start
);
89 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
90 struct drm_file
*file_priv
)
92 struct drm_i915_gem_init
*args
= data
;
95 mutex_lock(&dev
->struct_mutex
);
96 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
97 mutex_unlock(&dev
->struct_mutex
);
103 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
104 struct drm_file
*file_priv
)
106 struct drm_i915_gem_get_aperture
*args
= data
;
108 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
111 args
->aper_size
= dev
->gtt_total
;
112 args
->aper_available_size
= (args
->aper_size
-
113 atomic_read(&dev
->pin_memory
));
120 * Creates a new mm object and returns a handle to it.
123 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
124 struct drm_file
*file_priv
)
126 struct drm_i915_gem_create
*args
= data
;
127 struct drm_gem_object
*obj
;
131 args
->size
= roundup(args
->size
, PAGE_SIZE
);
133 /* Allocate the new object */
134 obj
= i915_gem_alloc_object(dev
, args
->size
);
138 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
140 drm_gem_object_unreference_unlocked(obj
);
144 /* Sink the floating reference from kref_init(handlecount) */
145 drm_gem_object_handle_unreference_unlocked(obj
);
147 args
->handle
= handle
;
152 fast_shmem_read(struct page
**pages
,
153 loff_t page_base
, int page_offset
,
160 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
163 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
164 kunmap_atomic(vaddr
, KM_USER0
);
172 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
174 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
175 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
177 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
178 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
182 slow_shmem_copy(struct page
*dst_page
,
184 struct page
*src_page
,
188 char *dst_vaddr
, *src_vaddr
;
190 dst_vaddr
= kmap(dst_page
);
191 src_vaddr
= kmap(src_page
);
193 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
200 slow_shmem_bit17_copy(struct page
*gpu_page
,
202 struct page
*cpu_page
,
207 char *gpu_vaddr
, *cpu_vaddr
;
209 /* Use the unswizzled path if this page isn't affected. */
210 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
212 return slow_shmem_copy(cpu_page
, cpu_offset
,
213 gpu_page
, gpu_offset
, length
);
215 return slow_shmem_copy(gpu_page
, gpu_offset
,
216 cpu_page
, cpu_offset
, length
);
219 gpu_vaddr
= kmap(gpu_page
);
220 cpu_vaddr
= kmap(cpu_page
);
222 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
223 * XORing with the other bits (A9 for Y, A9 and A10 for X)
226 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
227 int this_length
= min(cacheline_end
- gpu_offset
, length
);
228 int swizzled_gpu_offset
= gpu_offset
^ 64;
231 memcpy(cpu_vaddr
+ cpu_offset
,
232 gpu_vaddr
+ swizzled_gpu_offset
,
235 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
236 cpu_vaddr
+ cpu_offset
,
239 cpu_offset
+= this_length
;
240 gpu_offset
+= this_length
;
241 length
-= this_length
;
249 * This is the fast shmem pread path, which attempts to copy_from_user directly
250 * from the backing pages of the object to the user's address space. On a
251 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
254 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
255 struct drm_i915_gem_pread
*args
,
256 struct drm_file
*file_priv
)
258 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
260 loff_t offset
, page_base
;
261 char __user
*user_data
;
262 int page_offset
, page_length
;
265 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
268 mutex_lock(&dev
->struct_mutex
);
270 ret
= i915_gem_object_get_pages(obj
, 0);
274 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
279 obj_priv
= to_intel_bo(obj
);
280 offset
= args
->offset
;
283 /* Operation in this page
285 * page_base = page offset within aperture
286 * page_offset = offset within page
287 * page_length = bytes to copy for this page
289 page_base
= (offset
& ~(PAGE_SIZE
-1));
290 page_offset
= offset
& (PAGE_SIZE
-1);
291 page_length
= remain
;
292 if ((page_offset
+ remain
) > PAGE_SIZE
)
293 page_length
= PAGE_SIZE
- page_offset
;
295 ret
= fast_shmem_read(obj_priv
->pages
,
296 page_base
, page_offset
,
297 user_data
, page_length
);
301 remain
-= page_length
;
302 user_data
+= page_length
;
303 offset
+= page_length
;
307 i915_gem_object_put_pages(obj
);
309 mutex_unlock(&dev
->struct_mutex
);
315 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
319 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
321 /* If we've insufficient memory to map in the pages, attempt
322 * to make some space by throwing out some old buffers.
324 if (ret
== -ENOMEM
) {
325 struct drm_device
*dev
= obj
->dev
;
327 ret
= i915_gem_evict_something(dev
, obj
->size
,
328 i915_gem_get_gtt_alignment(obj
));
332 ret
= i915_gem_object_get_pages(obj
, 0);
339 * This is the fallback shmem pread path, which allocates temporary storage
340 * in kernel space to copy_to_user into outside of the struct_mutex, so we
341 * can copy out of the object's backing pages while holding the struct mutex
342 * and not take page faults.
345 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
346 struct drm_i915_gem_pread
*args
,
347 struct drm_file
*file_priv
)
349 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
350 struct mm_struct
*mm
= current
->mm
;
351 struct page
**user_pages
;
353 loff_t offset
, pinned_pages
, i
;
354 loff_t first_data_page
, last_data_page
, num_pages
;
355 int shmem_page_index
, shmem_page_offset
;
356 int data_page_index
, data_page_offset
;
359 uint64_t data_ptr
= args
->data_ptr
;
360 int do_bit17_swizzling
;
364 /* Pin the user pages containing the data. We can't fault while
365 * holding the struct mutex, yet we want to hold it while
366 * dereferencing the user data.
368 first_data_page
= data_ptr
/ PAGE_SIZE
;
369 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
370 num_pages
= last_data_page
- first_data_page
+ 1;
372 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
373 if (user_pages
== NULL
)
376 down_read(&mm
->mmap_sem
);
377 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
378 num_pages
, 1, 0, user_pages
, NULL
);
379 up_read(&mm
->mmap_sem
);
380 if (pinned_pages
< num_pages
) {
382 goto fail_put_user_pages
;
385 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
387 mutex_lock(&dev
->struct_mutex
);
389 ret
= i915_gem_object_get_pages_or_evict(obj
);
393 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
398 obj_priv
= to_intel_bo(obj
);
399 offset
= args
->offset
;
402 /* Operation in this page
404 * shmem_page_index = page number within shmem file
405 * shmem_page_offset = offset within page in shmem file
406 * data_page_index = page number in get_user_pages return
407 * data_page_offset = offset with data_page_index page.
408 * page_length = bytes to copy for this page
410 shmem_page_index
= offset
/ PAGE_SIZE
;
411 shmem_page_offset
= offset
& ~PAGE_MASK
;
412 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
413 data_page_offset
= data_ptr
& ~PAGE_MASK
;
415 page_length
= remain
;
416 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
417 page_length
= PAGE_SIZE
- shmem_page_offset
;
418 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
419 page_length
= PAGE_SIZE
- data_page_offset
;
421 if (do_bit17_swizzling
) {
422 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
424 user_pages
[data_page_index
],
429 slow_shmem_copy(user_pages
[data_page_index
],
431 obj_priv
->pages
[shmem_page_index
],
436 remain
-= page_length
;
437 data_ptr
+= page_length
;
438 offset
+= page_length
;
442 i915_gem_object_put_pages(obj
);
444 mutex_unlock(&dev
->struct_mutex
);
446 for (i
= 0; i
< pinned_pages
; i
++) {
447 SetPageDirty(user_pages
[i
]);
448 page_cache_release(user_pages
[i
]);
450 drm_free_large(user_pages
);
456 * Reads data from the object referenced by handle.
458 * On error, the contents of *data are undefined.
461 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
462 struct drm_file
*file_priv
)
464 struct drm_i915_gem_pread
*args
= data
;
465 struct drm_gem_object
*obj
;
466 struct drm_i915_gem_object
*obj_priv
;
469 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
472 obj_priv
= to_intel_bo(obj
);
474 /* Bounds check source. */
475 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
480 if (!access_ok(VERIFY_WRITE
,
481 (char __user
*)(uintptr_t)args
->data_ptr
,
487 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
488 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
490 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
492 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
497 drm_gem_object_unreference_unlocked(obj
);
501 /* This is the fast write path which cannot handle
502 * page faults in the source data
506 fast_user_write(struct io_mapping
*mapping
,
507 loff_t page_base
, int page_offset
,
508 char __user
*user_data
,
512 unsigned long unwritten
;
514 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
, KM_USER0
);
515 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
517 io_mapping_unmap_atomic(vaddr_atomic
, KM_USER0
);
523 /* Here's the write path which can sleep for
528 slow_kernel_write(struct io_mapping
*mapping
,
529 loff_t gtt_base
, int gtt_offset
,
530 struct page
*user_page
, int user_offset
,
533 char __iomem
*dst_vaddr
;
536 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
537 src_vaddr
= kmap(user_page
);
539 memcpy_toio(dst_vaddr
+ gtt_offset
,
540 src_vaddr
+ user_offset
,
544 io_mapping_unmap(dst_vaddr
);
548 fast_shmem_write(struct page
**pages
,
549 loff_t page_base
, int page_offset
,
554 unsigned long unwritten
;
556 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
559 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
560 kunmap_atomic(vaddr
, KM_USER0
);
568 * This is the fast pwrite path, where we copy the data directly from the
569 * user into the GTT, uncached.
572 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
573 struct drm_i915_gem_pwrite
*args
,
574 struct drm_file
*file_priv
)
576 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
577 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
579 loff_t offset
, page_base
;
580 char __user
*user_data
;
581 int page_offset
, page_length
;
584 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
588 mutex_lock(&dev
->struct_mutex
);
589 ret
= i915_gem_object_pin(obj
, 0);
591 mutex_unlock(&dev
->struct_mutex
);
594 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
598 obj_priv
= to_intel_bo(obj
);
599 offset
= obj_priv
->gtt_offset
+ args
->offset
;
602 /* Operation in this page
604 * page_base = page offset within aperture
605 * page_offset = offset within page
606 * page_length = bytes to copy for this page
608 page_base
= (offset
& ~(PAGE_SIZE
-1));
609 page_offset
= offset
& (PAGE_SIZE
-1);
610 page_length
= remain
;
611 if ((page_offset
+ remain
) > PAGE_SIZE
)
612 page_length
= PAGE_SIZE
- page_offset
;
614 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
615 page_offset
, user_data
, page_length
);
617 /* If we get a fault while copying data, then (presumably) our
618 * source page isn't available. Return the error and we'll
619 * retry in the slow path.
624 remain
-= page_length
;
625 user_data
+= page_length
;
626 offset
+= page_length
;
630 i915_gem_object_unpin(obj
);
631 mutex_unlock(&dev
->struct_mutex
);
637 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
638 * the memory and maps it using kmap_atomic for copying.
640 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
641 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
644 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
645 struct drm_i915_gem_pwrite
*args
,
646 struct drm_file
*file_priv
)
648 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
649 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
651 loff_t gtt_page_base
, offset
;
652 loff_t first_data_page
, last_data_page
, num_pages
;
653 loff_t pinned_pages
, i
;
654 struct page
**user_pages
;
655 struct mm_struct
*mm
= current
->mm
;
656 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
658 uint64_t data_ptr
= args
->data_ptr
;
662 /* Pin the user pages containing the data. We can't fault while
663 * holding the struct mutex, and all of the pwrite implementations
664 * want to hold it while dereferencing the user data.
666 first_data_page
= data_ptr
/ PAGE_SIZE
;
667 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
668 num_pages
= last_data_page
- first_data_page
+ 1;
670 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
671 if (user_pages
== NULL
)
674 down_read(&mm
->mmap_sem
);
675 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
676 num_pages
, 0, 0, user_pages
, NULL
);
677 up_read(&mm
->mmap_sem
);
678 if (pinned_pages
< num_pages
) {
680 goto out_unpin_pages
;
683 mutex_lock(&dev
->struct_mutex
);
684 ret
= i915_gem_object_pin(obj
, 0);
688 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
690 goto out_unpin_object
;
692 obj_priv
= to_intel_bo(obj
);
693 offset
= obj_priv
->gtt_offset
+ args
->offset
;
696 /* Operation in this page
698 * gtt_page_base = page offset within aperture
699 * gtt_page_offset = offset within page in aperture
700 * data_page_index = page number in get_user_pages return
701 * data_page_offset = offset with data_page_index page.
702 * page_length = bytes to copy for this page
704 gtt_page_base
= offset
& PAGE_MASK
;
705 gtt_page_offset
= offset
& ~PAGE_MASK
;
706 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
707 data_page_offset
= data_ptr
& ~PAGE_MASK
;
709 page_length
= remain
;
710 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
711 page_length
= PAGE_SIZE
- gtt_page_offset
;
712 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
713 page_length
= PAGE_SIZE
- data_page_offset
;
715 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
716 gtt_page_base
, gtt_page_offset
,
717 user_pages
[data_page_index
],
721 remain
-= page_length
;
722 offset
+= page_length
;
723 data_ptr
+= page_length
;
727 i915_gem_object_unpin(obj
);
729 mutex_unlock(&dev
->struct_mutex
);
731 for (i
= 0; i
< pinned_pages
; i
++)
732 page_cache_release(user_pages
[i
]);
733 drm_free_large(user_pages
);
739 * This is the fast shmem pwrite path, which attempts to directly
740 * copy_from_user into the kmapped pages backing the object.
743 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
744 struct drm_i915_gem_pwrite
*args
,
745 struct drm_file
*file_priv
)
747 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
749 loff_t offset
, page_base
;
750 char __user
*user_data
;
751 int page_offset
, page_length
;
754 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
757 mutex_lock(&dev
->struct_mutex
);
759 ret
= i915_gem_object_get_pages(obj
, 0);
763 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
767 obj_priv
= to_intel_bo(obj
);
768 offset
= args
->offset
;
772 /* Operation in this page
774 * page_base = page offset within aperture
775 * page_offset = offset within page
776 * page_length = bytes to copy for this page
778 page_base
= (offset
& ~(PAGE_SIZE
-1));
779 page_offset
= offset
& (PAGE_SIZE
-1);
780 page_length
= remain
;
781 if ((page_offset
+ remain
) > PAGE_SIZE
)
782 page_length
= PAGE_SIZE
- page_offset
;
784 ret
= fast_shmem_write(obj_priv
->pages
,
785 page_base
, page_offset
,
786 user_data
, page_length
);
790 remain
-= page_length
;
791 user_data
+= page_length
;
792 offset
+= page_length
;
796 i915_gem_object_put_pages(obj
);
798 mutex_unlock(&dev
->struct_mutex
);
804 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
805 * the memory and maps it using kmap_atomic for copying.
807 * This avoids taking mmap_sem for faulting on the user's address while the
808 * struct_mutex is held.
811 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
812 struct drm_i915_gem_pwrite
*args
,
813 struct drm_file
*file_priv
)
815 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
816 struct mm_struct
*mm
= current
->mm
;
817 struct page
**user_pages
;
819 loff_t offset
, pinned_pages
, i
;
820 loff_t first_data_page
, last_data_page
, num_pages
;
821 int shmem_page_index
, shmem_page_offset
;
822 int data_page_index
, data_page_offset
;
825 uint64_t data_ptr
= args
->data_ptr
;
826 int do_bit17_swizzling
;
830 /* Pin the user pages containing the data. We can't fault while
831 * holding the struct mutex, and all of the pwrite implementations
832 * want to hold it while dereferencing the user data.
834 first_data_page
= data_ptr
/ PAGE_SIZE
;
835 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
836 num_pages
= last_data_page
- first_data_page
+ 1;
838 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
839 if (user_pages
== NULL
)
842 down_read(&mm
->mmap_sem
);
843 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
844 num_pages
, 0, 0, user_pages
, NULL
);
845 up_read(&mm
->mmap_sem
);
846 if (pinned_pages
< num_pages
) {
848 goto fail_put_user_pages
;
851 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
853 mutex_lock(&dev
->struct_mutex
);
855 ret
= i915_gem_object_get_pages_or_evict(obj
);
859 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
863 obj_priv
= to_intel_bo(obj
);
864 offset
= args
->offset
;
868 /* Operation in this page
870 * shmem_page_index = page number within shmem file
871 * shmem_page_offset = offset within page in shmem file
872 * data_page_index = page number in get_user_pages return
873 * data_page_offset = offset with data_page_index page.
874 * page_length = bytes to copy for this page
876 shmem_page_index
= offset
/ PAGE_SIZE
;
877 shmem_page_offset
= offset
& ~PAGE_MASK
;
878 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
879 data_page_offset
= data_ptr
& ~PAGE_MASK
;
881 page_length
= remain
;
882 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
883 page_length
= PAGE_SIZE
- shmem_page_offset
;
884 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
885 page_length
= PAGE_SIZE
- data_page_offset
;
887 if (do_bit17_swizzling
) {
888 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
890 user_pages
[data_page_index
],
895 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
897 user_pages
[data_page_index
],
902 remain
-= page_length
;
903 data_ptr
+= page_length
;
904 offset
+= page_length
;
908 i915_gem_object_put_pages(obj
);
910 mutex_unlock(&dev
->struct_mutex
);
912 for (i
= 0; i
< pinned_pages
; i
++)
913 page_cache_release(user_pages
[i
]);
914 drm_free_large(user_pages
);
920 * Writes data to the object referenced by handle.
922 * On error, the contents of the buffer that were to be modified are undefined.
925 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
926 struct drm_file
*file_priv
)
928 struct drm_i915_gem_pwrite
*args
= data
;
929 struct drm_gem_object
*obj
;
930 struct drm_i915_gem_object
*obj_priv
;
933 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
936 obj_priv
= to_intel_bo(obj
);
938 /* Bounds check destination. */
939 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
944 if (!access_ok(VERIFY_READ
,
945 (char __user
*)(uintptr_t)args
->data_ptr
,
951 /* We can only do the GTT pwrite on untiled buffers, as otherwise
952 * it would end up going through the fenced access, and we'll get
953 * different detiling behavior between reading and writing.
954 * pread/pwrite currently are reading and writing from the CPU
955 * perspective, requiring manual detiling by the client.
957 if (obj_priv
->phys_obj
)
958 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
959 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
960 dev
->gtt_total
!= 0 &&
961 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
962 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
963 if (ret
== -EFAULT
) {
964 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
967 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
968 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
970 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
971 if (ret
== -EFAULT
) {
972 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
979 DRM_INFO("pwrite failed %d\n", ret
);
983 drm_gem_object_unreference_unlocked(obj
);
988 * Called when user space prepares to use an object with the CPU, either
989 * through the mmap ioctl's mapping or a GTT mapping.
992 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
993 struct drm_file
*file_priv
)
995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
996 struct drm_i915_gem_set_domain
*args
= data
;
997 struct drm_gem_object
*obj
;
998 struct drm_i915_gem_object
*obj_priv
;
999 uint32_t read_domains
= args
->read_domains
;
1000 uint32_t write_domain
= args
->write_domain
;
1003 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1006 /* Only handle setting domains to types used by the CPU. */
1007 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1010 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1013 /* Having something in the write domain implies it's in the read
1014 * domain, and only that read domain. Enforce that in the request.
1016 if (write_domain
!= 0 && read_domains
!= write_domain
)
1019 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1022 obj_priv
= to_intel_bo(obj
);
1024 mutex_lock(&dev
->struct_mutex
);
1026 intel_mark_busy(dev
, obj
);
1029 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1030 obj
, obj
->size
, read_domains
, write_domain
);
1032 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1033 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1035 /* Update the LRU on the fence for the CPU access that's
1038 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1039 struct drm_i915_fence_reg
*reg
=
1040 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1041 list_move_tail(®
->lru_list
,
1042 &dev_priv
->mm
.fence_list
);
1045 /* Silently promote "you're not bound, there was nothing to do"
1046 * to success, since the client was just asking us to
1047 * make sure everything was done.
1052 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1056 /* Maintain LRU order of "inactive" objects */
1057 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1058 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1060 drm_gem_object_unreference(obj
);
1061 mutex_unlock(&dev
->struct_mutex
);
1066 * Called when user space has done writes to this buffer
1069 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1070 struct drm_file
*file_priv
)
1072 struct drm_i915_gem_sw_finish
*args
= data
;
1073 struct drm_gem_object
*obj
;
1074 struct drm_i915_gem_object
*obj_priv
;
1077 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1080 mutex_lock(&dev
->struct_mutex
);
1081 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1083 mutex_unlock(&dev
->struct_mutex
);
1088 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1089 __func__
, args
->handle
, obj
, obj
->size
);
1091 obj_priv
= to_intel_bo(obj
);
1093 /* Pinned buffers may be scanout, so flush the cache */
1094 if (obj_priv
->pin_count
)
1095 i915_gem_object_flush_cpu_write_domain(obj
);
1097 drm_gem_object_unreference(obj
);
1098 mutex_unlock(&dev
->struct_mutex
);
1103 * Maps the contents of an object, returning the address it is mapped
1106 * While the mapping holds a reference on the contents of the object, it doesn't
1107 * imply a ref on the object itself.
1110 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1111 struct drm_file
*file_priv
)
1113 struct drm_i915_gem_mmap
*args
= data
;
1114 struct drm_gem_object
*obj
;
1118 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1121 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1125 offset
= args
->offset
;
1127 down_write(¤t
->mm
->mmap_sem
);
1128 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1129 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1131 up_write(¤t
->mm
->mmap_sem
);
1132 drm_gem_object_unreference_unlocked(obj
);
1133 if (IS_ERR((void *)addr
))
1136 args
->addr_ptr
= (uint64_t) addr
;
1142 * i915_gem_fault - fault a page into the GTT
1143 * vma: VMA in question
1146 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1147 * from userspace. The fault handler takes care of binding the object to
1148 * the GTT (if needed), allocating and programming a fence register (again,
1149 * only if needed based on whether the old reg is still valid or the object
1150 * is tiled) and inserting a new PTE into the faulting process.
1152 * Note that the faulting process may involve evicting existing objects
1153 * from the GTT and/or fence registers to make room. So performance may
1154 * suffer if the GTT working set is large or there are few fence registers
1157 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1159 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1160 struct drm_device
*dev
= obj
->dev
;
1161 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1162 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1163 pgoff_t page_offset
;
1166 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1168 /* We don't use vmf->pgoff since that has the fake offset */
1169 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1172 /* Now bind it into the GTT if needed */
1173 mutex_lock(&dev
->struct_mutex
);
1174 if (!obj_priv
->gtt_space
) {
1175 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1179 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1184 /* Need a new fence register? */
1185 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1186 ret
= i915_gem_object_get_fence_reg(obj
);
1191 if (i915_gem_object_is_inactive(obj_priv
))
1192 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1194 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1197 /* Finally, remap it using the new GTT offset */
1198 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1200 mutex_unlock(&dev
->struct_mutex
);
1205 return VM_FAULT_NOPAGE
;
1208 return VM_FAULT_OOM
;
1210 return VM_FAULT_SIGBUS
;
1215 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1216 * @obj: obj in question
1218 * GEM memory mapping works by handing back to userspace a fake mmap offset
1219 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1220 * up the object based on the offset and sets up the various memory mapping
1223 * This routine allocates and attaches a fake offset for @obj.
1226 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1228 struct drm_device
*dev
= obj
->dev
;
1229 struct drm_gem_mm
*mm
= dev
->mm_private
;
1230 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1231 struct drm_map_list
*list
;
1232 struct drm_local_map
*map
;
1235 /* Set the object up for mmap'ing */
1236 list
= &obj
->map_list
;
1237 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1242 map
->type
= _DRM_GEM
;
1243 map
->size
= obj
->size
;
1246 /* Get a DRM GEM mmap offset allocated... */
1247 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1248 obj
->size
/ PAGE_SIZE
, 0, 0);
1249 if (!list
->file_offset_node
) {
1250 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1255 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1256 obj
->size
/ PAGE_SIZE
, 0);
1257 if (!list
->file_offset_node
) {
1262 list
->hash
.key
= list
->file_offset_node
->start
;
1263 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1264 DRM_ERROR("failed to add to map hash\n");
1269 /* By now we should be all set, any drm_mmap request on the offset
1270 * below will get to our mmap & fault handler */
1271 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1276 drm_mm_put_block(list
->file_offset_node
);
1284 * i915_gem_release_mmap - remove physical page mappings
1285 * @obj: obj in question
1287 * Preserve the reservation of the mmapping with the DRM core code, but
1288 * relinquish ownership of the pages back to the system.
1290 * It is vital that we remove the page mapping if we have mapped a tiled
1291 * object through the GTT and then lose the fence register due to
1292 * resource pressure. Similarly if the object has been moved out of the
1293 * aperture, than pages mapped into userspace must be revoked. Removing the
1294 * mapping will then trigger a page fault on the next user access, allowing
1295 * fixup by i915_gem_fault().
1298 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1300 struct drm_device
*dev
= obj
->dev
;
1301 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1303 if (dev
->dev_mapping
)
1304 unmap_mapping_range(dev
->dev_mapping
,
1305 obj_priv
->mmap_offset
, obj
->size
, 1);
1309 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1311 struct drm_device
*dev
= obj
->dev
;
1312 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1313 struct drm_gem_mm
*mm
= dev
->mm_private
;
1314 struct drm_map_list
*list
;
1316 list
= &obj
->map_list
;
1317 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1319 if (list
->file_offset_node
) {
1320 drm_mm_put_block(list
->file_offset_node
);
1321 list
->file_offset_node
= NULL
;
1329 obj_priv
->mmap_offset
= 0;
1333 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1334 * @obj: object to check
1336 * Return the required GTT alignment for an object, taking into account
1337 * potential fence register mapping if needed.
1340 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1342 struct drm_device
*dev
= obj
->dev
;
1343 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1347 * Minimum alignment is 4k (GTT page size), but might be greater
1348 * if a fence register is needed for the object.
1350 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1354 * Previous chips need to be aligned to the size of the smallest
1355 * fence register that can contain the object.
1362 for (i
= start
; i
< obj
->size
; i
<<= 1)
1369 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1371 * @data: GTT mapping ioctl data
1372 * @file_priv: GEM object info
1374 * Simply returns the fake offset to userspace so it can mmap it.
1375 * The mmap call will end up in drm_gem_mmap(), which will set things
1376 * up so we can get faults in the handler above.
1378 * The fault handler will take care of binding the object into the GTT
1379 * (since it may have been evicted to make room for something), allocating
1380 * a fence register, and mapping the appropriate aperture address into
1384 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1385 struct drm_file
*file_priv
)
1387 struct drm_i915_gem_mmap_gtt
*args
= data
;
1388 struct drm_gem_object
*obj
;
1389 struct drm_i915_gem_object
*obj_priv
;
1392 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1395 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1399 mutex_lock(&dev
->struct_mutex
);
1401 obj_priv
= to_intel_bo(obj
);
1403 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1404 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1405 drm_gem_object_unreference(obj
);
1406 mutex_unlock(&dev
->struct_mutex
);
1411 if (!obj_priv
->mmap_offset
) {
1412 ret
= i915_gem_create_mmap_offset(obj
);
1414 drm_gem_object_unreference(obj
);
1415 mutex_unlock(&dev
->struct_mutex
);
1420 args
->offset
= obj_priv
->mmap_offset
;
1423 * Pull it into the GTT so that we have a page list (makes the
1424 * initial fault faster and any subsequent flushing possible).
1426 if (!obj_priv
->agp_mem
) {
1427 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1429 drm_gem_object_unreference(obj
);
1430 mutex_unlock(&dev
->struct_mutex
);
1435 drm_gem_object_unreference(obj
);
1436 mutex_unlock(&dev
->struct_mutex
);
1442 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1444 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1445 int page_count
= obj
->size
/ PAGE_SIZE
;
1448 BUG_ON(obj_priv
->pages_refcount
== 0);
1449 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1451 if (--obj_priv
->pages_refcount
!= 0)
1454 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1455 i915_gem_object_save_bit_17_swizzle(obj
);
1457 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1458 obj_priv
->dirty
= 0;
1460 for (i
= 0; i
< page_count
; i
++) {
1461 if (obj_priv
->dirty
)
1462 set_page_dirty(obj_priv
->pages
[i
]);
1464 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1465 mark_page_accessed(obj_priv
->pages
[i
]);
1467 page_cache_release(obj_priv
->pages
[i
]);
1469 obj_priv
->dirty
= 0;
1471 drm_free_large(obj_priv
->pages
);
1472 obj_priv
->pages
= NULL
;
1476 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
,
1477 struct intel_ring_buffer
*ring
)
1479 struct drm_device
*dev
= obj
->dev
;
1480 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1481 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1482 BUG_ON(ring
== NULL
);
1483 obj_priv
->ring
= ring
;
1485 /* Add a reference if we're newly entering the active list. */
1486 if (!obj_priv
->active
) {
1487 drm_gem_object_reference(obj
);
1488 obj_priv
->active
= 1;
1490 /* Move from whatever list we were on to the tail of execution. */
1491 spin_lock(&dev_priv
->mm
.active_list_lock
);
1492 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1493 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1494 obj_priv
->last_rendering_seqno
= seqno
;
1498 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1500 struct drm_device
*dev
= obj
->dev
;
1501 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1502 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1504 BUG_ON(!obj_priv
->active
);
1505 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1506 obj_priv
->last_rendering_seqno
= 0;
1509 /* Immediately discard the backing storage */
1511 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1513 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1514 struct inode
*inode
;
1516 /* Our goal here is to return as much of the memory as
1517 * is possible back to the system as we are called from OOM.
1518 * To do this we must instruct the shmfs to drop all of its
1519 * backing pages, *now*. Here we mirror the actions taken
1520 * when by shmem_delete_inode() to release the backing store.
1522 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1523 truncate_inode_pages(inode
->i_mapping
, 0);
1524 if (inode
->i_op
->truncate_range
)
1525 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1527 obj_priv
->madv
= __I915_MADV_PURGED
;
1531 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1533 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1537 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1539 struct drm_device
*dev
= obj
->dev
;
1540 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1541 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1543 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1544 if (obj_priv
->pin_count
!= 0)
1545 list_del_init(&obj_priv
->list
);
1547 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1549 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1551 obj_priv
->last_rendering_seqno
= 0;
1552 obj_priv
->ring
= NULL
;
1553 if (obj_priv
->active
) {
1554 obj_priv
->active
= 0;
1555 drm_gem_object_unreference(obj
);
1557 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1561 i915_gem_process_flushing_list(struct drm_device
*dev
,
1562 uint32_t flush_domains
, uint32_t seqno
,
1563 struct intel_ring_buffer
*ring
)
1565 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1566 struct drm_i915_gem_object
*obj_priv
, *next
;
1568 list_for_each_entry_safe(obj_priv
, next
,
1569 &dev_priv
->mm
.gpu_write_list
,
1571 struct drm_gem_object
*obj
= &obj_priv
->base
;
1573 if ((obj
->write_domain
& flush_domains
) ==
1574 obj
->write_domain
&&
1575 obj_priv
->ring
->ring_flag
== ring
->ring_flag
) {
1576 uint32_t old_write_domain
= obj
->write_domain
;
1578 obj
->write_domain
= 0;
1579 list_del_init(&obj_priv
->gpu_write_list
);
1580 i915_gem_object_move_to_active(obj
, seqno
, ring
);
1582 /* update the fence lru list */
1583 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1584 struct drm_i915_fence_reg
*reg
=
1585 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1586 list_move_tail(®
->lru_list
,
1587 &dev_priv
->mm
.fence_list
);
1590 trace_i915_gem_object_change_domain(obj
,
1598 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1599 uint32_t flush_domains
, struct intel_ring_buffer
*ring
)
1601 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1602 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1603 struct drm_i915_gem_request
*request
;
1607 if (file_priv
!= NULL
)
1608 i915_file_priv
= file_priv
->driver_priv
;
1610 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1611 if (request
== NULL
)
1614 seqno
= ring
->add_request(dev
, ring
, file_priv
, flush_domains
);
1616 request
->seqno
= seqno
;
1617 request
->ring
= ring
;
1618 request
->emitted_jiffies
= jiffies
;
1619 was_empty
= list_empty(&ring
->request_list
);
1620 list_add_tail(&request
->list
, &ring
->request_list
);
1622 if (i915_file_priv
) {
1623 list_add_tail(&request
->client_list
,
1624 &i915_file_priv
->mm
.request_list
);
1626 INIT_LIST_HEAD(&request
->client_list
);
1629 /* Associate any objects on the flushing list matching the write
1630 * domain we're flushing with our flush.
1632 if (flush_domains
!= 0)
1633 i915_gem_process_flushing_list(dev
, flush_domains
, seqno
, ring
);
1635 if (!dev_priv
->mm
.suspended
) {
1636 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1638 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1644 * Command execution barrier
1646 * Ensures that all commands in the ring are finished
1647 * before signalling the CPU
1650 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1652 uint32_t flush_domains
= 0;
1654 /* The sampler always gets flushed on i965 (sigh) */
1656 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1658 ring
->flush(dev
, ring
,
1659 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1660 return flush_domains
;
1664 * Moves buffers associated only with the given active seqno from the active
1665 * to inactive list, potentially freeing them.
1668 i915_gem_retire_request(struct drm_device
*dev
,
1669 struct drm_i915_gem_request
*request
)
1671 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1673 trace_i915_gem_request_retire(dev
, request
->seqno
);
1675 /* Move any buffers on the active list that are no longer referenced
1676 * by the ringbuffer to the flushing/inactive lists as appropriate.
1678 spin_lock(&dev_priv
->mm
.active_list_lock
);
1679 while (!list_empty(&request
->ring
->active_list
)) {
1680 struct drm_gem_object
*obj
;
1681 struct drm_i915_gem_object
*obj_priv
;
1683 obj_priv
= list_first_entry(&request
->ring
->active_list
,
1684 struct drm_i915_gem_object
,
1686 obj
= &obj_priv
->base
;
1688 /* If the seqno being retired doesn't match the oldest in the
1689 * list, then the oldest in the list must still be newer than
1692 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1696 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1697 __func__
, request
->seqno
, obj
);
1700 if (obj
->write_domain
!= 0)
1701 i915_gem_object_move_to_flushing(obj
);
1703 /* Take a reference on the object so it won't be
1704 * freed while the spinlock is held. The list
1705 * protection for this spinlock is safe when breaking
1706 * the lock like this since the next thing we do
1707 * is just get the head of the list again.
1709 drm_gem_object_reference(obj
);
1710 i915_gem_object_move_to_inactive(obj
);
1711 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1712 drm_gem_object_unreference(obj
);
1713 spin_lock(&dev_priv
->mm
.active_list_lock
);
1717 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1721 * Returns true if seq1 is later than seq2.
1724 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1726 return (int32_t)(seq1
- seq2
) >= 0;
1730 i915_get_gem_seqno(struct drm_device
*dev
,
1731 struct intel_ring_buffer
*ring
)
1733 return ring
->get_gem_seqno(dev
, ring
);
1737 * This function clears the request list as sequence numbers are passed.
1740 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1741 struct intel_ring_buffer
*ring
)
1743 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1746 if (!ring
->status_page
.page_addr
1747 || list_empty(&ring
->request_list
))
1750 seqno
= i915_get_gem_seqno(dev
, ring
);
1752 while (!list_empty(&ring
->request_list
)) {
1753 struct drm_i915_gem_request
*request
;
1754 uint32_t retiring_seqno
;
1756 request
= list_first_entry(&ring
->request_list
,
1757 struct drm_i915_gem_request
,
1759 retiring_seqno
= request
->seqno
;
1761 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1762 atomic_read(&dev_priv
->mm
.wedged
)) {
1763 i915_gem_retire_request(dev
, request
);
1765 list_del(&request
->list
);
1766 list_del(&request
->client_list
);
1772 if (unlikely (dev_priv
->trace_irq_seqno
&&
1773 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1775 ring
->user_irq_put(dev
, ring
);
1776 dev_priv
->trace_irq_seqno
= 0;
1781 i915_gem_retire_requests(struct drm_device
*dev
)
1783 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1785 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1786 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1788 /* We must be careful that during unbind() we do not
1789 * accidentally infinitely recurse into retire requests.
1791 * retire -> free -> unbind -> wait -> retire_ring
1793 list_for_each_entry_safe(obj_priv
, tmp
,
1794 &dev_priv
->mm
.deferred_free_list
,
1796 i915_gem_free_object_tail(&obj_priv
->base
);
1799 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1801 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1805 i915_gem_retire_work_handler(struct work_struct
*work
)
1807 drm_i915_private_t
*dev_priv
;
1808 struct drm_device
*dev
;
1810 dev_priv
= container_of(work
, drm_i915_private_t
,
1811 mm
.retire_work
.work
);
1812 dev
= dev_priv
->dev
;
1814 mutex_lock(&dev
->struct_mutex
);
1815 i915_gem_retire_requests(dev
);
1817 if (!dev_priv
->mm
.suspended
&&
1818 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1820 !list_empty(&dev_priv
->bsd_ring
.request_list
))))
1821 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1822 mutex_unlock(&dev
->struct_mutex
);
1826 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1827 int interruptible
, struct intel_ring_buffer
*ring
)
1829 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1835 if (atomic_read(&dev_priv
->mm
.wedged
))
1838 if (!i915_seqno_passed(ring
->get_gem_seqno(dev
, ring
), seqno
)) {
1839 if (HAS_PCH_SPLIT(dev
))
1840 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1842 ier
= I915_READ(IER
);
1844 DRM_ERROR("something (likely vbetool) disabled "
1845 "interrupts, re-enabling\n");
1846 i915_driver_irq_preinstall(dev
);
1847 i915_driver_irq_postinstall(dev
);
1850 trace_i915_gem_request_wait_begin(dev
, seqno
);
1852 ring
->waiting_gem_seqno
= seqno
;
1853 ring
->user_irq_get(dev
, ring
);
1855 ret
= wait_event_interruptible(ring
->irq_queue
,
1857 ring
->get_gem_seqno(dev
, ring
), seqno
)
1858 || atomic_read(&dev_priv
->mm
.wedged
));
1860 wait_event(ring
->irq_queue
,
1862 ring
->get_gem_seqno(dev
, ring
), seqno
)
1863 || atomic_read(&dev_priv
->mm
.wedged
));
1865 ring
->user_irq_put(dev
, ring
);
1866 ring
->waiting_gem_seqno
= 0;
1868 trace_i915_gem_request_wait_end(dev
, seqno
);
1870 if (atomic_read(&dev_priv
->mm
.wedged
))
1873 if (ret
&& ret
!= -ERESTARTSYS
)
1874 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1875 __func__
, ret
, seqno
, ring
->get_gem_seqno(dev
, ring
));
1877 /* Directly dispatch request retiring. While we have the work queue
1878 * to handle this, the waiter on a request often wants an associated
1879 * buffer to have made it to the inactive list, and we would need
1880 * a separate wait queue to handle that.
1883 i915_gem_retire_requests_ring(dev
, ring
);
1889 * Waits for a sequence number to be signaled, and cleans up the
1890 * request and object lists appropriately for that event.
1893 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1894 struct intel_ring_buffer
*ring
)
1896 return i915_do_wait_request(dev
, seqno
, 1, ring
);
1900 i915_gem_flush(struct drm_device
*dev
,
1901 uint32_t invalidate_domains
,
1902 uint32_t flush_domains
)
1904 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1905 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1906 drm_agp_chipset_flush(dev
);
1907 dev_priv
->render_ring
.flush(dev
, &dev_priv
->render_ring
,
1912 dev_priv
->bsd_ring
.flush(dev
, &dev_priv
->bsd_ring
,
1918 * Ensures that all rendering to the object has completed and the object is
1919 * safe to unbind from the GTT or access from the CPU.
1922 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1924 struct drm_device
*dev
= obj
->dev
;
1925 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1928 /* This function only exists to support waiting for existing rendering,
1929 * not for emitting required flushes.
1931 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1933 /* If there is rendering queued on the buffer being evicted, wait for
1936 if (obj_priv
->active
) {
1938 DRM_INFO("%s: object %p wait for seqno %08x\n",
1939 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1941 ret
= i915_wait_request(dev
,
1942 obj_priv
->last_rendering_seqno
, obj_priv
->ring
);
1951 * Unbinds an object from the GTT aperture.
1954 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1956 struct drm_device
*dev
= obj
->dev
;
1957 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1958 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1962 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1963 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1965 if (obj_priv
->gtt_space
== NULL
)
1968 if (obj_priv
->pin_count
!= 0) {
1969 DRM_ERROR("Attempting to unbind pinned buffer\n");
1973 /* blow away mappings if mapped through GTT */
1974 i915_gem_release_mmap(obj
);
1976 /* Move the object to the CPU domain to ensure that
1977 * any possible CPU writes while it's not in the GTT
1978 * are flushed when we go to remap it. This will
1979 * also ensure that all pending GPU writes are finished
1982 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1983 if (ret
== -ERESTARTSYS
)
1985 /* Continue on if we fail due to EIO, the GPU is hung so we
1986 * should be safe and we need to cleanup or else we might
1987 * cause memory corruption through use-after-free.
1990 /* release the fence reg _after_ flushing */
1991 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
1992 i915_gem_clear_fence_reg(obj
);
1994 if (obj_priv
->agp_mem
!= NULL
) {
1995 drm_unbind_agp(obj_priv
->agp_mem
);
1996 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
1997 obj_priv
->agp_mem
= NULL
;
2000 i915_gem_object_put_pages(obj
);
2001 BUG_ON(obj_priv
->pages_refcount
);
2003 if (obj_priv
->gtt_space
) {
2004 atomic_dec(&dev
->gtt_count
);
2005 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2007 drm_mm_put_block(obj_priv
->gtt_space
);
2008 obj_priv
->gtt_space
= NULL
;
2011 /* Remove ourselves from the LRU list if present. */
2012 spin_lock(&dev_priv
->mm
.active_list_lock
);
2013 if (!list_empty(&obj_priv
->list
))
2014 list_del_init(&obj_priv
->list
);
2015 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2017 if (i915_gem_object_is_purgeable(obj_priv
))
2018 i915_gem_object_truncate(obj
);
2020 trace_i915_gem_object_unbind(obj
);
2026 i915_gpu_idle(struct drm_device
*dev
)
2028 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2030 uint32_t seqno1
, seqno2
;
2033 spin_lock(&dev_priv
->mm
.active_list_lock
);
2034 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2035 list_empty(&dev_priv
->render_ring
.active_list
) &&
2037 list_empty(&dev_priv
->bsd_ring
.active_list
)));
2038 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2043 /* Flush everything onto the inactive list. */
2044 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2045 seqno1
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
,
2046 &dev_priv
->render_ring
);
2049 ret
= i915_wait_request(dev
, seqno1
, &dev_priv
->render_ring
);
2052 seqno2
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
,
2053 &dev_priv
->bsd_ring
);
2057 ret
= i915_wait_request(dev
, seqno2
, &dev_priv
->bsd_ring
);
2067 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2070 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2072 struct address_space
*mapping
;
2073 struct inode
*inode
;
2076 BUG_ON(obj_priv
->pages_refcount
2077 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2079 if (obj_priv
->pages_refcount
++ != 0)
2082 /* Get the list of pages out of our struct file. They'll be pinned
2083 * at this point until we release them.
2085 page_count
= obj
->size
/ PAGE_SIZE
;
2086 BUG_ON(obj_priv
->pages
!= NULL
);
2087 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2088 if (obj_priv
->pages
== NULL
) {
2089 obj_priv
->pages_refcount
--;
2093 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2094 mapping
= inode
->i_mapping
;
2095 for (i
= 0; i
< page_count
; i
++) {
2096 page
= read_cache_page_gfp(mapping
, i
,
2104 obj_priv
->pages
[i
] = page
;
2107 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2108 i915_gem_object_do_bit_17_swizzle(obj
);
2114 page_cache_release(obj_priv
->pages
[i
]);
2116 drm_free_large(obj_priv
->pages
);
2117 obj_priv
->pages
= NULL
;
2118 obj_priv
->pages_refcount
--;
2119 return PTR_ERR(page
);
2122 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2124 struct drm_gem_object
*obj
= reg
->obj
;
2125 struct drm_device
*dev
= obj
->dev
;
2126 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2127 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2128 int regnum
= obj_priv
->fence_reg
;
2131 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2133 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2134 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2135 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2137 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2138 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2139 val
|= I965_FENCE_REG_VALID
;
2141 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2144 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2146 struct drm_gem_object
*obj
= reg
->obj
;
2147 struct drm_device
*dev
= obj
->dev
;
2148 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2149 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2150 int regnum
= obj_priv
->fence_reg
;
2153 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2155 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2156 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2157 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2158 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2159 val
|= I965_FENCE_REG_VALID
;
2161 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2164 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2166 struct drm_gem_object
*obj
= reg
->obj
;
2167 struct drm_device
*dev
= obj
->dev
;
2168 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2169 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2170 int regnum
= obj_priv
->fence_reg
;
2172 uint32_t fence_reg
, val
;
2175 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2176 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2177 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2178 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2182 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2183 HAS_128_BYTE_Y_TILING(dev
))
2188 /* Note: pitch better be a power of two tile widths */
2189 pitch_val
= obj_priv
->stride
/ tile_width
;
2190 pitch_val
= ffs(pitch_val
) - 1;
2192 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2193 HAS_128_BYTE_Y_TILING(dev
))
2194 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2196 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2198 val
= obj_priv
->gtt_offset
;
2199 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2200 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2201 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2202 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2203 val
|= I830_FENCE_REG_VALID
;
2206 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2208 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2209 I915_WRITE(fence_reg
, val
);
2212 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2214 struct drm_gem_object
*obj
= reg
->obj
;
2215 struct drm_device
*dev
= obj
->dev
;
2216 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2217 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2218 int regnum
= obj_priv
->fence_reg
;
2221 uint32_t fence_size_bits
;
2223 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2224 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2225 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2226 __func__
, obj_priv
->gtt_offset
);
2230 pitch_val
= obj_priv
->stride
/ 128;
2231 pitch_val
= ffs(pitch_val
) - 1;
2232 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2234 val
= obj_priv
->gtt_offset
;
2235 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2236 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2237 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2238 WARN_ON(fence_size_bits
& ~0x00000f00);
2239 val
|= fence_size_bits
;
2240 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2241 val
|= I830_FENCE_REG_VALID
;
2243 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2246 static int i915_find_fence_reg(struct drm_device
*dev
)
2248 struct drm_i915_fence_reg
*reg
= NULL
;
2249 struct drm_i915_gem_object
*obj_priv
= NULL
;
2250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2251 struct drm_gem_object
*obj
= NULL
;
2254 /* First try to find a free reg */
2256 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2257 reg
= &dev_priv
->fence_regs
[i
];
2261 obj_priv
= to_intel_bo(reg
->obj
);
2262 if (!obj_priv
->pin_count
)
2269 /* None available, try to steal one or wait for a user to finish */
2270 i
= I915_FENCE_REG_NONE
;
2271 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2274 obj_priv
= to_intel_bo(obj
);
2276 if (obj_priv
->pin_count
)
2280 i
= obj_priv
->fence_reg
;
2284 BUG_ON(i
== I915_FENCE_REG_NONE
);
2286 /* We only have a reference on obj from the active list. put_fence_reg
2287 * might drop that one, causing a use-after-free in it. So hold a
2288 * private reference to obj like the other callers of put_fence_reg
2289 * (set_tiling ioctl) do. */
2290 drm_gem_object_reference(obj
);
2291 ret
= i915_gem_object_put_fence_reg(obj
);
2292 drm_gem_object_unreference(obj
);
2300 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2301 * @obj: object to map through a fence reg
2303 * When mapping objects through the GTT, userspace wants to be able to write
2304 * to them without having to worry about swizzling if the object is tiled.
2306 * This function walks the fence regs looking for a free one for @obj,
2307 * stealing one if it can't find any.
2309 * It then sets up the reg based on the object's properties: address, pitch
2310 * and tiling format.
2313 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2315 struct drm_device
*dev
= obj
->dev
;
2316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2317 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2318 struct drm_i915_fence_reg
*reg
= NULL
;
2321 /* Just update our place in the LRU if our fence is getting used. */
2322 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2323 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2324 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2328 switch (obj_priv
->tiling_mode
) {
2329 case I915_TILING_NONE
:
2330 WARN(1, "allocating a fence for non-tiled object?\n");
2333 if (!obj_priv
->stride
)
2335 WARN((obj_priv
->stride
& (512 - 1)),
2336 "object 0x%08x is X tiled but has non-512B pitch\n",
2337 obj_priv
->gtt_offset
);
2340 if (!obj_priv
->stride
)
2342 WARN((obj_priv
->stride
& (128 - 1)),
2343 "object 0x%08x is Y tiled but has non-128B pitch\n",
2344 obj_priv
->gtt_offset
);
2348 ret
= i915_find_fence_reg(dev
);
2352 obj_priv
->fence_reg
= ret
;
2353 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2354 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2358 switch (INTEL_INFO(dev
)->gen
) {
2360 sandybridge_write_fence_reg(reg
);
2364 i965_write_fence_reg(reg
);
2367 i915_write_fence_reg(reg
);
2370 i830_write_fence_reg(reg
);
2374 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2375 obj_priv
->tiling_mode
);
2381 * i915_gem_clear_fence_reg - clear out fence register info
2382 * @obj: object to clear
2384 * Zeroes out the fence register itself and clears out the associated
2385 * data structures in dev_priv and obj_priv.
2388 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2390 struct drm_device
*dev
= obj
->dev
;
2391 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2392 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2393 struct drm_i915_fence_reg
*reg
=
2394 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2397 switch (INTEL_INFO(dev
)->gen
) {
2399 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2400 (obj_priv
->fence_reg
* 8), 0);
2404 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2407 if (obj_priv
->fence_reg
>= 8)
2408 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2411 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2413 I915_WRITE(fence_reg
, 0);
2418 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2419 list_del_init(®
->lru_list
);
2423 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2424 * to the buffer to finish, and then resets the fence register.
2425 * @obj: tiled object holding a fence register.
2427 * Zeroes out the fence register itself and clears out the associated
2428 * data structures in dev_priv and obj_priv.
2431 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2433 struct drm_device
*dev
= obj
->dev
;
2434 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2436 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2439 /* If we've changed tiling, GTT-mappings of the object
2440 * need to re-fault to ensure that the correct fence register
2441 * setup is in place.
2443 i915_gem_release_mmap(obj
);
2445 /* On the i915, GPU access to tiled buffers is via a fence,
2446 * therefore we must wait for any outstanding access to complete
2447 * before clearing the fence.
2449 if (!IS_I965G(dev
)) {
2452 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2456 ret
= i915_gem_object_wait_rendering(obj
);
2461 i915_gem_object_flush_gtt_write_domain(obj
);
2462 i915_gem_clear_fence_reg (obj
);
2468 * Finds free space in the GTT aperture and binds the object there.
2471 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2473 struct drm_device
*dev
= obj
->dev
;
2474 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2475 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2476 struct drm_mm_node
*free_space
;
2477 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2480 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2481 DRM_ERROR("Attempting to bind a purgeable object\n");
2486 alignment
= i915_gem_get_gtt_alignment(obj
);
2487 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2488 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2492 /* If the object is bigger than the entire aperture, reject it early
2493 * before evicting everything in a vain attempt to find space.
2495 if (obj
->size
> dev
->gtt_total
) {
2496 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2501 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2502 obj
->size
, alignment
, 0);
2503 if (free_space
!= NULL
) {
2504 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2506 if (obj_priv
->gtt_space
!= NULL
)
2507 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2509 if (obj_priv
->gtt_space
== NULL
) {
2510 /* If the gtt is empty and we're still having trouble
2511 * fitting our object in, we're out of memory.
2514 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2516 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2524 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2525 obj
->size
, obj_priv
->gtt_offset
);
2527 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2529 drm_mm_put_block(obj_priv
->gtt_space
);
2530 obj_priv
->gtt_space
= NULL
;
2532 if (ret
== -ENOMEM
) {
2533 /* first try to clear up some space from the GTT */
2534 ret
= i915_gem_evict_something(dev
, obj
->size
,
2537 /* now try to shrink everyone else */
2552 /* Create an AGP memory structure pointing at our pages, and bind it
2555 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2557 obj
->size
>> PAGE_SHIFT
,
2558 obj_priv
->gtt_offset
,
2559 obj_priv
->agp_type
);
2560 if (obj_priv
->agp_mem
== NULL
) {
2561 i915_gem_object_put_pages(obj
);
2562 drm_mm_put_block(obj_priv
->gtt_space
);
2563 obj_priv
->gtt_space
= NULL
;
2565 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2571 atomic_inc(&dev
->gtt_count
);
2572 atomic_add(obj
->size
, &dev
->gtt_memory
);
2574 /* keep track of bounds object by adding it to the inactive list */
2575 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
2577 /* Assert that the object is not currently in any GPU domain. As it
2578 * wasn't in the GTT, there shouldn't be any way it could have been in
2581 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2582 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2584 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2590 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2592 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2594 /* If we don't have a page list set up, then we're not pinned
2595 * to GPU, and we can ignore the cache flush because it'll happen
2596 * again at bind time.
2598 if (obj_priv
->pages
== NULL
)
2601 trace_i915_gem_object_clflush(obj
);
2603 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2606 /** Flushes any GPU write domain for the object if it's dirty. */
2608 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2610 struct drm_device
*dev
= obj
->dev
;
2611 uint32_t old_write_domain
;
2612 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2614 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2617 /* Queue the GPU write cache flushing we need. */
2618 old_write_domain
= obj
->write_domain
;
2619 i915_gem_flush(dev
, 0, obj
->write_domain
);
2620 if (i915_add_request(dev
, NULL
, obj
->write_domain
, obj_priv
->ring
) == 0)
2623 trace_i915_gem_object_change_domain(obj
,
2629 /** Flushes the GTT write domain for the object if it's dirty. */
2631 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2633 uint32_t old_write_domain
;
2635 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2638 /* No actual flushing is required for the GTT write domain. Writes
2639 * to it immediately go to main memory as far as we know, so there's
2640 * no chipset flush. It also doesn't land in render cache.
2642 old_write_domain
= obj
->write_domain
;
2643 obj
->write_domain
= 0;
2645 trace_i915_gem_object_change_domain(obj
,
2650 /** Flushes the CPU write domain for the object if it's dirty. */
2652 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2654 struct drm_device
*dev
= obj
->dev
;
2655 uint32_t old_write_domain
;
2657 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2660 i915_gem_clflush_object(obj
);
2661 drm_agp_chipset_flush(dev
);
2662 old_write_domain
= obj
->write_domain
;
2663 obj
->write_domain
= 0;
2665 trace_i915_gem_object_change_domain(obj
,
2671 i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
)
2675 switch (obj
->write_domain
) {
2676 case I915_GEM_DOMAIN_GTT
:
2677 i915_gem_object_flush_gtt_write_domain(obj
);
2679 case I915_GEM_DOMAIN_CPU
:
2680 i915_gem_object_flush_cpu_write_domain(obj
);
2683 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2691 * Moves a single object to the GTT read, and possibly write domain.
2693 * This function returns when the move is complete, including waiting on
2697 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2699 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2700 uint32_t old_write_domain
, old_read_domains
;
2703 /* Not valid to be called on unbound objects. */
2704 if (obj_priv
->gtt_space
== NULL
)
2707 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2711 /* Wait on any GPU rendering and flushing to occur. */
2712 ret
= i915_gem_object_wait_rendering(obj
);
2716 old_write_domain
= obj
->write_domain
;
2717 old_read_domains
= obj
->read_domains
;
2719 /* If we're writing through the GTT domain, then CPU and GPU caches
2720 * will need to be invalidated at next use.
2723 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2725 i915_gem_object_flush_cpu_write_domain(obj
);
2727 /* It should now be out of any other write domains, and we can update
2728 * the domain values for our changes.
2730 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2731 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2733 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2734 obj_priv
->dirty
= 1;
2737 trace_i915_gem_object_change_domain(obj
,
2745 * Prepare buffer for display plane. Use uninterruptible for possible flush
2746 * wait, as in modesetting process we're not supposed to be interrupted.
2749 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
)
2751 struct drm_device
*dev
= obj
->dev
;
2752 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2753 uint32_t old_write_domain
, old_read_domains
;
2756 /* Not valid to be called on unbound objects. */
2757 if (obj_priv
->gtt_space
== NULL
)
2760 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2764 /* Wait on any GPU rendering and flushing to occur. */
2765 if (obj_priv
->active
) {
2767 DRM_INFO("%s: object %p wait for seqno %08x\n",
2768 __func__
, obj
, obj_priv
->last_rendering_seqno
);
2770 ret
= i915_do_wait_request(dev
,
2771 obj_priv
->last_rendering_seqno
,
2778 i915_gem_object_flush_cpu_write_domain(obj
);
2780 old_write_domain
= obj
->write_domain
;
2781 old_read_domains
= obj
->read_domains
;
2783 /* It should now be out of any other write domains, and we can update
2784 * the domain values for our changes.
2786 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2787 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2788 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2789 obj_priv
->dirty
= 1;
2791 trace_i915_gem_object_change_domain(obj
,
2799 * Moves a single object to the CPU read, and possibly write domain.
2801 * This function returns when the move is complete, including waiting on
2805 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2807 uint32_t old_write_domain
, old_read_domains
;
2810 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2814 /* Wait on any GPU rendering and flushing to occur. */
2815 ret
= i915_gem_object_wait_rendering(obj
);
2819 i915_gem_object_flush_gtt_write_domain(obj
);
2821 /* If we have a partially-valid cache of the object in the CPU,
2822 * finish invalidating it and free the per-page flags.
2824 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2826 old_write_domain
= obj
->write_domain
;
2827 old_read_domains
= obj
->read_domains
;
2829 /* Flush the CPU cache if it's still invalid. */
2830 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2831 i915_gem_clflush_object(obj
);
2833 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2836 /* It should now be out of any other write domains, and we can update
2837 * the domain values for our changes.
2839 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2841 /* If we're writing through the CPU, then the GPU read domains will
2842 * need to be invalidated at next use.
2845 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2846 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2849 trace_i915_gem_object_change_domain(obj
,
2857 * Set the next domain for the specified object. This
2858 * may not actually perform the necessary flushing/invaliding though,
2859 * as that may want to be batched with other set_domain operations
2861 * This is (we hope) the only really tricky part of gem. The goal
2862 * is fairly simple -- track which caches hold bits of the object
2863 * and make sure they remain coherent. A few concrete examples may
2864 * help to explain how it works. For shorthand, we use the notation
2865 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2866 * a pair of read and write domain masks.
2868 * Case 1: the batch buffer
2874 * 5. Unmapped from GTT
2877 * Let's take these a step at a time
2880 * Pages allocated from the kernel may still have
2881 * cache contents, so we set them to (CPU, CPU) always.
2882 * 2. Written by CPU (using pwrite)
2883 * The pwrite function calls set_domain (CPU, CPU) and
2884 * this function does nothing (as nothing changes)
2886 * This function asserts that the object is not
2887 * currently in any GPU-based read or write domains
2889 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2890 * As write_domain is zero, this function adds in the
2891 * current read domains (CPU+COMMAND, 0).
2892 * flush_domains is set to CPU.
2893 * invalidate_domains is set to COMMAND
2894 * clflush is run to get data out of the CPU caches
2895 * then i915_dev_set_domain calls i915_gem_flush to
2896 * emit an MI_FLUSH and drm_agp_chipset_flush
2897 * 5. Unmapped from GTT
2898 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2899 * flush_domains and invalidate_domains end up both zero
2900 * so no flushing/invalidating happens
2904 * Case 2: The shared render buffer
2908 * 3. Read/written by GPU
2909 * 4. set_domain to (CPU,CPU)
2910 * 5. Read/written by CPU
2911 * 6. Read/written by GPU
2914 * Same as last example, (CPU, CPU)
2916 * Nothing changes (assertions find that it is not in the GPU)
2917 * 3. Read/written by GPU
2918 * execbuffer calls set_domain (RENDER, RENDER)
2919 * flush_domains gets CPU
2920 * invalidate_domains gets GPU
2922 * MI_FLUSH and drm_agp_chipset_flush
2923 * 4. set_domain (CPU, CPU)
2924 * flush_domains gets GPU
2925 * invalidate_domains gets CPU
2926 * wait_rendering (obj) to make sure all drawing is complete.
2927 * This will include an MI_FLUSH to get the data from GPU
2929 * clflush (obj) to invalidate the CPU cache
2930 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2931 * 5. Read/written by CPU
2932 * cache lines are loaded and dirtied
2933 * 6. Read written by GPU
2934 * Same as last GPU access
2936 * Case 3: The constant buffer
2941 * 4. Updated (written) by CPU again
2950 * flush_domains = CPU
2951 * invalidate_domains = RENDER
2954 * drm_agp_chipset_flush
2955 * 4. Updated (written) by CPU again
2957 * flush_domains = 0 (no previous write domain)
2958 * invalidate_domains = 0 (no new read domains)
2961 * flush_domains = CPU
2962 * invalidate_domains = RENDER
2965 * drm_agp_chipset_flush
2968 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
2970 struct drm_device
*dev
= obj
->dev
;
2971 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2972 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2973 uint32_t invalidate_domains
= 0;
2974 uint32_t flush_domains
= 0;
2975 uint32_t old_read_domains
;
2977 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
2978 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
2980 intel_mark_busy(dev
, obj
);
2983 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2985 obj
->read_domains
, obj
->pending_read_domains
,
2986 obj
->write_domain
, obj
->pending_write_domain
);
2989 * If the object isn't moving to a new write domain,
2990 * let the object stay in multiple read domains
2992 if (obj
->pending_write_domain
== 0)
2993 obj
->pending_read_domains
|= obj
->read_domains
;
2995 obj_priv
->dirty
= 1;
2998 * Flush the current write domain if
2999 * the new read domains don't match. Invalidate
3000 * any read domains which differ from the old
3003 if (obj
->write_domain
&&
3004 obj
->write_domain
!= obj
->pending_read_domains
) {
3005 flush_domains
|= obj
->write_domain
;
3006 invalidate_domains
|=
3007 obj
->pending_read_domains
& ~obj
->write_domain
;
3010 * Invalidate any read caches which may have
3011 * stale data. That is, any new read domains.
3013 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3014 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3016 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3017 __func__
, flush_domains
, invalidate_domains
);
3019 i915_gem_clflush_object(obj
);
3022 old_read_domains
= obj
->read_domains
;
3024 /* The actual obj->write_domain will be updated with
3025 * pending_write_domain after we emit the accumulated flush for all
3026 * of our domain changes in execbuffers (which clears objects'
3027 * write_domains). So if we have a current write domain that we
3028 * aren't changing, set pending_write_domain to that.
3030 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3031 obj
->pending_write_domain
= obj
->write_domain
;
3032 obj
->read_domains
= obj
->pending_read_domains
;
3034 if (flush_domains
& I915_GEM_GPU_DOMAINS
) {
3035 if (obj_priv
->ring
== &dev_priv
->render_ring
)
3036 dev_priv
->flush_rings
|= FLUSH_RENDER_RING
;
3037 else if (obj_priv
->ring
== &dev_priv
->bsd_ring
)
3038 dev_priv
->flush_rings
|= FLUSH_BSD_RING
;
3041 dev
->invalidate_domains
|= invalidate_domains
;
3042 dev
->flush_domains
|= flush_domains
;
3044 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3046 obj
->read_domains
, obj
->write_domain
,
3047 dev
->invalidate_domains
, dev
->flush_domains
);
3050 trace_i915_gem_object_change_domain(obj
,
3056 * Moves the object from a partially CPU read to a full one.
3058 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3059 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3062 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3064 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3066 if (!obj_priv
->page_cpu_valid
)
3069 /* If we're partially in the CPU read domain, finish moving it in.
3071 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3074 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3075 if (obj_priv
->page_cpu_valid
[i
])
3077 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3081 /* Free the page_cpu_valid mappings which are now stale, whether
3082 * or not we've got I915_GEM_DOMAIN_CPU.
3084 kfree(obj_priv
->page_cpu_valid
);
3085 obj_priv
->page_cpu_valid
= NULL
;
3089 * Set the CPU read domain on a range of the object.
3091 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3092 * not entirely valid. The page_cpu_valid member of the object flags which
3093 * pages have been flushed, and will be respected by
3094 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3095 * of the whole object.
3097 * This function returns when the move is complete, including waiting on
3101 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3102 uint64_t offset
, uint64_t size
)
3104 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3105 uint32_t old_read_domains
;
3108 if (offset
== 0 && size
== obj
->size
)
3109 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3111 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3115 /* Wait on any GPU rendering and flushing to occur. */
3116 ret
= i915_gem_object_wait_rendering(obj
);
3119 i915_gem_object_flush_gtt_write_domain(obj
);
3121 /* If we're already fully in the CPU read domain, we're done. */
3122 if (obj_priv
->page_cpu_valid
== NULL
&&
3123 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3126 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3127 * newly adding I915_GEM_DOMAIN_CPU
3129 if (obj_priv
->page_cpu_valid
== NULL
) {
3130 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3132 if (obj_priv
->page_cpu_valid
== NULL
)
3134 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3135 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3137 /* Flush the cache on any pages that are still invalid from the CPU's
3140 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3142 if (obj_priv
->page_cpu_valid
[i
])
3145 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3147 obj_priv
->page_cpu_valid
[i
] = 1;
3150 /* It should now be out of any other write domains, and we can update
3151 * the domain values for our changes.
3153 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3155 old_read_domains
= obj
->read_domains
;
3156 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3158 trace_i915_gem_object_change_domain(obj
,
3166 * Pin an object to the GTT and evaluate the relocations landing in it.
3169 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3170 struct drm_file
*file_priv
,
3171 struct drm_i915_gem_exec_object2
*entry
,
3172 struct drm_i915_gem_relocation_entry
*relocs
)
3174 struct drm_device
*dev
= obj
->dev
;
3175 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3176 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3178 void __iomem
*reloc_page
;
3181 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3182 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3184 /* Check fence reg constraints and rebind if necessary */
3186 !i915_gem_object_fence_offset_ok(obj
,
3187 obj_priv
->tiling_mode
)) {
3188 ret
= i915_gem_object_unbind(obj
);
3193 /* Choose the GTT offset for our buffer and put it there. */
3194 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3199 * Pre-965 chips need a fence register set up in order to
3200 * properly handle blits to/from tiled surfaces.
3203 ret
= i915_gem_object_get_fence_reg(obj
);
3205 i915_gem_object_unpin(obj
);
3210 entry
->offset
= obj_priv
->gtt_offset
;
3212 /* Apply the relocations, using the GTT aperture to avoid cache
3213 * flushing requirements.
3215 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3216 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3217 struct drm_gem_object
*target_obj
;
3218 struct drm_i915_gem_object
*target_obj_priv
;
3219 uint32_t reloc_val
, reloc_offset
;
3220 uint32_t __iomem
*reloc_entry
;
3222 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3223 reloc
->target_handle
);
3224 if (target_obj
== NULL
) {
3225 i915_gem_object_unpin(obj
);
3228 target_obj_priv
= to_intel_bo(target_obj
);
3231 DRM_INFO("%s: obj %p offset %08x target %d "
3232 "read %08x write %08x gtt %08x "
3233 "presumed %08x delta %08x\n",
3236 (int) reloc
->offset
,
3237 (int) reloc
->target_handle
,
3238 (int) reloc
->read_domains
,
3239 (int) reloc
->write_domain
,
3240 (int) target_obj_priv
->gtt_offset
,
3241 (int) reloc
->presumed_offset
,
3245 /* The target buffer should have appeared before us in the
3246 * exec_object list, so it should have a GTT space bound by now.
3248 if (target_obj_priv
->gtt_space
== NULL
) {
3249 DRM_ERROR("No GTT space found for object %d\n",
3250 reloc
->target_handle
);
3251 drm_gem_object_unreference(target_obj
);
3252 i915_gem_object_unpin(obj
);
3256 /* Validate that the target is in a valid r/w GPU domain */
3257 if (reloc
->write_domain
& (reloc
->write_domain
- 1)) {
3258 DRM_ERROR("reloc with multiple write domains: "
3259 "obj %p target %d offset %d "
3260 "read %08x write %08x",
3261 obj
, reloc
->target_handle
,
3262 (int) reloc
->offset
,
3263 reloc
->read_domains
,
3264 reloc
->write_domain
);
3265 drm_gem_object_unreference(target_obj
);
3266 i915_gem_object_unpin(obj
);
3269 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3270 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3271 DRM_ERROR("reloc with read/write CPU domains: "
3272 "obj %p target %d offset %d "
3273 "read %08x write %08x",
3274 obj
, reloc
->target_handle
,
3275 (int) reloc
->offset
,
3276 reloc
->read_domains
,
3277 reloc
->write_domain
);
3278 drm_gem_object_unreference(target_obj
);
3279 i915_gem_object_unpin(obj
);
3282 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3283 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3284 DRM_ERROR("Write domain conflict: "
3285 "obj %p target %d offset %d "
3286 "new %08x old %08x\n",
3287 obj
, reloc
->target_handle
,
3288 (int) reloc
->offset
,
3289 reloc
->write_domain
,
3290 target_obj
->pending_write_domain
);
3291 drm_gem_object_unreference(target_obj
);
3292 i915_gem_object_unpin(obj
);
3296 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3297 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3299 /* If the relocation already has the right value in it, no
3300 * more work needs to be done.
3302 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3303 drm_gem_object_unreference(target_obj
);
3307 /* Check that the relocation address is valid... */
3308 if (reloc
->offset
> obj
->size
- 4) {
3309 DRM_ERROR("Relocation beyond object bounds: "
3310 "obj %p target %d offset %d size %d.\n",
3311 obj
, reloc
->target_handle
,
3312 (int) reloc
->offset
, (int) obj
->size
);
3313 drm_gem_object_unreference(target_obj
);
3314 i915_gem_object_unpin(obj
);
3317 if (reloc
->offset
& 3) {
3318 DRM_ERROR("Relocation not 4-byte aligned: "
3319 "obj %p target %d offset %d.\n",
3320 obj
, reloc
->target_handle
,
3321 (int) reloc
->offset
);
3322 drm_gem_object_unreference(target_obj
);
3323 i915_gem_object_unpin(obj
);
3327 /* and points to somewhere within the target object. */
3328 if (reloc
->delta
>= target_obj
->size
) {
3329 DRM_ERROR("Relocation beyond target object bounds: "
3330 "obj %p target %d delta %d size %d.\n",
3331 obj
, reloc
->target_handle
,
3332 (int) reloc
->delta
, (int) target_obj
->size
);
3333 drm_gem_object_unreference(target_obj
);
3334 i915_gem_object_unpin(obj
);
3338 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3340 drm_gem_object_unreference(target_obj
);
3341 i915_gem_object_unpin(obj
);
3345 /* Map the page containing the relocation we're going to
3348 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3349 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3353 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3354 (reloc_offset
& (PAGE_SIZE
- 1)));
3355 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3358 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3359 obj
, (unsigned int) reloc
->offset
,
3360 readl(reloc_entry
), reloc_val
);
3362 writel(reloc_val
, reloc_entry
);
3363 io_mapping_unmap_atomic(reloc_page
, KM_USER0
);
3365 /* The updated presumed offset for this entry will be
3366 * copied back out to the user.
3368 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3370 drm_gem_object_unreference(target_obj
);
3375 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3380 /* Throttle our rendering by waiting until the ring has completed our requests
3381 * emitted over 20 msec ago.
3383 * Note that if we were to use the current jiffies each time around the loop,
3384 * we wouldn't escape the function with any frames outstanding if the time to
3385 * render a frame was over 20ms.
3387 * This should get us reasonable parallelism between CPU and GPU but also
3388 * relatively low latency when blocking on a particular request to finish.
3391 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3393 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3395 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3397 mutex_lock(&dev
->struct_mutex
);
3398 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3399 struct drm_i915_gem_request
*request
;
3401 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3402 struct drm_i915_gem_request
,
3405 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3408 ret
= i915_wait_request(dev
, request
->seqno
, request
->ring
);
3412 mutex_unlock(&dev
->struct_mutex
);
3418 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3419 uint32_t buffer_count
,
3420 struct drm_i915_gem_relocation_entry
**relocs
)
3422 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3426 for (i
= 0; i
< buffer_count
; i
++) {
3427 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3429 reloc_count
+= exec_list
[i
].relocation_count
;
3432 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3433 if (*relocs
== NULL
) {
3434 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3438 for (i
= 0; i
< buffer_count
; i
++) {
3439 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3441 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3443 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3445 exec_list
[i
].relocation_count
*
3448 drm_free_large(*relocs
);
3453 reloc_index
+= exec_list
[i
].relocation_count
;
3460 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3461 uint32_t buffer_count
,
3462 struct drm_i915_gem_relocation_entry
*relocs
)
3464 uint32_t reloc_count
= 0, i
;
3470 for (i
= 0; i
< buffer_count
; i
++) {
3471 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3474 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3476 unwritten
= copy_to_user(user_relocs
,
3477 &relocs
[reloc_count
],
3478 exec_list
[i
].relocation_count
*
3486 reloc_count
+= exec_list
[i
].relocation_count
;
3490 drm_free_large(relocs
);
3496 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3497 uint64_t exec_offset
)
3499 uint32_t exec_start
, exec_len
;
3501 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3502 exec_len
= (uint32_t) exec
->batch_len
;
3504 if ((exec_start
| exec_len
) & 0x7)
3514 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3515 struct drm_gem_object
**object_list
,
3518 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3519 struct drm_i915_gem_object
*obj_priv
;
3524 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3525 &wait
, TASK_INTERRUPTIBLE
);
3526 for (i
= 0; i
< count
; i
++) {
3527 obj_priv
= to_intel_bo(object_list
[i
]);
3528 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3534 if (!signal_pending(current
)) {
3535 mutex_unlock(&dev
->struct_mutex
);
3537 mutex_lock(&dev
->struct_mutex
);
3543 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3550 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3551 struct drm_file
*file_priv
,
3552 struct drm_i915_gem_execbuffer2
*args
,
3553 struct drm_i915_gem_exec_object2
*exec_list
)
3555 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3556 struct drm_gem_object
**object_list
= NULL
;
3557 struct drm_gem_object
*batch_obj
;
3558 struct drm_i915_gem_object
*obj_priv
;
3559 struct drm_clip_rect
*cliprects
= NULL
;
3560 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3561 int ret
= 0, ret2
, i
, pinned
= 0;
3562 uint64_t exec_offset
;
3563 uint32_t seqno
, flush_domains
, reloc_index
;
3564 int pin_tries
, flips
;
3566 struct intel_ring_buffer
*ring
= NULL
;
3569 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3570 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3572 if (args
->flags
& I915_EXEC_BSD
) {
3573 if (!HAS_BSD(dev
)) {
3574 DRM_ERROR("execbuf with wrong flag\n");
3577 ring
= &dev_priv
->bsd_ring
;
3579 ring
= &dev_priv
->render_ring
;
3582 if (args
->buffer_count
< 1) {
3583 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3586 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3587 if (object_list
== NULL
) {
3588 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3589 args
->buffer_count
);
3594 if (args
->num_cliprects
!= 0) {
3595 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3597 if (cliprects
== NULL
) {
3602 ret
= copy_from_user(cliprects
,
3603 (struct drm_clip_rect __user
*)
3604 (uintptr_t) args
->cliprects_ptr
,
3605 sizeof(*cliprects
) * args
->num_cliprects
);
3607 DRM_ERROR("copy %d cliprects failed: %d\n",
3608 args
->num_cliprects
, ret
);
3614 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3619 mutex_lock(&dev
->struct_mutex
);
3621 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3623 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3624 mutex_unlock(&dev
->struct_mutex
);
3629 if (dev_priv
->mm
.suspended
) {
3630 mutex_unlock(&dev
->struct_mutex
);
3635 /* Look up object handles */
3637 for (i
= 0; i
< args
->buffer_count
; i
++) {
3638 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3639 exec_list
[i
].handle
);
3640 if (object_list
[i
] == NULL
) {
3641 DRM_ERROR("Invalid object handle %d at index %d\n",
3642 exec_list
[i
].handle
, i
);
3643 /* prevent error path from reading uninitialized data */
3644 args
->buffer_count
= i
+ 1;
3649 obj_priv
= to_intel_bo(object_list
[i
]);
3650 if (obj_priv
->in_execbuffer
) {
3651 DRM_ERROR("Object %p appears more than once in object list\n",
3653 /* prevent error path from reading uninitialized data */
3654 args
->buffer_count
= i
+ 1;
3658 obj_priv
->in_execbuffer
= true;
3659 flips
+= atomic_read(&obj_priv
->pending_flip
);
3663 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3664 args
->buffer_count
);
3669 /* Pin and relocate */
3670 for (pin_tries
= 0; ; pin_tries
++) {
3674 for (i
= 0; i
< args
->buffer_count
; i
++) {
3675 object_list
[i
]->pending_read_domains
= 0;
3676 object_list
[i
]->pending_write_domain
= 0;
3677 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3680 &relocs
[reloc_index
]);
3684 reloc_index
+= exec_list
[i
].relocation_count
;
3690 /* error other than GTT full, or we've already tried again */
3691 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3692 if (ret
!= -ERESTARTSYS
) {
3693 unsigned long long total_size
= 0;
3695 for (i
= 0; i
< args
->buffer_count
; i
++) {
3696 obj_priv
= to_intel_bo(object_list
[i
]);
3698 total_size
+= object_list
[i
]->size
;
3700 exec_list
[i
].flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3701 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3703 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3704 pinned
+1, args
->buffer_count
,
3705 total_size
, num_fences
,
3707 DRM_ERROR("%d objects [%d pinned], "
3708 "%d object bytes [%d pinned], "
3709 "%d/%d gtt bytes\n",
3710 atomic_read(&dev
->object_count
),
3711 atomic_read(&dev
->pin_count
),
3712 atomic_read(&dev
->object_memory
),
3713 atomic_read(&dev
->pin_memory
),
3714 atomic_read(&dev
->gtt_memory
),
3720 /* unpin all of our buffers */
3721 for (i
= 0; i
< pinned
; i
++)
3722 i915_gem_object_unpin(object_list
[i
]);
3725 /* evict everyone we can from the aperture */
3726 ret
= i915_gem_evict_everything(dev
);
3727 if (ret
&& ret
!= -ENOSPC
)
3731 /* Set the pending read domains for the batch buffer to COMMAND */
3732 batch_obj
= object_list
[args
->buffer_count
-1];
3733 if (batch_obj
->pending_write_domain
) {
3734 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3738 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3740 /* Sanity check the batch buffer, prior to moving objects */
3741 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3742 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3744 DRM_ERROR("execbuf with invalid offset/length\n");
3748 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3750 /* Zero the global flush/invalidate flags. These
3751 * will be modified as new domains are computed
3754 dev
->invalidate_domains
= 0;
3755 dev
->flush_domains
= 0;
3756 dev_priv
->flush_rings
= 0;
3758 for (i
= 0; i
< args
->buffer_count
; i
++) {
3759 struct drm_gem_object
*obj
= object_list
[i
];
3761 /* Compute new gpu domains and update invalidate/flush */
3762 i915_gem_object_set_to_gpu_domain(obj
);
3765 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3767 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3769 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3771 dev
->invalidate_domains
,
3772 dev
->flush_domains
);
3775 dev
->invalidate_domains
,
3776 dev
->flush_domains
);
3777 if (dev_priv
->flush_rings
& FLUSH_RENDER_RING
)
3778 (void)i915_add_request(dev
, file_priv
,
3780 &dev_priv
->render_ring
);
3781 if (dev_priv
->flush_rings
& FLUSH_BSD_RING
)
3782 (void)i915_add_request(dev
, file_priv
,
3784 &dev_priv
->bsd_ring
);
3787 for (i
= 0; i
< args
->buffer_count
; i
++) {
3788 struct drm_gem_object
*obj
= object_list
[i
];
3789 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3790 uint32_t old_write_domain
= obj
->write_domain
;
3792 obj
->write_domain
= obj
->pending_write_domain
;
3793 if (obj
->write_domain
)
3794 list_move_tail(&obj_priv
->gpu_write_list
,
3795 &dev_priv
->mm
.gpu_write_list
);
3797 list_del_init(&obj_priv
->gpu_write_list
);
3799 trace_i915_gem_object_change_domain(obj
,
3804 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3807 for (i
= 0; i
< args
->buffer_count
; i
++) {
3808 i915_gem_object_check_coherency(object_list
[i
],
3809 exec_list
[i
].handle
);
3814 i915_gem_dump_object(batch_obj
,
3820 /* Exec the batchbuffer */
3821 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3822 cliprects
, exec_offset
);
3824 DRM_ERROR("dispatch failed %d\n", ret
);
3829 * Ensure that the commands in the batch buffer are
3830 * finished before the interrupt fires
3832 flush_domains
= i915_retire_commands(dev
, ring
);
3834 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3837 * Get a seqno representing the execution of the current buffer,
3838 * which we can wait on. We would like to mitigate these interrupts,
3839 * likely by only creating seqnos occasionally (so that we have
3840 * *some* interrupts representing completion of buffers that we can
3841 * wait on when trying to clear up gtt space).
3843 seqno
= i915_add_request(dev
, file_priv
, flush_domains
, ring
);
3845 for (i
= 0; i
< args
->buffer_count
; i
++) {
3846 struct drm_gem_object
*obj
= object_list
[i
];
3847 obj_priv
= to_intel_bo(obj
);
3849 i915_gem_object_move_to_active(obj
, seqno
, ring
);
3851 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3855 i915_dump_lru(dev
, __func__
);
3858 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3861 for (i
= 0; i
< pinned
; i
++)
3862 i915_gem_object_unpin(object_list
[i
]);
3864 for (i
= 0; i
< args
->buffer_count
; i
++) {
3865 if (object_list
[i
]) {
3866 obj_priv
= to_intel_bo(object_list
[i
]);
3867 obj_priv
->in_execbuffer
= false;
3869 drm_gem_object_unreference(object_list
[i
]);
3872 mutex_unlock(&dev
->struct_mutex
);
3875 /* Copy the updated relocations out regardless of current error
3876 * state. Failure to update the relocs would mean that the next
3877 * time userland calls execbuf, it would do so with presumed offset
3878 * state that didn't match the actual object state.
3880 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3883 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3889 drm_free_large(object_list
);
3896 * Legacy execbuffer just creates an exec2 list from the original exec object
3897 * list array and passes it to the real function.
3900 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3901 struct drm_file
*file_priv
)
3903 struct drm_i915_gem_execbuffer
*args
= data
;
3904 struct drm_i915_gem_execbuffer2 exec2
;
3905 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3906 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3910 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3911 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3914 if (args
->buffer_count
< 1) {
3915 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3919 /* Copy in the exec list from userland */
3920 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3921 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3922 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3923 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3924 args
->buffer_count
);
3925 drm_free_large(exec_list
);
3926 drm_free_large(exec2_list
);
3929 ret
= copy_from_user(exec_list
,
3930 (struct drm_i915_relocation_entry __user
*)
3931 (uintptr_t) args
->buffers_ptr
,
3932 sizeof(*exec_list
) * args
->buffer_count
);
3934 DRM_ERROR("copy %d exec entries failed %d\n",
3935 args
->buffer_count
, ret
);
3936 drm_free_large(exec_list
);
3937 drm_free_large(exec2_list
);
3941 for (i
= 0; i
< args
->buffer_count
; i
++) {
3942 exec2_list
[i
].handle
= exec_list
[i
].handle
;
3943 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
3944 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
3945 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
3946 exec2_list
[i
].offset
= exec_list
[i
].offset
;
3948 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
3950 exec2_list
[i
].flags
= 0;
3953 exec2
.buffers_ptr
= args
->buffers_ptr
;
3954 exec2
.buffer_count
= args
->buffer_count
;
3955 exec2
.batch_start_offset
= args
->batch_start_offset
;
3956 exec2
.batch_len
= args
->batch_len
;
3957 exec2
.DR1
= args
->DR1
;
3958 exec2
.DR4
= args
->DR4
;
3959 exec2
.num_cliprects
= args
->num_cliprects
;
3960 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
3961 exec2
.flags
= I915_EXEC_RENDER
;
3963 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
3965 /* Copy the new buffer offsets back to the user's exec list. */
3966 for (i
= 0; i
< args
->buffer_count
; i
++)
3967 exec_list
[i
].offset
= exec2_list
[i
].offset
;
3968 /* ... and back out to userspace */
3969 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3970 (uintptr_t) args
->buffers_ptr
,
3972 sizeof(*exec_list
) * args
->buffer_count
);
3975 DRM_ERROR("failed to copy %d exec entries "
3976 "back to user (%d)\n",
3977 args
->buffer_count
, ret
);
3981 drm_free_large(exec_list
);
3982 drm_free_large(exec2_list
);
3987 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3988 struct drm_file
*file_priv
)
3990 struct drm_i915_gem_execbuffer2
*args
= data
;
3991 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3995 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3996 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3999 if (args
->buffer_count
< 1) {
4000 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4004 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4005 if (exec2_list
== NULL
) {
4006 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4007 args
->buffer_count
);
4010 ret
= copy_from_user(exec2_list
,
4011 (struct drm_i915_relocation_entry __user
*)
4012 (uintptr_t) args
->buffers_ptr
,
4013 sizeof(*exec2_list
) * args
->buffer_count
);
4015 DRM_ERROR("copy %d exec entries failed %d\n",
4016 args
->buffer_count
, ret
);
4017 drm_free_large(exec2_list
);
4021 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4023 /* Copy the new buffer offsets back to the user's exec list. */
4024 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4025 (uintptr_t) args
->buffers_ptr
,
4027 sizeof(*exec2_list
) * args
->buffer_count
);
4030 DRM_ERROR("failed to copy %d exec entries "
4031 "back to user (%d)\n",
4032 args
->buffer_count
, ret
);
4036 drm_free_large(exec2_list
);
4041 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4043 struct drm_device
*dev
= obj
->dev
;
4044 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4047 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4049 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4051 if (obj_priv
->gtt_space
!= NULL
) {
4053 alignment
= i915_gem_get_gtt_alignment(obj
);
4054 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4055 WARN(obj_priv
->pin_count
,
4056 "bo is already pinned with incorrect alignment:"
4057 " offset=%x, req.alignment=%x\n",
4058 obj_priv
->gtt_offset
, alignment
);
4059 ret
= i915_gem_object_unbind(obj
);
4065 if (obj_priv
->gtt_space
== NULL
) {
4066 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4071 obj_priv
->pin_count
++;
4073 /* If the object is not active and not pending a flush,
4074 * remove it from the inactive list
4076 if (obj_priv
->pin_count
== 1) {
4077 atomic_inc(&dev
->pin_count
);
4078 atomic_add(obj
->size
, &dev
->pin_memory
);
4079 if (!obj_priv
->active
&&
4080 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4081 list_del_init(&obj_priv
->list
);
4083 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4089 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4091 struct drm_device
*dev
= obj
->dev
;
4092 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4093 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4095 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4096 obj_priv
->pin_count
--;
4097 BUG_ON(obj_priv
->pin_count
< 0);
4098 BUG_ON(obj_priv
->gtt_space
== NULL
);
4100 /* If the object is no longer pinned, and is
4101 * neither active nor being flushed, then stick it on
4104 if (obj_priv
->pin_count
== 0) {
4105 if (!obj_priv
->active
&&
4106 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4107 list_move_tail(&obj_priv
->list
,
4108 &dev_priv
->mm
.inactive_list
);
4109 atomic_dec(&dev
->pin_count
);
4110 atomic_sub(obj
->size
, &dev
->pin_memory
);
4112 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4116 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4117 struct drm_file
*file_priv
)
4119 struct drm_i915_gem_pin
*args
= data
;
4120 struct drm_gem_object
*obj
;
4121 struct drm_i915_gem_object
*obj_priv
;
4124 mutex_lock(&dev
->struct_mutex
);
4126 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4128 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4130 mutex_unlock(&dev
->struct_mutex
);
4133 obj_priv
= to_intel_bo(obj
);
4135 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4136 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4137 drm_gem_object_unreference(obj
);
4138 mutex_unlock(&dev
->struct_mutex
);
4142 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4143 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4145 drm_gem_object_unreference(obj
);
4146 mutex_unlock(&dev
->struct_mutex
);
4150 obj_priv
->user_pin_count
++;
4151 obj_priv
->pin_filp
= file_priv
;
4152 if (obj_priv
->user_pin_count
== 1) {
4153 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4155 drm_gem_object_unreference(obj
);
4156 mutex_unlock(&dev
->struct_mutex
);
4161 /* XXX - flush the CPU caches for pinned objects
4162 * as the X server doesn't manage domains yet
4164 i915_gem_object_flush_cpu_write_domain(obj
);
4165 args
->offset
= obj_priv
->gtt_offset
;
4166 drm_gem_object_unreference(obj
);
4167 mutex_unlock(&dev
->struct_mutex
);
4173 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4174 struct drm_file
*file_priv
)
4176 struct drm_i915_gem_pin
*args
= data
;
4177 struct drm_gem_object
*obj
;
4178 struct drm_i915_gem_object
*obj_priv
;
4180 mutex_lock(&dev
->struct_mutex
);
4182 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4184 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4186 mutex_unlock(&dev
->struct_mutex
);
4190 obj_priv
= to_intel_bo(obj
);
4191 if (obj_priv
->pin_filp
!= file_priv
) {
4192 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4194 drm_gem_object_unreference(obj
);
4195 mutex_unlock(&dev
->struct_mutex
);
4198 obj_priv
->user_pin_count
--;
4199 if (obj_priv
->user_pin_count
== 0) {
4200 obj_priv
->pin_filp
= NULL
;
4201 i915_gem_object_unpin(obj
);
4204 drm_gem_object_unreference(obj
);
4205 mutex_unlock(&dev
->struct_mutex
);
4210 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4211 struct drm_file
*file_priv
)
4213 struct drm_i915_gem_busy
*args
= data
;
4214 struct drm_gem_object
*obj
;
4215 struct drm_i915_gem_object
*obj_priv
;
4217 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4219 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4224 mutex_lock(&dev
->struct_mutex
);
4226 /* Count all active objects as busy, even if they are currently not used
4227 * by the gpu. Users of this interface expect objects to eventually
4228 * become non-busy without any further actions, therefore emit any
4229 * necessary flushes here.
4231 obj_priv
= to_intel_bo(obj
);
4232 args
->busy
= obj_priv
->active
;
4234 /* Unconditionally flush objects, even when the gpu still uses this
4235 * object. Userspace calling this function indicates that it wants to
4236 * use this buffer rather sooner than later, so issuing the required
4237 * flush earlier is beneficial.
4239 if (obj
->write_domain
) {
4240 i915_gem_flush(dev
, 0, obj
->write_domain
);
4241 (void)i915_add_request(dev
, file_priv
, obj
->write_domain
, obj_priv
->ring
);
4244 /* Update the active list for the hardware's current position.
4245 * Otherwise this only updates on a delayed timer or when irqs
4246 * are actually unmasked, and our working set ends up being
4247 * larger than required.
4249 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4251 args
->busy
= obj_priv
->active
;
4254 drm_gem_object_unreference(obj
);
4255 mutex_unlock(&dev
->struct_mutex
);
4260 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4261 struct drm_file
*file_priv
)
4263 return i915_gem_ring_throttle(dev
, file_priv
);
4267 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4268 struct drm_file
*file_priv
)
4270 struct drm_i915_gem_madvise
*args
= data
;
4271 struct drm_gem_object
*obj
;
4272 struct drm_i915_gem_object
*obj_priv
;
4274 switch (args
->madv
) {
4275 case I915_MADV_DONTNEED
:
4276 case I915_MADV_WILLNEED
:
4282 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4284 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4289 mutex_lock(&dev
->struct_mutex
);
4290 obj_priv
= to_intel_bo(obj
);
4292 if (obj_priv
->pin_count
) {
4293 drm_gem_object_unreference(obj
);
4294 mutex_unlock(&dev
->struct_mutex
);
4296 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4300 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4301 obj_priv
->madv
= args
->madv
;
4303 /* if the object is no longer bound, discard its backing storage */
4304 if (i915_gem_object_is_purgeable(obj_priv
) &&
4305 obj_priv
->gtt_space
== NULL
)
4306 i915_gem_object_truncate(obj
);
4308 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4310 drm_gem_object_unreference(obj
);
4311 mutex_unlock(&dev
->struct_mutex
);
4316 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4319 struct drm_i915_gem_object
*obj
;
4321 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4325 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4330 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4331 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4333 obj
->agp_type
= AGP_USER_MEMORY
;
4334 obj
->base
.driver_private
= NULL
;
4335 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4336 INIT_LIST_HEAD(&obj
->list
);
4337 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4338 obj
->madv
= I915_MADV_WILLNEED
;
4340 trace_i915_gem_object_create(&obj
->base
);
4345 int i915_gem_init_object(struct drm_gem_object
*obj
)
4352 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4354 struct drm_device
*dev
= obj
->dev
;
4355 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4356 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4359 ret
= i915_gem_object_unbind(obj
);
4360 if (ret
== -ERESTARTSYS
) {
4361 list_move(&obj_priv
->list
,
4362 &dev_priv
->mm
.deferred_free_list
);
4366 if (obj_priv
->mmap_offset
)
4367 i915_gem_free_mmap_offset(obj
);
4369 drm_gem_object_release(obj
);
4371 kfree(obj_priv
->page_cpu_valid
);
4372 kfree(obj_priv
->bit_17
);
4376 void i915_gem_free_object(struct drm_gem_object
*obj
)
4378 struct drm_device
*dev
= obj
->dev
;
4379 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4381 trace_i915_gem_object_destroy(obj
);
4383 while (obj_priv
->pin_count
> 0)
4384 i915_gem_object_unpin(obj
);
4386 if (obj_priv
->phys_obj
)
4387 i915_gem_detach_phys_object(dev
, obj
);
4389 i915_gem_free_object_tail(obj
);
4393 i915_gem_idle(struct drm_device
*dev
)
4395 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4398 mutex_lock(&dev
->struct_mutex
);
4400 if (dev_priv
->mm
.suspended
||
4401 (dev_priv
->render_ring
.gem_object
== NULL
) ||
4403 dev_priv
->bsd_ring
.gem_object
== NULL
)) {
4404 mutex_unlock(&dev
->struct_mutex
);
4408 ret
= i915_gpu_idle(dev
);
4410 mutex_unlock(&dev
->struct_mutex
);
4414 /* Under UMS, be paranoid and evict. */
4415 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4416 ret
= i915_gem_evict_inactive(dev
);
4418 mutex_unlock(&dev
->struct_mutex
);
4423 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4424 * We need to replace this with a semaphore, or something.
4425 * And not confound mm.suspended!
4427 dev_priv
->mm
.suspended
= 1;
4428 del_timer(&dev_priv
->hangcheck_timer
);
4430 i915_kernel_lost_context(dev
);
4431 i915_gem_cleanup_ringbuffer(dev
);
4433 mutex_unlock(&dev
->struct_mutex
);
4435 /* Cancel the retire work handler, which should be idle now. */
4436 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4442 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4443 * over cache flushing.
4446 i915_gem_init_pipe_control(struct drm_device
*dev
)
4448 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4449 struct drm_gem_object
*obj
;
4450 struct drm_i915_gem_object
*obj_priv
;
4453 obj
= i915_gem_alloc_object(dev
, 4096);
4455 DRM_ERROR("Failed to allocate seqno page\n");
4459 obj_priv
= to_intel_bo(obj
);
4460 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4462 ret
= i915_gem_object_pin(obj
, 4096);
4466 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4467 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4468 if (dev_priv
->seqno_page
== NULL
)
4471 dev_priv
->seqno_obj
= obj
;
4472 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4477 i915_gem_object_unpin(obj
);
4479 drm_gem_object_unreference(obj
);
4486 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4488 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4489 struct drm_gem_object
*obj
;
4490 struct drm_i915_gem_object
*obj_priv
;
4492 obj
= dev_priv
->seqno_obj
;
4493 obj_priv
= to_intel_bo(obj
);
4494 kunmap(obj_priv
->pages
[0]);
4495 i915_gem_object_unpin(obj
);
4496 drm_gem_object_unreference(obj
);
4497 dev_priv
->seqno_obj
= NULL
;
4499 dev_priv
->seqno_page
= NULL
;
4503 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4505 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4508 dev_priv
->render_ring
= render_ring
;
4510 if (!I915_NEED_GFX_HWS(dev
)) {
4511 dev_priv
->render_ring
.status_page
.page_addr
4512 = dev_priv
->status_page_dmah
->vaddr
;
4513 memset(dev_priv
->render_ring
.status_page
.page_addr
,
4517 if (HAS_PIPE_CONTROL(dev
)) {
4518 ret
= i915_gem_init_pipe_control(dev
);
4523 ret
= intel_init_ring_buffer(dev
, &dev_priv
->render_ring
);
4525 goto cleanup_pipe_control
;
4528 dev_priv
->bsd_ring
= bsd_ring
;
4529 ret
= intel_init_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4531 goto cleanup_render_ring
;
4534 dev_priv
->next_seqno
= 1;
4538 cleanup_render_ring
:
4539 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4540 cleanup_pipe_control
:
4541 if (HAS_PIPE_CONTROL(dev
))
4542 i915_gem_cleanup_pipe_control(dev
);
4547 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4549 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4551 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4553 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4554 if (HAS_PIPE_CONTROL(dev
))
4555 i915_gem_cleanup_pipe_control(dev
);
4559 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4560 struct drm_file
*file_priv
)
4562 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4565 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4568 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4569 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4570 atomic_set(&dev_priv
->mm
.wedged
, 0);
4573 mutex_lock(&dev
->struct_mutex
);
4574 dev_priv
->mm
.suspended
= 0;
4576 ret
= i915_gem_init_ringbuffer(dev
);
4578 mutex_unlock(&dev
->struct_mutex
);
4582 spin_lock(&dev_priv
->mm
.active_list_lock
);
4583 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4584 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.active_list
));
4585 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4587 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4588 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4589 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4590 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.request_list
));
4591 mutex_unlock(&dev
->struct_mutex
);
4593 ret
= drm_irq_install(dev
);
4595 goto cleanup_ringbuffer
;
4600 mutex_lock(&dev
->struct_mutex
);
4601 i915_gem_cleanup_ringbuffer(dev
);
4602 dev_priv
->mm
.suspended
= 1;
4603 mutex_unlock(&dev
->struct_mutex
);
4609 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4610 struct drm_file
*file_priv
)
4612 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4615 drm_irq_uninstall(dev
);
4616 return i915_gem_idle(dev
);
4620 i915_gem_lastclose(struct drm_device
*dev
)
4624 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4627 ret
= i915_gem_idle(dev
);
4629 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4633 i915_gem_load(struct drm_device
*dev
)
4636 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4638 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4639 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4640 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4641 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4642 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4643 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4644 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4645 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4647 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4648 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4650 for (i
= 0; i
< 16; i
++)
4651 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4652 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4653 i915_gem_retire_work_handler
);
4654 spin_lock(&shrink_list_lock
);
4655 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4656 spin_unlock(&shrink_list_lock
);
4658 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4660 u32 tmp
= I915_READ(MI_ARB_STATE
);
4661 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4662 /* arb state is a masked write, so set bit + bit in mask */
4663 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4664 I915_WRITE(MI_ARB_STATE
, tmp
);
4668 /* Old X drivers will take 0-2 for front, back, depth buffers */
4669 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4670 dev_priv
->fence_reg_start
= 3;
4672 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4673 dev_priv
->num_fence_regs
= 16;
4675 dev_priv
->num_fence_regs
= 8;
4677 /* Initialize fence registers to zero */
4678 if (IS_I965G(dev
)) {
4679 for (i
= 0; i
< 16; i
++)
4680 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4682 for (i
= 0; i
< 8; i
++)
4683 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4684 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4685 for (i
= 0; i
< 8; i
++)
4686 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4688 i915_gem_detect_bit_6_swizzle(dev
);
4689 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4693 * Create a physically contiguous memory object for this object
4694 * e.g. for cursor + overlay regs
4696 int i915_gem_init_phys_object(struct drm_device
*dev
,
4697 int id
, int size
, int align
)
4699 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4700 struct drm_i915_gem_phys_object
*phys_obj
;
4703 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4706 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4712 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4713 if (!phys_obj
->handle
) {
4718 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4721 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4729 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4731 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4732 struct drm_i915_gem_phys_object
*phys_obj
;
4734 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4737 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4738 if (phys_obj
->cur_obj
) {
4739 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4743 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4745 drm_pci_free(dev
, phys_obj
->handle
);
4747 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4750 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4754 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4755 i915_gem_free_phys_object(dev
, i
);
4758 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4759 struct drm_gem_object
*obj
)
4761 struct drm_i915_gem_object
*obj_priv
;
4766 obj_priv
= to_intel_bo(obj
);
4767 if (!obj_priv
->phys_obj
)
4770 ret
= i915_gem_object_get_pages(obj
, 0);
4774 page_count
= obj
->size
/ PAGE_SIZE
;
4776 for (i
= 0; i
< page_count
; i
++) {
4777 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4778 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4780 memcpy(dst
, src
, PAGE_SIZE
);
4781 kunmap_atomic(dst
, KM_USER0
);
4783 drm_clflush_pages(obj_priv
->pages
, page_count
);
4784 drm_agp_chipset_flush(dev
);
4786 i915_gem_object_put_pages(obj
);
4788 obj_priv
->phys_obj
->cur_obj
= NULL
;
4789 obj_priv
->phys_obj
= NULL
;
4793 i915_gem_attach_phys_object(struct drm_device
*dev
,
4794 struct drm_gem_object
*obj
,
4798 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4799 struct drm_i915_gem_object
*obj_priv
;
4804 if (id
> I915_MAX_PHYS_OBJECT
)
4807 obj_priv
= to_intel_bo(obj
);
4809 if (obj_priv
->phys_obj
) {
4810 if (obj_priv
->phys_obj
->id
== id
)
4812 i915_gem_detach_phys_object(dev
, obj
);
4815 /* create a new object */
4816 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4817 ret
= i915_gem_init_phys_object(dev
, id
,
4820 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4825 /* bind to the object */
4826 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4827 obj_priv
->phys_obj
->cur_obj
= obj
;
4829 ret
= i915_gem_object_get_pages(obj
, 0);
4831 DRM_ERROR("failed to get page list\n");
4835 page_count
= obj
->size
/ PAGE_SIZE
;
4837 for (i
= 0; i
< page_count
; i
++) {
4838 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4839 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4841 memcpy(dst
, src
, PAGE_SIZE
);
4842 kunmap_atomic(src
, KM_USER0
);
4845 i915_gem_object_put_pages(obj
);
4853 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4854 struct drm_i915_gem_pwrite
*args
,
4855 struct drm_file
*file_priv
)
4857 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4860 char __user
*user_data
;
4862 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4863 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4865 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4866 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4870 drm_agp_chipset_flush(dev
);
4874 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
4876 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
4878 /* Clean up our request list when the client is going away, so that
4879 * later retire_requests won't dereference our soon-to-be-gone
4882 mutex_lock(&dev
->struct_mutex
);
4883 while (!list_empty(&i915_file_priv
->mm
.request_list
))
4884 list_del_init(i915_file_priv
->mm
.request_list
.next
);
4885 mutex_unlock(&dev
->struct_mutex
);
4889 i915_gpu_is_active(struct drm_device
*dev
)
4891 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4894 spin_lock(&dev_priv
->mm
.active_list_lock
);
4895 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4896 list_empty(&dev_priv
->render_ring
.active_list
);
4898 lists_empty
&= list_empty(&dev_priv
->bsd_ring
.active_list
);
4899 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4901 return !lists_empty
;
4905 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4907 drm_i915_private_t
*dev_priv
, *next_dev
;
4908 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4910 int would_deadlock
= 1;
4912 /* "fast-path" to count number of available objects */
4913 if (nr_to_scan
== 0) {
4914 spin_lock(&shrink_list_lock
);
4915 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4916 struct drm_device
*dev
= dev_priv
->dev
;
4918 if (mutex_trylock(&dev
->struct_mutex
)) {
4919 list_for_each_entry(obj_priv
,
4920 &dev_priv
->mm
.inactive_list
,
4923 mutex_unlock(&dev
->struct_mutex
);
4926 spin_unlock(&shrink_list_lock
);
4928 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4931 spin_lock(&shrink_list_lock
);
4934 /* first scan for clean buffers */
4935 list_for_each_entry_safe(dev_priv
, next_dev
,
4936 &shrink_list
, mm
.shrink_list
) {
4937 struct drm_device
*dev
= dev_priv
->dev
;
4939 if (! mutex_trylock(&dev
->struct_mutex
))
4942 spin_unlock(&shrink_list_lock
);
4943 i915_gem_retire_requests(dev
);
4945 list_for_each_entry_safe(obj_priv
, next_obj
,
4946 &dev_priv
->mm
.inactive_list
,
4948 if (i915_gem_object_is_purgeable(obj_priv
)) {
4949 i915_gem_object_unbind(&obj_priv
->base
);
4950 if (--nr_to_scan
<= 0)
4955 spin_lock(&shrink_list_lock
);
4956 mutex_unlock(&dev
->struct_mutex
);
4960 if (nr_to_scan
<= 0)
4964 /* second pass, evict/count anything still on the inactive list */
4965 list_for_each_entry_safe(dev_priv
, next_dev
,
4966 &shrink_list
, mm
.shrink_list
) {
4967 struct drm_device
*dev
= dev_priv
->dev
;
4969 if (! mutex_trylock(&dev
->struct_mutex
))
4972 spin_unlock(&shrink_list_lock
);
4974 list_for_each_entry_safe(obj_priv
, next_obj
,
4975 &dev_priv
->mm
.inactive_list
,
4977 if (nr_to_scan
> 0) {
4978 i915_gem_object_unbind(&obj_priv
->base
);
4984 spin_lock(&shrink_list_lock
);
4985 mutex_unlock(&dev
->struct_mutex
);
4994 * We are desperate for pages, so as a last resort, wait
4995 * for the GPU to finish and discard whatever we can.
4996 * This has a dramatic impact to reduce the number of
4997 * OOM-killer events whilst running the GPU aggressively.
4999 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5000 struct drm_device
*dev
= dev_priv
->dev
;
5002 if (!mutex_trylock(&dev
->struct_mutex
))
5005 spin_unlock(&shrink_list_lock
);
5007 if (i915_gpu_is_active(dev
)) {
5012 spin_lock(&shrink_list_lock
);
5013 mutex_unlock(&dev
->struct_mutex
);
5020 spin_unlock(&shrink_list_lock
);
5025 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5030 static struct shrinker shrinker
= {
5031 .shrink
= i915_gem_shrink
,
5032 .seeks
= DEFAULT_SEEKS
,
5036 i915_gem_shrinker_init(void)
5038 register_shrinker(&shrinker
);
5042 i915_gem_shrinker_exit(void)
5044 unregister_shrinker(&shrinker
);