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rt2x00: Implement Powersaving
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
blobbf5e81162f2598d98c39a159461c7d80912cabea
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2500pci.h"
38
39 /*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
52 #define WAIT_FOR_BBP(__dev, __reg) \
53 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54 #define WAIT_FOR_RF(__dev, __reg) \
55 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
56
57 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
58 const unsigned int word, const u8 value)
59 {
60 u32 reg;
61
62 mutex_lock(&rt2x00dev->csr_mutex);
63
64 /*
65 * Wait until the BBP becomes available, afterwards we
66 * can safely write the new data into the register.
67 */
68 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
69 reg = 0;
70 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
71 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
72 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
73 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
74
75 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
76 }
77
78 mutex_unlock(&rt2x00dev->csr_mutex);
79 }
80
81 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
82 const unsigned int word, u8 *value)
83 {
84 u32 reg;
85
86 mutex_lock(&rt2x00dev->csr_mutex);
87
88 /*
89 * Wait until the BBP becomes available, afterwards we
90 * can safely write the read request into the register.
91 * After the data has been written, we wait until hardware
92 * returns the correct value, if at any time the register
93 * doesn't become available in time, reg will be 0xffffffff
94 * which means we return 0xff to the caller.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97 reg = 0;
98 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
101
102 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
103
104 WAIT_FOR_BBP(rt2x00dev, &reg);
105 }
106
107 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, const u32 value)
114 {
115 u32 reg;
116
117 if (!word)
118 return;
119
120 mutex_lock(&rt2x00dev->csr_mutex);
121
122 /*
123 * Wait until the RF becomes available, afterwards we
124 * can safely write the new data into the register.
125 */
126 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
127 reg = 0;
128 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
129 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
130 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
131 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
132
133 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
134 rt2x00_rf_write(rt2x00dev, word, value);
135 }
136
137 mutex_unlock(&rt2x00dev->csr_mutex);
138 }
139
140 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
141 {
142 struct rt2x00_dev *rt2x00dev = eeprom->data;
143 u32 reg;
144
145 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
146
147 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
148 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
149 eeprom->reg_data_clock =
150 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
151 eeprom->reg_chip_select =
152 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
153 }
154
155 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
156 {
157 struct rt2x00_dev *rt2x00dev = eeprom->data;
158 u32 reg = 0;
159
160 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
161 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
162 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
163 !!eeprom->reg_data_clock);
164 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
165 !!eeprom->reg_chip_select);
166
167 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
168 }
169
170 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
171 static const struct rt2x00debug rt2500pci_rt2x00debug = {
172 .owner = THIS_MODULE,
173 .csr = {
174 .read = rt2x00pci_register_read,
175 .write = rt2x00pci_register_write,
176 .flags = RT2X00DEBUGFS_OFFSET,
177 .word_base = CSR_REG_BASE,
178 .word_size = sizeof(u32),
179 .word_count = CSR_REG_SIZE / sizeof(u32),
180 },
181 .eeprom = {
182 .read = rt2x00_eeprom_read,
183 .write = rt2x00_eeprom_write,
184 .word_base = EEPROM_BASE,
185 .word_size = sizeof(u16),
186 .word_count = EEPROM_SIZE / sizeof(u16),
187 },
188 .bbp = {
189 .read = rt2500pci_bbp_read,
190 .write = rt2500pci_bbp_write,
191 .word_base = BBP_BASE,
192 .word_size = sizeof(u8),
193 .word_count = BBP_SIZE / sizeof(u8),
194 },
195 .rf = {
196 .read = rt2x00_rf_read,
197 .write = rt2500pci_rf_write,
198 .word_base = RF_BASE,
199 .word_size = sizeof(u32),
200 .word_count = RF_SIZE / sizeof(u32),
201 },
202 };
203 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
204
205 #ifdef CONFIG_RT2X00_LIB_RFKILL
206 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
207 {
208 u32 reg;
209
210 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
211 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
212 }
213 #else
214 #define rt2500pci_rfkill_poll NULL
215 #endif /* CONFIG_RT2X00_LIB_RFKILL */
216
217 #ifdef CONFIG_RT2X00_LIB_LEDS
218 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
219 enum led_brightness brightness)
220 {
221 struct rt2x00_led *led =
222 container_of(led_cdev, struct rt2x00_led, led_dev);
223 unsigned int enabled = brightness != LED_OFF;
224 u32 reg;
225
226 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
227
228 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
229 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
230 else if (led->type == LED_TYPE_ACTIVITY)
231 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
232
233 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
234 }
235
236 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
237 unsigned long *delay_on,
238 unsigned long *delay_off)
239 {
240 struct rt2x00_led *led =
241 container_of(led_cdev, struct rt2x00_led, led_dev);
242 u32 reg;
243
244 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
245 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
246 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
247 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
248
249 return 0;
250 }
251
252 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
253 struct rt2x00_led *led,
254 enum led_type type)
255 {
256 led->rt2x00dev = rt2x00dev;
257 led->type = type;
258 led->led_dev.brightness_set = rt2500pci_brightness_set;
259 led->led_dev.blink_set = rt2500pci_blink_set;
260 led->flags = LED_INITIALIZED;
261 }
262 #endif /* CONFIG_RT2X00_LIB_LEDS */
263
264 /*
265 * Configuration handlers.
266 */
267 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
268 const unsigned int filter_flags)
269 {
270 u32 reg;
271
272 /*
273 * Start configuration steps.
274 * Note that the version error will always be dropped
275 * and broadcast frames will always be accepted since
276 * there is no filter for it at this time.
277 */
278 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
279 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
280 !(filter_flags & FIF_FCSFAIL));
281 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
282 !(filter_flags & FIF_PLCPFAIL));
283 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
284 !(filter_flags & FIF_CONTROL));
285 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
286 !(filter_flags & FIF_PROMISC_IN_BSS));
287 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
288 !(filter_flags & FIF_PROMISC_IN_BSS) &&
289 !rt2x00dev->intf_ap_count);
290 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
291 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
292 !(filter_flags & FIF_ALLMULTI));
293 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
294 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
295 }
296
297 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
298 struct rt2x00_intf *intf,
299 struct rt2x00intf_conf *conf,
300 const unsigned int flags)
301 {
302 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
303 unsigned int bcn_preload;
304 u32 reg;
305
306 if (flags & CONFIG_UPDATE_TYPE) {
307 /*
308 * Enable beacon config
309 */
310 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
311 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
312 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
313 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
314 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
315
316 /*
317 * Enable synchronisation.
318 */
319 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
320 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
321 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
322 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
323 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
324 }
325
326 if (flags & CONFIG_UPDATE_MAC)
327 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
328 conf->mac, sizeof(conf->mac));
329
330 if (flags & CONFIG_UPDATE_BSSID)
331 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
332 conf->bssid, sizeof(conf->bssid));
333 }
334
335 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
336 struct rt2x00lib_erp *erp)
337 {
338 int preamble_mask;
339 u32 reg;
340
341 /*
342 * When short preamble is enabled, we should set bit 0x08
343 */
344 preamble_mask = erp->short_preamble << 3;
345
346 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
347 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
348 erp->ack_timeout);
349 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
350 erp->ack_consume_time);
351 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
352
353 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
354 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
355 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
356 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
357 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
358
359 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
360 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
361 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
363 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
364
365 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
366 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
367 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
368 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
369 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
370
371 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
372 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
373 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
374 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
375 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
376
377 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
378
379 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
380 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
381 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
382
383 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
384 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
385 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
386 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
387
388 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
389 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
390 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
391 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
392 }
393
394 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
395 struct antenna_setup *ant)
396 {
397 u32 reg;
398 u8 r14;
399 u8 r2;
400
401 /*
402 * We should never come here because rt2x00lib is supposed
403 * to catch this and send us the correct antenna explicitely.
404 */
405 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
406 ant->tx == ANTENNA_SW_DIVERSITY);
407
408 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
409 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
410 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
411
412 /*
413 * Configure the TX antenna.
414 */
415 switch (ant->tx) {
416 case ANTENNA_A:
417 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
418 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
419 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
420 break;
421 case ANTENNA_B:
422 default:
423 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
424 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
425 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
426 break;
427 }
428
429 /*
430 * Configure the RX antenna.
431 */
432 switch (ant->rx) {
433 case ANTENNA_A:
434 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
435 break;
436 case ANTENNA_B:
437 default:
438 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
439 break;
440 }
441
442 /*
443 * RT2525E and RT5222 need to flip TX I/Q
444 */
445 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
446 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
447 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
448 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
449 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
450
451 /*
452 * RT2525E does not need RX I/Q Flip.
453 */
454 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
455 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
456 } else {
457 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
458 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
459 }
460
461 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
462 rt2500pci_bbp_write(rt2x00dev, 14, r14);
463 rt2500pci_bbp_write(rt2x00dev, 2, r2);
464 }
465
466 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
467 struct rf_channel *rf, const int txpower)
468 {
469 u8 r70;
470
471 /*
472 * Set TXpower.
473 */
474 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
475
476 /*
477 * Switch on tuning bits.
478 * For RT2523 devices we do not need to update the R1 register.
479 */
480 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
481 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
482 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
483
484 /*
485 * For RT2525 we should first set the channel to half band higher.
486 */
487 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
488 static const u32 vals[] = {
489 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
490 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
491 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
492 0x00080d2e, 0x00080d3a
493 };
494
495 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
496 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
497 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
498 if (rf->rf4)
499 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
500 }
501
502 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
503 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
504 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
505 if (rf->rf4)
506 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
507
508 /*
509 * Channel 14 requires the Japan filter bit to be set.
510 */
511 r70 = 0x46;
512 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
513 rt2500pci_bbp_write(rt2x00dev, 70, r70);
514
515 msleep(1);
516
517 /*
518 * Switch off tuning bits.
519 * For RT2523 devices we do not need to update the R1 register.
520 */
521 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
522 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
523 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
524 }
525
526 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
527 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
528
529 /*
530 * Clear false CRC during channel switch.
531 */
532 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
533 }
534
535 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
536 const int txpower)
537 {
538 u32 rf3;
539
540 rt2x00_rf_read(rt2x00dev, 3, &rf3);
541 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
542 rt2500pci_rf_write(rt2x00dev, 3, rf3);
543 }
544
545 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
546 struct rt2x00lib_conf *libconf)
547 {
548 u32 reg;
549
550 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
551 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
552 libconf->conf->long_frame_max_tx_count);
553 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
554 libconf->conf->short_frame_max_tx_count);
555 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
556 }
557
558 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
559 struct rt2x00lib_conf *libconf)
560 {
561 u32 reg;
562
563 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
564 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
565 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
566 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
567
568 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
569 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
570 libconf->conf->beacon_int * 16);
571 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
572 libconf->conf->beacon_int * 16);
573 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
574 }
575
576 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
577 struct rt2x00lib_conf *libconf)
578 {
579 enum dev_state state =
580 (libconf->conf->flags & IEEE80211_CONF_PS) ?
581 STATE_SLEEP : STATE_AWAKE;
582 u32 reg;
583
584 if (state == STATE_SLEEP) {
585 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
586 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
587 (libconf->conf->beacon_int - 20) * 16);
588 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
589 libconf->conf->listen_interval - 1);
590
591 /* We must first disable autowake before it can be enabled */
592 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
593 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
594
595 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
596 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
597 }
598
599 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
600 }
601
602 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
603 struct rt2x00lib_conf *libconf,
604 const unsigned int flags)
605 {
606 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
607 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
608 libconf->conf->power_level);
609 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
610 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
611 rt2500pci_config_txpower(rt2x00dev,
612 libconf->conf->power_level);
613 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
614 rt2500pci_config_retry_limit(rt2x00dev, libconf);
615 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
616 rt2500pci_config_duration(rt2x00dev, libconf);
617 if (flags & IEEE80211_CONF_CHANGE_PS)
618 rt2500pci_config_ps(rt2x00dev, libconf);
619 }
620
621 /*
622 * Link tuning
623 */
624 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
625 struct link_qual *qual)
626 {
627 u32 reg;
628
629 /*
630 * Update FCS error count from register.
631 */
632 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
633 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
634
635 /*
636 * Update False CCA count from register.
637 */
638 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
639 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
640 }
641
642 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
643 {
644 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
645 rt2x00dev->link.vgc_level = 0x48;
646 }
647
648 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
649 {
650 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
651 u8 r17;
652
653 /*
654 * To prevent collisions with MAC ASIC on chipsets
655 * up to version C the link tuning should halt after 20
656 * seconds while being associated.
657 */
658 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
659 rt2x00dev->intf_associated &&
660 rt2x00dev->link.count > 20)
661 return;
662
663 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
664
665 /*
666 * Chipset versions C and lower should directly continue
667 * to the dynamic CCA tuning. Chipset version D and higher
668 * should go straight to dynamic CCA tuning when they
669 * are not associated.
670 */
671 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
672 !rt2x00dev->intf_associated)
673 goto dynamic_cca_tune;
674
675 /*
676 * A too low RSSI will cause too much false CCA which will
677 * then corrupt the R17 tuning. To remidy this the tuning should
678 * be stopped (While making sure the R17 value will not exceed limits)
679 */
680 if (rssi < -80 && rt2x00dev->link.count > 20) {
681 if (r17 >= 0x41) {
682 r17 = rt2x00dev->link.vgc_level;
683 rt2500pci_bbp_write(rt2x00dev, 17, r17);
684 }
685 return;
686 }
687
688 /*
689 * Special big-R17 for short distance
690 */
691 if (rssi >= -58) {
692 if (r17 != 0x50)
693 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
694 return;
695 }
696
697 /*
698 * Special mid-R17 for middle distance
699 */
700 if (rssi >= -74) {
701 if (r17 != 0x41)
702 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
703 return;
704 }
705
706 /*
707 * Leave short or middle distance condition, restore r17
708 * to the dynamic tuning range.
709 */
710 if (r17 >= 0x41) {
711 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
712 return;
713 }
714
715 dynamic_cca_tune:
716
717 /*
718 * R17 is inside the dynamic tuning range,
719 * start tuning the link based on the false cca counter.
720 */
721 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
722 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
723 rt2x00dev->link.vgc_level = r17;
724 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
725 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
726 rt2x00dev->link.vgc_level = r17;
727 }
728 }
729
730 /*
731 * Initialization functions.
732 */
733 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
734 {
735 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
736 u32 word;
737
738 if (entry->queue->qid == QID_RX) {
739 rt2x00_desc_read(entry_priv->desc, 0, &word);
740
741 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
742 } else {
743 rt2x00_desc_read(entry_priv->desc, 0, &word);
744
745 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
746 rt2x00_get_field32(word, TXD_W0_VALID));
747 }
748 }
749
750 static void rt2500pci_clear_entry(struct queue_entry *entry)
751 {
752 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
753 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
754 u32 word;
755
756 if (entry->queue->qid == QID_RX) {
757 rt2x00_desc_read(entry_priv->desc, 1, &word);
758 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
759 rt2x00_desc_write(entry_priv->desc, 1, word);
760
761 rt2x00_desc_read(entry_priv->desc, 0, &word);
762 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
763 rt2x00_desc_write(entry_priv->desc, 0, word);
764 } else {
765 rt2x00_desc_read(entry_priv->desc, 0, &word);
766 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
767 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
768 rt2x00_desc_write(entry_priv->desc, 0, word);
769 }
770 }
771
772 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
773 {
774 struct queue_entry_priv_pci *entry_priv;
775 u32 reg;
776
777 /*
778 * Initialize registers.
779 */
780 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
781 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
782 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
783 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
784 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
785 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
786
787 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
788 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
789 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
790 entry_priv->desc_dma);
791 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
792
793 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
794 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
795 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
796 entry_priv->desc_dma);
797 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
798
799 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
800 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
801 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
802 entry_priv->desc_dma);
803 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
804
805 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
806 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
807 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
808 entry_priv->desc_dma);
809 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
810
811 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
812 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
813 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
814 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
815
816 entry_priv = rt2x00dev->rx->entries[0].priv_data;
817 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
818 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
819 entry_priv->desc_dma);
820 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
821
822 return 0;
823 }
824
825 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
826 {
827 u32 reg;
828
829 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
830 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
831 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
832 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
833
834 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
835 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
836 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
837 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
838 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
839
840 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
841 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
842 rt2x00dev->rx->data_size / 128);
843 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
844
845 /*
846 * Always use CWmin and CWmax set in descriptor.
847 */
848 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
849 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
850 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
851
852 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
853 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
854 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
855 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
856 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
857 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
858 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
859 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
860 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
861 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
862
863 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
864
865 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
866 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
867 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
868 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
869 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
870 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
871 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
872 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
873 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
874 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
875
876 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
877 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
878 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
879 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
880 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
881 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
882
883 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
884 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
885 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
886 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
887 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
888 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
889
890 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
891 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
892 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
893 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
894 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
895 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
896
897 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
898 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
899 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
900 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
901 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
902 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
903 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
904 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
905 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
906 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
907
908 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
909 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
910 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
911 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
912 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
913 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
914 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
915 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
916 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
917
918 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
919
920 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
921 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
922
923 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
924 return -EBUSY;
925
926 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
927 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
928
929 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
930 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
931 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
932
933 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
934 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
935 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
936 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
937 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
938 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
939 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
940 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
941
942 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
943
944 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
945
946 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
947 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
948 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
949 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
950 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
951
952 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
953 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
954 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
955 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
956
957 /*
958 * We must clear the FCS and FIFO error count.
959 * These registers are cleared on read,
960 * so we may pass a useless variable to store the value.
961 */
962 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
963 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
964
965 return 0;
966 }
967
968 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
969 {
970 unsigned int i;
971 u8 value;
972
973 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
974 rt2500pci_bbp_read(rt2x00dev, 0, &value);
975 if ((value != 0xff) && (value != 0x00))
976 return 0;
977 udelay(REGISTER_BUSY_DELAY);
978 }
979
980 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
981 return -EACCES;
982 }
983
984 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
985 {
986 unsigned int i;
987 u16 eeprom;
988 u8 reg_id;
989 u8 value;
990
991 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
992 return -EACCES;
993
994 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
995 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
996 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
997 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
998 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
999 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
1000 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
1001 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
1002 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1003 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1004 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1005 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1006 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1007 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1008 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1009 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1010 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1011 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1012 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1013 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1014 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1015 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1016 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1017 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1018 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1019 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1020 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1021 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1022 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1023 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1024
1025 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1026 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1027
1028 if (eeprom != 0xffff && eeprom != 0x0000) {
1029 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1030 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1031 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1032 }
1033 }
1034
1035 return 0;
1036 }
1037
1038 /*
1039 * Device state switch handlers.
1040 */
1041 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1042 enum dev_state state)
1043 {
1044 u32 reg;
1045
1046 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1047 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1048 (state == STATE_RADIO_RX_OFF) ||
1049 (state == STATE_RADIO_RX_OFF_LINK));
1050 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1051 }
1052
1053 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1054 enum dev_state state)
1055 {
1056 int mask = (state == STATE_RADIO_IRQ_OFF);
1057 u32 reg;
1058
1059 /*
1060 * When interrupts are being enabled, the interrupt registers
1061 * should clear the register to assure a clean state.
1062 */
1063 if (state == STATE_RADIO_IRQ_ON) {
1064 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1065 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1066 }
1067
1068 /*
1069 * Only toggle the interrupts bits we are going to use.
1070 * Non-checked interrupt bits are disabled by default.
1071 */
1072 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1073 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1074 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1075 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1076 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1077 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1078 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1079 }
1080
1081 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1082 {
1083 /*
1084 * Initialize all registers.
1085 */
1086 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1087 rt2500pci_init_registers(rt2x00dev) ||
1088 rt2500pci_init_bbp(rt2x00dev)))
1089 return -EIO;
1090
1091 return 0;
1092 }
1093
1094 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1095 {
1096 u32 reg;
1097
1098 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1099
1100 /*
1101 * Disable synchronisation.
1102 */
1103 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1104
1105 /*
1106 * Cancel RX and TX.
1107 */
1108 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1109 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1110 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1111 }
1112
1113 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1114 enum dev_state state)
1115 {
1116 u32 reg;
1117 unsigned int i;
1118 char put_to_sleep;
1119 char bbp_state;
1120 char rf_state;
1121
1122 put_to_sleep = (state != STATE_AWAKE);
1123
1124 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1125 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1126 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1127 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1128 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1129 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1130
1131 /*
1132 * Device is not guaranteed to be in the requested state yet.
1133 * We must wait until the register indicates that the
1134 * device has entered the correct state.
1135 */
1136 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1137 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1138 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1139 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1140 if (bbp_state == state && rf_state == state)
1141 return 0;
1142 msleep(10);
1143 }
1144
1145 return -EBUSY;
1146 }
1147
1148 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1149 enum dev_state state)
1150 {
1151 int retval = 0;
1152
1153 switch (state) {
1154 case STATE_RADIO_ON:
1155 retval = rt2500pci_enable_radio(rt2x00dev);
1156 break;
1157 case STATE_RADIO_OFF:
1158 rt2500pci_disable_radio(rt2x00dev);
1159 break;
1160 case STATE_RADIO_RX_ON:
1161 case STATE_RADIO_RX_ON_LINK:
1162 case STATE_RADIO_RX_OFF:
1163 case STATE_RADIO_RX_OFF_LINK:
1164 rt2500pci_toggle_rx(rt2x00dev, state);
1165 break;
1166 case STATE_RADIO_IRQ_ON:
1167 case STATE_RADIO_IRQ_OFF:
1168 rt2500pci_toggle_irq(rt2x00dev, state);
1169 break;
1170 case STATE_DEEP_SLEEP:
1171 case STATE_SLEEP:
1172 case STATE_STANDBY:
1173 case STATE_AWAKE:
1174 retval = rt2500pci_set_state(rt2x00dev, state);
1175 break;
1176 default:
1177 retval = -ENOTSUPP;
1178 break;
1179 }
1180
1181 if (unlikely(retval))
1182 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1183 state, retval);
1184
1185 return retval;
1186 }
1187
1188 /*
1189 * TX descriptor initialization
1190 */
1191 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1192 struct sk_buff *skb,
1193 struct txentry_desc *txdesc)
1194 {
1195 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1196 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1197 __le32 *txd = skbdesc->desc;
1198 u32 word;
1199
1200 /*
1201 * Start writing the descriptor words.
1202 */
1203 rt2x00_desc_read(entry_priv->desc, 1, &word);
1204 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1205 rt2x00_desc_write(entry_priv->desc, 1, word);
1206
1207 rt2x00_desc_read(txd, 2, &word);
1208 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1209 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1210 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1211 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1212 rt2x00_desc_write(txd, 2, word);
1213
1214 rt2x00_desc_read(txd, 3, &word);
1215 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1216 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1217 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1218 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1219 rt2x00_desc_write(txd, 3, word);
1220
1221 rt2x00_desc_read(txd, 10, &word);
1222 rt2x00_set_field32(&word, TXD_W10_RTS,
1223 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1224 rt2x00_desc_write(txd, 10, word);
1225
1226 rt2x00_desc_read(txd, 0, &word);
1227 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1228 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1229 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1230 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1231 rt2x00_set_field32(&word, TXD_W0_ACK,
1232 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1233 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1234 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1235 rt2x00_set_field32(&word, TXD_W0_OFDM,
1236 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1237 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1238 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1239 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1240 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1241 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1242 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1243 rt2x00_desc_write(txd, 0, word);
1244 }
1245
1246 /*
1247 * TX data initialization
1248 */
1249 static void rt2500pci_write_beacon(struct queue_entry *entry)
1250 {
1251 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1252 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1253 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1254 u32 word;
1255 u32 reg;
1256
1257 /*
1258 * Disable beaconing while we are reloading the beacon data,
1259 * otherwise we might be sending out invalid data.
1260 */
1261 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1262 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1263 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1264 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1265 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1266
1267 /*
1268 * Replace rt2x00lib allocated descriptor with the
1269 * pointer to the _real_ hardware descriptor.
1270 * After that, map the beacon to DMA and update the
1271 * descriptor.
1272 */
1273 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1274 skbdesc->desc = entry_priv->desc;
1275
1276 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1277
1278 rt2x00_desc_read(entry_priv->desc, 1, &word);
1279 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1280 rt2x00_desc_write(entry_priv->desc, 1, word);
1281 }
1282
1283 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1284 const enum data_queue_qid queue)
1285 {
1286 u32 reg;
1287
1288 if (queue == QID_BEACON) {
1289 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1290 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1291 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1292 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1293 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1294 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1295 }
1296 return;
1297 }
1298
1299 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1300 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1301 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1302 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1303 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1304 }
1305
1306 /*
1307 * RX control handlers
1308 */
1309 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1310 struct rxdone_entry_desc *rxdesc)
1311 {
1312 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1313 u32 word0;
1314 u32 word2;
1315
1316 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1317 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1318
1319 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1320 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1321 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1322 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1323
1324 /*
1325 * Obtain the status about this packet.
1326 * When frame was received with an OFDM bitrate,
1327 * the signal is the PLCP value. If it was received with
1328 * a CCK bitrate the signal is the rate in 100kbit/s.
1329 */
1330 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1331 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1332 entry->queue->rt2x00dev->rssi_offset;
1333 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1334
1335 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1336 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1337 else
1338 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1339 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1340 rxdesc->dev_flags |= RXDONE_MY_BSS;
1341 }
1342
1343 /*
1344 * Interrupt functions.
1345 */
1346 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1347 const enum data_queue_qid queue_idx)
1348 {
1349 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1350 struct queue_entry_priv_pci *entry_priv;
1351 struct queue_entry *entry;
1352 struct txdone_entry_desc txdesc;
1353 u32 word;
1354
1355 while (!rt2x00queue_empty(queue)) {
1356 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1357 entry_priv = entry->priv_data;
1358 rt2x00_desc_read(entry_priv->desc, 0, &word);
1359
1360 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1361 !rt2x00_get_field32(word, TXD_W0_VALID))
1362 break;
1363
1364 /*
1365 * Obtain the status about this packet.
1366 */
1367 txdesc.flags = 0;
1368 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1369 case 0: /* Success */
1370 case 1: /* Success with retry */
1371 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1372 break;
1373 case 2: /* Failure, excessive retries */
1374 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1375 /* Don't break, this is a failed frame! */
1376 default: /* Failure */
1377 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1378 }
1379 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1380
1381 rt2x00lib_txdone(entry, &txdesc);
1382 }
1383 }
1384
1385 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1386 {
1387 struct rt2x00_dev *rt2x00dev = dev_instance;
1388 u32 reg;
1389
1390 /*
1391 * Get the interrupt sources & saved to local variable.
1392 * Write register value back to clear pending interrupts.
1393 */
1394 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1395 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1396
1397 if (!reg)
1398 return IRQ_NONE;
1399
1400 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1401 return IRQ_HANDLED;
1402
1403 /*
1404 * Handle interrupts, walk through all bits
1405 * and run the tasks, the bits are checked in order of
1406 * priority.
1407 */
1408
1409 /*
1410 * 1 - Beacon timer expired interrupt.
1411 */
1412 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1413 rt2x00lib_beacondone(rt2x00dev);
1414
1415 /*
1416 * 2 - Rx ring done interrupt.
1417 */
1418 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1419 rt2x00pci_rxdone(rt2x00dev);
1420
1421 /*
1422 * 3 - Atim ring transmit done interrupt.
1423 */
1424 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1425 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1426
1427 /*
1428 * 4 - Priority ring transmit done interrupt.
1429 */
1430 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1431 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1432
1433 /*
1434 * 5 - Tx ring transmit done interrupt.
1435 */
1436 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1437 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1438
1439 return IRQ_HANDLED;
1440 }
1441
1442 /*
1443 * Device probe functions.
1444 */
1445 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1446 {
1447 struct eeprom_93cx6 eeprom;
1448 u32 reg;
1449 u16 word;
1450 u8 *mac;
1451
1452 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1453
1454 eeprom.data = rt2x00dev;
1455 eeprom.register_read = rt2500pci_eepromregister_read;
1456 eeprom.register_write = rt2500pci_eepromregister_write;
1457 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1458 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1459 eeprom.reg_data_in = 0;
1460 eeprom.reg_data_out = 0;
1461 eeprom.reg_data_clock = 0;
1462 eeprom.reg_chip_select = 0;
1463
1464 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1465 EEPROM_SIZE / sizeof(u16));
1466
1467 /*
1468 * Start validation of the data that has been read.
1469 */
1470 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1471 if (!is_valid_ether_addr(mac)) {
1472 random_ether_addr(mac);
1473 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1474 }
1475
1476 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1477 if (word == 0xffff) {
1478 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1479 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1480 ANTENNA_SW_DIVERSITY);
1481 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1482 ANTENNA_SW_DIVERSITY);
1483 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1484 LED_MODE_DEFAULT);
1485 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1486 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1487 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1488 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1489 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1490 }
1491
1492 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1493 if (word == 0xffff) {
1494 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1495 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1496 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1497 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1498 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1499 }
1500
1501 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1502 if (word == 0xffff) {
1503 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1504 DEFAULT_RSSI_OFFSET);
1505 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1506 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1507 }
1508
1509 return 0;
1510 }
1511
1512 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1513 {
1514 u32 reg;
1515 u16 value;
1516 u16 eeprom;
1517
1518 /*
1519 * Read EEPROM word for configuration.
1520 */
1521 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1522
1523 /*
1524 * Identify RF chipset.
1525 */
1526 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1527 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1528 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1529
1530 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1531 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1532 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1533 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1534 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1535 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1536 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1537 return -ENODEV;
1538 }
1539
1540 /*
1541 * Identify default antenna configuration.
1542 */
1543 rt2x00dev->default_ant.tx =
1544 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1545 rt2x00dev->default_ant.rx =
1546 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1547
1548 /*
1549 * Store led mode, for correct led behaviour.
1550 */
1551 #ifdef CONFIG_RT2X00_LIB_LEDS
1552 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1553
1554 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1555 if (value == LED_MODE_TXRX_ACTIVITY)
1556 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1557 LED_TYPE_ACTIVITY);
1558 #endif /* CONFIG_RT2X00_LIB_LEDS */
1559
1560 /*
1561 * Detect if this device has an hardware controlled radio.
1562 */
1563 #ifdef CONFIG_RT2X00_LIB_RFKILL
1564 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1565 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1566 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1567
1568 /*
1569 * Check if the BBP tuning should be enabled.
1570 */
1571 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1572
1573 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1574 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1575
1576 /*
1577 * Read the RSSI <-> dBm offset information.
1578 */
1579 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1580 rt2x00dev->rssi_offset =
1581 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1582
1583 return 0;
1584 }
1585
1586 /*
1587 * RF value list for RF2522
1588 * Supports: 2.4 GHz
1589 */
1590 static const struct rf_channel rf_vals_bg_2522[] = {
1591 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1592 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1593 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1594 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1595 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1596 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1597 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1598 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1599 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1600 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1601 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1602 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1603 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1604 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1605 };
1606
1607 /*
1608 * RF value list for RF2523
1609 * Supports: 2.4 GHz
1610 */
1611 static const struct rf_channel rf_vals_bg_2523[] = {
1612 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1613 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1614 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1615 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1616 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1617 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1618 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1619 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1620 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1621 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1622 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1623 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1624 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1625 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1626 };
1627
1628 /*
1629 * RF value list for RF2524
1630 * Supports: 2.4 GHz
1631 */
1632 static const struct rf_channel rf_vals_bg_2524[] = {
1633 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1634 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1635 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1636 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1637 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1638 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1639 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1640 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1641 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1642 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1643 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1644 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1645 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1646 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1647 };
1648
1649 /*
1650 * RF value list for RF2525
1651 * Supports: 2.4 GHz
1652 */
1653 static const struct rf_channel rf_vals_bg_2525[] = {
1654 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1655 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1656 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1657 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1658 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1659 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1660 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1661 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1662 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1663 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1664 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1665 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1666 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1667 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1668 };
1669
1670 /*
1671 * RF value list for RF2525e
1672 * Supports: 2.4 GHz
1673 */
1674 static const struct rf_channel rf_vals_bg_2525e[] = {
1675 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1676 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1677 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1678 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1679 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1680 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1681 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1682 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1683 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1684 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1685 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1686 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1687 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1688 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1689 };
1690
1691 /*
1692 * RF value list for RF5222
1693 * Supports: 2.4 GHz & 5.2 GHz
1694 */
1695 static const struct rf_channel rf_vals_5222[] = {
1696 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1697 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1698 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1699 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1700 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1701 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1702 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1703 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1704 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1705 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1706 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1707 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1708 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1709 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1710
1711 /* 802.11 UNI / HyperLan 2 */
1712 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1713 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1714 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1715 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1716 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1717 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1718 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1719 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1720
1721 /* 802.11 HyperLan 2 */
1722 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1723 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1724 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1725 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1726 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1727 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1728 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1729 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1730 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1731 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1732
1733 /* 802.11 UNII */
1734 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1735 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1736 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1737 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1738 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1739 };
1740
1741 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1742 {
1743 struct hw_mode_spec *spec = &rt2x00dev->spec;
1744 struct channel_info *info;
1745 char *tx_power;
1746 unsigned int i;
1747
1748 /*
1749 * Initialize all hw fields.
1750 */
1751 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1752 IEEE80211_HW_SIGNAL_DBM;
1753
1754 rt2x00dev->hw->extra_tx_headroom = 0;
1755
1756 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1757 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1758 rt2x00_eeprom_addr(rt2x00dev,
1759 EEPROM_MAC_ADDR_0));
1760
1761 /*
1762 * Initialize hw_mode information.
1763 */
1764 spec->supported_bands = SUPPORT_BAND_2GHZ;
1765 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1766
1767 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1768 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1769 spec->channels = rf_vals_bg_2522;
1770 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1771 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1772 spec->channels = rf_vals_bg_2523;
1773 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1774 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1775 spec->channels = rf_vals_bg_2524;
1776 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1777 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1778 spec->channels = rf_vals_bg_2525;
1779 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1780 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1781 spec->channels = rf_vals_bg_2525e;
1782 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1783 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1784 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1785 spec->channels = rf_vals_5222;
1786 }
1787
1788 /*
1789 * Create channel information array
1790 */
1791 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1792 if (!info)
1793 return -ENOMEM;
1794
1795 spec->channels_info = info;
1796
1797 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1798 for (i = 0; i < 14; i++)
1799 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1800
1801 if (spec->num_channels > 14) {
1802 for (i = 14; i < spec->num_channels; i++)
1803 info[i].tx_power1 = DEFAULT_TXPOWER;
1804 }
1805
1806 return 0;
1807 }
1808
1809 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1810 {
1811 int retval;
1812
1813 /*
1814 * Allocate eeprom data.
1815 */
1816 retval = rt2500pci_validate_eeprom(rt2x00dev);
1817 if (retval)
1818 return retval;
1819
1820 retval = rt2500pci_init_eeprom(rt2x00dev);
1821 if (retval)
1822 return retval;
1823
1824 /*
1825 * Initialize hw specifications.
1826 */
1827 retval = rt2500pci_probe_hw_mode(rt2x00dev);
1828 if (retval)
1829 return retval;
1830
1831 /*
1832 * This device requires the atim queue and DMA-mapped skbs.
1833 */
1834 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1835 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1836
1837 /*
1838 * Set the rssi offset.
1839 */
1840 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1841
1842 return 0;
1843 }
1844
1845 /*
1846 * IEEE80211 stack callback functions.
1847 */
1848 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1849 {
1850 struct rt2x00_dev *rt2x00dev = hw->priv;
1851 u64 tsf;
1852 u32 reg;
1853
1854 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1855 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1856 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1857 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1858
1859 return tsf;
1860 }
1861
1862 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1863 {
1864 struct rt2x00_dev *rt2x00dev = hw->priv;
1865 u32 reg;
1866
1867 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1868 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1869 }
1870
1871 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1872 .tx = rt2x00mac_tx,
1873 .start = rt2x00mac_start,
1874 .stop = rt2x00mac_stop,
1875 .add_interface = rt2x00mac_add_interface,
1876 .remove_interface = rt2x00mac_remove_interface,
1877 .config = rt2x00mac_config,
1878 .config_interface = rt2x00mac_config_interface,
1879 .configure_filter = rt2x00mac_configure_filter,
1880 .get_stats = rt2x00mac_get_stats,
1881 .bss_info_changed = rt2x00mac_bss_info_changed,
1882 .conf_tx = rt2x00mac_conf_tx,
1883 .get_tx_stats = rt2x00mac_get_tx_stats,
1884 .get_tsf = rt2500pci_get_tsf,
1885 .tx_last_beacon = rt2500pci_tx_last_beacon,
1886 };
1887
1888 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1889 .irq_handler = rt2500pci_interrupt,
1890 .probe_hw = rt2500pci_probe_hw,
1891 .initialize = rt2x00pci_initialize,
1892 .uninitialize = rt2x00pci_uninitialize,
1893 .get_entry_state = rt2500pci_get_entry_state,
1894 .clear_entry = rt2500pci_clear_entry,
1895 .set_device_state = rt2500pci_set_device_state,
1896 .rfkill_poll = rt2500pci_rfkill_poll,
1897 .link_stats = rt2500pci_link_stats,
1898 .reset_tuner = rt2500pci_reset_tuner,
1899 .link_tuner = rt2500pci_link_tuner,
1900 .write_tx_desc = rt2500pci_write_tx_desc,
1901 .write_tx_data = rt2x00pci_write_tx_data,
1902 .write_beacon = rt2500pci_write_beacon,
1903 .kick_tx_queue = rt2500pci_kick_tx_queue,
1904 .fill_rxdone = rt2500pci_fill_rxdone,
1905 .config_filter = rt2500pci_config_filter,
1906 .config_intf = rt2500pci_config_intf,
1907 .config_erp = rt2500pci_config_erp,
1908 .config_ant = rt2500pci_config_ant,
1909 .config = rt2500pci_config,
1910 };
1911
1912 static const struct data_queue_desc rt2500pci_queue_rx = {
1913 .entry_num = RX_ENTRIES,
1914 .data_size = DATA_FRAME_SIZE,
1915 .desc_size = RXD_DESC_SIZE,
1916 .priv_size = sizeof(struct queue_entry_priv_pci),
1917 };
1918
1919 static const struct data_queue_desc rt2500pci_queue_tx = {
1920 .entry_num = TX_ENTRIES,
1921 .data_size = DATA_FRAME_SIZE,
1922 .desc_size = TXD_DESC_SIZE,
1923 .priv_size = sizeof(struct queue_entry_priv_pci),
1924 };
1925
1926 static const struct data_queue_desc rt2500pci_queue_bcn = {
1927 .entry_num = BEACON_ENTRIES,
1928 .data_size = MGMT_FRAME_SIZE,
1929 .desc_size = TXD_DESC_SIZE,
1930 .priv_size = sizeof(struct queue_entry_priv_pci),
1931 };
1932
1933 static const struct data_queue_desc rt2500pci_queue_atim = {
1934 .entry_num = ATIM_ENTRIES,
1935 .data_size = DATA_FRAME_SIZE,
1936 .desc_size = TXD_DESC_SIZE,
1937 .priv_size = sizeof(struct queue_entry_priv_pci),
1938 };
1939
1940 static const struct rt2x00_ops rt2500pci_ops = {
1941 .name = KBUILD_MODNAME,
1942 .max_sta_intf = 1,
1943 .max_ap_intf = 1,
1944 .eeprom_size = EEPROM_SIZE,
1945 .rf_size = RF_SIZE,
1946 .tx_queues = NUM_TX_QUEUES,
1947 .rx = &rt2500pci_queue_rx,
1948 .tx = &rt2500pci_queue_tx,
1949 .bcn = &rt2500pci_queue_bcn,
1950 .atim = &rt2500pci_queue_atim,
1951 .lib = &rt2500pci_rt2x00_ops,
1952 .hw = &rt2500pci_mac80211_ops,
1953 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1954 .debugfs = &rt2500pci_rt2x00debug,
1955 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1956 };
1957
1958 /*
1959 * RT2500pci module information.
1960 */
1961 static struct pci_device_id rt2500pci_device_table[] = {
1962 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1963 { 0, }
1964 };
1965
1966 MODULE_AUTHOR(DRV_PROJECT);
1967 MODULE_VERSION(DRV_VERSION);
1968 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1969 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1970 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1971 MODULE_LICENSE("GPL");
1972
1973 static struct pci_driver rt2500pci_driver = {
1974 .name = KBUILD_MODNAME,
1975 .id_table = rt2500pci_device_table,
1976 .probe = rt2x00pci_probe,
1977 .remove = __devexit_p(rt2x00pci_remove),
1978 .suspend = rt2x00pci_suspend,
1979 .resume = rt2x00pci_resume,
1980 };
1981
1982 static int __init rt2500pci_init(void)
1983 {
1984 return pci_register_driver(&rt2500pci_driver);
1985 }
1986
1987 static void __exit rt2500pci_exit(void)
1988 {
1989 pci_unregister_driver(&rt2500pci_driver);
1990 }
1991
1992 module_init(rt2500pci_init);
1993 module_exit(rt2500pci_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree