arch/arm/mach-exynos4/gpiolib.c

   1 /* linux/arch/arm/mach-exynos4/gpiolib.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - GPIOlib support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/gpio.h>
  17
  18 #include <mach/map.h>
  19
  20 #include <plat/gpio-core.h>
  21 #include <plat/gpio-cfg.h>
  22 #include <plat/gpio-cfg-helpers.h>
  23
  24 static struct s3c_gpio_cfg gpio_cfg = {
  25         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
  26         .set_pull       = s3c_gpio_setpull_updown,
  27         .get_pull       = s3c_gpio_getpull_updown,
  28 };
  29
  30 static struct s3c_gpio_cfg gpio_cfg_noint = {
  31         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
  32         .set_pull       = s3c_gpio_setpull_updown,
  33         .get_pull       = s3c_gpio_getpull_updown,
  34 };
  35
  36 /*
  37  * Following are the gpio banks in v310.
  38  *
  39  * The 'config' member when left to NULL, is initialized to the default
  40  * structure gpio_cfg in the init function below.
  41  *
  42  * The 'base' member is also initialized in the init function below.
  43  * Note: The initialization of 'base' member of s3c_gpio_chip structure
  44  * uses the above macro and depends on the banks being listed in order here.
  45  */
  46 static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
  47         {
  48                 .chip   = {
  49                         .base   = EXYNOS4_GPA0(0),
  50                         .ngpio  = EXYNOS4_GPIO_A0_NR,
  51                         .label  = "GPA0",
  52                 },
  53         }, {
  54                 .chip   = {
  55                         .base   = EXYNOS4_GPA1(0),
  56                         .ngpio  = EXYNOS4_GPIO_A1_NR,
  57                         .label  = "GPA1",
  58                 },
  59         }, {
  60                 .chip   = {
  61                         .base   = EXYNOS4_GPB(0),
  62                         .ngpio  = EXYNOS4_GPIO_B_NR,
  63                         .label  = "GPB",
  64                 },
  65         }, {
  66                 .chip   = {
  67                         .base   = EXYNOS4_GPC0(0),
  68                         .ngpio  = EXYNOS4_GPIO_C0_NR,
  69                         .label  = "GPC0",
  70                 },
  71         }, {
  72                 .chip   = {
  73                         .base   = EXYNOS4_GPC1(0),
  74                         .ngpio  = EXYNOS4_GPIO_C1_NR,
  75                         .label  = "GPC1",
  76                 },
  77         }, {
  78                 .chip   = {
  79                         .base   = EXYNOS4_GPD0(0),
  80                         .ngpio  = EXYNOS4_GPIO_D0_NR,
  81                         .label  = "GPD0",
  82                 },
  83         }, {
  84                 .chip   = {
  85                         .base   = EXYNOS4_GPD1(0),
  86                         .ngpio  = EXYNOS4_GPIO_D1_NR,
  87                         .label  = "GPD1",
  88                 },
  89         }, {
  90                 .chip   = {
  91                         .base   = EXYNOS4_GPE0(0),
  92                         .ngpio  = EXYNOS4_GPIO_E0_NR,
  93                         .label  = "GPE0",
  94                 },
  95         }, {
  96                 .chip   = {
  97                         .base   = EXYNOS4_GPE1(0),
  98                         .ngpio  = EXYNOS4_GPIO_E1_NR,
  99                         .label  = "GPE1",
 100                 },
 101         }, {
 102                 .chip   = {
 103                         .base   = EXYNOS4_GPE2(0),
 104                         .ngpio  = EXYNOS4_GPIO_E2_NR,
 105                         .label  = "GPE2",
 106                 },
 107         }, {
 108                 .chip   = {
 109                         .base   = EXYNOS4_GPE3(0),
 110                         .ngpio  = EXYNOS4_GPIO_E3_NR,
 111                         .label  = "GPE3",
 112                 },
 113         }, {
 114                 .chip   = {
 115                         .base   = EXYNOS4_GPE4(0),
 116                         .ngpio  = EXYNOS4_GPIO_E4_NR,
 117                         .label  = "GPE4",
 118                 },
 119         }, {
 120                 .chip   = {
 121                         .base   = EXYNOS4_GPF0(0),
 122                         .ngpio  = EXYNOS4_GPIO_F0_NR,
 123                         .label  = "GPF0",
 124                 },
 125         }, {
 126                 .chip   = {
 127                         .base   = EXYNOS4_GPF1(0),
 128                         .ngpio  = EXYNOS4_GPIO_F1_NR,
 129                         .label  = "GPF1",
 130                 },
 131         }, {
 132                 .chip   = {
 133                         .base   = EXYNOS4_GPF2(0),
 134                         .ngpio  = EXYNOS4_GPIO_F2_NR,
 135                         .label  = "GPF2",
 136                 },
 137         }, {
 138                 .chip   = {
 139                         .base   = EXYNOS4_GPF3(0),
 140                         .ngpio  = EXYNOS4_GPIO_F3_NR,
 141                         .label  = "GPF3",
 142                 },
 143         },
 144 };
 145
 146 static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
 147         {
 148                 .chip   = {
 149                         .base   = EXYNOS4_GPJ0(0),
 150                         .ngpio  = EXYNOS4_GPIO_J0_NR,
 151                         .label  = "GPJ0",
 152                 },
 153         }, {
 154                 .chip   = {
 155                         .base   = EXYNOS4_GPJ1(0),
 156                         .ngpio  = EXYNOS4_GPIO_J1_NR,
 157                         .label  = "GPJ1",
 158                 },
 159         }, {
 160                 .chip   = {
 161                         .base   = EXYNOS4_GPK0(0),
 162                         .ngpio  = EXYNOS4_GPIO_K0_NR,
 163                         .label  = "GPK0",
 164                 },
 165         }, {
 166                 .chip   = {
 167                         .base   = EXYNOS4_GPK1(0),
 168                         .ngpio  = EXYNOS4_GPIO_K1_NR,
 169                         .label  = "GPK1",
 170                 },
 171         }, {
 172                 .chip   = {
 173                         .base   = EXYNOS4_GPK2(0),
 174                         .ngpio  = EXYNOS4_GPIO_K2_NR,
 175                         .label  = "GPK2",
 176                 },
 177         }, {
 178                 .chip   = {
 179                         .base   = EXYNOS4_GPK3(0),
 180                         .ngpio  = EXYNOS4_GPIO_K3_NR,
 181                         .label  = "GPK3",
 182                 },
 183         }, {
 184                 .chip   = {
 185                         .base   = EXYNOS4_GPL0(0),
 186                         .ngpio  = EXYNOS4_GPIO_L0_NR,
 187                         .label  = "GPL0",
 188                 },
 189         }, {
 190                 .chip   = {
 191                         .base   = EXYNOS4_GPL1(0),
 192                         .ngpio  = EXYNOS4_GPIO_L1_NR,
 193                         .label  = "GPL1",
 194                 },
 195         }, {
 196                 .chip   = {
 197                         .base   = EXYNOS4_GPL2(0),
 198                         .ngpio  = EXYNOS4_GPIO_L2_NR,
 199                         .label  = "GPL2",
 200                 },
 201         }, {
 202                 .base   = (S5P_VA_GPIO2 + 0xC00),
 203                 .config = &gpio_cfg_noint,
 204                 .irq_base = IRQ_EINT(0),
 205                 .chip   = {
 206                         .base   = EXYNOS4_GPX0(0),
 207                         .ngpio  = EXYNOS4_GPIO_X0_NR,
 208                         .label  = "GPX0",
 209                         .to_irq = samsung_gpiolib_to_irq,
 210                 },
 211         }, {
 212                 .base   = (S5P_VA_GPIO2 + 0xC20),
 213                 .config = &gpio_cfg_noint,
 214                 .irq_base = IRQ_EINT(8),
 215                 .chip   = {
 216                         .base   = EXYNOS4_GPX1(0),
 217                         .ngpio  = EXYNOS4_GPIO_X1_NR,
 218                         .label  = "GPX1",
 219                         .to_irq = samsung_gpiolib_to_irq,
 220                 },
 221         }, {
 222                 .base   = (S5P_VA_GPIO2 + 0xC40),
 223                 .config = &gpio_cfg_noint,
 224                 .irq_base = IRQ_EINT(16),
 225                 .chip   = {
 226                         .base   = EXYNOS4_GPX2(0),
 227                         .ngpio  = EXYNOS4_GPIO_X2_NR,
 228                         .label  = "GPX2",
 229                         .to_irq = samsung_gpiolib_to_irq,
 230                 },
 231         }, {
 232                 .base   = (S5P_VA_GPIO2 + 0xC60),
 233                 .config = &gpio_cfg_noint,
 234                 .irq_base = IRQ_EINT(24),
 235                 .chip   = {
 236                         .base   = EXYNOS4_GPX3(0),
 237                         .ngpio  = EXYNOS4_GPIO_X3_NR,
 238                         .label  = "GPX3",
 239                         .to_irq = samsung_gpiolib_to_irq,
 240                 },
 241         },
 242 };
 243
 244 static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
 245         {
 246                 .chip   = {
 247                         .base   = EXYNOS4_GPZ(0),
 248                         .ngpio  = EXYNOS4_GPIO_Z_NR,
 249                         .label  = "GPZ",
 250                 },
 251         },
 252 };
 253
 254 static __init int exynos4_gpiolib_init(void)
 255 {
 256         struct s3c_gpio_chip *chip;
 257         int i;
 258         int nr_chips;
 259
 260         /* GPIO part 1 */
 261
 262         chip = exynos4_gpio_part1_4bit;
 263         nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
 264
 265         for (i = 0; i < nr_chips; i++, chip++) {
 266                 if (chip->config == NULL)
 267                         chip->config = &gpio_cfg;
 268                 if (chip->base == NULL)
 269                         chip->base = S5P_VA_GPIO1 + (i) * 0x20;
 270         }
 271
 272         samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
 273
 274         /* GPIO part 2 */
 275
 276         chip = exynos4_gpio_part2_4bit;
 277         nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
 278
 279         for (i = 0; i < nr_chips; i++, chip++) {
 280                 if (chip->config == NULL)
 281                         chip->config = &gpio_cfg;
 282                 if (chip->base == NULL)
 283                         chip->base = S5P_VA_GPIO2 + (i) * 0x20;
 284         }
 285
 286         samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
 287
 288         /* GPIO part 3 */
 289
 290         chip = exynos4_gpio_part3_4bit;
 291         nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
 292
 293         for (i = 0; i < nr_chips; i++, chip++) {
 294                 if (chip->config == NULL)
 295                         chip->config = &gpio_cfg;
 296                 if (chip->base == NULL)
 297                         chip->base = S5P_VA_GPIO3 + (i) * 0x20;
 298         }
 299
 300         samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
 301
 302         return 0;
 303 }
 304 core_initcall(exynos4_gpiolib_init);