arch/arm/mach-exynos4/cpu.c

   1 /* linux/arch/arm/mach-exynos4/cpu.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/sched.h>
  12 #include <linux/sysdev.h>
  13
  14 #include <asm/mach/map.h>
  15 #include <asm/mach/irq.h>
  16
  17 #include <asm/proc-fns.h>
  18 #include <asm/hardware/cache-l2x0.h>
  19
  20 #include <plat/cpu.h>
  21 #include <plat/clock.h>
  22 #include <plat/exynos4.h>
  23 #include <plat/sdhci.h>
  24
  25 #include <mach/regs-irq.h>
  26
  27 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
  28                          unsigned int irq_start);
  29 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
  30
  31 /* Initial IO mappings */
  32 static struct map_desc exynos4_iodesc[] __initdata = {
  33         {
  34                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
  35                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
  36                 .length         = SZ_4K,
  37                 .type           = MT_DEVICE,
  38         }, {
  39                 .virtual        = (unsigned long)S5P_VA_CMU,
  40                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
  41                 .length         = SZ_128K,
  42                 .type           = MT_DEVICE,
  43         }, {
  44                 .virtual        = (unsigned long)S5P_VA_PMU,
  45                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
  46                 .length         = SZ_64K,
  47                 .type           = MT_DEVICE,
  48         }, {
  49                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  50                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  51                 .length         = SZ_4K,
  52                 .type           = MT_DEVICE,
  53         }, {
  54                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  55                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  56                 .length         = SZ_8K,
  57                 .type           = MT_DEVICE,
  58         }, {
  59                 .virtual        = (unsigned long)S5P_VA_L2CC,
  60                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
  61                 .length         = SZ_4K,
  62                 .type           = MT_DEVICE,
  63         }, {
  64                 .virtual        = (unsigned long)S5P_VA_GPIO1,
  65                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
  66                 .length         = SZ_4K,
  67                 .type           = MT_DEVICE,
  68         }, {
  69                 .virtual        = (unsigned long)S5P_VA_GPIO2,
  70                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
  71                 .length         = SZ_4K,
  72                 .type           = MT_DEVICE,
  73         }, {
  74                 .virtual        = (unsigned long)S5P_VA_GPIO3,
  75                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
  76                 .length         = SZ_256,
  77                 .type           = MT_DEVICE,
  78         }, {
  79                 .virtual        = (unsigned long)S5P_VA_DMC0,
  80                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
  81                 .length         = SZ_4K,
  82                 .type           = MT_DEVICE,
  83         }, {
  84                 .virtual        = (unsigned long)S3C_VA_UART,
  85                 .pfn            = __phys_to_pfn(S3C_PA_UART),
  86                 .length         = SZ_512K,
  87                 .type           = MT_DEVICE,
  88         }, {
  89                 .virtual        = (unsigned long)S5P_VA_SROMC,
  90                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
  91                 .length         = SZ_4K,
  92                 .type           = MT_DEVICE,
  93         },
  94 };
  95
  96 static void exynos4_idle(void)
  97 {
  98         if (!need_resched())
  99                 cpu_do_idle();
 100
 101         local_irq_enable();
 102 }
 103
 104 /*
 105  * exynos4_map_io
 106  *
 107  * register the standard cpu IO areas
 108  */
 109 void __init exynos4_map_io(void)
 110 {
 111         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 112
 113         /* initialize device information early */
 114         exynos4_default_sdhci0();
 115         exynos4_default_sdhci1();
 116         exynos4_default_sdhci2();
 117         exynos4_default_sdhci3();
 118 }
 119
 120 void __init exynos4_init_clocks(int xtal)
 121 {
 122         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 123
 124         s3c24xx_register_baseclocks(xtal);
 125         s5p_register_clocks(xtal);
 126         exynos4_register_clocks();
 127         exynos4_setup_clocks();
 128 }
 129
 130 void __init exynos4_init_irq(void)
 131 {
 132         int irq;
 133
 134         gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 135
 136         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 137
 138                 /*
 139                  * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
 140                  * connected to the interrupt combiner. These irqs
 141                  * should be initialized to support cascade interrupt.
 142                  */
 143                 if ((irq >= 40) && !(irq == 51) && !(irq == 53))
 144                         continue;
 145
 146                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 147                                 COMBINER_IRQ(irq, 0));
 148                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 149         }
 150
 151         /* The parameters of s5p_init_irq() are for VIC init.
 152          * Theses parameters should be NULL and 0 because EXYNOS4
 153          * uses GIC instead of VIC.
 154          */
 155         s5p_init_irq(NULL, 0);
 156 }
 157
 158 struct sysdev_class exynos4_sysclass = {
 159         .name   = "exynos4-core",
 160 };
 161
 162 static struct sys_device exynos4_sysdev = {
 163         .cls    = &exynos4_sysclass,
 164 };
 165
 166 static int __init exynos4_core_init(void)
 167 {
 168         return sysdev_class_register(&exynos4_sysclass);
 169 }
 170
 171 core_initcall(exynos4_core_init);
 172
 173 #ifdef CONFIG_CACHE_L2X0
 174 static int __init exynos4_l2x0_cache_init(void)
 175 {
 176         /* TAG, Data Latency Control: 2cycle */
 177         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 178         __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 179
 180         /* L2X0 Prefetch Control */
 181         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 182
 183         /* L2X0 Power Control */
 184         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 185                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 186
 187         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 188
 189         return 0;
 190 }
 191
 192 early_initcall(exynos4_l2x0_cache_init);
 193 #endif
 194
 195 int __init exynos4_init(void)
 196 {
 197         printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
 198
 199         /* set idle function */
 200         pm_idle = exynos4_idle;
 201
 202         return sysdev_register(&exynos4_sysdev);
 203 }