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atmel-mci: Driver for Atmel on-chip MMC controllers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / avr32 / mach-at32ap / at32ap700x.c
blob021d5121718469387fc1c4d95dd797a12f40bb3b
1 /*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/fb.h>
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/spi/spi.h>
15 #include <linux/usb/atmel_usba_udc.h>
16
17 #include <asm/atmel-mci.h>
18 #include <asm/io.h>
19 #include <asm/irq.h>
20
21 #include <asm/arch/at32ap700x.h>
22 #include <asm/arch/board.h>
23 #include <asm/arch/portmux.h>
24 #include <asm/arch/sram.h>
25
26 #include <video/atmel_lcdc.h>
27
28 #include "clock.h"
29 #include "hmatrix.h"
30 #include "pio.h"
31 #include "pm.h"
32
33
34 #define PBMEM(base) \
35 { \
36 .start = base, \
37 .end = base + 0x3ff, \
38 .flags = IORESOURCE_MEM, \
39 }
40 #define IRQ(num) \
41 { \
42 .start = num, \
43 .end = num, \
44 .flags = IORESOURCE_IRQ, \
45 }
46 #define NAMED_IRQ(num, _name) \
47 { \
48 .start = num, \
49 .end = num, \
50 .name = _name, \
51 .flags = IORESOURCE_IRQ, \
52 }
53
54 /* REVISIT these assume *every* device supports DMA, but several
55 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
56 */
57 #define DEFINE_DEV(_name, _id) \
58 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
59 static struct platform_device _name##_id##_device = { \
60 .name = #_name, \
61 .id = _id, \
62 .dev = { \
63 .dma_mask = &_name##_id##_dma_mask, \
64 .coherent_dma_mask = DMA_32BIT_MASK, \
65 }, \
66 .resource = _name##_id##_resource, \
67 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
68 }
69 #define DEFINE_DEV_DATA(_name, _id) \
70 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
71 static struct platform_device _name##_id##_device = { \
72 .name = #_name, \
73 .id = _id, \
74 .dev = { \
75 .dma_mask = &_name##_id##_dma_mask, \
76 .platform_data = &_name##_id##_data, \
77 .coherent_dma_mask = DMA_32BIT_MASK, \
78 }, \
79 .resource = _name##_id##_resource, \
80 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
81 }
82
83 #define select_peripheral(pin, periph, flags) \
84 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
85
86 #define DEV_CLK(_name, devname, bus, _index) \
87 static struct clk devname##_##_name = { \
88 .name = #_name, \
89 .dev = &devname##_device.dev, \
90 .parent = &bus##_clk, \
91 .mode = bus##_clk_mode, \
92 .get_rate = bus##_clk_get_rate, \
93 .index = _index, \
94 }
95
96 static DEFINE_SPINLOCK(pm_lock);
97
98 static struct clk osc0;
99 static struct clk osc1;
100
101 static unsigned long osc_get_rate(struct clk *clk)
102 {
103 return at32_board_osc_rates[clk->index];
104 }
105
106 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
107 {
108 unsigned long div, mul, rate;
109
110 div = PM_BFEXT(PLLDIV, control) + 1;
111 mul = PM_BFEXT(PLLMUL, control) + 1;
112
113 rate = clk->parent->get_rate(clk->parent);
114 rate = (rate + div / 2) / div;
115 rate *= mul;
116
117 return rate;
118 }
119
120 static long pll_set_rate(struct clk *clk, unsigned long rate,
121 u32 *pll_ctrl)
122 {
123 unsigned long mul;
124 unsigned long mul_best_fit = 0;
125 unsigned long div;
126 unsigned long div_min;
127 unsigned long div_max;
128 unsigned long div_best_fit = 0;
129 unsigned long base;
130 unsigned long pll_in;
131 unsigned long actual = 0;
132 unsigned long rate_error;
133 unsigned long rate_error_prev = ~0UL;
134 u32 ctrl;
135
136 /* Rate must be between 80 MHz and 200 Mhz. */
137 if (rate < 80000000UL || rate > 200000000UL)
138 return -EINVAL;
139
140 ctrl = PM_BF(PLLOPT, 4);
141 base = clk->parent->get_rate(clk->parent);
142
143 /* PLL input frequency must be between 6 MHz and 32 MHz. */
144 div_min = DIV_ROUND_UP(base, 32000000UL);
145 div_max = base / 6000000UL;
146
147 if (div_max < div_min)
148 return -EINVAL;
149
150 for (div = div_min; div <= div_max; div++) {
151 pll_in = (base + div / 2) / div;
152 mul = (rate + pll_in / 2) / pll_in;
153
154 if (mul == 0)
155 continue;
156
157 actual = pll_in * mul;
158 rate_error = abs(actual - rate);
159
160 if (rate_error < rate_error_prev) {
161 mul_best_fit = mul;
162 div_best_fit = div;
163 rate_error_prev = rate_error;
164 }
165
166 if (rate_error == 0)
167 break;
168 }
169
170 if (div_best_fit == 0)
171 return -EINVAL;
172
173 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
174 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
175 ctrl |= PM_BF(PLLCOUNT, 16);
176
177 if (clk->parent == &osc1)
178 ctrl |= PM_BIT(PLLOSC);
179
180 *pll_ctrl = ctrl;
181
182 return actual;
183 }
184
185 static unsigned long pll0_get_rate(struct clk *clk)
186 {
187 u32 control;
188
189 control = pm_readl(PLL0);
190
191 return pll_get_rate(clk, control);
192 }
193
194 static void pll1_mode(struct clk *clk, int enabled)
195 {
196 unsigned long timeout;
197 u32 status;
198 u32 ctrl;
199
200 ctrl = pm_readl(PLL1);
201
202 if (enabled) {
203 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
204 pr_debug("clk %s: failed to enable, rate not set\n",
205 clk->name);
206 return;
207 }
208
209 ctrl |= PM_BIT(PLLEN);
210 pm_writel(PLL1, ctrl);
211
212 /* Wait for PLL lock. */
213 for (timeout = 10000; timeout; timeout--) {
214 status = pm_readl(ISR);
215 if (status & PM_BIT(LOCK1))
216 break;
217 udelay(10);
218 }
219
220 if (!(status & PM_BIT(LOCK1)))
221 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
222 clk->name);
223 } else {
224 ctrl &= ~PM_BIT(PLLEN);
225 pm_writel(PLL1, ctrl);
226 }
227 }
228
229 static unsigned long pll1_get_rate(struct clk *clk)
230 {
231 u32 control;
232
233 control = pm_readl(PLL1);
234
235 return pll_get_rate(clk, control);
236 }
237
238 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
239 {
240 u32 ctrl = 0;
241 unsigned long actual_rate;
242
243 actual_rate = pll_set_rate(clk, rate, &ctrl);
244
245 if (apply) {
246 if (actual_rate != rate)
247 return -EINVAL;
248 if (clk->users > 0)
249 return -EBUSY;
250 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
251 clk->name, rate, actual_rate);
252 pm_writel(PLL1, ctrl);
253 }
254
255 return actual_rate;
256 }
257
258 static int pll1_set_parent(struct clk *clk, struct clk *parent)
259 {
260 u32 ctrl;
261
262 if (clk->users > 0)
263 return -EBUSY;
264
265 ctrl = pm_readl(PLL1);
266 WARN_ON(ctrl & PM_BIT(PLLEN));
267
268 if (parent == &osc0)
269 ctrl &= ~PM_BIT(PLLOSC);
270 else if (parent == &osc1)
271 ctrl |= PM_BIT(PLLOSC);
272 else
273 return -EINVAL;
274
275 pm_writel(PLL1, ctrl);
276 clk->parent = parent;
277
278 return 0;
279 }
280
281 /*
282 * The AT32AP7000 has five primary clock sources: One 32kHz
283 * oscillator, two crystal oscillators and two PLLs.
284 */
285 static struct clk osc32k = {
286 .name = "osc32k",
287 .get_rate = osc_get_rate,
288 .users = 1,
289 .index = 0,
290 };
291 static struct clk osc0 = {
292 .name = "osc0",
293 .get_rate = osc_get_rate,
294 .users = 1,
295 .index = 1,
296 };
297 static struct clk osc1 = {
298 .name = "osc1",
299 .get_rate = osc_get_rate,
300 .index = 2,
301 };
302 static struct clk pll0 = {
303 .name = "pll0",
304 .get_rate = pll0_get_rate,
305 .parent = &osc0,
306 };
307 static struct clk pll1 = {
308 .name = "pll1",
309 .mode = pll1_mode,
310 .get_rate = pll1_get_rate,
311 .set_rate = pll1_set_rate,
312 .set_parent = pll1_set_parent,
313 .parent = &osc0,
314 };
315
316 /*
317 * The main clock can be either osc0 or pll0. The boot loader may
318 * have chosen one for us, so we don't really know which one until we
319 * have a look at the SM.
320 */
321 static struct clk *main_clock;
322
323 /*
324 * Synchronous clocks are generated from the main clock. The clocks
325 * must satisfy the constraint
326 * fCPU >= fHSB >= fPB
327 * i.e. each clock must not be faster than its parent.
328 */
329 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
330 {
331 return main_clock->get_rate(main_clock) >> shift;
332 };
333
334 static void cpu_clk_mode(struct clk *clk, int enabled)
335 {
336 unsigned long flags;
337 u32 mask;
338
339 spin_lock_irqsave(&pm_lock, flags);
340 mask = pm_readl(CPU_MASK);
341 if (enabled)
342 mask |= 1 << clk->index;
343 else
344 mask &= ~(1 << clk->index);
345 pm_writel(CPU_MASK, mask);
346 spin_unlock_irqrestore(&pm_lock, flags);
347 }
348
349 static unsigned long cpu_clk_get_rate(struct clk *clk)
350 {
351 unsigned long cksel, shift = 0;
352
353 cksel = pm_readl(CKSEL);
354 if (cksel & PM_BIT(CPUDIV))
355 shift = PM_BFEXT(CPUSEL, cksel) + 1;
356
357 return bus_clk_get_rate(clk, shift);
358 }
359
360 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
361 {
362 u32 control;
363 unsigned long parent_rate, child_div, actual_rate, div;
364
365 parent_rate = clk->parent->get_rate(clk->parent);
366 control = pm_readl(CKSEL);
367
368 if (control & PM_BIT(HSBDIV))
369 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
370 else
371 child_div = 1;
372
373 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
374 actual_rate = parent_rate;
375 control &= ~PM_BIT(CPUDIV);
376 } else {
377 unsigned int cpusel;
378 div = (parent_rate + rate / 2) / rate;
379 if (div > child_div)
380 div = child_div;
381 cpusel = (div > 1) ? (fls(div) - 2) : 0;
382 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
383 actual_rate = parent_rate / (1 << (cpusel + 1));
384 }
385
386 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
387 clk->name, rate, actual_rate);
388
389 if (apply)
390 pm_writel(CKSEL, control);
391
392 return actual_rate;
393 }
394
395 static void hsb_clk_mode(struct clk *clk, int enabled)
396 {
397 unsigned long flags;
398 u32 mask;
399
400 spin_lock_irqsave(&pm_lock, flags);
401 mask = pm_readl(HSB_MASK);
402 if (enabled)
403 mask |= 1 << clk->index;
404 else
405 mask &= ~(1 << clk->index);
406 pm_writel(HSB_MASK, mask);
407 spin_unlock_irqrestore(&pm_lock, flags);
408 }
409
410 static unsigned long hsb_clk_get_rate(struct clk *clk)
411 {
412 unsigned long cksel, shift = 0;
413
414 cksel = pm_readl(CKSEL);
415 if (cksel & PM_BIT(HSBDIV))
416 shift = PM_BFEXT(HSBSEL, cksel) + 1;
417
418 return bus_clk_get_rate(clk, shift);
419 }
420
421 static void pba_clk_mode(struct clk *clk, int enabled)
422 {
423 unsigned long flags;
424 u32 mask;
425
426 spin_lock_irqsave(&pm_lock, flags);
427 mask = pm_readl(PBA_MASK);
428 if (enabled)
429 mask |= 1 << clk->index;
430 else
431 mask &= ~(1 << clk->index);
432 pm_writel(PBA_MASK, mask);
433 spin_unlock_irqrestore(&pm_lock, flags);
434 }
435
436 static unsigned long pba_clk_get_rate(struct clk *clk)
437 {
438 unsigned long cksel, shift = 0;
439
440 cksel = pm_readl(CKSEL);
441 if (cksel & PM_BIT(PBADIV))
442 shift = PM_BFEXT(PBASEL, cksel) + 1;
443
444 return bus_clk_get_rate(clk, shift);
445 }
446
447 static void pbb_clk_mode(struct clk *clk, int enabled)
448 {
449 unsigned long flags;
450 u32 mask;
451
452 spin_lock_irqsave(&pm_lock, flags);
453 mask = pm_readl(PBB_MASK);
454 if (enabled)
455 mask |= 1 << clk->index;
456 else
457 mask &= ~(1 << clk->index);
458 pm_writel(PBB_MASK, mask);
459 spin_unlock_irqrestore(&pm_lock, flags);
460 }
461
462 static unsigned long pbb_clk_get_rate(struct clk *clk)
463 {
464 unsigned long cksel, shift = 0;
465
466 cksel = pm_readl(CKSEL);
467 if (cksel & PM_BIT(PBBDIV))
468 shift = PM_BFEXT(PBBSEL, cksel) + 1;
469
470 return bus_clk_get_rate(clk, shift);
471 }
472
473 static struct clk cpu_clk = {
474 .name = "cpu",
475 .get_rate = cpu_clk_get_rate,
476 .set_rate = cpu_clk_set_rate,
477 .users = 1,
478 };
479 static struct clk hsb_clk = {
480 .name = "hsb",
481 .parent = &cpu_clk,
482 .get_rate = hsb_clk_get_rate,
483 };
484 static struct clk pba_clk = {
485 .name = "pba",
486 .parent = &hsb_clk,
487 .mode = hsb_clk_mode,
488 .get_rate = pba_clk_get_rate,
489 .index = 1,
490 };
491 static struct clk pbb_clk = {
492 .name = "pbb",
493 .parent = &hsb_clk,
494 .mode = hsb_clk_mode,
495 .get_rate = pbb_clk_get_rate,
496 .users = 1,
497 .index = 2,
498 };
499
500 /* --------------------------------------------------------------------
501 * Generic Clock operations
502 * -------------------------------------------------------------------- */
503
504 static void genclk_mode(struct clk *clk, int enabled)
505 {
506 u32 control;
507
508 control = pm_readl(GCCTRL(clk->index));
509 if (enabled)
510 control |= PM_BIT(CEN);
511 else
512 control &= ~PM_BIT(CEN);
513 pm_writel(GCCTRL(clk->index), control);
514 }
515
516 static unsigned long genclk_get_rate(struct clk *clk)
517 {
518 u32 control;
519 unsigned long div = 1;
520
521 control = pm_readl(GCCTRL(clk->index));
522 if (control & PM_BIT(DIVEN))
523 div = 2 * (PM_BFEXT(DIV, control) + 1);
524
525 return clk->parent->get_rate(clk->parent) / div;
526 }
527
528 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
529 {
530 u32 control;
531 unsigned long parent_rate, actual_rate, div;
532
533 parent_rate = clk->parent->get_rate(clk->parent);
534 control = pm_readl(GCCTRL(clk->index));
535
536 if (rate > 3 * parent_rate / 4) {
537 actual_rate = parent_rate;
538 control &= ~PM_BIT(DIVEN);
539 } else {
540 div = (parent_rate + rate) / (2 * rate) - 1;
541 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
542 actual_rate = parent_rate / (2 * (div + 1));
543 }
544
545 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
546 clk->name, rate, actual_rate);
547
548 if (apply)
549 pm_writel(GCCTRL(clk->index), control);
550
551 return actual_rate;
552 }
553
554 int genclk_set_parent(struct clk *clk, struct clk *parent)
555 {
556 u32 control;
557
558 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
559 clk->name, parent->name, clk->parent->name);
560
561 control = pm_readl(GCCTRL(clk->index));
562
563 if (parent == &osc1 || parent == &pll1)
564 control |= PM_BIT(OSCSEL);
565 else if (parent == &osc0 || parent == &pll0)
566 control &= ~PM_BIT(OSCSEL);
567 else
568 return -EINVAL;
569
570 if (parent == &pll0 || parent == &pll1)
571 control |= PM_BIT(PLLSEL);
572 else
573 control &= ~PM_BIT(PLLSEL);
574
575 pm_writel(GCCTRL(clk->index), control);
576 clk->parent = parent;
577
578 return 0;
579 }
580
581 static void __init genclk_init_parent(struct clk *clk)
582 {
583 u32 control;
584 struct clk *parent;
585
586 BUG_ON(clk->index > 7);
587
588 control = pm_readl(GCCTRL(clk->index));
589 if (control & PM_BIT(OSCSEL))
590 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
591 else
592 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
593
594 clk->parent = parent;
595 }
596
597 /* --------------------------------------------------------------------
598 * System peripherals
599 * -------------------------------------------------------------------- */
600 static struct resource at32_pm0_resource[] = {
601 {
602 .start = 0xfff00000,
603 .end = 0xfff0007f,
604 .flags = IORESOURCE_MEM,
605 },
606 IRQ(20),
607 };
608
609 static struct resource at32ap700x_rtc0_resource[] = {
610 {
611 .start = 0xfff00080,
612 .end = 0xfff000af,
613 .flags = IORESOURCE_MEM,
614 },
615 IRQ(21),
616 };
617
618 static struct resource at32_wdt0_resource[] = {
619 {
620 .start = 0xfff000b0,
621 .end = 0xfff000cf,
622 .flags = IORESOURCE_MEM,
623 },
624 };
625
626 static struct resource at32_eic0_resource[] = {
627 {
628 .start = 0xfff00100,
629 .end = 0xfff0013f,
630 .flags = IORESOURCE_MEM,
631 },
632 IRQ(19),
633 };
634
635 DEFINE_DEV(at32_pm, 0);
636 DEFINE_DEV(at32ap700x_rtc, 0);
637 DEFINE_DEV(at32_wdt, 0);
638 DEFINE_DEV(at32_eic, 0);
639
640 /*
641 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
642 * is always running.
643 */
644 static struct clk at32_pm_pclk = {
645 .name = "pclk",
646 .dev = &at32_pm0_device.dev,
647 .parent = &pbb_clk,
648 .mode = pbb_clk_mode,
649 .get_rate = pbb_clk_get_rate,
650 .users = 1,
651 .index = 0,
652 };
653
654 static struct resource intc0_resource[] = {
655 PBMEM(0xfff00400),
656 };
657 struct platform_device at32_intc0_device = {
658 .name = "intc",
659 .id = 0,
660 .resource = intc0_resource,
661 .num_resources = ARRAY_SIZE(intc0_resource),
662 };
663 DEV_CLK(pclk, at32_intc0, pbb, 1);
664
665 static struct clk ebi_clk = {
666 .name = "ebi",
667 .parent = &hsb_clk,
668 .mode = hsb_clk_mode,
669 .get_rate = hsb_clk_get_rate,
670 .users = 1,
671 };
672 static struct clk hramc_clk = {
673 .name = "hramc",
674 .parent = &hsb_clk,
675 .mode = hsb_clk_mode,
676 .get_rate = hsb_clk_get_rate,
677 .users = 1,
678 .index = 3,
679 };
680 static struct clk sdramc_clk = {
681 .name = "sdramc_clk",
682 .parent = &pbb_clk,
683 .mode = pbb_clk_mode,
684 .get_rate = pbb_clk_get_rate,
685 .users = 1,
686 .index = 14,
687 };
688
689 static struct resource smc0_resource[] = {
690 PBMEM(0xfff03400),
691 };
692 DEFINE_DEV(smc, 0);
693 DEV_CLK(pclk, smc0, pbb, 13);
694 DEV_CLK(mck, smc0, hsb, 0);
695
696 static struct platform_device pdc_device = {
697 .name = "pdc",
698 .id = 0,
699 };
700 DEV_CLK(hclk, pdc, hsb, 4);
701 DEV_CLK(pclk, pdc, pba, 16);
702
703 static struct clk pico_clk = {
704 .name = "pico",
705 .parent = &cpu_clk,
706 .mode = cpu_clk_mode,
707 .get_rate = cpu_clk_get_rate,
708 .users = 1,
709 };
710
711 static struct resource dmaca0_resource[] = {
712 {
713 .start = 0xff200000,
714 .end = 0xff20ffff,
715 .flags = IORESOURCE_MEM,
716 },
717 IRQ(2),
718 };
719 DEFINE_DEV(dmaca, 0);
720 DEV_CLK(hclk, dmaca0, hsb, 10);
721
722 /* --------------------------------------------------------------------
723 * HMATRIX
724 * -------------------------------------------------------------------- */
725
726 static struct clk hmatrix_clk = {
727 .name = "hmatrix_clk",
728 .parent = &pbb_clk,
729 .mode = pbb_clk_mode,
730 .get_rate = pbb_clk_get_rate,
731 .index = 2,
732 .users = 1,
733 };
734 #define HMATRIX_BASE ((void __iomem *)0xfff00800)
735
736 #define hmatrix_readl(reg) \
737 __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
738 #define hmatrix_writel(reg,value) \
739 __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
740
741 /*
742 * Set bits in the HMATRIX Special Function Register (SFR) used by the
743 * External Bus Interface (EBI). This can be used to enable special
744 * features like CompactFlash support, NAND Flash support, etc. on
745 * certain chipselects.
746 */
747 static inline void set_ebi_sfr_bits(u32 mask)
748 {
749 u32 sfr;
750
751 clk_enable(&hmatrix_clk);
752 sfr = hmatrix_readl(SFR4);
753 sfr |= mask;
754 hmatrix_writel(SFR4, sfr);
755 clk_disable(&hmatrix_clk);
756 }
757
758 /* --------------------------------------------------------------------
759 * Timer/Counter (TC)
760 * -------------------------------------------------------------------- */
761
762 static struct resource at32_tcb0_resource[] = {
763 PBMEM(0xfff00c00),
764 IRQ(22),
765 };
766 static struct platform_device at32_tcb0_device = {
767 .name = "atmel_tcb",
768 .id = 0,
769 .resource = at32_tcb0_resource,
770 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
771 };
772 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
773
774 static struct resource at32_tcb1_resource[] = {
775 PBMEM(0xfff01000),
776 IRQ(23),
777 };
778 static struct platform_device at32_tcb1_device = {
779 .name = "atmel_tcb",
780 .id = 1,
781 .resource = at32_tcb1_resource,
782 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
783 };
784 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
785
786 /* --------------------------------------------------------------------
787 * PIO
788 * -------------------------------------------------------------------- */
789
790 static struct resource pio0_resource[] = {
791 PBMEM(0xffe02800),
792 IRQ(13),
793 };
794 DEFINE_DEV(pio, 0);
795 DEV_CLK(mck, pio0, pba, 10);
796
797 static struct resource pio1_resource[] = {
798 PBMEM(0xffe02c00),
799 IRQ(14),
800 };
801 DEFINE_DEV(pio, 1);
802 DEV_CLK(mck, pio1, pba, 11);
803
804 static struct resource pio2_resource[] = {
805 PBMEM(0xffe03000),
806 IRQ(15),
807 };
808 DEFINE_DEV(pio, 2);
809 DEV_CLK(mck, pio2, pba, 12);
810
811 static struct resource pio3_resource[] = {
812 PBMEM(0xffe03400),
813 IRQ(16),
814 };
815 DEFINE_DEV(pio, 3);
816 DEV_CLK(mck, pio3, pba, 13);
817
818 static struct resource pio4_resource[] = {
819 PBMEM(0xffe03800),
820 IRQ(17),
821 };
822 DEFINE_DEV(pio, 4);
823 DEV_CLK(mck, pio4, pba, 14);
824
825 void __init at32_add_system_devices(void)
826 {
827 platform_device_register(&at32_pm0_device);
828 platform_device_register(&at32_intc0_device);
829 platform_device_register(&at32ap700x_rtc0_device);
830 platform_device_register(&at32_wdt0_device);
831 platform_device_register(&at32_eic0_device);
832 platform_device_register(&smc0_device);
833 platform_device_register(&pdc_device);
834 platform_device_register(&dmaca0_device);
835
836 platform_device_register(&at32_tcb0_device);
837 platform_device_register(&at32_tcb1_device);
838
839 platform_device_register(&pio0_device);
840 platform_device_register(&pio1_device);
841 platform_device_register(&pio2_device);
842 platform_device_register(&pio3_device);
843 platform_device_register(&pio4_device);
844 }
845
846 /* --------------------------------------------------------------------
847 * PSIF
848 * -------------------------------------------------------------------- */
849 static struct resource atmel_psif0_resource[] __initdata = {
850 {
851 .start = 0xffe03c00,
852 .end = 0xffe03cff,
853 .flags = IORESOURCE_MEM,
854 },
855 IRQ(18),
856 };
857 static struct clk atmel_psif0_pclk = {
858 .name = "pclk",
859 .parent = &pba_clk,
860 .mode = pba_clk_mode,
861 .get_rate = pba_clk_get_rate,
862 .index = 15,
863 };
864
865 static struct resource atmel_psif1_resource[] __initdata = {
866 {
867 .start = 0xffe03d00,
868 .end = 0xffe03dff,
869 .flags = IORESOURCE_MEM,
870 },
871 IRQ(18),
872 };
873 static struct clk atmel_psif1_pclk = {
874 .name = "pclk",
875 .parent = &pba_clk,
876 .mode = pba_clk_mode,
877 .get_rate = pba_clk_get_rate,
878 .index = 15,
879 };
880
881 struct platform_device *__init at32_add_device_psif(unsigned int id)
882 {
883 struct platform_device *pdev;
884
885 if (!(id == 0 || id == 1))
886 return NULL;
887
888 pdev = platform_device_alloc("atmel_psif", id);
889 if (!pdev)
890 return NULL;
891
892 switch (id) {
893 case 0:
894 if (platform_device_add_resources(pdev, atmel_psif0_resource,
895 ARRAY_SIZE(atmel_psif0_resource)))
896 goto err_add_resources;
897 atmel_psif0_pclk.dev = &pdev->dev;
898 select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
899 select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
900 break;
901 case 1:
902 if (platform_device_add_resources(pdev, atmel_psif1_resource,
903 ARRAY_SIZE(atmel_psif1_resource)))
904 goto err_add_resources;
905 atmel_psif1_pclk.dev = &pdev->dev;
906 select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
907 select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
908 break;
909 default:
910 return NULL;
911 }
912
913 platform_device_add(pdev);
914 return pdev;
915
916 err_add_resources:
917 platform_device_put(pdev);
918 return NULL;
919 }
920
921 /* --------------------------------------------------------------------
922 * USART
923 * -------------------------------------------------------------------- */
924
925 static struct atmel_uart_data atmel_usart0_data = {
926 .use_dma_tx = 1,
927 .use_dma_rx = 1,
928 };
929 static struct resource atmel_usart0_resource[] = {
930 PBMEM(0xffe00c00),
931 IRQ(6),
932 };
933 DEFINE_DEV_DATA(atmel_usart, 0);
934 DEV_CLK(usart, atmel_usart0, pba, 3);
935
936 static struct atmel_uart_data atmel_usart1_data = {
937 .use_dma_tx = 1,
938 .use_dma_rx = 1,
939 };
940 static struct resource atmel_usart1_resource[] = {
941 PBMEM(0xffe01000),
942 IRQ(7),
943 };
944 DEFINE_DEV_DATA(atmel_usart, 1);
945 DEV_CLK(usart, atmel_usart1, pba, 4);
946
947 static struct atmel_uart_data atmel_usart2_data = {
948 .use_dma_tx = 1,
949 .use_dma_rx = 1,
950 };
951 static struct resource atmel_usart2_resource[] = {
952 PBMEM(0xffe01400),
953 IRQ(8),
954 };
955 DEFINE_DEV_DATA(atmel_usart, 2);
956 DEV_CLK(usart, atmel_usart2, pba, 5);
957
958 static struct atmel_uart_data atmel_usart3_data = {
959 .use_dma_tx = 1,
960 .use_dma_rx = 1,
961 };
962 static struct resource atmel_usart3_resource[] = {
963 PBMEM(0xffe01800),
964 IRQ(9),
965 };
966 DEFINE_DEV_DATA(atmel_usart, 3);
967 DEV_CLK(usart, atmel_usart3, pba, 6);
968
969 static inline void configure_usart0_pins(void)
970 {
971 select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
972 select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
973 }
974
975 static inline void configure_usart1_pins(void)
976 {
977 select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
978 select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
979 }
980
981 static inline void configure_usart2_pins(void)
982 {
983 select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
984 select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
985 }
986
987 static inline void configure_usart3_pins(void)
988 {
989 select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
990 select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
991 }
992
993 static struct platform_device *__initdata at32_usarts[4];
994
995 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
996 {
997 struct platform_device *pdev;
998
999 switch (hw_id) {
1000 case 0:
1001 pdev = &atmel_usart0_device;
1002 configure_usart0_pins();
1003 break;
1004 case 1:
1005 pdev = &atmel_usart1_device;
1006 configure_usart1_pins();
1007 break;
1008 case 2:
1009 pdev = &atmel_usart2_device;
1010 configure_usart2_pins();
1011 break;
1012 case 3:
1013 pdev = &atmel_usart3_device;
1014 configure_usart3_pins();
1015 break;
1016 default:
1017 return;
1018 }
1019
1020 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1021 /* Addresses in the P4 segment are permanently mapped 1:1 */
1022 struct atmel_uart_data *data = pdev->dev.platform_data;
1023 data->regs = (void __iomem *)pdev->resource[0].start;
1024 }
1025
1026 pdev->id = line;
1027 at32_usarts[line] = pdev;
1028 }
1029
1030 struct platform_device *__init at32_add_device_usart(unsigned int id)
1031 {
1032 platform_device_register(at32_usarts[id]);
1033 return at32_usarts[id];
1034 }
1035
1036 struct platform_device *atmel_default_console_device;
1037
1038 void __init at32_setup_serial_console(unsigned int usart_id)
1039 {
1040 atmel_default_console_device = at32_usarts[usart_id];
1041 }
1042
1043 /* --------------------------------------------------------------------
1044 * Ethernet
1045 * -------------------------------------------------------------------- */
1046
1047 #ifdef CONFIG_CPU_AT32AP7000
1048 static struct eth_platform_data macb0_data;
1049 static struct resource macb0_resource[] = {
1050 PBMEM(0xfff01800),
1051 IRQ(25),
1052 };
1053 DEFINE_DEV_DATA(macb, 0);
1054 DEV_CLK(hclk, macb0, hsb, 8);
1055 DEV_CLK(pclk, macb0, pbb, 6);
1056
1057 static struct eth_platform_data macb1_data;
1058 static struct resource macb1_resource[] = {
1059 PBMEM(0xfff01c00),
1060 IRQ(26),
1061 };
1062 DEFINE_DEV_DATA(macb, 1);
1063 DEV_CLK(hclk, macb1, hsb, 9);
1064 DEV_CLK(pclk, macb1, pbb, 7);
1065
1066 struct platform_device *__init
1067 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1068 {
1069 struct platform_device *pdev;
1070
1071 switch (id) {
1072 case 0:
1073 pdev = &macb0_device;
1074
1075 select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
1076 select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
1077 select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
1078 select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
1079 select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
1080 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
1081 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
1082 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
1083 select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
1084 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
1085
1086 if (!data->is_rmii) {
1087 select_peripheral(PC(0), PERIPH_A, 0); /* COL */
1088 select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
1089 select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
1090 select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
1091 select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
1092 select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
1093 select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
1094 select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
1095 select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
1096 }
1097 break;
1098
1099 case 1:
1100 pdev = &macb1_device;
1101
1102 select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
1103 select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
1104 select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
1105 select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
1106 select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
1107 select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
1108 select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
1109 select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
1110 select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
1111 select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
1112
1113 if (!data->is_rmii) {
1114 select_peripheral(PC(19), PERIPH_B, 0); /* COL */
1115 select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
1116 select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
1117 select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
1118 select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
1119 select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
1120 select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
1121 select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
1122 select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
1123 }
1124 break;
1125
1126 default:
1127 return NULL;
1128 }
1129
1130 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1131 platform_device_register(pdev);
1132
1133 return pdev;
1134 }
1135 #endif
1136
1137 /* --------------------------------------------------------------------
1138 * SPI
1139 * -------------------------------------------------------------------- */
1140 static struct resource atmel_spi0_resource[] = {
1141 PBMEM(0xffe00000),
1142 IRQ(3),
1143 };
1144 DEFINE_DEV(atmel_spi, 0);
1145 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1146
1147 static struct resource atmel_spi1_resource[] = {
1148 PBMEM(0xffe00400),
1149 IRQ(4),
1150 };
1151 DEFINE_DEV(atmel_spi, 1);
1152 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1153
1154 static void __init
1155 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1156 unsigned int n, const u8 *pins)
1157 {
1158 unsigned int pin, mode;
1159
1160 for (; n; n--, b++) {
1161 b->bus_num = bus_num;
1162 if (b->chip_select >= 4)
1163 continue;
1164 pin = (unsigned)b->controller_data;
1165 if (!pin) {
1166 pin = pins[b->chip_select];
1167 b->controller_data = (void *)pin;
1168 }
1169 mode = AT32_GPIOF_OUTPUT;
1170 if (!(b->mode & SPI_CS_HIGH))
1171 mode |= AT32_GPIOF_HIGH;
1172 at32_select_gpio(pin, mode);
1173 }
1174 }
1175
1176 struct platform_device *__init
1177 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1178 {
1179 /*
1180 * Manage the chipselects as GPIOs, normally using the same pins
1181 * the SPI controller expects; but boards can use other pins.
1182 */
1183 static u8 __initdata spi0_pins[] =
1184 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1185 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1186 static u8 __initdata spi1_pins[] =
1187 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1188 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1189 struct platform_device *pdev;
1190
1191 switch (id) {
1192 case 0:
1193 pdev = &atmel_spi0_device;
1194 /* pullup MISO so a level is always defined */
1195 select_peripheral(PA(0), PERIPH_A, AT32_GPIOF_PULLUP);
1196 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
1197 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
1198 at32_spi_setup_slaves(0, b, n, spi0_pins);
1199 break;
1200
1201 case 1:
1202 pdev = &atmel_spi1_device;
1203 /* pullup MISO so a level is always defined */
1204 select_peripheral(PB(0), PERIPH_B, AT32_GPIOF_PULLUP);
1205 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
1206 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
1207 at32_spi_setup_slaves(1, b, n, spi1_pins);
1208 break;
1209
1210 default:
1211 return NULL;
1212 }
1213
1214 spi_register_board_info(b, n);
1215 platform_device_register(pdev);
1216 return pdev;
1217 }
1218
1219 /* --------------------------------------------------------------------
1220 * TWI
1221 * -------------------------------------------------------------------- */
1222 static struct resource atmel_twi0_resource[] __initdata = {
1223 PBMEM(0xffe00800),
1224 IRQ(5),
1225 };
1226 static struct clk atmel_twi0_pclk = {
1227 .name = "twi_pclk",
1228 .parent = &pba_clk,
1229 .mode = pba_clk_mode,
1230 .get_rate = pba_clk_get_rate,
1231 .index = 2,
1232 };
1233
1234 struct platform_device *__init at32_add_device_twi(unsigned int id,
1235 struct i2c_board_info *b,
1236 unsigned int n)
1237 {
1238 struct platform_device *pdev;
1239
1240 if (id != 0)
1241 return NULL;
1242
1243 pdev = platform_device_alloc("atmel_twi", id);
1244 if (!pdev)
1245 return NULL;
1246
1247 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1248 ARRAY_SIZE(atmel_twi0_resource)))
1249 goto err_add_resources;
1250
1251 select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
1252 select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
1253
1254 atmel_twi0_pclk.dev = &pdev->dev;
1255
1256 if (b)
1257 i2c_register_board_info(id, b, n);
1258
1259 platform_device_add(pdev);
1260 return pdev;
1261
1262 err_add_resources:
1263 platform_device_put(pdev);
1264 return NULL;
1265 }
1266
1267 /* --------------------------------------------------------------------
1268 * MMC
1269 * -------------------------------------------------------------------- */
1270 static struct resource atmel_mci0_resource[] __initdata = {
1271 PBMEM(0xfff02400),
1272 IRQ(28),
1273 };
1274 static struct clk atmel_mci0_pclk = {
1275 .name = "mci_clk",
1276 .parent = &pbb_clk,
1277 .mode = pbb_clk_mode,
1278 .get_rate = pbb_clk_get_rate,
1279 .index = 9,
1280 };
1281
1282 struct platform_device *__init
1283 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1284 {
1285 struct mci_platform_data _data;
1286 struct platform_device *pdev;
1287 struct dw_dma_slave *dws;
1288
1289 if (id != 0)
1290 return NULL;
1291
1292 pdev = platform_device_alloc("atmel_mci", id);
1293 if (!pdev)
1294 goto fail;
1295
1296 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1297 ARRAY_SIZE(atmel_mci0_resource)))
1298 goto fail;
1299
1300 if (!data) {
1301 data = &_data;
1302 memset(data, 0, sizeof(struct mci_platform_data));
1303 }
1304
1305 if (platform_device_add_data(pdev, data,
1306 sizeof(struct mci_platform_data)))
1307 goto fail;
1308
1309 select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
1310 select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
1311 select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1312 select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1313 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1314 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1315
1316 if (data) {
1317 if (data->detect_pin != GPIO_PIN_NONE)
1318 at32_select_gpio(data->detect_pin, 0);
1319 if (data->wp_pin != GPIO_PIN_NONE)
1320 at32_select_gpio(data->wp_pin, 0);
1321 }
1322
1323 atmel_mci0_pclk.dev = &pdev->dev;
1324
1325 platform_device_add(pdev);
1326 return pdev;
1327
1328 fail:
1329 platform_device_put(pdev);
1330 return NULL;
1331 }
1332
1333 /* --------------------------------------------------------------------
1334 * LCDC
1335 * -------------------------------------------------------------------- */
1336 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1337 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1338 static struct resource atmel_lcdfb0_resource[] = {
1339 {
1340 .start = 0xff000000,
1341 .end = 0xff000fff,
1342 .flags = IORESOURCE_MEM,
1343 },
1344 IRQ(1),
1345 {
1346 /* Placeholder for pre-allocated fb memory */
1347 .start = 0x00000000,
1348 .end = 0x00000000,
1349 .flags = 0,
1350 },
1351 };
1352 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1353 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1354 static struct clk atmel_lcdfb0_pixclk = {
1355 .name = "lcdc_clk",
1356 .dev = &atmel_lcdfb0_device.dev,
1357 .mode = genclk_mode,
1358 .get_rate = genclk_get_rate,
1359 .set_rate = genclk_set_rate,
1360 .set_parent = genclk_set_parent,
1361 .index = 7,
1362 };
1363
1364 struct platform_device *__init
1365 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1366 unsigned long fbmem_start, unsigned long fbmem_len,
1367 unsigned int pin_config)
1368 {
1369 struct platform_device *pdev;
1370 struct atmel_lcdfb_info *info;
1371 struct fb_monspecs *monspecs;
1372 struct fb_videomode *modedb;
1373 unsigned int modedb_size;
1374
1375 /*
1376 * Do a deep copy of the fb data, monspecs and modedb. Make
1377 * sure all allocations are done before setting up the
1378 * portmux.
1379 */
1380 monspecs = kmemdup(data->default_monspecs,
1381 sizeof(struct fb_monspecs), GFP_KERNEL);
1382 if (!monspecs)
1383 return NULL;
1384
1385 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1386 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1387 if (!modedb)
1388 goto err_dup_modedb;
1389 monspecs->modedb = modedb;
1390
1391 switch (id) {
1392 case 0:
1393 pdev = &atmel_lcdfb0_device;
1394
1395 switch (pin_config) {
1396 case 0:
1397 select_peripheral(PC(19), PERIPH_A, 0); /* CC */
1398 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1399 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1400 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1401 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
1402 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
1403 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1404 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
1405 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
1406 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
1407 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
1408 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
1409 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1410 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1411 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1412 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
1413 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
1414 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
1415 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
1416 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
1417 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1418 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1419 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1420 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1421 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1422 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1423 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1424 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1425 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1426 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1427 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1428 break;
1429 case 1:
1430 select_peripheral(PE(0), PERIPH_B, 0); /* CC */
1431 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1432 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1433 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1434 select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */
1435 select_peripheral(PE(2), PERIPH_B, 0); /* MODE */
1436 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1437 select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */
1438 select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */
1439 select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */
1440 select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */
1441 select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */
1442 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1443 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1444 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1445 select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */
1446 select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */
1447 select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
1448 select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
1449 select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
1450 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1451 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1452 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1453 select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
1454 select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
1455 select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
1456 select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
1457 select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
1458 select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
1459 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1460 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1461 break;
1462 default:
1463 goto err_invalid_id;
1464 }
1465
1466 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1467 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1468 break;
1469
1470 default:
1471 goto err_invalid_id;
1472 }
1473
1474 if (fbmem_len) {
1475 pdev->resource[2].start = fbmem_start;
1476 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1477 pdev->resource[2].flags = IORESOURCE_MEM;
1478 }
1479
1480 info = pdev->dev.platform_data;
1481 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1482 info->default_monspecs = monspecs;
1483
1484 platform_device_register(pdev);
1485 return pdev;
1486
1487 err_invalid_id:
1488 kfree(modedb);
1489 err_dup_modedb:
1490 kfree(monspecs);
1491 return NULL;
1492 }
1493 #endif
1494
1495 /* --------------------------------------------------------------------
1496 * PWM
1497 * -------------------------------------------------------------------- */
1498 static struct resource atmel_pwm0_resource[] __initdata = {
1499 PBMEM(0xfff01400),
1500 IRQ(24),
1501 };
1502 static struct clk atmel_pwm0_mck = {
1503 .name = "pwm_clk",
1504 .parent = &pbb_clk,
1505 .mode = pbb_clk_mode,
1506 .get_rate = pbb_clk_get_rate,
1507 .index = 5,
1508 };
1509
1510 struct platform_device *__init at32_add_device_pwm(u32 mask)
1511 {
1512 struct platform_device *pdev;
1513
1514 if (!mask)
1515 return NULL;
1516
1517 pdev = platform_device_alloc("atmel_pwm", 0);
1518 if (!pdev)
1519 return NULL;
1520
1521 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1522 ARRAY_SIZE(atmel_pwm0_resource)))
1523 goto out_free_pdev;
1524
1525 if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1526 goto out_free_pdev;
1527
1528 if (mask & (1 << 0))
1529 select_peripheral(PA(28), PERIPH_A, 0);
1530 if (mask & (1 << 1))
1531 select_peripheral(PA(29), PERIPH_A, 0);
1532 if (mask & (1 << 2))
1533 select_peripheral(PA(21), PERIPH_B, 0);
1534 if (mask & (1 << 3))
1535 select_peripheral(PA(22), PERIPH_B, 0);
1536
1537 atmel_pwm0_mck.dev = &pdev->dev;
1538
1539 platform_device_add(pdev);
1540
1541 return pdev;
1542
1543 out_free_pdev:
1544 platform_device_put(pdev);
1545 return NULL;
1546 }
1547
1548 /* --------------------------------------------------------------------
1549 * SSC
1550 * -------------------------------------------------------------------- */
1551 static struct resource ssc0_resource[] = {
1552 PBMEM(0xffe01c00),
1553 IRQ(10),
1554 };
1555 DEFINE_DEV(ssc, 0);
1556 DEV_CLK(pclk, ssc0, pba, 7);
1557
1558 static struct resource ssc1_resource[] = {
1559 PBMEM(0xffe02000),
1560 IRQ(11),
1561 };
1562 DEFINE_DEV(ssc, 1);
1563 DEV_CLK(pclk, ssc1, pba, 8);
1564
1565 static struct resource ssc2_resource[] = {
1566 PBMEM(0xffe02400),
1567 IRQ(12),
1568 };
1569 DEFINE_DEV(ssc, 2);
1570 DEV_CLK(pclk, ssc2, pba, 9);
1571
1572 struct platform_device *__init
1573 at32_add_device_ssc(unsigned int id, unsigned int flags)
1574 {
1575 struct platform_device *pdev;
1576
1577 switch (id) {
1578 case 0:
1579 pdev = &ssc0_device;
1580 if (flags & ATMEL_SSC_RF)
1581 select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1582 if (flags & ATMEL_SSC_RK)
1583 select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1584 if (flags & ATMEL_SSC_TK)
1585 select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1586 if (flags & ATMEL_SSC_TF)
1587 select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1588 if (flags & ATMEL_SSC_TD)
1589 select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1590 if (flags & ATMEL_SSC_RD)
1591 select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1592 break;
1593 case 1:
1594 pdev = &ssc1_device;
1595 if (flags & ATMEL_SSC_RF)
1596 select_peripheral(PA(0), PERIPH_B, 0); /* RF */
1597 if (flags & ATMEL_SSC_RK)
1598 select_peripheral(PA(1), PERIPH_B, 0); /* RK */
1599 if (flags & ATMEL_SSC_TK)
1600 select_peripheral(PA(2), PERIPH_B, 0); /* TK */
1601 if (flags & ATMEL_SSC_TF)
1602 select_peripheral(PA(3), PERIPH_B, 0); /* TF */
1603 if (flags & ATMEL_SSC_TD)
1604 select_peripheral(PA(4), PERIPH_B, 0); /* TD */
1605 if (flags & ATMEL_SSC_RD)
1606 select_peripheral(PA(5), PERIPH_B, 0); /* RD */
1607 break;
1608 case 2:
1609 pdev = &ssc2_device;
1610 if (flags & ATMEL_SSC_TD)
1611 select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1612 if (flags & ATMEL_SSC_RD)
1613 select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1614 if (flags & ATMEL_SSC_TK)
1615 select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1616 if (flags & ATMEL_SSC_TF)
1617 select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1618 if (flags & ATMEL_SSC_RF)
1619 select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1620 if (flags & ATMEL_SSC_RK)
1621 select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1622 break;
1623 default:
1624 return NULL;
1625 }
1626
1627 platform_device_register(pdev);
1628 return pdev;
1629 }
1630
1631 /* --------------------------------------------------------------------
1632 * USB Device Controller
1633 * -------------------------------------------------------------------- */
1634 static struct resource usba0_resource[] __initdata = {
1635 {
1636 .start = 0xff300000,
1637 .end = 0xff3fffff,
1638 .flags = IORESOURCE_MEM,
1639 }, {
1640 .start = 0xfff03000,
1641 .end = 0xfff033ff,
1642 .flags = IORESOURCE_MEM,
1643 },
1644 IRQ(31),
1645 };
1646 static struct clk usba0_pclk = {
1647 .name = "pclk",
1648 .parent = &pbb_clk,
1649 .mode = pbb_clk_mode,
1650 .get_rate = pbb_clk_get_rate,
1651 .index = 12,
1652 };
1653 static struct clk usba0_hclk = {
1654 .name = "hclk",
1655 .parent = &hsb_clk,
1656 .mode = hsb_clk_mode,
1657 .get_rate = hsb_clk_get_rate,
1658 .index = 6,
1659 };
1660
1661 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1662 [idx] = { \
1663 .name = nam, \
1664 .index = idx, \
1665 .fifo_size = maxpkt, \
1666 .nr_banks = maxbk, \
1667 .can_dma = dma, \
1668 .can_isoc = isoc, \
1669 }
1670
1671 static struct usba_ep_data at32_usba_ep[] __initdata = {
1672 EP("ep0", 0, 64, 1, 0, 0),
1673 EP("ep1", 1, 512, 2, 1, 1),
1674 EP("ep2", 2, 512, 2, 1, 1),
1675 EP("ep3-int", 3, 64, 3, 1, 0),
1676 EP("ep4-int", 4, 64, 3, 1, 0),
1677 EP("ep5", 5, 1024, 3, 1, 1),
1678 EP("ep6", 6, 1024, 3, 1, 1),
1679 };
1680
1681 #undef EP
1682
1683 struct platform_device *__init
1684 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1685 {
1686 /*
1687 * pdata doesn't have room for any endpoints, so we need to
1688 * append room for the ones we need right after it.
1689 */
1690 struct {
1691 struct usba_platform_data pdata;
1692 struct usba_ep_data ep[7];
1693 } usba_data;
1694 struct platform_device *pdev;
1695
1696 if (id != 0)
1697 return NULL;
1698
1699 pdev = platform_device_alloc("atmel_usba_udc", 0);
1700 if (!pdev)
1701 return NULL;
1702
1703 if (platform_device_add_resources(pdev, usba0_resource,
1704 ARRAY_SIZE(usba0_resource)))
1705 goto out_free_pdev;
1706
1707 if (data)
1708 usba_data.pdata.vbus_pin = data->vbus_pin;
1709 else
1710 usba_data.pdata.vbus_pin = -EINVAL;
1711
1712 data = &usba_data.pdata;
1713 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1714 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1715
1716 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1717 goto out_free_pdev;
1718
1719 if (data->vbus_pin >= 0)
1720 at32_select_gpio(data->vbus_pin, 0);
1721
1722 usba0_pclk.dev = &pdev->dev;
1723 usba0_hclk.dev = &pdev->dev;
1724
1725 platform_device_add(pdev);
1726
1727 return pdev;
1728
1729 out_free_pdev:
1730 platform_device_put(pdev);
1731 return NULL;
1732 }
1733
1734 /* --------------------------------------------------------------------
1735 * IDE / CompactFlash
1736 * -------------------------------------------------------------------- */
1737 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1738 static struct resource at32_smc_cs4_resource[] __initdata = {
1739 {
1740 .start = 0x04000000,
1741 .end = 0x07ffffff,
1742 .flags = IORESOURCE_MEM,
1743 },
1744 IRQ(~0UL), /* Magic IRQ will be overridden */
1745 };
1746 static struct resource at32_smc_cs5_resource[] __initdata = {
1747 {
1748 .start = 0x20000000,
1749 .end = 0x23ffffff,
1750 .flags = IORESOURCE_MEM,
1751 },
1752 IRQ(~0UL), /* Magic IRQ will be overridden */
1753 };
1754
1755 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1756 unsigned int cs, unsigned int extint)
1757 {
1758 static unsigned int extint_pin_map[4] __initdata = {
1759 GPIO_PIN_PB(25),
1760 GPIO_PIN_PB(26),
1761 GPIO_PIN_PB(27),
1762 GPIO_PIN_PB(28),
1763 };
1764 static bool common_pins_initialized __initdata = false;
1765 unsigned int extint_pin;
1766 int ret;
1767
1768 if (extint >= ARRAY_SIZE(extint_pin_map))
1769 return -EINVAL;
1770 extint_pin = extint_pin_map[extint];
1771
1772 switch (cs) {
1773 case 4:
1774 ret = platform_device_add_resources(pdev,
1775 at32_smc_cs4_resource,
1776 ARRAY_SIZE(at32_smc_cs4_resource));
1777 if (ret)
1778 return ret;
1779
1780 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
1781 set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
1782 break;
1783 case 5:
1784 ret = platform_device_add_resources(pdev,
1785 at32_smc_cs5_resource,
1786 ARRAY_SIZE(at32_smc_cs5_resource));
1787 if (ret)
1788 return ret;
1789
1790 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
1791 set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
1792 break;
1793 default:
1794 return -EINVAL;
1795 }
1796
1797 if (!common_pins_initialized) {
1798 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
1799 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
1800 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
1801 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
1802 common_pins_initialized = true;
1803 }
1804
1805 at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1806
1807 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1808 pdev->resource[1].end = pdev->resource[1].start;
1809
1810 return 0;
1811 }
1812
1813 struct platform_device *__init
1814 at32_add_device_ide(unsigned int id, unsigned int extint,
1815 struct ide_platform_data *data)
1816 {
1817 struct platform_device *pdev;
1818
1819 pdev = platform_device_alloc("at32_ide", id);
1820 if (!pdev)
1821 goto fail;
1822
1823 if (platform_device_add_data(pdev, data,
1824 sizeof(struct ide_platform_data)))
1825 goto fail;
1826
1827 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1828 goto fail;
1829
1830 platform_device_add(pdev);
1831 return pdev;
1832
1833 fail:
1834 platform_device_put(pdev);
1835 return NULL;
1836 }
1837
1838 struct platform_device *__init
1839 at32_add_device_cf(unsigned int id, unsigned int extint,
1840 struct cf_platform_data *data)
1841 {
1842 struct platform_device *pdev;
1843
1844 pdev = platform_device_alloc("at32_cf", id);
1845 if (!pdev)
1846 goto fail;
1847
1848 if (platform_device_add_data(pdev, data,
1849 sizeof(struct cf_platform_data)))
1850 goto fail;
1851
1852 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1853 goto fail;
1854
1855 if (data->detect_pin != GPIO_PIN_NONE)
1856 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1857 if (data->reset_pin != GPIO_PIN_NONE)
1858 at32_select_gpio(data->reset_pin, 0);
1859 if (data->vcc_pin != GPIO_PIN_NONE)
1860 at32_select_gpio(data->vcc_pin, 0);
1861 /* READY is used as extint, so we can't select it as gpio */
1862
1863 platform_device_add(pdev);
1864 return pdev;
1865
1866 fail:
1867 platform_device_put(pdev);
1868 return NULL;
1869 }
1870 #endif
1871
1872 /* --------------------------------------------------------------------
1873 * AC97C
1874 * -------------------------------------------------------------------- */
1875 static struct resource atmel_ac97c0_resource[] __initdata = {
1876 PBMEM(0xfff02800),
1877 IRQ(29),
1878 };
1879 static struct clk atmel_ac97c0_pclk = {
1880 .name = "pclk",
1881 .parent = &pbb_clk,
1882 .mode = pbb_clk_mode,
1883 .get_rate = pbb_clk_get_rate,
1884 .index = 10,
1885 };
1886
1887 struct platform_device *__init at32_add_device_ac97c(unsigned int id)
1888 {
1889 struct platform_device *pdev;
1890
1891 if (id != 0)
1892 return NULL;
1893
1894 pdev = platform_device_alloc("atmel_ac97c", id);
1895 if (!pdev)
1896 return NULL;
1897
1898 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1899 ARRAY_SIZE(atmel_ac97c0_resource)))
1900 goto err_add_resources;
1901
1902 select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
1903 select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
1904 select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
1905 select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
1906
1907 atmel_ac97c0_pclk.dev = &pdev->dev;
1908
1909 platform_device_add(pdev);
1910 return pdev;
1911
1912 err_add_resources:
1913 platform_device_put(pdev);
1914 return NULL;
1915 }
1916
1917 /* --------------------------------------------------------------------
1918 * ABDAC
1919 * -------------------------------------------------------------------- */
1920 static struct resource abdac0_resource[] __initdata = {
1921 PBMEM(0xfff02000),
1922 IRQ(27),
1923 };
1924 static struct clk abdac0_pclk = {
1925 .name = "pclk",
1926 .parent = &pbb_clk,
1927 .mode = pbb_clk_mode,
1928 .get_rate = pbb_clk_get_rate,
1929 .index = 8,
1930 };
1931 static struct clk abdac0_sample_clk = {
1932 .name = "sample_clk",
1933 .mode = genclk_mode,
1934 .get_rate = genclk_get_rate,
1935 .set_rate = genclk_set_rate,
1936 .set_parent = genclk_set_parent,
1937 .index = 6,
1938 };
1939
1940 struct platform_device *__init at32_add_device_abdac(unsigned int id)
1941 {
1942 struct platform_device *pdev;
1943
1944 if (id != 0)
1945 return NULL;
1946
1947 pdev = platform_device_alloc("abdac", id);
1948 if (!pdev)
1949 return NULL;
1950
1951 if (platform_device_add_resources(pdev, abdac0_resource,
1952 ARRAY_SIZE(abdac0_resource)))
1953 goto err_add_resources;
1954
1955 select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
1956 select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
1957 select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
1958 select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
1959
1960 abdac0_pclk.dev = &pdev->dev;
1961 abdac0_sample_clk.dev = &pdev->dev;
1962
1963 platform_device_add(pdev);
1964 return pdev;
1965
1966 err_add_resources:
1967 platform_device_put(pdev);
1968 return NULL;
1969 }
1970
1971 /* --------------------------------------------------------------------
1972 * GCLK
1973 * -------------------------------------------------------------------- */
1974 static struct clk gclk0 = {
1975 .name = "gclk0",
1976 .mode = genclk_mode,
1977 .get_rate = genclk_get_rate,
1978 .set_rate = genclk_set_rate,
1979 .set_parent = genclk_set_parent,
1980 .index = 0,
1981 };
1982 static struct clk gclk1 = {
1983 .name = "gclk1",
1984 .mode = genclk_mode,
1985 .get_rate = genclk_get_rate,
1986 .set_rate = genclk_set_rate,
1987 .set_parent = genclk_set_parent,
1988 .index = 1,
1989 };
1990 static struct clk gclk2 = {
1991 .name = "gclk2",
1992 .mode = genclk_mode,
1993 .get_rate = genclk_get_rate,
1994 .set_rate = genclk_set_rate,
1995 .set_parent = genclk_set_parent,
1996 .index = 2,
1997 };
1998 static struct clk gclk3 = {
1999 .name = "gclk3",
2000 .mode = genclk_mode,
2001 .get_rate = genclk_get_rate,
2002 .set_rate = genclk_set_rate,
2003 .set_parent = genclk_set_parent,
2004 .index = 3,
2005 };
2006 static struct clk gclk4 = {
2007 .name = "gclk4",
2008 .mode = genclk_mode,
2009 .get_rate = genclk_get_rate,
2010 .set_rate = genclk_set_rate,
2011 .set_parent = genclk_set_parent,
2012 .index = 4,
2013 };
2014
2015 struct clk *at32_clock_list[] = {
2016 &osc32k,
2017 &osc0,
2018 &osc1,
2019 &pll0,
2020 &pll1,
2021 &cpu_clk,
2022 &hsb_clk,
2023 &pba_clk,
2024 &pbb_clk,
2025 &at32_pm_pclk,
2026 &at32_intc0_pclk,
2027 &hmatrix_clk,
2028 &ebi_clk,
2029 &hramc_clk,
2030 &sdramc_clk,
2031 &smc0_pclk,
2032 &smc0_mck,
2033 &pdc_hclk,
2034 &pdc_pclk,
2035 &dmaca0_hclk,
2036 &pico_clk,
2037 &pio0_mck,
2038 &pio1_mck,
2039 &pio2_mck,
2040 &pio3_mck,
2041 &pio4_mck,
2042 &at32_tcb0_t0_clk,
2043 &at32_tcb1_t0_clk,
2044 &atmel_psif0_pclk,
2045 &atmel_psif1_pclk,
2046 &atmel_usart0_usart,
2047 &atmel_usart1_usart,
2048 &atmel_usart2_usart,
2049 &atmel_usart3_usart,
2050 &atmel_pwm0_mck,
2051 #if defined(CONFIG_CPU_AT32AP7000)
2052 &macb0_hclk,
2053 &macb0_pclk,
2054 &macb1_hclk,
2055 &macb1_pclk,
2056 #endif
2057 &atmel_spi0_spi_clk,
2058 &atmel_spi1_spi_clk,
2059 &atmel_twi0_pclk,
2060 &atmel_mci0_pclk,
2061 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2062 &atmel_lcdfb0_hck1,
2063 &atmel_lcdfb0_pixclk,
2064 #endif
2065 &ssc0_pclk,
2066 &ssc1_pclk,
2067 &ssc2_pclk,
2068 &usba0_hclk,
2069 &usba0_pclk,
2070 &atmel_ac97c0_pclk,
2071 &abdac0_pclk,
2072 &abdac0_sample_clk,
2073 &gclk0,
2074 &gclk1,
2075 &gclk2,
2076 &gclk3,
2077 &gclk4,
2078 };
2079 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
2080
2081 void __init setup_platform(void)
2082 {
2083 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2084 int i;
2085
2086 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2087 main_clock = &pll0;
2088 cpu_clk.parent = &pll0;
2089 } else {
2090 main_clock = &osc0;
2091 cpu_clk.parent = &osc0;
2092 }
2093
2094 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2095 pll0.parent = &osc1;
2096 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2097 pll1.parent = &osc1;
2098
2099 genclk_init_parent(&gclk0);
2100 genclk_init_parent(&gclk1);
2101 genclk_init_parent(&gclk2);
2102 genclk_init_parent(&gclk3);
2103 genclk_init_parent(&gclk4);
2104 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2105 genclk_init_parent(&atmel_lcdfb0_pixclk);
2106 #endif
2107 genclk_init_parent(&abdac0_sample_clk);
2108
2109 /*
2110 * Turn on all clocks that have at least one user already, and
2111 * turn off everything else. We only do this for module
2112 * clocks, and even though it isn't particularly pretty to
2113 * check the address of the mode function, it should do the
2114 * trick...
2115 */
2116 for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
2117 struct clk *clk = at32_clock_list[i];
2118
2119 if (clk->users == 0)
2120 continue;
2121
2122 if (clk->mode == &cpu_clk_mode)
2123 cpu_mask |= 1 << clk->index;
2124 else if (clk->mode == &hsb_clk_mode)
2125 hsb_mask |= 1 << clk->index;
2126 else if (clk->mode == &pba_clk_mode)
2127 pba_mask |= 1 << clk->index;
2128 else if (clk->mode == &pbb_clk_mode)
2129 pbb_mask |= 1 << clk->index;
2130 }
2131
2132 pm_writel(CPU_MASK, cpu_mask);
2133 pm_writel(HSB_MASK, hsb_mask);
2134 pm_writel(PBA_MASK, pba_mask);
2135 pm_writel(PBB_MASK, pbb_mask);
2136
2137 /* Initialize the port muxes */
2138 at32_init_pio(&pio0_device);
2139 at32_init_pio(&pio1_device);
2140 at32_init_pio(&pio2_device);
2141 at32_init_pio(&pio3_device);
2142 at32_init_pio(&pio4_device);
2143 }
2144
2145 struct gen_pool *sram_pool;
2146
2147 static int __init sram_init(void)
2148 {
2149 struct gen_pool *pool;
2150
2151 /* 1KiB granularity */
2152 pool = gen_pool_create(10, -1);
2153 if (!pool)
2154 goto fail;
2155
2156 if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2157 goto err_pool_add;
2158
2159 sram_pool = pool;
2160 return 0;
2161
2162 err_pool_add:
2163 gen_pool_destroy(pool);
2164 fail:
2165 pr_err("Failed to create SRAM pool\n");
2166 return -ENOMEM;
2167 }
2168 core_initcall(sram_init);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree