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iwlwifi: fix frame injection for HT channels
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn-tx.c
bloba709d05c5868f3e6a19d586bcdffd560cb69bf6f
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-sta.h"
38 #include "iwl-io.h"
39 #include "iwl-helpers.h"
40 #include "iwl-agn-hw.h"
41 #include "iwl-agn.h"
42
43 /*
44 * mac80211 queues, ACs, hardware queues, FIFOs.
45 *
46 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
47 *
48 * Mac80211 uses the following numbers, which we get as from it
49 * by way of skb_get_queue_mapping(skb):
50 *
51 * VO 0
52 * VI 1
53 * BE 2
54 * BK 3
55 *
56 *
57 * Regular (not A-MPDU) frames are put into hardware queues corresponding
58 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
59 * own queue per aggregation session (RA/TID combination), such queues are
60 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
61 * order to map frames to the right queue, we also need an AC->hw queue
62 * mapping. This is implemented here.
63 *
64 * Due to the way hw queues are set up (by the hw specific modules like
65 * iwl-4965.c, iwl-5000.c etc.), the AC->hw queue mapping is the identity
66 * mapping.
67 */
68
69 static const u8 tid_to_ac[] = {
70 IEEE80211_AC_BE,
71 IEEE80211_AC_BK,
72 IEEE80211_AC_BK,
73 IEEE80211_AC_BE,
74 IEEE80211_AC_VI,
75 IEEE80211_AC_VI,
76 IEEE80211_AC_VO,
77 IEEE80211_AC_VO
78 };
79
80 static inline int get_ac_from_tid(u16 tid)
81 {
82 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
83 return tid_to_ac[tid];
84
85 /* no support for TIDs 8-15 yet */
86 return -EINVAL;
87 }
88
89 static inline int get_fifo_from_tid(struct iwl_rxon_context *ctx, u16 tid)
90 {
91 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
92 return ctx->ac_to_fifo[tid_to_ac[tid]];
93
94 /* no support for TIDs 8-15 yet */
95 return -EINVAL;
96 }
97
98 /**
99 * iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
100 */
101 void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
102 struct iwl_tx_queue *txq,
103 u16 byte_cnt)
104 {
105 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
106 int write_ptr = txq->q.write_ptr;
107 int txq_id = txq->q.id;
108 u8 sec_ctl = 0;
109 u8 sta_id = 0;
110 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
111 __le16 bc_ent;
112
113 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
114
115 if (txq_id != priv->cmd_queue) {
116 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
117 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
118
119 switch (sec_ctl & TX_CMD_SEC_MSK) {
120 case TX_CMD_SEC_CCM:
121 len += CCMP_MIC_LEN;
122 break;
123 case TX_CMD_SEC_TKIP:
124 len += TKIP_ICV_LEN;
125 break;
126 case TX_CMD_SEC_WEP:
127 len += WEP_IV_LEN + WEP_ICV_LEN;
128 break;
129 }
130 }
131
132 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
133
134 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
135
136 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
137 scd_bc_tbl[txq_id].
138 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
139 }
140
141 void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
142 struct iwl_tx_queue *txq)
143 {
144 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
145 int txq_id = txq->q.id;
146 int read_ptr = txq->q.read_ptr;
147 u8 sta_id = 0;
148 __le16 bc_ent;
149
150 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
151
152 if (txq_id != priv->cmd_queue)
153 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
154
155 bc_ent = cpu_to_le16(1 | (sta_id << 12));
156 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
157
158 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
159 scd_bc_tbl[txq_id].
160 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
161 }
162
163 static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
164 u16 txq_id)
165 {
166 u32 tbl_dw_addr;
167 u32 tbl_dw;
168 u16 scd_q2ratid;
169
170 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
171
172 tbl_dw_addr = priv->scd_base_addr +
173 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
174
175 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
176
177 if (txq_id & 0x1)
178 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
179 else
180 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
181
182 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
183
184 return 0;
185 }
186
187 static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
188 {
189 /* Simply stop the queue, but don't change any configuration;
190 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
191 iwl_write_prph(priv,
192 IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
193 (0 << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
194 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
195 }
196
197 void iwlagn_set_wr_ptrs(struct iwl_priv *priv,
198 int txq_id, u32 index)
199 {
200 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
201 (index & 0xff) | (txq_id << 8));
202 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(txq_id), index);
203 }
204
205 void iwlagn_tx_queue_set_status(struct iwl_priv *priv,
206 struct iwl_tx_queue *txq,
207 int tx_fifo_id, int scd_retry)
208 {
209 int txq_id = txq->q.id;
210 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
211
212 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
213 (active << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
214 (tx_fifo_id << IWLAGN_SCD_QUEUE_STTS_REG_POS_TXF) |
215 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_WSL) |
216 IWLAGN_SCD_QUEUE_STTS_REG_MSK);
217
218 txq->sched_retry = scd_retry;
219
220 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
221 active ? "Activate" : "Deactivate",
222 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
223 }
224
225 int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id,
226 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
227 {
228 unsigned long flags;
229 u16 ra_tid;
230 int ret;
231
232 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
233 (IWLAGN_FIRST_AMPDU_QUEUE +
234 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
235 IWL_WARN(priv,
236 "queue number out of range: %d, must be %d to %d\n",
237 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
238 IWLAGN_FIRST_AMPDU_QUEUE +
239 priv->cfg->base_params->num_of_ampdu_queues - 1);
240 return -EINVAL;
241 }
242
243 ra_tid = BUILD_RAxTID(sta_id, tid);
244
245 /* Modify device's station table to Tx this TID */
246 ret = iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
247 if (ret)
248 return ret;
249
250 spin_lock_irqsave(&priv->lock, flags);
251
252 /* Stop this Tx queue before configuring it */
253 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
254
255 /* Map receiver-address / traffic-ID to this queue */
256 iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
257
258 /* Set this queue as a chain-building queue */
259 iwl_set_bits_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL, (1<<txq_id));
260
261 /* enable aggregations for the queue */
262 iwl_set_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1<<txq_id));
263
264 /* Place first TFD at index corresponding to start sequence number.
265 * Assumes that ssn_idx is valid (!= 0xFFF) */
266 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
267 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
268 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
269
270 /* Set up Tx window size and frame limit for this queue */
271 iwl_write_targ_mem(priv, priv->scd_base_addr +
272 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
273 sizeof(u32),
274 ((SCD_WIN_SIZE <<
275 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
276 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
277 ((SCD_FRAME_LIMIT <<
278 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
279 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
280
281 iwl_set_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
282
283 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
284 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
285
286 spin_unlock_irqrestore(&priv->lock, flags);
287
288 return 0;
289 }
290
291 int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
292 u16 ssn_idx, u8 tx_fifo)
293 {
294 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
295 (IWLAGN_FIRST_AMPDU_QUEUE +
296 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
297 IWL_ERR(priv,
298 "queue number out of range: %d, must be %d to %d\n",
299 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
300 IWLAGN_FIRST_AMPDU_QUEUE +
301 priv->cfg->base_params->num_of_ampdu_queues - 1);
302 return -EINVAL;
303 }
304
305 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
306
307 iwl_clear_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1 << txq_id));
308
309 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
310 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
311 /* supposes that ssn_idx is valid (!= 0xFFF) */
312 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
313
314 iwl_clear_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
315 iwl_txq_ctx_deactivate(priv, txq_id);
316 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
317
318 return 0;
319 }
320
321 /*
322 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
323 * must be called under priv->lock and mac access
324 */
325 void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask)
326 {
327 iwl_write_prph(priv, IWLAGN_SCD_TXFACT, mask);
328 }
329
330 /*
331 * handle build REPLY_TX command notification.
332 */
333 static void iwlagn_tx_cmd_build_basic(struct iwl_priv *priv,
334 struct sk_buff *skb,
335 struct iwl_tx_cmd *tx_cmd,
336 struct ieee80211_tx_info *info,
337 struct ieee80211_hdr *hdr,
338 u8 std_id)
339 {
340 __le16 fc = hdr->frame_control;
341 __le32 tx_flags = tx_cmd->tx_flags;
342
343 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
344 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
345 tx_flags |= TX_CMD_FLG_ACK_MSK;
346 if (ieee80211_is_mgmt(fc))
347 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
348 if (ieee80211_is_probe_resp(fc) &&
349 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
350 tx_flags |= TX_CMD_FLG_TSF_MSK;
351 } else {
352 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
353 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
354 }
355
356 if (ieee80211_is_back_req(fc))
357 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
358 else if (info->band == IEEE80211_BAND_2GHZ &&
359 priv->cfg->bt_params &&
360 priv->cfg->bt_params->advanced_bt_coexist &&
361 (ieee80211_is_auth(fc) || ieee80211_is_assoc_req(fc) ||
362 ieee80211_is_reassoc_req(fc) ||
363 skb->protocol == cpu_to_be16(ETH_P_PAE)))
364 tx_flags |= TX_CMD_FLG_IGNORE_BT;
365
366
367 tx_cmd->sta_id = std_id;
368 if (ieee80211_has_morefrags(fc))
369 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
370
371 if (ieee80211_is_data_qos(fc)) {
372 u8 *qc = ieee80211_get_qos_ctl(hdr);
373 tx_cmd->tid_tspec = qc[0] & 0xf;
374 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
375 } else {
376 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
377 }
378
379 priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags);
380
381 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
382 if (ieee80211_is_mgmt(fc)) {
383 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
384 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
385 else
386 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
387 } else {
388 tx_cmd->timeout.pm_frame_timeout = 0;
389 }
390
391 tx_cmd->driver_txop = 0;
392 tx_cmd->tx_flags = tx_flags;
393 tx_cmd->next_frame_len = 0;
394 }
395
396 #define RTS_DFAULT_RETRY_LIMIT 60
397
398 static void iwlagn_tx_cmd_build_rate(struct iwl_priv *priv,
399 struct iwl_tx_cmd *tx_cmd,
400 struct ieee80211_tx_info *info,
401 __le16 fc)
402 {
403 u32 rate_flags;
404 int rate_idx;
405 u8 rts_retry_limit;
406 u8 data_retry_limit;
407 u8 rate_plcp;
408
409 /* Set retry limit on DATA packets and Probe Responses*/
410 if (ieee80211_is_probe_resp(fc))
411 data_retry_limit = 3;
412 else
413 data_retry_limit = IWLAGN_DEFAULT_TX_RETRY;
414 tx_cmd->data_retry_limit = data_retry_limit;
415
416 /* Set retry limit on RTS packets */
417 rts_retry_limit = RTS_DFAULT_RETRY_LIMIT;
418 if (data_retry_limit < rts_retry_limit)
419 rts_retry_limit = data_retry_limit;
420 tx_cmd->rts_retry_limit = rts_retry_limit;
421
422 /* DATA packets will use the uCode station table for rate/antenna
423 * selection */
424 if (ieee80211_is_data(fc)) {
425 tx_cmd->initial_rate_index = 0;
426 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
427 return;
428 }
429
430 /**
431 * If the current TX rate stored in mac80211 has the MCS bit set, it's
432 * not really a TX rate. Thus, we use the lowest supported rate for
433 * this band. Also use the lowest supported rate if the stored rate
434 * index is invalid.
435 */
436 rate_idx = info->control.rates[0].idx;
437 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
438 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
439 rate_idx = rate_lowest_index(&priv->bands[info->band],
440 info->control.sta);
441 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
442 if (info->band == IEEE80211_BAND_5GHZ)
443 rate_idx += IWL_FIRST_OFDM_RATE;
444 /* Get PLCP rate for tx_cmd->rate_n_flags */
445 rate_plcp = iwl_rates[rate_idx].plcp;
446 /* Zero out flags for this packet */
447 rate_flags = 0;
448
449 /* Set CCK flag as needed */
450 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
451 rate_flags |= RATE_MCS_CCK_MSK;
452
453 /* Set up antennas */
454 if (priv->cfg->bt_params &&
455 priv->cfg->bt_params->advanced_bt_coexist &&
456 priv->bt_full_concurrent) {
457 /* operated as 1x1 in full concurrency mode */
458 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
459 first_antenna(priv->hw_params.valid_tx_ant));
460 } else
461 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
462 priv->hw_params.valid_tx_ant);
463 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
464
465 /* Set the rate in the TX cmd */
466 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
467 }
468
469 static void iwlagn_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
470 struct ieee80211_tx_info *info,
471 struct iwl_tx_cmd *tx_cmd,
472 struct sk_buff *skb_frag,
473 int sta_id)
474 {
475 struct ieee80211_key_conf *keyconf = info->control.hw_key;
476
477 switch (keyconf->cipher) {
478 case WLAN_CIPHER_SUITE_CCMP:
479 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
480 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
481 if (info->flags & IEEE80211_TX_CTL_AMPDU)
482 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
483 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
484 break;
485
486 case WLAN_CIPHER_SUITE_TKIP:
487 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
488 ieee80211_get_tkip_key(keyconf, skb_frag,
489 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
490 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
491 break;
492
493 case WLAN_CIPHER_SUITE_WEP104:
494 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
495 /* fall through */
496 case WLAN_CIPHER_SUITE_WEP40:
497 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
498 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
499
500 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
501
502 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
503 "with key %d\n", keyconf->keyidx);
504 break;
505
506 default:
507 IWL_ERR(priv, "Unknown encode cipher %x\n", keyconf->cipher);
508 break;
509 }
510 }
511
512 /*
513 * start REPLY_TX command process
514 */
515 int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
516 {
517 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
518 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
519 struct ieee80211_sta *sta = info->control.sta;
520 struct iwl_station_priv *sta_priv = NULL;
521 struct iwl_tx_queue *txq;
522 struct iwl_queue *q;
523 struct iwl_device_cmd *out_cmd;
524 struct iwl_cmd_meta *out_meta;
525 struct iwl_tx_cmd *tx_cmd;
526 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
527 int txq_id;
528 dma_addr_t phys_addr;
529 dma_addr_t txcmd_phys;
530 dma_addr_t scratch_phys;
531 u16 len, firstlen, secondlen;
532 u16 seq_number = 0;
533 __le16 fc;
534 u8 hdr_len;
535 u8 sta_id;
536 u8 wait_write_ptr = 0;
537 u8 tid = 0;
538 u8 *qc = NULL;
539 unsigned long flags;
540 bool is_agg = false;
541
542 /*
543 * If the frame needs to go out off-channel, then
544 * we'll have put the PAN context to that channel,
545 * so make the frame go out there.
546 */
547 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
548 ctx = &priv->contexts[IWL_RXON_CTX_PAN];
549 else if (info->control.vif)
550 ctx = iwl_rxon_ctx_from_vif(info->control.vif);
551
552 spin_lock_irqsave(&priv->lock, flags);
553 if (iwl_is_rfkill(priv)) {
554 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
555 goto drop_unlock;
556 }
557
558 fc = hdr->frame_control;
559
560 #ifdef CONFIG_IWLWIFI_DEBUG
561 if (ieee80211_is_auth(fc))
562 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
563 else if (ieee80211_is_assoc_req(fc))
564 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
565 else if (ieee80211_is_reassoc_req(fc))
566 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
567 #endif
568
569 hdr_len = ieee80211_hdrlen(fc);
570
571 /* Find index into station table for destination station */
572 sta_id = iwl_sta_id_or_broadcast(priv, ctx, info->control.sta);
573 if (sta_id == IWL_INVALID_STATION) {
574 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
575 hdr->addr1);
576 goto drop_unlock;
577 }
578
579 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
580
581 if (sta)
582 sta_priv = (void *)sta->drv_priv;
583
584 if (sta_priv && sta_priv->asleep &&
585 (info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE)) {
586 /*
587 * This sends an asynchronous command to the device,
588 * but we can rely on it being processed before the
589 * next frame is processed -- and the next frame to
590 * this station is the one that will consume this
591 * counter.
592 * For now set the counter to just 1 since we do not
593 * support uAPSD yet.
594 */
595 iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
596 }
597
598 /*
599 * Send this frame after DTIM -- there's a special queue
600 * reserved for this for contexts that support AP mode.
601 */
602 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
603 txq_id = ctx->mcast_queue;
604 /*
605 * The microcode will clear the more data
606 * bit in the last frame it transmits.
607 */
608 hdr->frame_control |=
609 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
610 } else
611 txq_id = ctx->ac_to_queue[skb_get_queue_mapping(skb)];
612
613 /* irqs already disabled/saved above when locking priv->lock */
614 spin_lock(&priv->sta_lock);
615
616 if (ieee80211_is_data_qos(fc)) {
617 qc = ieee80211_get_qos_ctl(hdr);
618 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
619 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
620 spin_unlock(&priv->sta_lock);
621 goto drop_unlock;
622 }
623 seq_number = priv->stations[sta_id].tid[tid].seq_number;
624 seq_number &= IEEE80211_SCTL_SEQ;
625 hdr->seq_ctrl = hdr->seq_ctrl &
626 cpu_to_le16(IEEE80211_SCTL_FRAG);
627 hdr->seq_ctrl |= cpu_to_le16(seq_number);
628 seq_number += 0x10;
629 /* aggregation is on for this <sta,tid> */
630 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
631 priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) {
632 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
633 is_agg = true;
634 }
635 }
636
637 txq = &priv->txq[txq_id];
638 q = &txq->q;
639
640 if (unlikely(iwl_queue_space(q) < q->high_mark)) {
641 spin_unlock(&priv->sta_lock);
642 goto drop_unlock;
643 }
644
645 if (ieee80211_is_data_qos(fc)) {
646 priv->stations[sta_id].tid[tid].tfds_in_queue++;
647 if (!ieee80211_has_morefrags(fc))
648 priv->stations[sta_id].tid[tid].seq_number = seq_number;
649 }
650
651 spin_unlock(&priv->sta_lock);
652
653 /* Set up driver data for this TFD */
654 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
655 txq->txb[q->write_ptr].skb = skb;
656 txq->txb[q->write_ptr].ctx = ctx;
657
658 /* Set up first empty entry in queue's array of Tx/cmd buffers */
659 out_cmd = txq->cmd[q->write_ptr];
660 out_meta = &txq->meta[q->write_ptr];
661 tx_cmd = &out_cmd->cmd.tx;
662 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
663 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
664
665 /*
666 * Set up the Tx-command (not MAC!) header.
667 * Store the chosen Tx queue and TFD index within the sequence field;
668 * after Tx, uCode's Tx response will return this value so driver can
669 * locate the frame within the tx queue and do post-tx processing.
670 */
671 out_cmd->hdr.cmd = REPLY_TX;
672 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
673 INDEX_TO_SEQ(q->write_ptr)));
674
675 /* Copy MAC header from skb into command buffer */
676 memcpy(tx_cmd->hdr, hdr, hdr_len);
677
678
679 /* Total # bytes to be transmitted */
680 len = (u16)skb->len;
681 tx_cmd->len = cpu_to_le16(len);
682
683 if (info->control.hw_key)
684 iwlagn_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
685
686 /* TODO need this for burst mode later on */
687 iwlagn_tx_cmd_build_basic(priv, skb, tx_cmd, info, hdr, sta_id);
688 iwl_dbg_log_tx_data_frame(priv, len, hdr);
689
690 iwlagn_tx_cmd_build_rate(priv, tx_cmd, info, fc);
691
692 iwl_update_stats(priv, true, fc, len);
693 /*
694 * Use the first empty entry in this queue's command buffer array
695 * to contain the Tx command and MAC header concatenated together
696 * (payload data will be in another buffer).
697 * Size of this varies, due to varying MAC header length.
698 * If end is not dword aligned, we'll have 2 extra bytes at the end
699 * of the MAC header (device reads on dword boundaries).
700 * We'll tell device about this padding later.
701 */
702 len = sizeof(struct iwl_tx_cmd) +
703 sizeof(struct iwl_cmd_header) + hdr_len;
704 firstlen = (len + 3) & ~3;
705
706 /* Tell NIC about any 2-byte padding after MAC header */
707 if (firstlen != len)
708 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
709
710 /* Physical address of this Tx command's header (not MAC header!),
711 * within command buffer array. */
712 txcmd_phys = pci_map_single(priv->pci_dev,
713 &out_cmd->hdr, firstlen,
714 PCI_DMA_BIDIRECTIONAL);
715 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
716 dma_unmap_len_set(out_meta, len, firstlen);
717 /* Add buffer containing Tx command and MAC(!) header to TFD's
718 * first entry */
719 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
720 txcmd_phys, firstlen, 1, 0);
721
722 if (!ieee80211_has_morefrags(hdr->frame_control)) {
723 txq->need_update = 1;
724 } else {
725 wait_write_ptr = 1;
726 txq->need_update = 0;
727 }
728
729 /* Set up TFD's 2nd entry to point directly to remainder of skb,
730 * if any (802.11 null frames have no payload). */
731 secondlen = skb->len - hdr_len;
732 if (secondlen > 0) {
733 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
734 secondlen, PCI_DMA_TODEVICE);
735 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
736 phys_addr, secondlen,
737 0, 0);
738 }
739
740 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
741 offsetof(struct iwl_tx_cmd, scratch);
742
743 /* take back ownership of DMA buffer to enable update */
744 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
745 firstlen, PCI_DMA_BIDIRECTIONAL);
746 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
747 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
748
749 IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
750 le16_to_cpu(out_cmd->hdr.sequence));
751 IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
752 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
753 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
754
755 /* Set up entry for this TFD in Tx byte-count array */
756 if (info->flags & IEEE80211_TX_CTL_AMPDU)
757 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
758 le16_to_cpu(tx_cmd->len));
759
760 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
761 firstlen, PCI_DMA_BIDIRECTIONAL);
762
763 trace_iwlwifi_dev_tx(priv,
764 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
765 sizeof(struct iwl_tfd),
766 &out_cmd->hdr, firstlen,
767 skb->data + hdr_len, secondlen);
768
769 /* Tell device the write index *just past* this latest filled TFD */
770 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
771 iwl_txq_update_write_ptr(priv, txq);
772 spin_unlock_irqrestore(&priv->lock, flags);
773
774 /*
775 * At this point the frame is "transmitted" successfully
776 * and we will get a TX status notification eventually,
777 * regardless of the value of ret. "ret" only indicates
778 * whether or not we should update the write pointer.
779 */
780
781 /*
782 * Avoid atomic ops if it isn't an associated client.
783 * Also, if this is a packet for aggregation, don't
784 * increase the counter because the ucode will stop
785 * aggregation queues when their respective station
786 * goes to sleep.
787 */
788 if (sta_priv && sta_priv->client && !is_agg)
789 atomic_inc(&sta_priv->pending_frames);
790
791 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
792 if (wait_write_ptr) {
793 spin_lock_irqsave(&priv->lock, flags);
794 txq->need_update = 1;
795 iwl_txq_update_write_ptr(priv, txq);
796 spin_unlock_irqrestore(&priv->lock, flags);
797 } else {
798 iwl_stop_queue(priv, txq);
799 }
800 }
801
802 return 0;
803
804 drop_unlock:
805 spin_unlock_irqrestore(&priv->lock, flags);
806 return -1;
807 }
808
809 static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
810 struct iwl_dma_ptr *ptr, size_t size)
811 {
812 ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma,
813 GFP_KERNEL);
814 if (!ptr->addr)
815 return -ENOMEM;
816 ptr->size = size;
817 return 0;
818 }
819
820 static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
821 struct iwl_dma_ptr *ptr)
822 {
823 if (unlikely(!ptr->addr))
824 return;
825
826 dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
827 memset(ptr, 0, sizeof(*ptr));
828 }
829
830 /**
831 * iwlagn_hw_txq_ctx_free - Free TXQ Context
832 *
833 * Destroy all TX DMA queues and structures
834 */
835 void iwlagn_hw_txq_ctx_free(struct iwl_priv *priv)
836 {
837 int txq_id;
838
839 /* Tx queues */
840 if (priv->txq) {
841 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
842 if (txq_id == priv->cmd_queue)
843 iwl_cmd_queue_free(priv);
844 else
845 iwl_tx_queue_free(priv, txq_id);
846 }
847 iwlagn_free_dma_ptr(priv, &priv->kw);
848
849 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
850
851 /* free tx queue structure */
852 iwl_free_txq_mem(priv);
853 }
854
855 /**
856 * iwlagn_txq_ctx_alloc - allocate TX queue context
857 * Allocate all Tx DMA structures and initialize them
858 *
859 * @param priv
860 * @return error code
861 */
862 int iwlagn_txq_ctx_alloc(struct iwl_priv *priv)
863 {
864 int ret;
865 int txq_id, slots_num;
866 unsigned long flags;
867
868 /* Free all tx/cmd queues and keep-warm buffer */
869 iwlagn_hw_txq_ctx_free(priv);
870
871 ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
872 priv->hw_params.scd_bc_tbls_size);
873 if (ret) {
874 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
875 goto error_bc_tbls;
876 }
877 /* Alloc keep-warm buffer */
878 ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
879 if (ret) {
880 IWL_ERR(priv, "Keep Warm allocation failed\n");
881 goto error_kw;
882 }
883
884 /* allocate tx queue structure */
885 ret = iwl_alloc_txq_mem(priv);
886 if (ret)
887 goto error;
888
889 spin_lock_irqsave(&priv->lock, flags);
890
891 /* Turn off all Tx DMA fifos */
892 priv->cfg->ops->lib->txq_set_sched(priv, 0);
893
894 /* Tell NIC where to find the "keep warm" buffer */
895 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
896
897 spin_unlock_irqrestore(&priv->lock, flags);
898
899 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
900 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
901 slots_num = (txq_id == priv->cmd_queue) ?
902 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
903 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
904 txq_id);
905 if (ret) {
906 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
907 goto error;
908 }
909 }
910
911 return ret;
912
913 error:
914 iwlagn_hw_txq_ctx_free(priv);
915 iwlagn_free_dma_ptr(priv, &priv->kw);
916 error_kw:
917 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
918 error_bc_tbls:
919 return ret;
920 }
921
922 void iwlagn_txq_ctx_reset(struct iwl_priv *priv)
923 {
924 int txq_id, slots_num;
925 unsigned long flags;
926
927 spin_lock_irqsave(&priv->lock, flags);
928
929 /* Turn off all Tx DMA fifos */
930 priv->cfg->ops->lib->txq_set_sched(priv, 0);
931
932 /* Tell NIC where to find the "keep warm" buffer */
933 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
934
935 spin_unlock_irqrestore(&priv->lock, flags);
936
937 /* Alloc and init all Tx queues, including the command queue (#4) */
938 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
939 slots_num = txq_id == priv->cmd_queue ?
940 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
941 iwl_tx_queue_reset(priv, &priv->txq[txq_id], slots_num, txq_id);
942 }
943 }
944
945 /**
946 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
947 */
948 void iwlagn_txq_ctx_stop(struct iwl_priv *priv)
949 {
950 int ch, txq_id;
951 unsigned long flags;
952
953 /* Turn off all Tx DMA fifos */
954 spin_lock_irqsave(&priv->lock, flags);
955
956 priv->cfg->ops->lib->txq_set_sched(priv, 0);
957
958 /* Stop each Tx DMA channel, and wait for it to be idle */
959 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
960 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
961 if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
962 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
963 1000))
964 IWL_ERR(priv, "Failing on timeout while stopping"
965 " DMA channel %d [0x%08x]", ch,
966 iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
967 }
968 spin_unlock_irqrestore(&priv->lock, flags);
969
970 if (!priv->txq)
971 return;
972
973 /* Unmap DMA from host system and free skb's */
974 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
975 if (txq_id == priv->cmd_queue)
976 iwl_cmd_queue_unmap(priv);
977 else
978 iwl_tx_queue_unmap(priv, txq_id);
979 }
980
981 /*
982 * Find first available (lowest unused) Tx Queue, mark it "active".
983 * Called only when finding queue for aggregation.
984 * Should never return anything < 7, because they should already
985 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
986 */
987 static int iwlagn_txq_ctx_activate_free(struct iwl_priv *priv)
988 {
989 int txq_id;
990
991 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
992 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
993 return txq_id;
994 return -1;
995 }
996
997 int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif,
998 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
999 {
1000 int sta_id;
1001 int tx_fifo;
1002 int txq_id;
1003 int ret;
1004 unsigned long flags;
1005 struct iwl_tid_data *tid_data;
1006
1007 tx_fifo = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid);
1008 if (unlikely(tx_fifo < 0))
1009 return tx_fifo;
1010
1011 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1012 __func__, sta->addr, tid);
1013
1014 sta_id = iwl_sta_id(sta);
1015 if (sta_id == IWL_INVALID_STATION) {
1016 IWL_ERR(priv, "Start AGG on invalid station\n");
1017 return -ENXIO;
1018 }
1019 if (unlikely(tid >= MAX_TID_COUNT))
1020 return -EINVAL;
1021
1022 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1023 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1024 return -ENXIO;
1025 }
1026
1027 txq_id = iwlagn_txq_ctx_activate_free(priv);
1028 if (txq_id == -1) {
1029 IWL_ERR(priv, "No free aggregation queue available\n");
1030 return -ENXIO;
1031 }
1032
1033 spin_lock_irqsave(&priv->sta_lock, flags);
1034 tid_data = &priv->stations[sta_id].tid[tid];
1035 *ssn = SEQ_TO_SN(tid_data->seq_number);
1036 tid_data->agg.txq_id = txq_id;
1037 iwl_set_swq_id(&priv->txq[txq_id], get_ac_from_tid(tid), txq_id);
1038 spin_unlock_irqrestore(&priv->sta_lock, flags);
1039
1040 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1041 sta_id, tid, *ssn);
1042 if (ret)
1043 return ret;
1044
1045 spin_lock_irqsave(&priv->sta_lock, flags);
1046 tid_data = &priv->stations[sta_id].tid[tid];
1047 if (tid_data->tfds_in_queue == 0) {
1048 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1049 tid_data->agg.state = IWL_AGG_ON;
1050 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1051 } else {
1052 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1053 tid_data->tfds_in_queue);
1054 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1055 }
1056 spin_unlock_irqrestore(&priv->sta_lock, flags);
1057 return ret;
1058 }
1059
1060 int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif,
1061 struct ieee80211_sta *sta, u16 tid)
1062 {
1063 int tx_fifo_id, txq_id, sta_id, ssn;
1064 struct iwl_tid_data *tid_data;
1065 int write_ptr, read_ptr;
1066 unsigned long flags;
1067
1068 tx_fifo_id = get_fifo_from_tid(iwl_rxon_ctx_from_vif(vif), tid);
1069 if (unlikely(tx_fifo_id < 0))
1070 return tx_fifo_id;
1071
1072 sta_id = iwl_sta_id(sta);
1073
1074 if (sta_id == IWL_INVALID_STATION) {
1075 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1076 return -ENXIO;
1077 }
1078
1079 spin_lock_irqsave(&priv->sta_lock, flags);
1080
1081 tid_data = &priv->stations[sta_id].tid[tid];
1082 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1083 txq_id = tid_data->agg.txq_id;
1084
1085 switch (priv->stations[sta_id].tid[tid].agg.state) {
1086 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1087 /*
1088 * This can happen if the peer stops aggregation
1089 * again before we've had a chance to drain the
1090 * queue we selected previously, i.e. before the
1091 * session was really started completely.
1092 */
1093 IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
1094 goto turn_off;
1095 case IWL_AGG_ON:
1096 break;
1097 default:
1098 IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
1099 }
1100
1101 write_ptr = priv->txq[txq_id].q.write_ptr;
1102 read_ptr = priv->txq[txq_id].q.read_ptr;
1103
1104 /* The queue is not empty */
1105 if (write_ptr != read_ptr) {
1106 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1107 priv->stations[sta_id].tid[tid].agg.state =
1108 IWL_EMPTYING_HW_QUEUE_DELBA;
1109 spin_unlock_irqrestore(&priv->sta_lock, flags);
1110 return 0;
1111 }
1112
1113 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1114 turn_off:
1115 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1116
1117 /* do not restore/save irqs */
1118 spin_unlock(&priv->sta_lock);
1119 spin_lock(&priv->lock);
1120
1121 /*
1122 * the only reason this call can fail is queue number out of range,
1123 * which can happen if uCode is reloaded and all the station
1124 * information are lost. if it is outside the range, there is no need
1125 * to deactivate the uCode queue, just return "success" to allow
1126 * mac80211 to clean up it own data.
1127 */
1128 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1129 tx_fifo_id);
1130 spin_unlock_irqrestore(&priv->lock, flags);
1131
1132 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1133
1134 return 0;
1135 }
1136
1137 int iwlagn_txq_check_empty(struct iwl_priv *priv,
1138 int sta_id, u8 tid, int txq_id)
1139 {
1140 struct iwl_queue *q = &priv->txq[txq_id].q;
1141 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1142 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1143 struct iwl_rxon_context *ctx;
1144
1145 ctx = &priv->contexts[priv->stations[sta_id].ctxid];
1146
1147 lockdep_assert_held(&priv->sta_lock);
1148
1149 switch (priv->stations[sta_id].tid[tid].agg.state) {
1150 case IWL_EMPTYING_HW_QUEUE_DELBA:
1151 /* We are reclaiming the last packet of the */
1152 /* aggregated HW queue */
1153 if ((txq_id == tid_data->agg.txq_id) &&
1154 (q->read_ptr == q->write_ptr)) {
1155 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1156 int tx_fifo = get_fifo_from_tid(ctx, tid);
1157 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1158 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1159 ssn, tx_fifo);
1160 tid_data->agg.state = IWL_AGG_OFF;
1161 ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
1162 }
1163 break;
1164 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1165 /* We are reclaiming the last packet of the queue */
1166 if (tid_data->tfds_in_queue == 0) {
1167 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1168 tid_data->agg.state = IWL_AGG_ON;
1169 ieee80211_start_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
1170 }
1171 break;
1172 }
1173
1174 return 0;
1175 }
1176
1177 static void iwlagn_non_agg_tx_status(struct iwl_priv *priv,
1178 struct iwl_rxon_context *ctx,
1179 const u8 *addr1)
1180 {
1181 struct ieee80211_sta *sta;
1182 struct iwl_station_priv *sta_priv;
1183
1184 rcu_read_lock();
1185 sta = ieee80211_find_sta(ctx->vif, addr1);
1186 if (sta) {
1187 sta_priv = (void *)sta->drv_priv;
1188 /* avoid atomic ops if this isn't a client */
1189 if (sta_priv->client &&
1190 atomic_dec_return(&sta_priv->pending_frames) == 0)
1191 ieee80211_sta_block_awake(priv->hw, sta, false);
1192 }
1193 rcu_read_unlock();
1194 }
1195
1196 static void iwlagn_tx_status(struct iwl_priv *priv, struct iwl_tx_info *tx_info,
1197 bool is_agg)
1198 {
1199 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) tx_info->skb->data;
1200
1201 if (!is_agg)
1202 iwlagn_non_agg_tx_status(priv, tx_info->ctx, hdr->addr1);
1203
1204 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
1205 }
1206
1207 int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1208 {
1209 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1210 struct iwl_queue *q = &txq->q;
1211 struct iwl_tx_info *tx_info;
1212 int nfreed = 0;
1213 struct ieee80211_hdr *hdr;
1214
1215 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1216 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1217 "is out of range [0-%d] %d %d.\n", txq_id,
1218 index, q->n_bd, q->write_ptr, q->read_ptr);
1219 return 0;
1220 }
1221
1222 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1223 q->read_ptr != index;
1224 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1225
1226 tx_info = &txq->txb[txq->q.read_ptr];
1227 iwlagn_tx_status(priv, tx_info,
1228 txq_id >= IWLAGN_FIRST_AMPDU_QUEUE);
1229
1230 hdr = (struct ieee80211_hdr *)tx_info->skb->data;
1231 if (hdr && ieee80211_is_data_qos(hdr->frame_control))
1232 nfreed++;
1233 tx_info->skb = NULL;
1234
1235 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1236 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1237
1238 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1239 }
1240 return nfreed;
1241 }
1242
1243 /**
1244 * iwlagn_tx_status_reply_compressed_ba - Update tx status from block-ack
1245 *
1246 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1247 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1248 */
1249 static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1250 struct iwl_ht_agg *agg,
1251 struct iwl_compressed_ba_resp *ba_resp)
1252
1253 {
1254 int i, sh, ack;
1255 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1256 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1257 int successes = 0;
1258 struct ieee80211_tx_info *info;
1259
1260 if (unlikely(!agg->wait_for_ba)) {
1261 if (unlikely(ba_resp->bitmap))
1262 IWL_ERR(priv, "Received BA when not expected\n");
1263 return -EINVAL;
1264 }
1265
1266 /* Mark that the expected block-ack response arrived */
1267 agg->wait_for_ba = 0;
1268 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1269
1270 /* Calculate shift to align block-ack bits with our Tx window bits */
1271 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1272 if (sh < 0) /* tbw something is wrong with indices */
1273 sh += 0x100;
1274
1275 if (agg->frame_count > (64 - sh)) {
1276 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1277 return -1;
1278 }
1279 if (!priv->cfg->base_params->no_agg_framecnt_info && ba_resp->txed) {
1280 /*
1281 * sent and ack information provided by uCode
1282 * use it instead of figure out ourself
1283 */
1284 if (ba_resp->txed_2_done > ba_resp->txed) {
1285 IWL_DEBUG_TX_REPLY(priv,
1286 "bogus sent(%d) and ack(%d) count\n",
1287 ba_resp->txed, ba_resp->txed_2_done);
1288 /*
1289 * set txed_2_done = txed,
1290 * so it won't impact rate scale
1291 */
1292 ba_resp->txed = ba_resp->txed_2_done;
1293 }
1294 IWL_DEBUG_HT(priv, "agg frames sent:%d, acked:%d\n",
1295 ba_resp->txed, ba_resp->txed_2_done);
1296 } else {
1297 u64 bitmap, sent_bitmap;
1298
1299 /* don't use 64-bit values for now */
1300 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1301
1302 /* check for success or failure according to the
1303 * transmitted bitmap and block-ack bitmap */
1304 sent_bitmap = bitmap & agg->bitmap;
1305
1306 /* For each frame attempted in aggregation,
1307 * update driver's record of tx frame's status. */
1308 i = 0;
1309 while (sent_bitmap) {
1310 ack = sent_bitmap & 1ULL;
1311 successes += ack;
1312 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1313 ack ? "ACK" : "NACK", i,
1314 (agg->start_idx + i) & 0xff,
1315 agg->start_idx + i);
1316 sent_bitmap >>= 1;
1317 ++i;
1318 }
1319
1320 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n",
1321 (unsigned long long)bitmap);
1322 }
1323
1324 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb);
1325 memset(&info->status, 0, sizeof(info->status));
1326 info->flags |= IEEE80211_TX_STAT_ACK;
1327 info->flags |= IEEE80211_TX_STAT_AMPDU;
1328 if (!priv->cfg->base_params->no_agg_framecnt_info && ba_resp->txed) {
1329 info->status.ampdu_ack_len = ba_resp->txed_2_done;
1330 info->status.ampdu_len = ba_resp->txed;
1331
1332 } else {
1333 info->status.ampdu_ack_len = successes;
1334 info->status.ampdu_len = agg->frame_count;
1335 }
1336 iwlagn_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1337
1338 return 0;
1339 }
1340
1341 /**
1342 * translate ucode response to mac80211 tx status control values
1343 */
1344 void iwlagn_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
1345 struct ieee80211_tx_info *info)
1346 {
1347 struct ieee80211_tx_rate *r = &info->control.rates[0];
1348
1349 info->antenna_sel_tx =
1350 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
1351 if (rate_n_flags & RATE_MCS_HT_MSK)
1352 r->flags |= IEEE80211_TX_RC_MCS;
1353 if (rate_n_flags & RATE_MCS_GF_MSK)
1354 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
1355 if (rate_n_flags & RATE_MCS_HT40_MSK)
1356 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
1357 if (rate_n_flags & RATE_MCS_DUP_MSK)
1358 r->flags |= IEEE80211_TX_RC_DUP_DATA;
1359 if (rate_n_flags & RATE_MCS_SGI_MSK)
1360 r->flags |= IEEE80211_TX_RC_SHORT_GI;
1361 r->idx = iwlagn_hwrate_to_mac80211_idx(rate_n_flags, info->band);
1362 }
1363
1364 /**
1365 * iwlagn_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1366 *
1367 * Handles block-acknowledge notification from device, which reports success
1368 * of frames sent via aggregation.
1369 */
1370 void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv,
1371 struct iwl_rx_mem_buffer *rxb)
1372 {
1373 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1374 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1375 struct iwl_tx_queue *txq = NULL;
1376 struct iwl_ht_agg *agg;
1377 int index;
1378 int sta_id;
1379 int tid;
1380 unsigned long flags;
1381
1382 /* "flow" corresponds to Tx queue */
1383 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1384
1385 /* "ssn" is start of block-ack Tx window, corresponds to index
1386 * (in Tx queue's circular buffer) of first TFD/frame in window */
1387 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1388
1389 if (scd_flow >= priv->hw_params.max_txq_num) {
1390 IWL_ERR(priv,
1391 "BUG_ON scd_flow is bigger than number of queues\n");
1392 return;
1393 }
1394
1395 txq = &priv->txq[scd_flow];
1396 sta_id = ba_resp->sta_id;
1397 tid = ba_resp->tid;
1398 agg = &priv->stations[sta_id].tid[tid].agg;
1399 if (unlikely(agg->txq_id != scd_flow)) {
1400 /*
1401 * FIXME: this is a uCode bug which need to be addressed,
1402 * log the information and return for now!
1403 * since it is possible happen very often and in order
1404 * not to fill the syslog, don't enable the logging by default
1405 */
1406 IWL_DEBUG_TX_REPLY(priv,
1407 "BA scd_flow %d does not match txq_id %d\n",
1408 scd_flow, agg->txq_id);
1409 return;
1410 }
1411
1412 /* Find index just before block-ack window */
1413 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1414
1415 spin_lock_irqsave(&priv->sta_lock, flags);
1416
1417 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1418 "sta_id = %d\n",
1419 agg->wait_for_ba,
1420 (u8 *) &ba_resp->sta_addr_lo32,
1421 ba_resp->sta_id);
1422 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1423 "%d, scd_ssn = %d\n",
1424 ba_resp->tid,
1425 ba_resp->seq_ctl,
1426 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1427 ba_resp->scd_flow,
1428 ba_resp->scd_ssn);
1429 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx\n",
1430 agg->start_idx,
1431 (unsigned long long)agg->bitmap);
1432
1433 /* Update driver's record of ACK vs. not for each frame in window */
1434 iwlagn_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1435
1436 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1437 * block-ack window (we assume that they've been successfully
1438 * transmitted ... if not, it's too late anyway). */
1439 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1440 /* calculate mac80211 ampdu sw queue to wake */
1441 int freed = iwlagn_tx_queue_reclaim(priv, scd_flow, index);
1442 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1443
1444 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1445 priv->mac80211_registered &&
1446 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1447 iwl_wake_queue(priv, txq);
1448
1449 iwlagn_txq_check_empty(priv, sta_id, tid, scd_flow);
1450 }
1451
1452 spin_unlock_irqrestore(&priv->sta_lock, flags);
1453 }
1454
1455 #ifdef CONFIG_IWLWIFI_DEBUG
1456 const char *iwl_get_tx_fail_reason(u32 status)
1457 {
1458 #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
1459 #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
1460
1461 switch (status & TX_STATUS_MSK) {
1462 case TX_STATUS_SUCCESS:
1463 return "SUCCESS";
1464 TX_STATUS_POSTPONE(DELAY);
1465 TX_STATUS_POSTPONE(FEW_BYTES);
1466 TX_STATUS_POSTPONE(BT_PRIO);
1467 TX_STATUS_POSTPONE(QUIET_PERIOD);
1468 TX_STATUS_POSTPONE(CALC_TTAK);
1469 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
1470 TX_STATUS_FAIL(SHORT_LIMIT);
1471 TX_STATUS_FAIL(LONG_LIMIT);
1472 TX_STATUS_FAIL(FIFO_UNDERRUN);
1473 TX_STATUS_FAIL(DRAIN_FLOW);
1474 TX_STATUS_FAIL(RFKILL_FLUSH);
1475 TX_STATUS_FAIL(LIFE_EXPIRE);
1476 TX_STATUS_FAIL(DEST_PS);
1477 TX_STATUS_FAIL(HOST_ABORTED);
1478 TX_STATUS_FAIL(BT_RETRY);
1479 TX_STATUS_FAIL(STA_INVALID);
1480 TX_STATUS_FAIL(FRAG_DROPPED);
1481 TX_STATUS_FAIL(TID_DISABLE);
1482 TX_STATUS_FAIL(FIFO_FLUSHED);
1483 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
1484 TX_STATUS_FAIL(PASSIVE_NO_RX);
1485 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
1486 }
1487
1488 return "UNKNOWN";
1489
1490 #undef TX_STATUS_FAIL
1491 #undef TX_STATUS_POSTPONE
1492 }
1493 #endif /* CONFIG_IWLWIFI_DEBUG */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree