2 * Performance counter x86 architecture code
4 * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar
6 * Copyright(C) 2009 Jaswinder Singh Rajput
7 * Copyright(C) 2009 Advanced Micro Devices, Inc., Robert Richter
9 * For licencing details see kernel-base/COPYING
12 #include <linux/perf_counter.h>
13 #include <linux/capability.h>
14 #include <linux/notifier.h>
15 #include <linux/hardirq.h>
16 #include <linux/kprobes.h>
17 #include <linux/module.h>
18 #include <linux/kdebug.h>
19 #include <linux/sched.h>
20 #include <linux/uaccess.h>
23 #include <asm/stacktrace.h>
26 static bool perf_counters_initialized __read_mostly
;
27 static u64 perf_counter_mask __read_mostly
;
29 struct cpu_hw_counters
{
30 struct perf_counter
*counters
[X86_PMC_IDX_MAX
];
31 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
32 unsigned long active
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
33 unsigned long interrupts
;
39 * struct x86_pmu - generic x86 pmu
44 int (*handle_irq
)(struct pt_regs
*, int);
45 u64 (*save_disable_all
)(void);
46 void (*restore_all
)(u64
);
47 void (*enable
)(struct hw_perf_counter
*, int);
48 void (*disable
)(int, u64
);
51 u64 (*event_map
)(int);
52 u64 (*raw_event
)(u64
);
55 int num_counters_fixed
;
60 static struct x86_pmu x86_pmu __read_mostly
;
62 static DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
) = {
67 * Intel PerfMon v3. Used on Core2 and later.
69 static const u64 intel_perfmon_event_map
[] =
71 [PERF_COUNT_CPU_CYCLES
] = 0x003c,
72 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
73 [PERF_COUNT_CACHE_REFERENCES
] = 0x4f2e,
74 [PERF_COUNT_CACHE_MISSES
] = 0x412e,
75 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
76 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
77 [PERF_COUNT_BUS_CYCLES
] = 0x013c,
80 static u64
intel_pmu_event_map(int event
)
82 return intel_perfmon_event_map
[event
];
85 static u64
intel_pmu_raw_event(u64 event
)
87 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
88 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
89 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
91 #define CORE_EVNTSEL_MASK \
92 (CORE_EVNTSEL_EVENT_MASK | \
93 CORE_EVNTSEL_UNIT_MASK | \
94 CORE_EVNTSEL_COUNTER_MASK)
96 return event
& CORE_EVNTSEL_MASK
;
100 * AMD Performance Monitor K7 and later.
102 static const u64 amd_perfmon_event_map
[] =
104 [PERF_COUNT_CPU_CYCLES
] = 0x0076,
105 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
106 [PERF_COUNT_CACHE_REFERENCES
] = 0x0080,
107 [PERF_COUNT_CACHE_MISSES
] = 0x0081,
108 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
109 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
112 static u64
amd_pmu_event_map(int event
)
114 return amd_perfmon_event_map
[event
];
117 static u64
amd_pmu_raw_event(u64 event
)
119 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
120 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
121 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
123 #define K7_EVNTSEL_MASK \
124 (K7_EVNTSEL_EVENT_MASK | \
125 K7_EVNTSEL_UNIT_MASK | \
126 K7_EVNTSEL_COUNTER_MASK)
128 return event
& K7_EVNTSEL_MASK
;
132 * Propagate counter elapsed time into the generic counter.
133 * Can only be executed on the CPU where the counter is active.
134 * Returns the delta events processed.
137 x86_perf_counter_update(struct perf_counter
*counter
,
138 struct hw_perf_counter
*hwc
, int idx
)
140 u64 prev_raw_count
, new_raw_count
, delta
;
143 * Careful: an NMI might modify the previous counter value.
145 * Our tactic to handle this is to first atomically read and
146 * exchange a new raw count - then add that new-prev delta
147 * count to the generic counter atomically:
150 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
151 rdmsrl(hwc
->counter_base
+ idx
, new_raw_count
);
153 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
154 new_raw_count
) != prev_raw_count
)
158 * Now we have the new raw value and have updated the prev
159 * timestamp already. We can now calculate the elapsed delta
160 * (counter-)time and add that to the generic counter.
162 * Careful, not all hw sign-extends above the physical width
163 * of the count, so we do that by clipping the delta to 32 bits:
165 delta
= (u64
)(u32
)((s32
)new_raw_count
- (s32
)prev_raw_count
);
167 atomic64_add(delta
, &counter
->count
);
168 atomic64_sub(delta
, &hwc
->period_left
);
171 static atomic_t num_counters
;
172 static DEFINE_MUTEX(pmc_reserve_mutex
);
174 static bool reserve_pmc_hardware(void)
178 if (nmi_watchdog
== NMI_LOCAL_APIC
)
179 disable_lapic_nmi_watchdog();
181 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
182 if (!reserve_perfctr_nmi(x86_pmu
.perfctr
+ i
))
186 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
187 if (!reserve_evntsel_nmi(x86_pmu
.eventsel
+ i
))
194 for (i
--; i
>= 0; i
--)
195 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
197 i
= x86_pmu
.num_counters
;
200 for (i
--; i
>= 0; i
--)
201 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
203 if (nmi_watchdog
== NMI_LOCAL_APIC
)
204 enable_lapic_nmi_watchdog();
209 static void release_pmc_hardware(void)
213 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
214 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
215 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
218 if (nmi_watchdog
== NMI_LOCAL_APIC
)
219 enable_lapic_nmi_watchdog();
222 static void hw_perf_counter_destroy(struct perf_counter
*counter
)
224 if (atomic_dec_and_mutex_lock(&num_counters
, &pmc_reserve_mutex
)) {
225 release_pmc_hardware();
226 mutex_unlock(&pmc_reserve_mutex
);
231 * Setup the hardware configuration for a given hw_event_type
233 static int __hw_perf_counter_init(struct perf_counter
*counter
)
235 struct perf_counter_hw_event
*hw_event
= &counter
->hw_event
;
236 struct hw_perf_counter
*hwc
= &counter
->hw
;
239 /* disable temporarily */
240 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
243 if (unlikely(!perf_counters_initialized
))
247 if (atomic_inc_not_zero(&num_counters
)) {
248 mutex_lock(&pmc_reserve_mutex
);
249 if (atomic_read(&num_counters
) == 0 && !reserve_pmc_hardware())
252 atomic_inc(&num_counters
);
253 mutex_unlock(&pmc_reserve_mutex
);
260 * (keep 'enabled' bit clear for now)
262 hwc
->config
= ARCH_PERFMON_EVENTSEL_INT
;
265 * Count user and OS events unless requested not to.
267 if (!hw_event
->exclude_user
)
268 hwc
->config
|= ARCH_PERFMON_EVENTSEL_USR
;
269 if (!hw_event
->exclude_kernel
)
270 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
273 * If privileged enough, allow NMI events:
276 if (capable(CAP_SYS_ADMIN
) && hw_event
->nmi
)
279 hwc
->irq_period
= hw_event
->irq_period
;
281 * Intel PMCs cannot be accessed sanely above 32 bit width,
282 * so we install an artificial 1<<31 period regardless of
283 * the generic counter period:
285 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
286 if ((s64
)hwc
->irq_period
<= 0 || hwc
->irq_period
> 0x7FFFFFFF)
287 hwc
->irq_period
= 0x7FFFFFFF;
289 atomic64_set(&hwc
->period_left
, hwc
->irq_period
);
292 * Raw event type provide the config in the event structure
294 if (perf_event_raw(hw_event
)) {
295 hwc
->config
|= x86_pmu
.raw_event(perf_event_config(hw_event
));
297 if (perf_event_id(hw_event
) >= x86_pmu
.max_events
)
302 hwc
->config
|= x86_pmu
.event_map(perf_event_id(hw_event
));
305 counter
->destroy
= hw_perf_counter_destroy
;
310 static u64
intel_pmu_save_disable_all(void)
314 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
315 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
320 static u64
amd_pmu_save_disable_all(void)
322 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
325 enabled
= cpuc
->enabled
;
328 * ensure we write the disable before we start disabling the
329 * counters proper, so that amd_pmu_enable_counter() does the
334 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
337 if (!test_bit(idx
, cpuc
->active
))
339 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
340 if (!(val
& ARCH_PERFMON_EVENTSEL0_ENABLE
))
342 val
&= ~ARCH_PERFMON_EVENTSEL0_ENABLE
;
343 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
349 u64
hw_perf_save_disable(void)
351 if (unlikely(!perf_counters_initialized
))
354 return x86_pmu
.save_disable_all();
357 * Exported because of ACPI idle
359 EXPORT_SYMBOL_GPL(hw_perf_save_disable
);
361 static void intel_pmu_restore_all(u64 ctrl
)
363 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
366 static void amd_pmu_restore_all(u64 ctrl
)
368 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
371 cpuc
->enabled
= ctrl
;
376 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
379 if (!test_bit(idx
, cpuc
->active
))
381 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
382 if (val
& ARCH_PERFMON_EVENTSEL0_ENABLE
)
384 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
385 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
389 void hw_perf_restore(u64 ctrl
)
391 if (unlikely(!perf_counters_initialized
))
394 x86_pmu
.restore_all(ctrl
);
397 * Exported because of ACPI idle
399 EXPORT_SYMBOL_GPL(hw_perf_restore
);
401 static inline u64
intel_pmu_get_status(u64 mask
)
405 if (unlikely(!perf_counters_initialized
))
407 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
412 static inline void intel_pmu_ack_status(u64 ack
)
414 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
417 static inline void x86_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
421 if (unlikely(!perf_counters_initialized
))
424 err
= checking_wrmsrl(hwc
->config_base
+ idx
,
425 hwc
->config
| ARCH_PERFMON_EVENTSEL0_ENABLE
);
428 static void intel_pmu_disable_counter(int idx
, u64 config
)
430 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ idx
, config
);
433 static void amd_pmu_disable_counter(int idx
, u64 config
)
435 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, config
);
439 static void hw_perf_disable(int idx
, u64 config
)
441 if (unlikely(!perf_counters_initialized
))
444 x86_pmu
.disable(idx
, config
);
448 __pmc_fixed_disable(struct perf_counter
*counter
,
449 struct hw_perf_counter
*hwc
, int __idx
)
451 int idx
= __idx
- X86_PMC_IDX_FIXED
;
455 mask
= 0xfULL
<< (idx
* 4);
457 rdmsrl(hwc
->config_base
, ctrl_val
);
459 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
463 __x86_pmu_disable(struct perf_counter
*counter
,
464 struct hw_perf_counter
*hwc
, int idx
)
466 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
467 __pmc_fixed_disable(counter
, hwc
, idx
);
469 hw_perf_disable(idx
, hwc
->config
);
472 static DEFINE_PER_CPU(u64
, prev_left
[X86_PMC_IDX_MAX
]);
475 * Set the next IRQ period, based on the hwc->period_left value.
476 * To be called with the counter disabled in hw:
479 x86_perf_counter_set_period(struct perf_counter
*counter
,
480 struct hw_perf_counter
*hwc
, int idx
)
482 s64 left
= atomic64_read(&hwc
->period_left
);
483 s64 period
= hwc
->irq_period
;
487 * If we are way outside a reasoable range then just skip forward:
489 if (unlikely(left
<= -period
)) {
491 atomic64_set(&hwc
->period_left
, left
);
494 if (unlikely(left
<= 0)) {
496 atomic64_set(&hwc
->period_left
, left
);
499 per_cpu(prev_left
[idx
], smp_processor_id()) = left
;
502 * The hw counter starts counting from this counter offset,
503 * mark it to be able to extra future deltas:
505 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
507 err
= checking_wrmsrl(hwc
->counter_base
+ idx
,
508 (u64
)(-left
) & x86_pmu
.counter_mask
);
512 intel_pmu_enable_fixed(struct hw_perf_counter
*hwc
, int __idx
)
514 int idx
= __idx
- X86_PMC_IDX_FIXED
;
515 u64 ctrl_val
, bits
, mask
;
519 * Enable IRQ generation (0x8),
520 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
524 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_USR
)
526 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
529 mask
= 0xfULL
<< (idx
* 4);
531 rdmsrl(hwc
->config_base
, ctrl_val
);
534 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
537 static void intel_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
539 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
540 intel_pmu_enable_fixed(hwc
, idx
);
544 x86_pmu_enable_counter(hwc
, idx
);
547 static void amd_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
549 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
552 x86_pmu_enable_counter(hwc
, idx
);
554 amd_pmu_disable_counter(idx
, hwc
->config
);
558 fixed_mode_idx(struct perf_counter
*counter
, struct hw_perf_counter
*hwc
)
562 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
565 if (unlikely(hwc
->nmi
))
568 event
= hwc
->config
& ARCH_PERFMON_EVENT_MASK
;
570 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_INSTRUCTIONS
)))
571 return X86_PMC_IDX_FIXED_INSTRUCTIONS
;
572 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_CPU_CYCLES
)))
573 return X86_PMC_IDX_FIXED_CPU_CYCLES
;
574 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_BUS_CYCLES
)))
575 return X86_PMC_IDX_FIXED_BUS_CYCLES
;
581 * Find a PMC slot for the freshly enabled / scheduled in counter:
583 static int x86_pmu_enable(struct perf_counter
*counter
)
585 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
586 struct hw_perf_counter
*hwc
= &counter
->hw
;
589 idx
= fixed_mode_idx(counter
, hwc
);
592 * Try to get the fixed counter, if that is already taken
593 * then try to get a generic counter:
595 if (test_and_set_bit(idx
, cpuc
->used
))
598 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
600 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
601 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
604 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
608 /* Try to get the previous generic counter again */
609 if (test_and_set_bit(idx
, cpuc
->used
)) {
611 idx
= find_first_zero_bit(cpuc
->used
,
612 x86_pmu
.num_counters
);
613 if (idx
== x86_pmu
.num_counters
)
616 set_bit(idx
, cpuc
->used
);
619 hwc
->config_base
= x86_pmu
.eventsel
;
620 hwc
->counter_base
= x86_pmu
.perfctr
;
623 perf_counters_lapic_init(hwc
->nmi
);
625 __x86_pmu_disable(counter
, hwc
, idx
);
627 cpuc
->counters
[idx
] = counter
;
628 set_bit(idx
, cpuc
->active
);
630 x86_perf_counter_set_period(counter
, hwc
, idx
);
631 x86_pmu
.enable(hwc
, idx
);
636 void perf_counter_print_debug(void)
638 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
639 struct cpu_hw_counters
*cpuc
;
642 if (!x86_pmu
.num_counters
)
647 cpu
= smp_processor_id();
648 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
650 if (x86_pmu
.version
>= 2) {
651 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
652 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
653 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
654 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
657 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
658 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
659 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
660 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
662 pr_info("CPU#%d: used: %016llx\n", cpu
, *(u64
*)cpuc
->used
);
664 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
665 rdmsrl(x86_pmu
.eventsel
+ idx
, pmc_ctrl
);
666 rdmsrl(x86_pmu
.perfctr
+ idx
, pmc_count
);
668 prev_left
= per_cpu(prev_left
[idx
], cpu
);
670 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
672 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
673 cpu
, idx
, pmc_count
);
674 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
675 cpu
, idx
, prev_left
);
677 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
678 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
680 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
681 cpu
, idx
, pmc_count
);
686 static void x86_pmu_disable(struct perf_counter
*counter
)
688 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
689 struct hw_perf_counter
*hwc
= &counter
->hw
;
693 * Must be done before we disable, otherwise the nmi handler
694 * could reenable again:
696 clear_bit(idx
, cpuc
->active
);
697 __x86_pmu_disable(counter
, hwc
, idx
);
700 * Make sure the cleared pointer becomes visible before we
701 * (potentially) free the counter:
706 * Drain the remaining delta count out of a counter
707 * that we are disabling:
709 x86_perf_counter_update(counter
, hwc
, idx
);
710 cpuc
->counters
[idx
] = NULL
;
711 clear_bit(idx
, cpuc
->used
);
715 * Save and restart an expired counter. Called by NMI contexts,
716 * so it has to be careful about preempting normal counter ops:
718 static void intel_pmu_save_and_restart(struct perf_counter
*counter
)
720 struct hw_perf_counter
*hwc
= &counter
->hw
;
723 x86_perf_counter_update(counter
, hwc
, idx
);
724 x86_perf_counter_set_period(counter
, hwc
, idx
);
726 if (counter
->state
== PERF_COUNTER_STATE_ACTIVE
)
727 intel_pmu_enable_counter(hwc
, idx
);
731 * Maximum interrupt frequency of 100KHz per CPU
733 #define PERFMON_MAX_INTERRUPTS (100000/HZ)
736 * This handler is triggered by the local APIC, so the APIC IRQ handling
739 static int intel_pmu_handle_irq(struct pt_regs
*regs
, int nmi
)
741 int bit
, cpu
= smp_processor_id();
743 struct cpu_hw_counters
*cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
746 cpuc
->throttle_ctrl
= intel_pmu_save_disable_all();
748 status
= intel_pmu_get_status(cpuc
->throttle_ctrl
);
754 inc_irq_stat(apic_perf_irqs
);
756 for_each_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
757 struct perf_counter
*counter
= cpuc
->counters
[bit
];
759 clear_bit(bit
, (unsigned long *) &status
);
760 if (!test_bit(bit
, cpuc
->active
))
763 intel_pmu_save_and_restart(counter
);
764 if (perf_counter_overflow(counter
, nmi
, regs
, 0))
765 __x86_pmu_disable(counter
, &counter
->hw
, bit
);
768 intel_pmu_ack_status(ack
);
771 * Repeat if there is more work to be done:
773 status
= intel_pmu_get_status(cpuc
->throttle_ctrl
);
778 * Restore - do not reenable when global enable is off or throttled:
780 if (++cpuc
->interrupts
< PERFMON_MAX_INTERRUPTS
)
781 intel_pmu_restore_all(cpuc
->throttle_ctrl
);
786 static int amd_pmu_handle_irq(struct pt_regs
*regs
, int nmi
) { return 0; }
788 void perf_counter_unthrottle(void)
790 struct cpu_hw_counters
*cpuc
;
792 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
795 if (unlikely(!perf_counters_initialized
))
798 cpuc
= &__get_cpu_var(cpu_hw_counters
);
799 if (cpuc
->interrupts
>= PERFMON_MAX_INTERRUPTS
) {
800 if (printk_ratelimit())
801 printk(KERN_WARNING
"PERFMON: max interrupts exceeded!\n");
802 hw_perf_restore(cpuc
->throttle_ctrl
);
804 cpuc
->interrupts
= 0;
807 void smp_perf_counter_interrupt(struct pt_regs
*regs
)
810 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
812 x86_pmu
.handle_irq(regs
, 0);
816 void smp_perf_pending_interrupt(struct pt_regs
*regs
)
820 inc_irq_stat(apic_pending_irqs
);
821 perf_counter_do_pending();
825 void set_perf_counter_pending(void)
827 apic
->send_IPI_self(LOCAL_PENDING_VECTOR
);
830 void perf_counters_lapic_init(int nmi
)
834 if (!perf_counters_initialized
)
837 * Enable the performance counter vector in the APIC LVT:
839 apic_val
= apic_read(APIC_LVTERR
);
841 apic_write(APIC_LVTERR
, apic_val
| APIC_LVT_MASKED
);
843 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
845 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
846 apic_write(APIC_LVTERR
, apic_val
);
850 perf_counter_nmi_handler(struct notifier_block
*self
,
851 unsigned long cmd
, void *__args
)
853 struct die_args
*args
= __args
;
854 struct pt_regs
*regs
;
868 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
869 ret
= x86_pmu
.handle_irq(regs
, 1);
871 return ret
? NOTIFY_STOP
: NOTIFY_OK
;
874 static __read_mostly
struct notifier_block perf_counter_nmi_notifier
= {
875 .notifier_call
= perf_counter_nmi_handler
,
880 static struct x86_pmu intel_pmu
= {
882 .handle_irq
= intel_pmu_handle_irq
,
883 .save_disable_all
= intel_pmu_save_disable_all
,
884 .restore_all
= intel_pmu_restore_all
,
885 .enable
= intel_pmu_enable_counter
,
886 .disable
= intel_pmu_disable_counter
,
887 .eventsel
= MSR_ARCH_PERFMON_EVENTSEL0
,
888 .perfctr
= MSR_ARCH_PERFMON_PERFCTR0
,
889 .event_map
= intel_pmu_event_map
,
890 .raw_event
= intel_pmu_raw_event
,
891 .max_events
= ARRAY_SIZE(intel_perfmon_event_map
),
894 static struct x86_pmu amd_pmu
= {
896 .handle_irq
= amd_pmu_handle_irq
,
897 .save_disable_all
= amd_pmu_save_disable_all
,
898 .restore_all
= amd_pmu_restore_all
,
899 .enable
= amd_pmu_enable_counter
,
900 .disable
= amd_pmu_disable_counter
,
901 .eventsel
= MSR_K7_EVNTSEL0
,
902 .perfctr
= MSR_K7_PERFCTR0
,
903 .event_map
= amd_pmu_event_map
,
904 .raw_event
= amd_pmu_raw_event
,
905 .max_events
= ARRAY_SIZE(amd_perfmon_event_map
),
908 .counter_mask
= (1ULL << 48) - 1,
911 static int intel_pmu_init(void)
913 union cpuid10_edx edx
;
914 union cpuid10_eax eax
;
919 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
923 * Check whether the Architectural PerfMon supports
924 * Branch Misses Retired Event or not.
926 cpuid(10, &eax
.full
, &ebx
, &unused
, &edx
.full
);
927 if (eax
.split
.mask_length
<= ARCH_PERFMON_BRANCH_MISSES_RETIRED
)
930 version
= eax
.split
.version_id
;
935 x86_pmu
.version
= version
;
936 x86_pmu
.num_counters
= eax
.split
.num_counters
;
937 x86_pmu
.num_counters_fixed
= edx
.split
.num_counters_fixed
;
938 x86_pmu
.counter_bits
= eax
.split
.bit_width
;
939 x86_pmu
.counter_mask
= (1ULL << eax
.split
.bit_width
) - 1;
944 static int amd_pmu_init(void)
950 void __init
init_hw_perf_counters(void)
954 switch (boot_cpu_data
.x86_vendor
) {
955 case X86_VENDOR_INTEL
:
956 err
= intel_pmu_init();
959 err
= amd_pmu_init();
967 pr_info("%s Performance Monitoring support detected.\n", x86_pmu
.name
);
968 pr_info("... version: %d\n", x86_pmu
.version
);
969 pr_info("... bit width: %d\n", x86_pmu
.counter_bits
);
971 pr_info("... num counters: %d\n", x86_pmu
.num_counters
);
972 if (x86_pmu
.num_counters
> X86_PMC_MAX_GENERIC
) {
973 x86_pmu
.num_counters
= X86_PMC_MAX_GENERIC
;
974 WARN(1, KERN_ERR
"hw perf counters %d > max(%d), clipping!",
975 x86_pmu
.num_counters
, X86_PMC_MAX_GENERIC
);
977 perf_counter_mask
= (1 << x86_pmu
.num_counters
) - 1;
978 perf_max_counters
= x86_pmu
.num_counters
;
980 pr_info("... value mask: %016Lx\n", x86_pmu
.counter_mask
);
982 if (x86_pmu
.num_counters_fixed
> X86_PMC_MAX_FIXED
) {
983 x86_pmu
.num_counters_fixed
= X86_PMC_MAX_FIXED
;
984 WARN(1, KERN_ERR
"hw perf counters fixed %d > max(%d), clipping!",
985 x86_pmu
.num_counters_fixed
, X86_PMC_MAX_FIXED
);
987 pr_info("... fixed counters: %d\n", x86_pmu
.num_counters_fixed
);
990 ((1LL << x86_pmu
.num_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
992 pr_info("... counter mask: %016Lx\n", perf_counter_mask
);
993 perf_counters_initialized
= true;
995 perf_counters_lapic_init(0);
996 register_die_notifier(&perf_counter_nmi_notifier
);
999 static inline void x86_pmu_read(struct perf_counter
*counter
)
1001 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
1004 static const struct pmu pmu
= {
1005 .enable
= x86_pmu_enable
,
1006 .disable
= x86_pmu_disable
,
1007 .read
= x86_pmu_read
,
1010 const struct pmu
*hw_perf_counter_init(struct perf_counter
*counter
)
1014 err
= __hw_perf_counter_init(counter
);
1016 return ERR_PTR(err
);
1026 void callchain_store(struct perf_callchain_entry
*entry
, unsigned long ip
)
1028 if (entry
->nr
< MAX_STACK_DEPTH
)
1029 entry
->ip
[entry
->nr
++] = ip
;
1032 static DEFINE_PER_CPU(struct perf_callchain_entry
, irq_entry
);
1033 static DEFINE_PER_CPU(struct perf_callchain_entry
, nmi_entry
);
1037 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1039 /* Ignore warnings */
1042 static void backtrace_warning(void *data
, char *msg
)
1044 /* Ignore warnings */
1047 static int backtrace_stack(void *data
, char *name
)
1049 /* Don't bother with IRQ stacks for now */
1053 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1055 struct perf_callchain_entry
*entry
= data
;
1058 callchain_store(entry
, addr
);
1061 static const struct stacktrace_ops backtrace_ops
= {
1062 .warning
= backtrace_warning
,
1063 .warning_symbol
= backtrace_warning_symbol
,
1064 .stack
= backtrace_stack
,
1065 .address
= backtrace_address
,
1069 perf_callchain_kernel(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1075 callchain_store(entry
, instruction_pointer(regs
));
1077 stack
= ((char *)regs
+ sizeof(struct pt_regs
));
1078 #ifdef CONFIG_FRAME_POINTER
1079 bp
= frame_pointer(regs
);
1084 dump_trace(NULL
, regs
, (void *)stack
, bp
, &backtrace_ops
, entry
);
1086 entry
->kernel
= entry
->nr
- nr
;
1090 struct stack_frame
{
1091 const void __user
*next_fp
;
1092 unsigned long return_address
;
1095 static int copy_stack_frame(const void __user
*fp
, struct stack_frame
*frame
)
1099 if (!access_ok(VERIFY_READ
, fp
, sizeof(*frame
)))
1103 pagefault_disable();
1104 if (__copy_from_user_inatomic(frame
, fp
, sizeof(*frame
)))
1112 perf_callchain_user(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1114 struct stack_frame frame
;
1115 const void __user
*fp
;
1118 regs
= (struct pt_regs
*)current
->thread
.sp0
- 1;
1119 fp
= (void __user
*)regs
->bp
;
1121 callchain_store(entry
, regs
->ip
);
1123 while (entry
->nr
< MAX_STACK_DEPTH
) {
1124 frame
.next_fp
= NULL
;
1125 frame
.return_address
= 0;
1127 if (!copy_stack_frame(fp
, &frame
))
1130 if ((unsigned long)fp
< user_stack_pointer(regs
))
1133 callchain_store(entry
, frame
.return_address
);
1137 entry
->user
= entry
->nr
- nr
;
1141 perf_do_callchain(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1148 is_user
= user_mode(regs
);
1150 if (!current
|| current
->pid
== 0)
1153 if (is_user
&& current
->state
!= TASK_RUNNING
)
1157 perf_callchain_kernel(regs
, entry
);
1160 perf_callchain_user(regs
, entry
);
1163 struct perf_callchain_entry
*perf_callchain(struct pt_regs
*regs
)
1165 struct perf_callchain_entry
*entry
;
1168 entry
= &__get_cpu_var(nmi_entry
);
1170 entry
= &__get_cpu_var(irq_entry
);
1177 perf_do_callchain(regs
, entry
);