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x86/amd-iommu: Keep devices per domain in a list
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kernel / amd_iommu.c
blob530d6080940ffe6b798eab9a4cbb1b7ed4db8f5a
1 /*
2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
30 #include <asm/gart.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
34
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36
37 #define EXIT_LOOP_COUNT 10000000
38
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44
45 /*
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
48 */
49 static struct protection_domain *pt_domain;
50
51 static struct iommu_ops amd_iommu_ops;
52
53 /*
54 * general struct to manage commands send to an IOMMU
55 */
56 struct iommu_cmd {
57 u32 data[4];
58 };
59
60 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
61 static void update_domain(struct protection_domain *domain);
62
63 /****************************************************************************
64 *
65 * Helper functions
66 *
67 ****************************************************************************/
68
69 static inline u16 get_device_id(struct device *dev)
70 {
71 struct pci_dev *pdev = to_pci_dev(dev);
72
73 return calc_devid(pdev->bus->number, pdev->devfn);
74 }
75
76 static struct iommu_dev_data *get_dev_data(struct device *dev)
77 {
78 return dev->archdata.iommu;
79 }
80
81 /*
82 * In this function the list of preallocated protection domains is traversed to
83 * find the domain for a specific device
84 */
85 static struct dma_ops_domain *find_protection_domain(u16 devid)
86 {
87 struct dma_ops_domain *entry, *ret = NULL;
88 unsigned long flags;
89 u16 alias = amd_iommu_alias_table[devid];
90
91 if (list_empty(&iommu_pd_list))
92 return NULL;
93
94 spin_lock_irqsave(&iommu_pd_list_lock, flags);
95
96 list_for_each_entry(entry, &iommu_pd_list, list) {
97 if (entry->target_dev == devid ||
98 entry->target_dev == alias) {
99 ret = entry;
100 break;
101 }
102 }
103
104 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
105
106 return ret;
107 }
108
109 /*
110 * This function checks if the driver got a valid device from the caller to
111 * avoid dereferencing invalid pointers.
112 */
113 static bool check_device(struct device *dev)
114 {
115 u16 devid;
116
117 if (!dev || !dev->dma_mask)
118 return false;
119
120 /* No device or no PCI device */
121 if (!dev || dev->bus != &pci_bus_type)
122 return false;
123
124 devid = get_device_id(dev);
125
126 /* Out of our scope? */
127 if (devid > amd_iommu_last_bdf)
128 return false;
129
130 if (amd_iommu_rlookup_table[devid] == NULL)
131 return false;
132
133 return true;
134 }
135
136 static int iommu_init_device(struct device *dev)
137 {
138 struct iommu_dev_data *dev_data;
139 struct pci_dev *pdev;
140 u16 devid, alias;
141
142 if (dev->archdata.iommu)
143 return 0;
144
145 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
146 if (!dev_data)
147 return -ENOMEM;
148
149 devid = get_device_id(dev);
150 alias = amd_iommu_alias_table[devid];
151 pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
152 if (pdev)
153 dev_data->alias = &pdev->dev;
154
155 atomic_set(&dev_data->bind, 0);
156
157 dev->archdata.iommu = dev_data;
158
159
160 return 0;
161 }
162
163 static void iommu_uninit_device(struct device *dev)
164 {
165 kfree(dev->archdata.iommu);
166 }
167 #ifdef CONFIG_AMD_IOMMU_STATS
168
169 /*
170 * Initialization code for statistics collection
171 */
172
173 DECLARE_STATS_COUNTER(compl_wait);
174 DECLARE_STATS_COUNTER(cnt_map_single);
175 DECLARE_STATS_COUNTER(cnt_unmap_single);
176 DECLARE_STATS_COUNTER(cnt_map_sg);
177 DECLARE_STATS_COUNTER(cnt_unmap_sg);
178 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
179 DECLARE_STATS_COUNTER(cnt_free_coherent);
180 DECLARE_STATS_COUNTER(cross_page);
181 DECLARE_STATS_COUNTER(domain_flush_single);
182 DECLARE_STATS_COUNTER(domain_flush_all);
183 DECLARE_STATS_COUNTER(alloced_io_mem);
184 DECLARE_STATS_COUNTER(total_map_requests);
185
186 static struct dentry *stats_dir;
187 static struct dentry *de_fflush;
188
189 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
190 {
191 if (stats_dir == NULL)
192 return;
193
194 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
195 &cnt->value);
196 }
197
198 static void amd_iommu_stats_init(void)
199 {
200 stats_dir = debugfs_create_dir("amd-iommu", NULL);
201 if (stats_dir == NULL)
202 return;
203
204 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
205 (u32 *)&amd_iommu_unmap_flush);
206
207 amd_iommu_stats_add(&compl_wait);
208 amd_iommu_stats_add(&cnt_map_single);
209 amd_iommu_stats_add(&cnt_unmap_single);
210 amd_iommu_stats_add(&cnt_map_sg);
211 amd_iommu_stats_add(&cnt_unmap_sg);
212 amd_iommu_stats_add(&cnt_alloc_coherent);
213 amd_iommu_stats_add(&cnt_free_coherent);
214 amd_iommu_stats_add(&cross_page);
215 amd_iommu_stats_add(&domain_flush_single);
216 amd_iommu_stats_add(&domain_flush_all);
217 amd_iommu_stats_add(&alloced_io_mem);
218 amd_iommu_stats_add(&total_map_requests);
219 }
220
221 #endif
222
223 /****************************************************************************
224 *
225 * Interrupt handling functions
226 *
227 ****************************************************************************/
228
229 static void dump_dte_entry(u16 devid)
230 {
231 int i;
232
233 for (i = 0; i < 8; ++i)
234 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
235 amd_iommu_dev_table[devid].data[i]);
236 }
237
238 static void dump_command(unsigned long phys_addr)
239 {
240 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
241 int i;
242
243 for (i = 0; i < 4; ++i)
244 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
245 }
246
247 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
248 {
249 u32 *event = __evt;
250 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
251 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
252 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
253 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
254 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
255
256 printk(KERN_ERR "AMD-Vi: Event logged [");
257
258 switch (type) {
259 case EVENT_TYPE_ILL_DEV:
260 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
261 "address=0x%016llx flags=0x%04x]\n",
262 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
263 address, flags);
264 dump_dte_entry(devid);
265 break;
266 case EVENT_TYPE_IO_FAULT:
267 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
268 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
269 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
270 domid, address, flags);
271 break;
272 case EVENT_TYPE_DEV_TAB_ERR:
273 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
274 "address=0x%016llx flags=0x%04x]\n",
275 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
276 address, flags);
277 break;
278 case EVENT_TYPE_PAGE_TAB_ERR:
279 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
280 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
281 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
282 domid, address, flags);
283 break;
284 case EVENT_TYPE_ILL_CMD:
285 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
286 reset_iommu_command_buffer(iommu);
287 dump_command(address);
288 break;
289 case EVENT_TYPE_CMD_HARD_ERR:
290 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
291 "flags=0x%04x]\n", address, flags);
292 break;
293 case EVENT_TYPE_IOTLB_INV_TO:
294 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
295 "address=0x%016llx]\n",
296 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
297 address);
298 break;
299 case EVENT_TYPE_INV_DEV_REQ:
300 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
301 "address=0x%016llx flags=0x%04x]\n",
302 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
303 address, flags);
304 break;
305 default:
306 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
307 }
308 }
309
310 static void iommu_poll_events(struct amd_iommu *iommu)
311 {
312 u32 head, tail;
313 unsigned long flags;
314
315 spin_lock_irqsave(&iommu->lock, flags);
316
317 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
318 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
319
320 while (head != tail) {
321 iommu_print_event(iommu, iommu->evt_buf + head);
322 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
323 }
324
325 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
326
327 spin_unlock_irqrestore(&iommu->lock, flags);
328 }
329
330 irqreturn_t amd_iommu_int_handler(int irq, void *data)
331 {
332 struct amd_iommu *iommu;
333
334 for_each_iommu(iommu)
335 iommu_poll_events(iommu);
336
337 return IRQ_HANDLED;
338 }
339
340 /****************************************************************************
341 *
342 * IOMMU command queuing functions
343 *
344 ****************************************************************************/
345
346 /*
347 * Writes the command to the IOMMUs command buffer and informs the
348 * hardware about the new command. Must be called with iommu->lock held.
349 */
350 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
351 {
352 u32 tail, head;
353 u8 *target;
354
355 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
356 target = iommu->cmd_buf + tail;
357 memcpy_toio(target, cmd, sizeof(*cmd));
358 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
359 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
360 if (tail == head)
361 return -ENOMEM;
362 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
363
364 return 0;
365 }
366
367 /*
368 * General queuing function for commands. Takes iommu->lock and calls
369 * __iommu_queue_command().
370 */
371 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
372 {
373 unsigned long flags;
374 int ret;
375
376 spin_lock_irqsave(&iommu->lock, flags);
377 ret = __iommu_queue_command(iommu, cmd);
378 if (!ret)
379 iommu->need_sync = true;
380 spin_unlock_irqrestore(&iommu->lock, flags);
381
382 return ret;
383 }
384
385 /*
386 * This function waits until an IOMMU has completed a completion
387 * wait command
388 */
389 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
390 {
391 int ready = 0;
392 unsigned status = 0;
393 unsigned long i = 0;
394
395 INC_STATS_COUNTER(compl_wait);
396
397 while (!ready && (i < EXIT_LOOP_COUNT)) {
398 ++i;
399 /* wait for the bit to become one */
400 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
401 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
402 }
403
404 /* set bit back to zero */
405 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
406 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
407
408 if (unlikely(i == EXIT_LOOP_COUNT)) {
409 spin_unlock(&iommu->lock);
410 reset_iommu_command_buffer(iommu);
411 spin_lock(&iommu->lock);
412 }
413 }
414
415 /*
416 * This function queues a completion wait command into the command
417 * buffer of an IOMMU
418 */
419 static int __iommu_completion_wait(struct amd_iommu *iommu)
420 {
421 struct iommu_cmd cmd;
422
423 memset(&cmd, 0, sizeof(cmd));
424 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
425 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
426
427 return __iommu_queue_command(iommu, &cmd);
428 }
429
430 /*
431 * This function is called whenever we need to ensure that the IOMMU has
432 * completed execution of all commands we sent. It sends a
433 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
434 * us about that by writing a value to a physical address we pass with
435 * the command.
436 */
437 static int iommu_completion_wait(struct amd_iommu *iommu)
438 {
439 int ret = 0;
440 unsigned long flags;
441
442 spin_lock_irqsave(&iommu->lock, flags);
443
444 if (!iommu->need_sync)
445 goto out;
446
447 ret = __iommu_completion_wait(iommu);
448
449 iommu->need_sync = false;
450
451 if (ret)
452 goto out;
453
454 __iommu_wait_for_completion(iommu);
455
456 out:
457 spin_unlock_irqrestore(&iommu->lock, flags);
458
459 return 0;
460 }
461
462 static void iommu_flush_complete(struct protection_domain *domain)
463 {
464 int i;
465
466 for (i = 0; i < amd_iommus_present; ++i) {
467 if (!domain->dev_iommu[i])
468 continue;
469
470 /*
471 * Devices of this domain are behind this IOMMU
472 * We need to wait for completion of all commands.
473 */
474 iommu_completion_wait(amd_iommus[i]);
475 }
476 }
477
478 /*
479 * Command send function for invalidating a device table entry
480 */
481 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
482 {
483 struct iommu_cmd cmd;
484 int ret;
485
486 BUG_ON(iommu == NULL);
487
488 memset(&cmd, 0, sizeof(cmd));
489 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
490 cmd.data[0] = devid;
491
492 ret = iommu_queue_command(iommu, &cmd);
493
494 return ret;
495 }
496
497 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
498 u16 domid, int pde, int s)
499 {
500 memset(cmd, 0, sizeof(*cmd));
501 address &= PAGE_MASK;
502 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
503 cmd->data[1] |= domid;
504 cmd->data[2] = lower_32_bits(address);
505 cmd->data[3] = upper_32_bits(address);
506 if (s) /* size bit - we flush more than one 4kb page */
507 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
508 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
509 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
510 }
511
512 /*
513 * Generic command send function for invalidaing TLB entries
514 */
515 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
516 u64 address, u16 domid, int pde, int s)
517 {
518 struct iommu_cmd cmd;
519 int ret;
520
521 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
522
523 ret = iommu_queue_command(iommu, &cmd);
524
525 return ret;
526 }
527
528 /*
529 * TLB invalidation function which is called from the mapping functions.
530 * It invalidates a single PTE if the range to flush is within a single
531 * page. Otherwise it flushes the whole TLB of the IOMMU.
532 */
533 static void __iommu_flush_pages(struct protection_domain *domain,
534 u64 address, size_t size, int pde)
535 {
536 int s = 0, i;
537 unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE);
538
539 address &= PAGE_MASK;
540
541 if (pages > 1) {
542 /*
543 * If we have to flush more than one page, flush all
544 * TLB entries for this domain
545 */
546 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
547 s = 1;
548 }
549
550
551 for (i = 0; i < amd_iommus_present; ++i) {
552 if (!domain->dev_iommu[i])
553 continue;
554
555 /*
556 * Devices of this domain are behind this IOMMU
557 * We need a TLB flush
558 */
559 iommu_queue_inv_iommu_pages(amd_iommus[i], address,
560 domain->id, pde, s);
561 }
562
563 return;
564 }
565
566 static void iommu_flush_pages(struct protection_domain *domain,
567 u64 address, size_t size)
568 {
569 __iommu_flush_pages(domain, address, size, 0);
570 }
571
572 /* Flush the whole IO/TLB for a given protection domain */
573 static void iommu_flush_tlb(struct protection_domain *domain)
574 {
575 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
576 }
577
578 /* Flush the whole IO/TLB for a given protection domain - including PDE */
579 static void iommu_flush_tlb_pde(struct protection_domain *domain)
580 {
581 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
582 }
583
584 /*
585 * This function flushes all domains that have devices on the given IOMMU
586 */
587 static void flush_all_domains_on_iommu(struct amd_iommu *iommu)
588 {
589 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
590 struct protection_domain *domain;
591 unsigned long flags;
592
593 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
594
595 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
596 if (domain->dev_iommu[iommu->index] == 0)
597 continue;
598
599 spin_lock(&domain->lock);
600 iommu_queue_inv_iommu_pages(iommu, address, domain->id, 1, 1);
601 iommu_flush_complete(domain);
602 spin_unlock(&domain->lock);
603 }
604
605 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
606 }
607
608 /*
609 * This function uses heavy locking and may disable irqs for some time. But
610 * this is no issue because it is only called during resume.
611 */
612 void amd_iommu_flush_all_domains(void)
613 {
614 struct protection_domain *domain;
615 unsigned long flags;
616
617 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
618
619 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
620 spin_lock(&domain->lock);
621 iommu_flush_tlb_pde(domain);
622 iommu_flush_complete(domain);
623 spin_unlock(&domain->lock);
624 }
625
626 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
627 }
628
629 static void flush_all_devices_for_iommu(struct amd_iommu *iommu)
630 {
631 int i;
632
633 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
634 if (iommu != amd_iommu_rlookup_table[i])
635 continue;
636
637 iommu_queue_inv_dev_entry(iommu, i);
638 iommu_completion_wait(iommu);
639 }
640 }
641
642 static void flush_devices_by_domain(struct protection_domain *domain)
643 {
644 struct amd_iommu *iommu;
645 int i;
646
647 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
648 if ((domain == NULL && amd_iommu_pd_table[i] == NULL) ||
649 (amd_iommu_pd_table[i] != domain))
650 continue;
651
652 iommu = amd_iommu_rlookup_table[i];
653 if (!iommu)
654 continue;
655
656 iommu_queue_inv_dev_entry(iommu, i);
657 iommu_completion_wait(iommu);
658 }
659 }
660
661 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
662 {
663 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
664
665 if (iommu->reset_in_progress)
666 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
667
668 iommu->reset_in_progress = true;
669
670 amd_iommu_reset_cmd_buffer(iommu);
671 flush_all_devices_for_iommu(iommu);
672 flush_all_domains_on_iommu(iommu);
673
674 iommu->reset_in_progress = false;
675 }
676
677 void amd_iommu_flush_all_devices(void)
678 {
679 flush_devices_by_domain(NULL);
680 }
681
682 /****************************************************************************
683 *
684 * The functions below are used the create the page table mappings for
685 * unity mapped regions.
686 *
687 ****************************************************************************/
688
689 /*
690 * This function is used to add another level to an IO page table. Adding
691 * another level increases the size of the address space by 9 bits to a size up
692 * to 64 bits.
693 */
694 static bool increase_address_space(struct protection_domain *domain,
695 gfp_t gfp)
696 {
697 u64 *pte;
698
699 if (domain->mode == PAGE_MODE_6_LEVEL)
700 /* address space already 64 bit large */
701 return false;
702
703 pte = (void *)get_zeroed_page(gfp);
704 if (!pte)
705 return false;
706
707 *pte = PM_LEVEL_PDE(domain->mode,
708 virt_to_phys(domain->pt_root));
709 domain->pt_root = pte;
710 domain->mode += 1;
711 domain->updated = true;
712
713 return true;
714 }
715
716 static u64 *alloc_pte(struct protection_domain *domain,
717 unsigned long address,
718 int end_lvl,
719 u64 **pte_page,
720 gfp_t gfp)
721 {
722 u64 *pte, *page;
723 int level;
724
725 while (address > PM_LEVEL_SIZE(domain->mode))
726 increase_address_space(domain, gfp);
727
728 level = domain->mode - 1;
729 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
730
731 while (level > end_lvl) {
732 if (!IOMMU_PTE_PRESENT(*pte)) {
733 page = (u64 *)get_zeroed_page(gfp);
734 if (!page)
735 return NULL;
736 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
737 }
738
739 level -= 1;
740
741 pte = IOMMU_PTE_PAGE(*pte);
742
743 if (pte_page && level == end_lvl)
744 *pte_page = pte;
745
746 pte = &pte[PM_LEVEL_INDEX(level, address)];
747 }
748
749 return pte;
750 }
751
752 /*
753 * This function checks if there is a PTE for a given dma address. If
754 * there is one, it returns the pointer to it.
755 */
756 static u64 *fetch_pte(struct protection_domain *domain,
757 unsigned long address, int map_size)
758 {
759 int level;
760 u64 *pte;
761
762 level = domain->mode - 1;
763 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
764
765 while (level > map_size) {
766 if (!IOMMU_PTE_PRESENT(*pte))
767 return NULL;
768
769 level -= 1;
770
771 pte = IOMMU_PTE_PAGE(*pte);
772 pte = &pte[PM_LEVEL_INDEX(level, address)];
773
774 if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
775 pte = NULL;
776 break;
777 }
778 }
779
780 return pte;
781 }
782
783 /*
784 * Generic mapping functions. It maps a physical address into a DMA
785 * address space. It allocates the page table pages if necessary.
786 * In the future it can be extended to a generic mapping function
787 * supporting all features of AMD IOMMU page tables like level skipping
788 * and full 64 bit address spaces.
789 */
790 static int iommu_map_page(struct protection_domain *dom,
791 unsigned long bus_addr,
792 unsigned long phys_addr,
793 int prot,
794 int map_size)
795 {
796 u64 __pte, *pte;
797
798 bus_addr = PAGE_ALIGN(bus_addr);
799 phys_addr = PAGE_ALIGN(phys_addr);
800
801 BUG_ON(!PM_ALIGNED(map_size, bus_addr));
802 BUG_ON(!PM_ALIGNED(map_size, phys_addr));
803
804 if (!(prot & IOMMU_PROT_MASK))
805 return -EINVAL;
806
807 pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
808
809 if (IOMMU_PTE_PRESENT(*pte))
810 return -EBUSY;
811
812 __pte = phys_addr | IOMMU_PTE_P;
813 if (prot & IOMMU_PROT_IR)
814 __pte |= IOMMU_PTE_IR;
815 if (prot & IOMMU_PROT_IW)
816 __pte |= IOMMU_PTE_IW;
817
818 *pte = __pte;
819
820 update_domain(dom);
821
822 return 0;
823 }
824
825 static void iommu_unmap_page(struct protection_domain *dom,
826 unsigned long bus_addr, int map_size)
827 {
828 u64 *pte = fetch_pte(dom, bus_addr, map_size);
829
830 if (pte)
831 *pte = 0;
832 }
833
834 /*
835 * This function checks if a specific unity mapping entry is needed for
836 * this specific IOMMU.
837 */
838 static int iommu_for_unity_map(struct amd_iommu *iommu,
839 struct unity_map_entry *entry)
840 {
841 u16 bdf, i;
842
843 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
844 bdf = amd_iommu_alias_table[i];
845 if (amd_iommu_rlookup_table[bdf] == iommu)
846 return 1;
847 }
848
849 return 0;
850 }
851
852 /*
853 * This function actually applies the mapping to the page table of the
854 * dma_ops domain.
855 */
856 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
857 struct unity_map_entry *e)
858 {
859 u64 addr;
860 int ret;
861
862 for (addr = e->address_start; addr < e->address_end;
863 addr += PAGE_SIZE) {
864 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
865 PM_MAP_4k);
866 if (ret)
867 return ret;
868 /*
869 * if unity mapping is in aperture range mark the page
870 * as allocated in the aperture
871 */
872 if (addr < dma_dom->aperture_size)
873 __set_bit(addr >> PAGE_SHIFT,
874 dma_dom->aperture[0]->bitmap);
875 }
876
877 return 0;
878 }
879
880 /*
881 * Init the unity mappings for a specific IOMMU in the system
882 *
883 * Basically iterates over all unity mapping entries and applies them to
884 * the default domain DMA of that IOMMU if necessary.
885 */
886 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
887 {
888 struct unity_map_entry *entry;
889 int ret;
890
891 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
892 if (!iommu_for_unity_map(iommu, entry))
893 continue;
894 ret = dma_ops_unity_map(iommu->default_dom, entry);
895 if (ret)
896 return ret;
897 }
898
899 return 0;
900 }
901
902 /*
903 * Inits the unity mappings required for a specific device
904 */
905 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
906 u16 devid)
907 {
908 struct unity_map_entry *e;
909 int ret;
910
911 list_for_each_entry(e, &amd_iommu_unity_map, list) {
912 if (!(devid >= e->devid_start && devid <= e->devid_end))
913 continue;
914 ret = dma_ops_unity_map(dma_dom, e);
915 if (ret)
916 return ret;
917 }
918
919 return 0;
920 }
921
922 /****************************************************************************
923 *
924 * The next functions belong to the address allocator for the dma_ops
925 * interface functions. They work like the allocators in the other IOMMU
926 * drivers. Its basically a bitmap which marks the allocated pages in
927 * the aperture. Maybe it could be enhanced in the future to a more
928 * efficient allocator.
929 *
930 ****************************************************************************/
931
932 /*
933 * The address allocator core functions.
934 *
935 * called with domain->lock held
936 */
937
938 /*
939 * Used to reserve address ranges in the aperture (e.g. for exclusion
940 * ranges.
941 */
942 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
943 unsigned long start_page,
944 unsigned int pages)
945 {
946 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
947
948 if (start_page + pages > last_page)
949 pages = last_page - start_page;
950
951 for (i = start_page; i < start_page + pages; ++i) {
952 int index = i / APERTURE_RANGE_PAGES;
953 int page = i % APERTURE_RANGE_PAGES;
954 __set_bit(page, dom->aperture[index]->bitmap);
955 }
956 }
957
958 /*
959 * This function is used to add a new aperture range to an existing
960 * aperture in case of dma_ops domain allocation or address allocation
961 * failure.
962 */
963 static int alloc_new_range(struct dma_ops_domain *dma_dom,
964 bool populate, gfp_t gfp)
965 {
966 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
967 struct amd_iommu *iommu;
968 int i;
969
970 #ifdef CONFIG_IOMMU_STRESS
971 populate = false;
972 #endif
973
974 if (index >= APERTURE_MAX_RANGES)
975 return -ENOMEM;
976
977 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
978 if (!dma_dom->aperture[index])
979 return -ENOMEM;
980
981 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
982 if (!dma_dom->aperture[index]->bitmap)
983 goto out_free;
984
985 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
986
987 if (populate) {
988 unsigned long address = dma_dom->aperture_size;
989 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
990 u64 *pte, *pte_page;
991
992 for (i = 0; i < num_ptes; ++i) {
993 pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
994 &pte_page, gfp);
995 if (!pte)
996 goto out_free;
997
998 dma_dom->aperture[index]->pte_pages[i] = pte_page;
999
1000 address += APERTURE_RANGE_SIZE / 64;
1001 }
1002 }
1003
1004 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1005
1006 /* Intialize the exclusion range if necessary */
1007 for_each_iommu(iommu) {
1008 if (iommu->exclusion_start &&
1009 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1010 && iommu->exclusion_start < dma_dom->aperture_size) {
1011 unsigned long startpage;
1012 int pages = iommu_num_pages(iommu->exclusion_start,
1013 iommu->exclusion_length,
1014 PAGE_SIZE);
1015 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1016 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1017 }
1018 }
1019
1020 /*
1021 * Check for areas already mapped as present in the new aperture
1022 * range and mark those pages as reserved in the allocator. Such
1023 * mappings may already exist as a result of requested unity
1024 * mappings for devices.
1025 */
1026 for (i = dma_dom->aperture[index]->offset;
1027 i < dma_dom->aperture_size;
1028 i += PAGE_SIZE) {
1029 u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k);
1030 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1031 continue;
1032
1033 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
1034 }
1035
1036 update_domain(&dma_dom->domain);
1037
1038 return 0;
1039
1040 out_free:
1041 update_domain(&dma_dom->domain);
1042
1043 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1044
1045 kfree(dma_dom->aperture[index]);
1046 dma_dom->aperture[index] = NULL;
1047
1048 return -ENOMEM;
1049 }
1050
1051 static unsigned long dma_ops_area_alloc(struct device *dev,
1052 struct dma_ops_domain *dom,
1053 unsigned int pages,
1054 unsigned long align_mask,
1055 u64 dma_mask,
1056 unsigned long start)
1057 {
1058 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1059 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1060 int i = start >> APERTURE_RANGE_SHIFT;
1061 unsigned long boundary_size;
1062 unsigned long address = -1;
1063 unsigned long limit;
1064
1065 next_bit >>= PAGE_SHIFT;
1066
1067 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1068 PAGE_SIZE) >> PAGE_SHIFT;
1069
1070 for (;i < max_index; ++i) {
1071 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1072
1073 if (dom->aperture[i]->offset >= dma_mask)
1074 break;
1075
1076 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1077 dma_mask >> PAGE_SHIFT);
1078
1079 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1080 limit, next_bit, pages, 0,
1081 boundary_size, align_mask);
1082 if (address != -1) {
1083 address = dom->aperture[i]->offset +
1084 (address << PAGE_SHIFT);
1085 dom->next_address = address + (pages << PAGE_SHIFT);
1086 break;
1087 }
1088
1089 next_bit = 0;
1090 }
1091
1092 return address;
1093 }
1094
1095 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1096 struct dma_ops_domain *dom,
1097 unsigned int pages,
1098 unsigned long align_mask,
1099 u64 dma_mask)
1100 {
1101 unsigned long address;
1102
1103 #ifdef CONFIG_IOMMU_STRESS
1104 dom->next_address = 0;
1105 dom->need_flush = true;
1106 #endif
1107
1108 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1109 dma_mask, dom->next_address);
1110
1111 if (address == -1) {
1112 dom->next_address = 0;
1113 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1114 dma_mask, 0);
1115 dom->need_flush = true;
1116 }
1117
1118 if (unlikely(address == -1))
1119 address = DMA_ERROR_CODE;
1120
1121 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1122
1123 return address;
1124 }
1125
1126 /*
1127 * The address free function.
1128 *
1129 * called with domain->lock held
1130 */
1131 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1132 unsigned long address,
1133 unsigned int pages)
1134 {
1135 unsigned i = address >> APERTURE_RANGE_SHIFT;
1136 struct aperture_range *range = dom->aperture[i];
1137
1138 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1139
1140 #ifdef CONFIG_IOMMU_STRESS
1141 if (i < 4)
1142 return;
1143 #endif
1144
1145 if (address >= dom->next_address)
1146 dom->need_flush = true;
1147
1148 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1149
1150 iommu_area_free(range->bitmap, address, pages);
1151
1152 }
1153
1154 /****************************************************************************
1155 *
1156 * The next functions belong to the domain allocation. A domain is
1157 * allocated for every IOMMU as the default domain. If device isolation
1158 * is enabled, every device get its own domain. The most important thing
1159 * about domains is the page table mapping the DMA address space they
1160 * contain.
1161 *
1162 ****************************************************************************/
1163
1164 /*
1165 * This function adds a protection domain to the global protection domain list
1166 */
1167 static void add_domain_to_list(struct protection_domain *domain)
1168 {
1169 unsigned long flags;
1170
1171 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1172 list_add(&domain->list, &amd_iommu_pd_list);
1173 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1174 }
1175
1176 /*
1177 * This function removes a protection domain to the global
1178 * protection domain list
1179 */
1180 static void del_domain_from_list(struct protection_domain *domain)
1181 {
1182 unsigned long flags;
1183
1184 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1185 list_del(&domain->list);
1186 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1187 }
1188
1189 static u16 domain_id_alloc(void)
1190 {
1191 unsigned long flags;
1192 int id;
1193
1194 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1195 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1196 BUG_ON(id == 0);
1197 if (id > 0 && id < MAX_DOMAIN_ID)
1198 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1199 else
1200 id = 0;
1201 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1202
1203 return id;
1204 }
1205
1206 static void domain_id_free(int id)
1207 {
1208 unsigned long flags;
1209
1210 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1211 if (id > 0 && id < MAX_DOMAIN_ID)
1212 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1213 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1214 }
1215
1216 static void free_pagetable(struct protection_domain *domain)
1217 {
1218 int i, j;
1219 u64 *p1, *p2, *p3;
1220
1221 p1 = domain->pt_root;
1222
1223 if (!p1)
1224 return;
1225
1226 for (i = 0; i < 512; ++i) {
1227 if (!IOMMU_PTE_PRESENT(p1[i]))
1228 continue;
1229
1230 p2 = IOMMU_PTE_PAGE(p1[i]);
1231 for (j = 0; j < 512; ++j) {
1232 if (!IOMMU_PTE_PRESENT(p2[j]))
1233 continue;
1234 p3 = IOMMU_PTE_PAGE(p2[j]);
1235 free_page((unsigned long)p3);
1236 }
1237
1238 free_page((unsigned long)p2);
1239 }
1240
1241 free_page((unsigned long)p1);
1242
1243 domain->pt_root = NULL;
1244 }
1245
1246 /*
1247 * Free a domain, only used if something went wrong in the
1248 * allocation path and we need to free an already allocated page table
1249 */
1250 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1251 {
1252 int i;
1253
1254 if (!dom)
1255 return;
1256
1257 del_domain_from_list(&dom->domain);
1258
1259 free_pagetable(&dom->domain);
1260
1261 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1262 if (!dom->aperture[i])
1263 continue;
1264 free_page((unsigned long)dom->aperture[i]->bitmap);
1265 kfree(dom->aperture[i]);
1266 }
1267
1268 kfree(dom);
1269 }
1270
1271 /*
1272 * Allocates a new protection domain usable for the dma_ops functions.
1273 * It also intializes the page table and the address allocator data
1274 * structures required for the dma_ops interface
1275 */
1276 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1277 {
1278 struct dma_ops_domain *dma_dom;
1279
1280 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1281 if (!dma_dom)
1282 return NULL;
1283
1284 spin_lock_init(&dma_dom->domain.lock);
1285
1286 dma_dom->domain.id = domain_id_alloc();
1287 if (dma_dom->domain.id == 0)
1288 goto free_dma_dom;
1289 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1290 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1291 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1292 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1293 dma_dom->domain.priv = dma_dom;
1294 if (!dma_dom->domain.pt_root)
1295 goto free_dma_dom;
1296
1297 dma_dom->need_flush = false;
1298 dma_dom->target_dev = 0xffff;
1299
1300 add_domain_to_list(&dma_dom->domain);
1301
1302 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1303 goto free_dma_dom;
1304
1305 /*
1306 * mark the first page as allocated so we never return 0 as
1307 * a valid dma-address. So we can use 0 as error value
1308 */
1309 dma_dom->aperture[0]->bitmap[0] = 1;
1310 dma_dom->next_address = 0;
1311
1312
1313 return dma_dom;
1314
1315 free_dma_dom:
1316 dma_ops_domain_free(dma_dom);
1317
1318 return NULL;
1319 }
1320
1321 /*
1322 * little helper function to check whether a given protection domain is a
1323 * dma_ops domain
1324 */
1325 static bool dma_ops_domain(struct protection_domain *domain)
1326 {
1327 return domain->flags & PD_DMA_OPS_MASK;
1328 }
1329
1330 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1331 {
1332 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1333 u64 pte_root = virt_to_phys(domain->pt_root);
1334
1335 BUG_ON(amd_iommu_pd_table[devid] != NULL);
1336
1337 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1338 << DEV_ENTRY_MODE_SHIFT;
1339 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1340
1341 amd_iommu_dev_table[devid].data[2] = domain->id;
1342 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1343 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1344
1345 amd_iommu_pd_table[devid] = domain;
1346
1347 /* Do reference counting */
1348 domain->dev_iommu[iommu->index] += 1;
1349 domain->dev_cnt += 1;
1350
1351 /* Flush the changes DTE entry */
1352 iommu_queue_inv_dev_entry(iommu, devid);
1353 }
1354
1355 static void clear_dte_entry(u16 devid)
1356 {
1357 struct protection_domain *domain = amd_iommu_pd_table[devid];
1358 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1359
1360 BUG_ON(domain == NULL);
1361
1362 /* remove domain from the lookup table */
1363 amd_iommu_pd_table[devid] = NULL;
1364
1365 /* remove entry from the device table seen by the hardware */
1366 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1367 amd_iommu_dev_table[devid].data[1] = 0;
1368 amd_iommu_dev_table[devid].data[2] = 0;
1369
1370 amd_iommu_apply_erratum_63(devid);
1371
1372 /* decrease reference counters */
1373 domain->dev_iommu[iommu->index] -= 1;
1374 domain->dev_cnt -= 1;
1375
1376 iommu_queue_inv_dev_entry(iommu, devid);
1377 }
1378
1379 /*
1380 * If a device is not yet associated with a domain, this function does
1381 * assigns it visible for the hardware
1382 */
1383 static int __attach_device(struct device *dev,
1384 struct protection_domain *domain)
1385 {
1386 struct iommu_dev_data *dev_data, *alias_data;
1387 u16 devid, alias;
1388
1389 devid = get_device_id(dev);
1390 alias = amd_iommu_alias_table[devid];
1391 dev_data = get_dev_data(dev);
1392 alias_data = get_dev_data(dev_data->alias);
1393 if (!alias_data)
1394 return -EINVAL;
1395
1396 /* lock domain */
1397 spin_lock(&domain->lock);
1398
1399 /* Some sanity checks */
1400 if (alias_data->domain != NULL &&
1401 alias_data->domain != domain)
1402 return -EBUSY;
1403
1404 if (dev_data->domain != NULL &&
1405 dev_data->domain != domain)
1406 return -EBUSY;
1407
1408 /* Do real assignment */
1409 if (alias != devid) {
1410 if (alias_data->domain == NULL) {
1411 alias_data->domain = domain;
1412 list_add(&alias_data->list, &domain->dev_list);
1413 set_dte_entry(alias, domain);
1414 }
1415
1416 atomic_inc(&alias_data->bind);
1417 }
1418
1419 if (dev_data->domain == NULL) {
1420 dev_data->domain = domain;
1421 list_add(&dev_data->list, &domain->dev_list);
1422 set_dte_entry(devid, domain);
1423 }
1424
1425 atomic_inc(&dev_data->bind);
1426
1427 /* ready */
1428 spin_unlock(&domain->lock);
1429
1430 return 0;
1431 }
1432
1433 /*
1434 * If a device is not yet associated with a domain, this function does
1435 * assigns it visible for the hardware
1436 */
1437 static int attach_device(struct device *dev,
1438 struct protection_domain *domain)
1439 {
1440 unsigned long flags;
1441 int ret;
1442
1443 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1444 ret = __attach_device(dev, domain);
1445 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1446
1447 /*
1448 * We might boot into a crash-kernel here. The crashed kernel
1449 * left the caches in the IOMMU dirty. So we have to flush
1450 * here to evict all dirty stuff.
1451 */
1452 iommu_flush_tlb_pde(domain);
1453
1454 return ret;
1455 }
1456
1457 /*
1458 * Removes a device from a protection domain (unlocked)
1459 */
1460 static void __detach_device(struct device *dev)
1461 {
1462 u16 devid = get_device_id(dev), alias;
1463 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1464 struct iommu_dev_data *dev_data = get_dev_data(dev);
1465 struct iommu_dev_data *alias_data;
1466 unsigned long flags;
1467
1468 BUG_ON(!iommu);
1469
1470 devid = get_device_id(dev);
1471 alias = get_device_id(dev_data->alias);
1472
1473 if (devid != alias) {
1474 alias_data = get_dev_data(dev_data->alias);
1475 if (atomic_dec_and_test(&alias_data->bind)) {
1476 spin_lock_irqsave(&alias_data->domain->lock, flags);
1477 clear_dte_entry(alias);
1478 list_del(&alias_data->list);
1479 spin_unlock_irqrestore(&alias_data->domain->lock, flags);
1480 alias_data->domain = NULL;
1481 }
1482 }
1483
1484 if (atomic_dec_and_test(&dev_data->bind)) {
1485 spin_lock_irqsave(&dev_data->domain->lock, flags);
1486 clear_dte_entry(devid);
1487 list_del(&dev_data->list);
1488 spin_unlock_irqrestore(&dev_data->domain->lock, flags);
1489 dev_data->domain = NULL;
1490 }
1491
1492 /*
1493 * If we run in passthrough mode the device must be assigned to the
1494 * passthrough domain if it is detached from any other domain
1495 */
1496 if (iommu_pass_through && dev_data->domain == NULL)
1497 __attach_device(dev, pt_domain);
1498 }
1499
1500 /*
1501 * Removes a device from a protection domain (with devtable_lock held)
1502 */
1503 static void detach_device(struct device *dev)
1504 {
1505 unsigned long flags;
1506
1507 /* lock device table */
1508 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1509 __detach_device(dev);
1510 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1511 }
1512
1513 /*
1514 * Find out the protection domain structure for a given PCI device. This
1515 * will give us the pointer to the page table root for example.
1516 */
1517 static struct protection_domain *domain_for_device(struct device *dev)
1518 {
1519 struct protection_domain *dom;
1520 struct iommu_dev_data *dev_data, *alias_data;
1521 unsigned long flags;
1522 u16 devid, alias;
1523
1524 devid = get_device_id(dev);
1525 alias = amd_iommu_alias_table[devid];
1526 dev_data = get_dev_data(dev);
1527 alias_data = get_dev_data(dev_data->alias);
1528 if (!alias_data)
1529 return NULL;
1530
1531 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1532 dom = dev_data->domain;
1533 if (dom == NULL &&
1534 alias_data->domain != NULL) {
1535 __attach_device(dev, alias_data->domain);
1536 dom = alias_data->domain;
1537 }
1538
1539 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1540
1541 return dom;
1542 }
1543
1544 static int device_change_notifier(struct notifier_block *nb,
1545 unsigned long action, void *data)
1546 {
1547 struct device *dev = data;
1548 u16 devid;
1549 struct protection_domain *domain;
1550 struct dma_ops_domain *dma_domain;
1551 struct amd_iommu *iommu;
1552 unsigned long flags;
1553
1554 if (!check_device(dev))
1555 return 0;
1556
1557 devid = get_device_id(dev);
1558 iommu = amd_iommu_rlookup_table[devid];
1559
1560 switch (action) {
1561 case BUS_NOTIFY_UNBOUND_DRIVER:
1562
1563 domain = domain_for_device(dev);
1564
1565 if (!domain)
1566 goto out;
1567 if (iommu_pass_through)
1568 break;
1569 detach_device(dev);
1570 break;
1571 case BUS_NOTIFY_ADD_DEVICE:
1572
1573 iommu_init_device(dev);
1574
1575 domain = domain_for_device(dev);
1576
1577 /* allocate a protection domain if a device is added */
1578 dma_domain = find_protection_domain(devid);
1579 if (dma_domain)
1580 goto out;
1581 dma_domain = dma_ops_domain_alloc();
1582 if (!dma_domain)
1583 goto out;
1584 dma_domain->target_dev = devid;
1585
1586 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1587 list_add_tail(&dma_domain->list, &iommu_pd_list);
1588 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1589
1590 break;
1591 case BUS_NOTIFY_DEL_DEVICE:
1592
1593 iommu_uninit_device(dev);
1594
1595 default:
1596 goto out;
1597 }
1598
1599 iommu_queue_inv_dev_entry(iommu, devid);
1600 iommu_completion_wait(iommu);
1601
1602 out:
1603 return 0;
1604 }
1605
1606 static struct notifier_block device_nb = {
1607 .notifier_call = device_change_notifier,
1608 };
1609
1610 /*****************************************************************************
1611 *
1612 * The next functions belong to the dma_ops mapping/unmapping code.
1613 *
1614 *****************************************************************************/
1615
1616 /*
1617 * In the dma_ops path we only have the struct device. This function
1618 * finds the corresponding IOMMU, the protection domain and the
1619 * requestor id for a given device.
1620 * If the device is not yet associated with a domain this is also done
1621 * in this function.
1622 */
1623 static struct protection_domain *get_domain(struct device *dev)
1624 {
1625 struct protection_domain *domain;
1626 struct dma_ops_domain *dma_dom;
1627 u16 devid = get_device_id(dev);
1628
1629 if (!check_device(dev))
1630 return ERR_PTR(-EINVAL);
1631
1632 domain = domain_for_device(dev);
1633 if (domain != NULL && !dma_ops_domain(domain))
1634 return ERR_PTR(-EBUSY);
1635
1636 if (domain != NULL)
1637 return domain;
1638
1639 /* Device not bount yet - bind it */
1640 dma_dom = find_protection_domain(devid);
1641 if (!dma_dom)
1642 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1643 attach_device(dev, &dma_dom->domain);
1644 DUMP_printk("Using protection domain %d for device %s\n",
1645 dma_dom->domain.id, dev_name(dev));
1646
1647 return &dma_dom->domain;
1648 }
1649
1650 static void update_device_table(struct protection_domain *domain)
1651 {
1652 unsigned long flags;
1653 int i;
1654
1655 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
1656 if (amd_iommu_pd_table[i] != domain)
1657 continue;
1658 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1659 set_dte_entry(i, domain);
1660 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1661 }
1662 }
1663
1664 static void update_domain(struct protection_domain *domain)
1665 {
1666 if (!domain->updated)
1667 return;
1668
1669 update_device_table(domain);
1670 flush_devices_by_domain(domain);
1671 iommu_flush_tlb_pde(domain);
1672
1673 domain->updated = false;
1674 }
1675
1676 /*
1677 * This function fetches the PTE for a given address in the aperture
1678 */
1679 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1680 unsigned long address)
1681 {
1682 struct aperture_range *aperture;
1683 u64 *pte, *pte_page;
1684
1685 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1686 if (!aperture)
1687 return NULL;
1688
1689 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1690 if (!pte) {
1691 pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
1692 GFP_ATOMIC);
1693 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1694 } else
1695 pte += PM_LEVEL_INDEX(0, address);
1696
1697 update_domain(&dom->domain);
1698
1699 return pte;
1700 }
1701
1702 /*
1703 * This is the generic map function. It maps one 4kb page at paddr to
1704 * the given address in the DMA address space for the domain.
1705 */
1706 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1707 unsigned long address,
1708 phys_addr_t paddr,
1709 int direction)
1710 {
1711 u64 *pte, __pte;
1712
1713 WARN_ON(address > dom->aperture_size);
1714
1715 paddr &= PAGE_MASK;
1716
1717 pte = dma_ops_get_pte(dom, address);
1718 if (!pte)
1719 return DMA_ERROR_CODE;
1720
1721 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1722
1723 if (direction == DMA_TO_DEVICE)
1724 __pte |= IOMMU_PTE_IR;
1725 else if (direction == DMA_FROM_DEVICE)
1726 __pte |= IOMMU_PTE_IW;
1727 else if (direction == DMA_BIDIRECTIONAL)
1728 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1729
1730 WARN_ON(*pte);
1731
1732 *pte = __pte;
1733
1734 return (dma_addr_t)address;
1735 }
1736
1737 /*
1738 * The generic unmapping function for on page in the DMA address space.
1739 */
1740 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1741 unsigned long address)
1742 {
1743 struct aperture_range *aperture;
1744 u64 *pte;
1745
1746 if (address >= dom->aperture_size)
1747 return;
1748
1749 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1750 if (!aperture)
1751 return;
1752
1753 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1754 if (!pte)
1755 return;
1756
1757 pte += PM_LEVEL_INDEX(0, address);
1758
1759 WARN_ON(!*pte);
1760
1761 *pte = 0ULL;
1762 }
1763
1764 /*
1765 * This function contains common code for mapping of a physically
1766 * contiguous memory region into DMA address space. It is used by all
1767 * mapping functions provided with this IOMMU driver.
1768 * Must be called with the domain lock held.
1769 */
1770 static dma_addr_t __map_single(struct device *dev,
1771 struct dma_ops_domain *dma_dom,
1772 phys_addr_t paddr,
1773 size_t size,
1774 int dir,
1775 bool align,
1776 u64 dma_mask)
1777 {
1778 dma_addr_t offset = paddr & ~PAGE_MASK;
1779 dma_addr_t address, start, ret;
1780 unsigned int pages;
1781 unsigned long align_mask = 0;
1782 int i;
1783
1784 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1785 paddr &= PAGE_MASK;
1786
1787 INC_STATS_COUNTER(total_map_requests);
1788
1789 if (pages > 1)
1790 INC_STATS_COUNTER(cross_page);
1791
1792 if (align)
1793 align_mask = (1UL << get_order(size)) - 1;
1794
1795 retry:
1796 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1797 dma_mask);
1798 if (unlikely(address == DMA_ERROR_CODE)) {
1799 /*
1800 * setting next_address here will let the address
1801 * allocator only scan the new allocated range in the
1802 * first run. This is a small optimization.
1803 */
1804 dma_dom->next_address = dma_dom->aperture_size;
1805
1806 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1807 goto out;
1808
1809 /*
1810 * aperture was sucessfully enlarged by 128 MB, try
1811 * allocation again
1812 */
1813 goto retry;
1814 }
1815
1816 start = address;
1817 for (i = 0; i < pages; ++i) {
1818 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
1819 if (ret == DMA_ERROR_CODE)
1820 goto out_unmap;
1821
1822 paddr += PAGE_SIZE;
1823 start += PAGE_SIZE;
1824 }
1825 address += offset;
1826
1827 ADD_STATS_COUNTER(alloced_io_mem, size);
1828
1829 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1830 iommu_flush_tlb(&dma_dom->domain);
1831 dma_dom->need_flush = false;
1832 } else if (unlikely(amd_iommu_np_cache))
1833 iommu_flush_pages(&dma_dom->domain, address, size);
1834
1835 out:
1836 return address;
1837
1838 out_unmap:
1839
1840 for (--i; i >= 0; --i) {
1841 start -= PAGE_SIZE;
1842 dma_ops_domain_unmap(dma_dom, start);
1843 }
1844
1845 dma_ops_free_addresses(dma_dom, address, pages);
1846
1847 return DMA_ERROR_CODE;
1848 }
1849
1850 /*
1851 * Does the reverse of the __map_single function. Must be called with
1852 * the domain lock held too
1853 */
1854 static void __unmap_single(struct dma_ops_domain *dma_dom,
1855 dma_addr_t dma_addr,
1856 size_t size,
1857 int dir)
1858 {
1859 dma_addr_t i, start;
1860 unsigned int pages;
1861
1862 if ((dma_addr == DMA_ERROR_CODE) ||
1863 (dma_addr + size > dma_dom->aperture_size))
1864 return;
1865
1866 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1867 dma_addr &= PAGE_MASK;
1868 start = dma_addr;
1869
1870 for (i = 0; i < pages; ++i) {
1871 dma_ops_domain_unmap(dma_dom, start);
1872 start += PAGE_SIZE;
1873 }
1874
1875 SUB_STATS_COUNTER(alloced_io_mem, size);
1876
1877 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1878
1879 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1880 iommu_flush_pages(&dma_dom->domain, dma_addr, size);
1881 dma_dom->need_flush = false;
1882 }
1883 }
1884
1885 /*
1886 * The exported map_single function for dma_ops.
1887 */
1888 static dma_addr_t map_page(struct device *dev, struct page *page,
1889 unsigned long offset, size_t size,
1890 enum dma_data_direction dir,
1891 struct dma_attrs *attrs)
1892 {
1893 unsigned long flags;
1894 struct protection_domain *domain;
1895 dma_addr_t addr;
1896 u64 dma_mask;
1897 phys_addr_t paddr = page_to_phys(page) + offset;
1898
1899 INC_STATS_COUNTER(cnt_map_single);
1900
1901 domain = get_domain(dev);
1902 if (PTR_ERR(domain) == -EINVAL)
1903 return (dma_addr_t)paddr;
1904 else if (IS_ERR(domain))
1905 return DMA_ERROR_CODE;
1906
1907 dma_mask = *dev->dma_mask;
1908
1909 spin_lock_irqsave(&domain->lock, flags);
1910
1911 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
1912 dma_mask);
1913 if (addr == DMA_ERROR_CODE)
1914 goto out;
1915
1916 iommu_flush_complete(domain);
1917
1918 out:
1919 spin_unlock_irqrestore(&domain->lock, flags);
1920
1921 return addr;
1922 }
1923
1924 /*
1925 * The exported unmap_single function for dma_ops.
1926 */
1927 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1928 enum dma_data_direction dir, struct dma_attrs *attrs)
1929 {
1930 unsigned long flags;
1931 struct protection_domain *domain;
1932
1933 INC_STATS_COUNTER(cnt_unmap_single);
1934
1935 domain = get_domain(dev);
1936 if (IS_ERR(domain))
1937 return;
1938
1939 spin_lock_irqsave(&domain->lock, flags);
1940
1941 __unmap_single(domain->priv, dma_addr, size, dir);
1942
1943 iommu_flush_complete(domain);
1944
1945 spin_unlock_irqrestore(&domain->lock, flags);
1946 }
1947
1948 /*
1949 * This is a special map_sg function which is used if we should map a
1950 * device which is not handled by an AMD IOMMU in the system.
1951 */
1952 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1953 int nelems, int dir)
1954 {
1955 struct scatterlist *s;
1956 int i;
1957
1958 for_each_sg(sglist, s, nelems, i) {
1959 s->dma_address = (dma_addr_t)sg_phys(s);
1960 s->dma_length = s->length;
1961 }
1962
1963 return nelems;
1964 }
1965
1966 /*
1967 * The exported map_sg function for dma_ops (handles scatter-gather
1968 * lists).
1969 */
1970 static int map_sg(struct device *dev, struct scatterlist *sglist,
1971 int nelems, enum dma_data_direction dir,
1972 struct dma_attrs *attrs)
1973 {
1974 unsigned long flags;
1975 struct protection_domain *domain;
1976 int i;
1977 struct scatterlist *s;
1978 phys_addr_t paddr;
1979 int mapped_elems = 0;
1980 u64 dma_mask;
1981
1982 INC_STATS_COUNTER(cnt_map_sg);
1983
1984 domain = get_domain(dev);
1985 if (PTR_ERR(domain) == -EINVAL)
1986 return map_sg_no_iommu(dev, sglist, nelems, dir);
1987 else if (IS_ERR(domain))
1988 return 0;
1989
1990 dma_mask = *dev->dma_mask;
1991
1992 spin_lock_irqsave(&domain->lock, flags);
1993
1994 for_each_sg(sglist, s, nelems, i) {
1995 paddr = sg_phys(s);
1996
1997 s->dma_address = __map_single(dev, domain->priv,
1998 paddr, s->length, dir, false,
1999 dma_mask);
2000
2001 if (s->dma_address) {
2002 s->dma_length = s->length;
2003 mapped_elems++;
2004 } else
2005 goto unmap;
2006 }
2007
2008 iommu_flush_complete(domain);
2009
2010 out:
2011 spin_unlock_irqrestore(&domain->lock, flags);
2012
2013 return mapped_elems;
2014 unmap:
2015 for_each_sg(sglist, s, mapped_elems, i) {
2016 if (s->dma_address)
2017 __unmap_single(domain->priv, s->dma_address,
2018 s->dma_length, dir);
2019 s->dma_address = s->dma_length = 0;
2020 }
2021
2022 mapped_elems = 0;
2023
2024 goto out;
2025 }
2026
2027 /*
2028 * The exported map_sg function for dma_ops (handles scatter-gather
2029 * lists).
2030 */
2031 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2032 int nelems, enum dma_data_direction dir,
2033 struct dma_attrs *attrs)
2034 {
2035 unsigned long flags;
2036 struct protection_domain *domain;
2037 struct scatterlist *s;
2038 int i;
2039
2040 INC_STATS_COUNTER(cnt_unmap_sg);
2041
2042 domain = get_domain(dev);
2043 if (IS_ERR(domain))
2044 return;
2045
2046 spin_lock_irqsave(&domain->lock, flags);
2047
2048 for_each_sg(sglist, s, nelems, i) {
2049 __unmap_single(domain->priv, s->dma_address,
2050 s->dma_length, dir);
2051 s->dma_address = s->dma_length = 0;
2052 }
2053
2054 iommu_flush_complete(domain);
2055
2056 spin_unlock_irqrestore(&domain->lock, flags);
2057 }
2058
2059 /*
2060 * The exported alloc_coherent function for dma_ops.
2061 */
2062 static void *alloc_coherent(struct device *dev, size_t size,
2063 dma_addr_t *dma_addr, gfp_t flag)
2064 {
2065 unsigned long flags;
2066 void *virt_addr;
2067 struct protection_domain *domain;
2068 phys_addr_t paddr;
2069 u64 dma_mask = dev->coherent_dma_mask;
2070
2071 INC_STATS_COUNTER(cnt_alloc_coherent);
2072
2073 domain = get_domain(dev);
2074 if (PTR_ERR(domain) == -EINVAL) {
2075 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2076 *dma_addr = __pa(virt_addr);
2077 return virt_addr;
2078 } else if (IS_ERR(domain))
2079 return NULL;
2080
2081 dma_mask = dev->coherent_dma_mask;
2082 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2083 flag |= __GFP_ZERO;
2084
2085 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2086 if (!virt_addr)
2087 return NULL;
2088
2089 paddr = virt_to_phys(virt_addr);
2090
2091 if (!dma_mask)
2092 dma_mask = *dev->dma_mask;
2093
2094 spin_lock_irqsave(&domain->lock, flags);
2095
2096 *dma_addr = __map_single(dev, domain->priv, paddr,
2097 size, DMA_BIDIRECTIONAL, true, dma_mask);
2098
2099 if (*dma_addr == DMA_ERROR_CODE) {
2100 spin_unlock_irqrestore(&domain->lock, flags);
2101 goto out_free;
2102 }
2103
2104 iommu_flush_complete(domain);
2105
2106 spin_unlock_irqrestore(&domain->lock, flags);
2107
2108 return virt_addr;
2109
2110 out_free:
2111
2112 free_pages((unsigned long)virt_addr, get_order(size));
2113
2114 return NULL;
2115 }
2116
2117 /*
2118 * The exported free_coherent function for dma_ops.
2119 */
2120 static void free_coherent(struct device *dev, size_t size,
2121 void *virt_addr, dma_addr_t dma_addr)
2122 {
2123 unsigned long flags;
2124 struct protection_domain *domain;
2125
2126 INC_STATS_COUNTER(cnt_free_coherent);
2127
2128 domain = get_domain(dev);
2129 if (IS_ERR(domain))
2130 goto free_mem;
2131
2132 spin_lock_irqsave(&domain->lock, flags);
2133
2134 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2135
2136 iommu_flush_complete(domain);
2137
2138 spin_unlock_irqrestore(&domain->lock, flags);
2139
2140 free_mem:
2141 free_pages((unsigned long)virt_addr, get_order(size));
2142 }
2143
2144 /*
2145 * This function is called by the DMA layer to find out if we can handle a
2146 * particular device. It is part of the dma_ops.
2147 */
2148 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2149 {
2150 return check_device(dev);
2151 }
2152
2153 /*
2154 * The function for pre-allocating protection domains.
2155 *
2156 * If the driver core informs the DMA layer if a driver grabs a device
2157 * we don't need to preallocate the protection domains anymore.
2158 * For now we have to.
2159 */
2160 static void prealloc_protection_domains(void)
2161 {
2162 struct pci_dev *dev = NULL;
2163 struct dma_ops_domain *dma_dom;
2164 u16 devid;
2165
2166 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2167
2168 /* Do we handle this device? */
2169 if (!check_device(&dev->dev))
2170 continue;
2171
2172 iommu_init_device(&dev->dev);
2173
2174 /* Is there already any domain for it? */
2175 if (domain_for_device(&dev->dev))
2176 continue;
2177
2178 devid = get_device_id(&dev->dev);
2179
2180 dma_dom = dma_ops_domain_alloc();
2181 if (!dma_dom)
2182 continue;
2183 init_unity_mappings_for_device(dma_dom, devid);
2184 dma_dom->target_dev = devid;
2185
2186 attach_device(&dev->dev, &dma_dom->domain);
2187
2188 list_add_tail(&dma_dom->list, &iommu_pd_list);
2189 }
2190 }
2191
2192 static struct dma_map_ops amd_iommu_dma_ops = {
2193 .alloc_coherent = alloc_coherent,
2194 .free_coherent = free_coherent,
2195 .map_page = map_page,
2196 .unmap_page = unmap_page,
2197 .map_sg = map_sg,
2198 .unmap_sg = unmap_sg,
2199 .dma_supported = amd_iommu_dma_supported,
2200 };
2201
2202 /*
2203 * The function which clues the AMD IOMMU driver into dma_ops.
2204 */
2205 int __init amd_iommu_init_dma_ops(void)
2206 {
2207 struct amd_iommu *iommu;
2208 int ret;
2209
2210 /*
2211 * first allocate a default protection domain for every IOMMU we
2212 * found in the system. Devices not assigned to any other
2213 * protection domain will be assigned to the default one.
2214 */
2215 for_each_iommu(iommu) {
2216 iommu->default_dom = dma_ops_domain_alloc();
2217 if (iommu->default_dom == NULL)
2218 return -ENOMEM;
2219 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2220 ret = iommu_init_unity_mappings(iommu);
2221 if (ret)
2222 goto free_domains;
2223 }
2224
2225 /*
2226 * Pre-allocate the protection domains for each device.
2227 */
2228 prealloc_protection_domains();
2229
2230 iommu_detected = 1;
2231 swiotlb = 0;
2232 #ifdef CONFIG_GART_IOMMU
2233 gart_iommu_aperture_disabled = 1;
2234 gart_iommu_aperture = 0;
2235 #endif
2236
2237 /* Make the driver finally visible to the drivers */
2238 dma_ops = &amd_iommu_dma_ops;
2239
2240 register_iommu(&amd_iommu_ops);
2241
2242 bus_register_notifier(&pci_bus_type, &device_nb);
2243
2244 amd_iommu_stats_init();
2245
2246 return 0;
2247
2248 free_domains:
2249
2250 for_each_iommu(iommu) {
2251 if (iommu->default_dom)
2252 dma_ops_domain_free(iommu->default_dom);
2253 }
2254
2255 return ret;
2256 }
2257
2258 /*****************************************************************************
2259 *
2260 * The following functions belong to the exported interface of AMD IOMMU
2261 *
2262 * This interface allows access to lower level functions of the IOMMU
2263 * like protection domain handling and assignement of devices to domains
2264 * which is not possible with the dma_ops interface.
2265 *
2266 *****************************************************************************/
2267
2268 static void cleanup_domain(struct protection_domain *domain)
2269 {
2270 unsigned long flags;
2271 u16 devid;
2272
2273 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2274
2275 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2276 if (amd_iommu_pd_table[devid] == domain)
2277 clear_dte_entry(devid);
2278
2279 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2280 }
2281
2282 static void protection_domain_free(struct protection_domain *domain)
2283 {
2284 if (!domain)
2285 return;
2286
2287 del_domain_from_list(domain);
2288
2289 if (domain->id)
2290 domain_id_free(domain->id);
2291
2292 kfree(domain);
2293 }
2294
2295 static struct protection_domain *protection_domain_alloc(void)
2296 {
2297 struct protection_domain *domain;
2298
2299 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2300 if (!domain)
2301 return NULL;
2302
2303 spin_lock_init(&domain->lock);
2304 domain->id = domain_id_alloc();
2305 if (!domain->id)
2306 goto out_err;
2307 INIT_LIST_HEAD(&domain->dev_list);
2308
2309 add_domain_to_list(domain);
2310
2311 return domain;
2312
2313 out_err:
2314 kfree(domain);
2315
2316 return NULL;
2317 }
2318
2319 static int amd_iommu_domain_init(struct iommu_domain *dom)
2320 {
2321 struct protection_domain *domain;
2322
2323 domain = protection_domain_alloc();
2324 if (!domain)
2325 goto out_free;
2326
2327 domain->mode = PAGE_MODE_3_LEVEL;
2328 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2329 if (!domain->pt_root)
2330 goto out_free;
2331
2332 dom->priv = domain;
2333
2334 return 0;
2335
2336 out_free:
2337 protection_domain_free(domain);
2338
2339 return -ENOMEM;
2340 }
2341
2342 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2343 {
2344 struct protection_domain *domain = dom->priv;
2345
2346 if (!domain)
2347 return;
2348
2349 if (domain->dev_cnt > 0)
2350 cleanup_domain(domain);
2351
2352 BUG_ON(domain->dev_cnt != 0);
2353
2354 free_pagetable(domain);
2355
2356 domain_id_free(domain->id);
2357
2358 kfree(domain);
2359
2360 dom->priv = NULL;
2361 }
2362
2363 static void amd_iommu_detach_device(struct iommu_domain *dom,
2364 struct device *dev)
2365 {
2366 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2367 struct amd_iommu *iommu;
2368 u16 devid;
2369
2370 if (!check_device(dev))
2371 return;
2372
2373 devid = get_device_id(dev);
2374
2375 if (dev_data->domain != NULL)
2376 detach_device(dev);
2377
2378 iommu = amd_iommu_rlookup_table[devid];
2379 if (!iommu)
2380 return;
2381
2382 iommu_queue_inv_dev_entry(iommu, devid);
2383 iommu_completion_wait(iommu);
2384 }
2385
2386 static int amd_iommu_attach_device(struct iommu_domain *dom,
2387 struct device *dev)
2388 {
2389 struct protection_domain *domain = dom->priv;
2390 struct iommu_dev_data *dev_data;
2391 struct amd_iommu *iommu;
2392 int ret;
2393 u16 devid;
2394
2395 if (!check_device(dev))
2396 return -EINVAL;
2397
2398 dev_data = dev->archdata.iommu;
2399
2400 devid = get_device_id(dev);
2401
2402 iommu = amd_iommu_rlookup_table[devid];
2403 if (!iommu)
2404 return -EINVAL;
2405
2406 if (dev_data->domain)
2407 detach_device(dev);
2408
2409 ret = attach_device(dev, domain);
2410
2411 iommu_completion_wait(iommu);
2412
2413 return ret;
2414 }
2415
2416 static int amd_iommu_map_range(struct iommu_domain *dom,
2417 unsigned long iova, phys_addr_t paddr,
2418 size_t size, int iommu_prot)
2419 {
2420 struct protection_domain *domain = dom->priv;
2421 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2422 int prot = 0;
2423 int ret;
2424
2425 if (iommu_prot & IOMMU_READ)
2426 prot |= IOMMU_PROT_IR;
2427 if (iommu_prot & IOMMU_WRITE)
2428 prot |= IOMMU_PROT_IW;
2429
2430 iova &= PAGE_MASK;
2431 paddr &= PAGE_MASK;
2432
2433 for (i = 0; i < npages; ++i) {
2434 ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
2435 if (ret)
2436 return ret;
2437
2438 iova += PAGE_SIZE;
2439 paddr += PAGE_SIZE;
2440 }
2441
2442 return 0;
2443 }
2444
2445 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2446 unsigned long iova, size_t size)
2447 {
2448
2449 struct protection_domain *domain = dom->priv;
2450 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2451
2452 iova &= PAGE_MASK;
2453
2454 for (i = 0; i < npages; ++i) {
2455 iommu_unmap_page(domain, iova, PM_MAP_4k);
2456 iova += PAGE_SIZE;
2457 }
2458
2459 iommu_flush_tlb_pde(domain);
2460 }
2461
2462 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2463 unsigned long iova)
2464 {
2465 struct protection_domain *domain = dom->priv;
2466 unsigned long offset = iova & ~PAGE_MASK;
2467 phys_addr_t paddr;
2468 u64 *pte;
2469
2470 pte = fetch_pte(domain, iova, PM_MAP_4k);
2471
2472 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2473 return 0;
2474
2475 paddr = *pte & IOMMU_PAGE_MASK;
2476 paddr |= offset;
2477
2478 return paddr;
2479 }
2480
2481 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2482 unsigned long cap)
2483 {
2484 return 0;
2485 }
2486
2487 static struct iommu_ops amd_iommu_ops = {
2488 .domain_init = amd_iommu_domain_init,
2489 .domain_destroy = amd_iommu_domain_destroy,
2490 .attach_dev = amd_iommu_attach_device,
2491 .detach_dev = amd_iommu_detach_device,
2492 .map = amd_iommu_map_range,
2493 .unmap = amd_iommu_unmap_range,
2494 .iova_to_phys = amd_iommu_iova_to_phys,
2495 .domain_has_cap = amd_iommu_domain_has_cap,
2496 };
2497
2498 /*****************************************************************************
2499 *
2500 * The next functions do a basic initialization of IOMMU for pass through
2501 * mode
2502 *
2503 * In passthrough mode the IOMMU is initialized and enabled but not used for
2504 * DMA-API translation.
2505 *
2506 *****************************************************************************/
2507
2508 int __init amd_iommu_init_passthrough(void)
2509 {
2510 struct amd_iommu *iommu;
2511 struct pci_dev *dev = NULL;
2512 u16 devid;
2513
2514 /* allocate passthroug domain */
2515 pt_domain = protection_domain_alloc();
2516 if (!pt_domain)
2517 return -ENOMEM;
2518
2519 pt_domain->mode |= PAGE_MODE_NONE;
2520
2521 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2522
2523 if (!check_device(&dev->dev))
2524 continue;
2525
2526 devid = get_device_id(&dev->dev);
2527
2528 iommu = amd_iommu_rlookup_table[devid];
2529 if (!iommu)
2530 continue;
2531
2532 attach_device(&dev->dev, pt_domain);
2533 }
2534
2535 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
2536
2537 return 0;
2538 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree