2 * Support for the Tundra Universe I/II VME-PCI Bridge Chips
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
10 * Derived from ca91c042.c by Michael Wyrick
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/module.h>
20 #include <linux/types.h>
21 #include <linux/errno.h>
22 #include <linux/pci.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/poll.h>
25 #include <linux/interrupt.h>
26 #include <linux/spinlock.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/time.h>
31 #include <linux/uaccess.h>
34 #include "../vme_bridge.h"
35 #include "vme_ca91cx42.h"
37 static int __init
ca91cx42_init(void);
38 static int ca91cx42_probe(struct pci_dev
*, const struct pci_device_id
*);
39 static void ca91cx42_remove(struct pci_dev
*);
40 static void __exit
ca91cx42_exit(void);
42 /* Module parameters */
45 static char driver_name
[] = "vme_ca91cx42";
47 static const struct pci_device_id ca91cx42_ids
[] = {
48 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA
, PCI_DEVICE_ID_TUNDRA_CA91C142
) },
52 static struct pci_driver ca91cx42_driver
= {
54 .id_table
= ca91cx42_ids
,
55 .probe
= ca91cx42_probe
,
56 .remove
= ca91cx42_remove
,
59 static u32
ca91cx42_DMA_irqhandler(struct ca91cx42_driver
*bridge
)
61 wake_up(&(bridge
->dma_queue
));
63 return CA91CX42_LINT_DMA
;
66 static u32
ca91cx42_LM_irqhandler(struct ca91cx42_driver
*bridge
, u32 stat
)
71 for (i
= 0; i
< 4; i
++) {
72 if (stat
& CA91CX42_LINT_LM
[i
]) {
73 /* We only enable interrupts if the callback is set */
74 bridge
->lm_callback
[i
](i
);
75 serviced
|= CA91CX42_LINT_LM
[i
];
82 /* XXX This needs to be split into 4 queues */
83 static u32
ca91cx42_MB_irqhandler(struct ca91cx42_driver
*bridge
, int mbox_mask
)
85 wake_up(&(bridge
->mbox_queue
));
87 return CA91CX42_LINT_MBOX
;
90 static u32
ca91cx42_IACK_irqhandler(struct ca91cx42_driver
*bridge
)
92 wake_up(&(bridge
->iack_queue
));
94 return CA91CX42_LINT_SW_IACK
;
97 static u32
ca91cx42_VERR_irqhandler(struct vme_bridge
*ca91cx42_bridge
)
100 struct ca91cx42_driver
*bridge
;
102 bridge
= ca91cx42_bridge
->driver_priv
;
104 val
= ioread32(bridge
->base
+ DGCS
);
106 if (!(val
& 0x00000800)) {
107 dev_err(ca91cx42_bridge
->parent
, "ca91cx42_VERR_irqhandler DMA "
108 "Read Error DGCS=%08X\n", val
);
111 return CA91CX42_LINT_VERR
;
114 static u32
ca91cx42_LERR_irqhandler(struct vme_bridge
*ca91cx42_bridge
)
117 struct ca91cx42_driver
*bridge
;
119 bridge
= ca91cx42_bridge
->driver_priv
;
121 val
= ioread32(bridge
->base
+ DGCS
);
123 if (!(val
& 0x00000800))
124 dev_err(ca91cx42_bridge
->parent
, "ca91cx42_LERR_irqhandler DMA "
125 "Read Error DGCS=%08X\n", val
);
127 return CA91CX42_LINT_LERR
;
131 static u32
ca91cx42_VIRQ_irqhandler(struct vme_bridge
*ca91cx42_bridge
,
134 int vec
, i
, serviced
= 0;
135 struct ca91cx42_driver
*bridge
;
137 bridge
= ca91cx42_bridge
->driver_priv
;
140 for (i
= 7; i
> 0; i
--) {
141 if (stat
& (1 << i
)) {
142 vec
= ioread32(bridge
->base
+
143 CA91CX42_V_STATID
[i
]) & 0xff;
145 vme_irq_handler(ca91cx42_bridge
, i
, vec
);
147 serviced
|= (1 << i
);
154 static irqreturn_t
ca91cx42_irqhandler(int irq
, void *ptr
)
156 u32 stat
, enable
, serviced
= 0;
157 struct vme_bridge
*ca91cx42_bridge
;
158 struct ca91cx42_driver
*bridge
;
160 ca91cx42_bridge
= ptr
;
162 bridge
= ca91cx42_bridge
->driver_priv
;
164 enable
= ioread32(bridge
->base
+ LINT_EN
);
165 stat
= ioread32(bridge
->base
+ LINT_STAT
);
167 /* Only look at unmasked interrupts */
173 if (stat
& CA91CX42_LINT_DMA
)
174 serviced
|= ca91cx42_DMA_irqhandler(bridge
);
175 if (stat
& (CA91CX42_LINT_LM0
| CA91CX42_LINT_LM1
| CA91CX42_LINT_LM2
|
177 serviced
|= ca91cx42_LM_irqhandler(bridge
, stat
);
178 if (stat
& CA91CX42_LINT_MBOX
)
179 serviced
|= ca91cx42_MB_irqhandler(bridge
, stat
);
180 if (stat
& CA91CX42_LINT_SW_IACK
)
181 serviced
|= ca91cx42_IACK_irqhandler(bridge
);
182 if (stat
& CA91CX42_LINT_VERR
)
183 serviced
|= ca91cx42_VERR_irqhandler(ca91cx42_bridge
);
184 if (stat
& CA91CX42_LINT_LERR
)
185 serviced
|= ca91cx42_LERR_irqhandler(ca91cx42_bridge
);
186 if (stat
& (CA91CX42_LINT_VIRQ1
| CA91CX42_LINT_VIRQ2
|
187 CA91CX42_LINT_VIRQ3
| CA91CX42_LINT_VIRQ4
|
188 CA91CX42_LINT_VIRQ5
| CA91CX42_LINT_VIRQ6
|
189 CA91CX42_LINT_VIRQ7
))
190 serviced
|= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge
, stat
);
192 /* Clear serviced interrupts */
193 iowrite32(stat
, bridge
->base
+ LINT_STAT
);
198 static int ca91cx42_irq_init(struct vme_bridge
*ca91cx42_bridge
)
201 struct pci_dev
*pdev
;
202 struct ca91cx42_driver
*bridge
;
204 bridge
= ca91cx42_bridge
->driver_priv
;
207 pdev
= container_of(ca91cx42_bridge
->parent
, struct pci_dev
, dev
);
209 /* Initialise list for VME bus errors */
210 INIT_LIST_HEAD(&(ca91cx42_bridge
->vme_errors
));
212 mutex_init(&(ca91cx42_bridge
->irq_mtx
));
214 /* Disable interrupts from PCI to VME */
215 iowrite32(0, bridge
->base
+ VINT_EN
);
217 /* Disable PCI interrupts */
218 iowrite32(0, bridge
->base
+ LINT_EN
);
219 /* Clear Any Pending PCI Interrupts */
220 iowrite32(0x00FFFFFF, bridge
->base
+ LINT_STAT
);
222 result
= request_irq(pdev
->irq
, ca91cx42_irqhandler
, IRQF_SHARED
,
223 driver_name
, ca91cx42_bridge
);
225 dev_err(&pdev
->dev
, "Can't get assigned pci irq vector %02X\n",
230 /* Ensure all interrupts are mapped to PCI Interrupt 0 */
231 iowrite32(0, bridge
->base
+ LINT_MAP0
);
232 iowrite32(0, bridge
->base
+ LINT_MAP1
);
233 iowrite32(0, bridge
->base
+ LINT_MAP2
);
235 /* Enable DMA, mailbox & LM Interrupts */
236 tmp
= CA91CX42_LINT_MBOX3
| CA91CX42_LINT_MBOX2
| CA91CX42_LINT_MBOX1
|
237 CA91CX42_LINT_MBOX0
| CA91CX42_LINT_SW_IACK
|
238 CA91CX42_LINT_VERR
| CA91CX42_LINT_LERR
| CA91CX42_LINT_DMA
;
240 iowrite32(tmp
, bridge
->base
+ LINT_EN
);
245 static void ca91cx42_irq_exit(struct ca91cx42_driver
*bridge
,
246 struct pci_dev
*pdev
)
248 /* Disable interrupts from PCI to VME */
249 iowrite32(0, bridge
->base
+ VINT_EN
);
251 /* Disable PCI interrupts */
252 iowrite32(0, bridge
->base
+ LINT_EN
);
253 /* Clear Any Pending PCI Interrupts */
254 iowrite32(0x00FFFFFF, bridge
->base
+ LINT_STAT
);
256 free_irq(pdev
->irq
, pdev
);
260 * Set up an VME interrupt
262 void ca91cx42_irq_set(struct vme_bridge
*ca91cx42_bridge
, int level
, int state
,
266 struct pci_dev
*pdev
;
268 struct ca91cx42_driver
*bridge
;
270 bridge
= ca91cx42_bridge
->driver_priv
;
272 /* Enable IRQ level */
273 tmp
= ioread32(bridge
->base
+ LINT_EN
);
276 tmp
&= ~CA91CX42_LINT_VIRQ
[level
];
278 tmp
|= CA91CX42_LINT_VIRQ
[level
];
280 iowrite32(tmp
, bridge
->base
+ LINT_EN
);
282 if ((state
== 0) && (sync
!= 0)) {
283 pdev
= container_of(ca91cx42_bridge
->parent
, struct pci_dev
,
286 synchronize_irq(pdev
->irq
);
290 int ca91cx42_irq_generate(struct vme_bridge
*ca91cx42_bridge
, int level
,
294 struct ca91cx42_driver
*bridge
;
296 bridge
= ca91cx42_bridge
->driver_priv
;
298 /* Universe can only generate even vectors */
302 mutex_lock(&(bridge
->vme_int
));
304 tmp
= ioread32(bridge
->base
+ VINT_EN
);
307 iowrite32(statid
<< 24, bridge
->base
+ STATID
);
309 /* Assert VMEbus IRQ */
310 tmp
= tmp
| (1 << (level
+ 24));
311 iowrite32(tmp
, bridge
->base
+ VINT_EN
);
314 wait_event_interruptible(bridge
->iack_queue
, 0);
316 /* Return interrupt to low state */
317 tmp
= ioread32(bridge
->base
+ VINT_EN
);
318 tmp
= tmp
& ~(1 << (level
+ 24));
319 iowrite32(tmp
, bridge
->base
+ VINT_EN
);
321 mutex_unlock(&(bridge
->vme_int
));
326 int ca91cx42_slave_set(struct vme_slave_resource
*image
, int enabled
,
327 unsigned long long vme_base
, unsigned long long size
,
328 dma_addr_t pci_base
, vme_address_t aspace
, vme_cycle_t cycle
)
330 unsigned int i
, addr
= 0, granularity
;
331 unsigned int temp_ctl
= 0;
332 unsigned int vme_bound
, pci_offset
;
333 struct vme_bridge
*ca91cx42_bridge
;
334 struct ca91cx42_driver
*bridge
;
336 ca91cx42_bridge
= image
->parent
;
338 bridge
= ca91cx42_bridge
->driver_priv
;
344 addr
|= CA91CX42_VSI_CTL_VAS_A16
;
347 addr
|= CA91CX42_VSI_CTL_VAS_A24
;
350 addr
|= CA91CX42_VSI_CTL_VAS_A32
;
353 addr
|= CA91CX42_VSI_CTL_VAS_USER1
;
356 addr
|= CA91CX42_VSI_CTL_VAS_USER2
;
363 dev_err(ca91cx42_bridge
->parent
, "Invalid address space\n");
369 * Bound address is a valid address for the window, adjust
372 vme_bound
= vme_base
+ size
;
373 pci_offset
= pci_base
- vme_base
;
375 if ((i
== 0) || (i
== 4))
376 granularity
= 0x1000;
378 granularity
= 0x10000;
380 if (vme_base
& (granularity
- 1)) {
381 dev_err(ca91cx42_bridge
->parent
, "Invalid VME base "
385 if (vme_bound
& (granularity
- 1)) {
386 dev_err(ca91cx42_bridge
->parent
, "Invalid VME bound "
390 if (pci_offset
& (granularity
- 1)) {
391 dev_err(ca91cx42_bridge
->parent
, "Invalid PCI Offset "
396 /* Disable while we are mucking around */
397 temp_ctl
= ioread32(bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
398 temp_ctl
&= ~CA91CX42_VSI_CTL_EN
;
399 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
402 iowrite32(vme_base
, bridge
->base
+ CA91CX42_VSI_BS
[i
]);
403 iowrite32(vme_bound
, bridge
->base
+ CA91CX42_VSI_BD
[i
]);
404 iowrite32(pci_offset
, bridge
->base
+ CA91CX42_VSI_TO
[i
]);
406 /* Setup address space */
407 temp_ctl
&= ~CA91CX42_VSI_CTL_VAS_M
;
410 /* Setup cycle types */
411 temp_ctl
&= ~(CA91CX42_VSI_CTL_PGM_M
| CA91CX42_VSI_CTL_SUPER_M
);
412 if (cycle
& VME_SUPER
)
413 temp_ctl
|= CA91CX42_VSI_CTL_SUPER_SUPR
;
414 if (cycle
& VME_USER
)
415 temp_ctl
|= CA91CX42_VSI_CTL_SUPER_NPRIV
;
416 if (cycle
& VME_PROG
)
417 temp_ctl
|= CA91CX42_VSI_CTL_PGM_PGM
;
418 if (cycle
& VME_DATA
)
419 temp_ctl
|= CA91CX42_VSI_CTL_PGM_DATA
;
421 /* Write ctl reg without enable */
422 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
425 temp_ctl
|= CA91CX42_VSI_CTL_EN
;
427 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
432 int ca91cx42_slave_get(struct vme_slave_resource
*image
, int *enabled
,
433 unsigned long long *vme_base
, unsigned long long *size
,
434 dma_addr_t
*pci_base
, vme_address_t
*aspace
, vme_cycle_t
*cycle
)
436 unsigned int i
, granularity
= 0, ctl
= 0;
437 unsigned long long vme_bound
, pci_offset
;
438 struct ca91cx42_driver
*bridge
;
440 bridge
= image
->parent
->driver_priv
;
444 if ((i
== 0) || (i
== 4))
445 granularity
= 0x1000;
447 granularity
= 0x10000;
450 ctl
= ioread32(bridge
->base
+ CA91CX42_VSI_CTL
[i
]);
452 *vme_base
= ioread32(bridge
->base
+ CA91CX42_VSI_BS
[i
]);
453 vme_bound
= ioread32(bridge
->base
+ CA91CX42_VSI_BD
[i
]);
454 pci_offset
= ioread32(bridge
->base
+ CA91CX42_VSI_TO
[i
]);
456 *pci_base
= (dma_addr_t
)vme_base
+ pci_offset
;
457 *size
= (unsigned long long)((vme_bound
- *vme_base
) + granularity
);
463 if (ctl
& CA91CX42_VSI_CTL_EN
)
466 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_A16
)
468 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_A24
)
470 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_A32
)
472 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_USER1
)
474 if ((ctl
& CA91CX42_VSI_CTL_VAS_M
) == CA91CX42_VSI_CTL_VAS_USER2
)
477 if (ctl
& CA91CX42_VSI_CTL_SUPER_SUPR
)
479 if (ctl
& CA91CX42_VSI_CTL_SUPER_NPRIV
)
481 if (ctl
& CA91CX42_VSI_CTL_PGM_PGM
)
483 if (ctl
& CA91CX42_VSI_CTL_PGM_DATA
)
490 * Allocate and map PCI Resource
492 static int ca91cx42_alloc_resource(struct vme_master_resource
*image
,
493 unsigned long long size
)
495 unsigned long long existing_size
;
497 struct pci_dev
*pdev
;
498 struct vme_bridge
*ca91cx42_bridge
;
500 ca91cx42_bridge
= image
->parent
;
502 /* Find pci_dev container of dev */
503 if (ca91cx42_bridge
->parent
== NULL
) {
504 dev_err(ca91cx42_bridge
->parent
, "Dev entry NULL\n");
507 pdev
= container_of(ca91cx42_bridge
->parent
, struct pci_dev
, dev
);
509 existing_size
= (unsigned long long)(image
->bus_resource
.end
-
510 image
->bus_resource
.start
);
512 /* If the existing size is OK, return */
513 if (existing_size
== (size
- 1))
516 if (existing_size
!= 0) {
517 iounmap(image
->kern_base
);
518 image
->kern_base
= NULL
;
519 if (image
->bus_resource
.name
!= NULL
)
520 kfree(image
->bus_resource
.name
);
521 release_resource(&(image
->bus_resource
));
522 memset(&(image
->bus_resource
), 0, sizeof(struct resource
));
525 if (image
->bus_resource
.name
== NULL
) {
526 image
->bus_resource
.name
= kmalloc(VMENAMSIZ
+3, GFP_ATOMIC
);
527 if (image
->bus_resource
.name
== NULL
) {
528 dev_err(ca91cx42_bridge
->parent
, "Unable to allocate "
529 "memory for resource name\n");
535 sprintf((char *)image
->bus_resource
.name
, "%s.%d",
536 ca91cx42_bridge
->name
, image
->number
);
538 image
->bus_resource
.start
= 0;
539 image
->bus_resource
.end
= (unsigned long)size
;
540 image
->bus_resource
.flags
= IORESOURCE_MEM
;
542 retval
= pci_bus_alloc_resource(pdev
->bus
,
543 &(image
->bus_resource
), size
, size
, PCIBIOS_MIN_MEM
,
546 dev_err(ca91cx42_bridge
->parent
, "Failed to allocate mem "
547 "resource for window %d size 0x%lx start 0x%lx\n",
548 image
->number
, (unsigned long)size
,
549 (unsigned long)image
->bus_resource
.start
);
553 image
->kern_base
= ioremap_nocache(
554 image
->bus_resource
.start
, size
);
555 if (image
->kern_base
== NULL
) {
556 dev_err(ca91cx42_bridge
->parent
, "Failed to remap resource\n");
563 iounmap(image
->kern_base
);
564 image
->kern_base
= NULL
;
566 release_resource(&(image
->bus_resource
));
568 kfree(image
->bus_resource
.name
);
569 memset(&(image
->bus_resource
), 0, sizeof(struct resource
));
575 * Free and unmap PCI Resource
577 static void ca91cx42_free_resource(struct vme_master_resource
*image
)
579 iounmap(image
->kern_base
);
580 image
->kern_base
= NULL
;
581 release_resource(&(image
->bus_resource
));
582 kfree(image
->bus_resource
.name
);
583 memset(&(image
->bus_resource
), 0, sizeof(struct resource
));
587 int ca91cx42_master_set(struct vme_master_resource
*image
, int enabled
,
588 unsigned long long vme_base
, unsigned long long size
,
589 vme_address_t aspace
, vme_cycle_t cycle
, vme_width_t dwidth
)
592 unsigned int i
, granularity
= 0;
593 unsigned int temp_ctl
= 0;
594 unsigned long long pci_bound
, vme_offset
, pci_base
;
595 struct vme_bridge
*ca91cx42_bridge
;
596 struct ca91cx42_driver
*bridge
;
598 ca91cx42_bridge
= image
->parent
;
600 bridge
= ca91cx42_bridge
->driver_priv
;
604 if ((i
== 0) || (i
== 4))
605 granularity
= 0x1000;
607 granularity
= 0x10000;
609 /* Verify input data */
610 if (vme_base
& (granularity
- 1)) {
611 dev_err(ca91cx42_bridge
->parent
, "Invalid VME Window "
616 if (size
& (granularity
- 1)) {
617 dev_err(ca91cx42_bridge
->parent
, "Invalid VME Window "
623 spin_lock(&(image
->lock
));
626 * Let's allocate the resource here rather than further up the stack as
627 * it avoids pushing loads of bus dependant stuff up the stack
629 retval
= ca91cx42_alloc_resource(image
, size
);
631 spin_unlock(&(image
->lock
));
632 dev_err(ca91cx42_bridge
->parent
, "Unable to allocate memory "
633 "for resource name\n");
638 pci_base
= (unsigned long long)image
->bus_resource
.start
;
641 * Bound address is a valid address for the window, adjust
642 * according to window granularity.
644 pci_bound
= pci_base
+ size
;
645 vme_offset
= vme_base
- pci_base
;
647 /* Disable while we are mucking around */
648 temp_ctl
= ioread32(bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
649 temp_ctl
&= ~CA91CX42_LSI_CTL_EN
;
650 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
652 /* Setup cycle types */
653 temp_ctl
&= ~CA91CX42_LSI_CTL_VCT_M
;
655 temp_ctl
|= CA91CX42_LSI_CTL_VCT_BLT
;
656 if (cycle
& VME_MBLT
)
657 temp_ctl
|= CA91CX42_LSI_CTL_VCT_MBLT
;
659 /* Setup data width */
660 temp_ctl
&= ~CA91CX42_LSI_CTL_VDW_M
;
663 temp_ctl
|= CA91CX42_LSI_CTL_VDW_D8
;
666 temp_ctl
|= CA91CX42_LSI_CTL_VDW_D16
;
669 temp_ctl
|= CA91CX42_LSI_CTL_VDW_D32
;
672 temp_ctl
|= CA91CX42_LSI_CTL_VDW_D64
;
675 spin_unlock(&(image
->lock
));
676 dev_err(ca91cx42_bridge
->parent
, "Invalid data width\n");
682 /* Setup address space */
683 temp_ctl
&= ~CA91CX42_LSI_CTL_VAS_M
;
686 temp_ctl
|= CA91CX42_LSI_CTL_VAS_A16
;
689 temp_ctl
|= CA91CX42_LSI_CTL_VAS_A24
;
692 temp_ctl
|= CA91CX42_LSI_CTL_VAS_A32
;
695 temp_ctl
|= CA91CX42_LSI_CTL_VAS_CRCSR
;
698 temp_ctl
|= CA91CX42_LSI_CTL_VAS_USER1
;
701 temp_ctl
|= CA91CX42_LSI_CTL_VAS_USER2
;
707 spin_unlock(&(image
->lock
));
708 dev_err(ca91cx42_bridge
->parent
, "Invalid address space\n");
714 temp_ctl
&= ~(CA91CX42_LSI_CTL_PGM_M
| CA91CX42_LSI_CTL_SUPER_M
);
715 if (cycle
& VME_SUPER
)
716 temp_ctl
|= CA91CX42_LSI_CTL_SUPER_SUPR
;
717 if (cycle
& VME_PROG
)
718 temp_ctl
|= CA91CX42_LSI_CTL_PGM_PGM
;
721 iowrite32(pci_base
, bridge
->base
+ CA91CX42_LSI_BS
[i
]);
722 iowrite32(pci_bound
, bridge
->base
+ CA91CX42_LSI_BD
[i
]);
723 iowrite32(vme_offset
, bridge
->base
+ CA91CX42_LSI_TO
[i
]);
725 /* Write ctl reg without enable */
726 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
729 temp_ctl
|= CA91CX42_LSI_CTL_EN
;
731 iowrite32(temp_ctl
, bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
733 spin_unlock(&(image
->lock
));
738 ca91cx42_free_resource(image
);
744 int __ca91cx42_master_get(struct vme_master_resource
*image
, int *enabled
,
745 unsigned long long *vme_base
, unsigned long long *size
,
746 vme_address_t
*aspace
, vme_cycle_t
*cycle
, vme_width_t
*dwidth
)
749 unsigned long long pci_base
, pci_bound
, vme_offset
;
750 struct ca91cx42_driver
*bridge
;
752 bridge
= image
->parent
->driver_priv
;
756 ctl
= ioread32(bridge
->base
+ CA91CX42_LSI_CTL
[i
]);
758 pci_base
= ioread32(bridge
->base
+ CA91CX42_LSI_BS
[i
]);
759 vme_offset
= ioread32(bridge
->base
+ CA91CX42_LSI_TO
[i
]);
760 pci_bound
= ioread32(bridge
->base
+ CA91CX42_LSI_BD
[i
]);
762 *vme_base
= pci_base
+ vme_offset
;
763 *size
= (unsigned long long)(pci_bound
- pci_base
);
770 if (ctl
& CA91CX42_LSI_CTL_EN
)
773 /* Setup address space */
774 switch (ctl
& CA91CX42_LSI_CTL_VAS_M
) {
775 case CA91CX42_LSI_CTL_VAS_A16
:
778 case CA91CX42_LSI_CTL_VAS_A24
:
781 case CA91CX42_LSI_CTL_VAS_A32
:
784 case CA91CX42_LSI_CTL_VAS_CRCSR
:
787 case CA91CX42_LSI_CTL_VAS_USER1
:
790 case CA91CX42_LSI_CTL_VAS_USER2
:
795 /* XXX Not sure howto check for MBLT */
796 /* Setup cycle types */
797 if (ctl
& CA91CX42_LSI_CTL_VCT_BLT
)
802 if (ctl
& CA91CX42_LSI_CTL_SUPER_SUPR
)
807 if (ctl
& CA91CX42_LSI_CTL_PGM_PGM
)
812 /* Setup data width */
813 switch (ctl
& CA91CX42_LSI_CTL_VDW_M
) {
814 case CA91CX42_LSI_CTL_VDW_D8
:
817 case CA91CX42_LSI_CTL_VDW_D16
:
820 case CA91CX42_LSI_CTL_VDW_D32
:
823 case CA91CX42_LSI_CTL_VDW_D64
:
831 int ca91cx42_master_get(struct vme_master_resource
*image
, int *enabled
,
832 unsigned long long *vme_base
, unsigned long long *size
,
833 vme_address_t
*aspace
, vme_cycle_t
*cycle
, vme_width_t
*dwidth
)
837 spin_lock(&(image
->lock
));
839 retval
= __ca91cx42_master_get(image
, enabled
, vme_base
, size
, aspace
,
842 spin_unlock(&(image
->lock
));
847 ssize_t
ca91cx42_master_read(struct vme_master_resource
*image
, void *buf
,
848 size_t count
, loff_t offset
)
852 spin_lock(&(image
->lock
));
854 memcpy_fromio(buf
, image
->kern_base
+ offset
, (unsigned int)count
);
857 spin_unlock(&(image
->lock
));
862 ssize_t
ca91cx42_master_write(struct vme_master_resource
*image
, void *buf
,
863 size_t count
, loff_t offset
)
867 spin_lock(&(image
->lock
));
869 memcpy_toio(image
->kern_base
+ offset
, buf
, (unsigned int)count
);
872 spin_unlock(&(image
->lock
));
877 unsigned int ca91cx42_master_rmw(struct vme_master_resource
*image
,
878 unsigned int mask
, unsigned int compare
, unsigned int swap
,
881 u32 pci_addr
, result
;
883 struct ca91cx42_driver
*bridge
;
886 bridge
= image
->parent
->driver_priv
;
887 dev
= image
->parent
->parent
;
889 /* Find the PCI address that maps to the desired VME address */
892 /* Locking as we can only do one of these at a time */
893 mutex_lock(&(bridge
->vme_rmw
));
896 spin_lock(&(image
->lock
));
898 pci_addr
= (u32
)image
->kern_base
+ offset
;
900 /* Address must be 4-byte aligned */
901 if (pci_addr
& 0x3) {
902 dev_err(dev
, "RMW Address not 4-byte aligned\n");
907 /* Ensure RMW Disabled whilst configuring */
908 iowrite32(0, bridge
->base
+ SCYC_CTL
);
910 /* Configure registers */
911 iowrite32(mask
, bridge
->base
+ SCYC_EN
);
912 iowrite32(compare
, bridge
->base
+ SCYC_CMP
);
913 iowrite32(swap
, bridge
->base
+ SCYC_SWP
);
914 iowrite32(pci_addr
, bridge
->base
+ SCYC_ADDR
);
917 iowrite32(CA91CX42_SCYC_CTL_CYC_RMW
, bridge
->base
+ SCYC_CTL
);
919 /* Kick process off with a read to the required address. */
920 result
= ioread32(image
->kern_base
+ offset
);
923 iowrite32(0, bridge
->base
+ SCYC_CTL
);
926 spin_unlock(&(image
->lock
));
928 mutex_unlock(&(bridge
->vme_rmw
));
933 int ca91cx42_dma_list_add(struct vme_dma_list
*list
, struct vme_dma_attr
*src
,
934 struct vme_dma_attr
*dest
, size_t count
)
936 struct ca91cx42_dma_entry
*entry
, *prev
;
937 struct vme_dma_pci
*pci_attr
;
938 struct vme_dma_vme
*vme_attr
;
943 dev
= list
->parent
->parent
->parent
;
945 /* XXX descriptor must be aligned on 64-bit boundaries */
946 entry
= kmalloc(sizeof(struct ca91cx42_dma_entry
), GFP_KERNEL
);
948 dev_err(dev
, "Failed to allocate memory for dma resource "
954 /* Test descriptor alignment */
955 if ((unsigned long)&(entry
->descriptor
) & CA91CX42_DCPP_M
) {
956 dev_err(dev
, "Descriptor not aligned to 16 byte boundary as "
957 "required: %p\n", &(entry
->descriptor
));
962 memset(&(entry
->descriptor
), 0, sizeof(struct ca91cx42_dma_descriptor
));
964 if (dest
->type
== VME_DMA_VME
) {
965 entry
->descriptor
.dctl
|= CA91CX42_DCTL_L2V
;
966 vme_attr
= (struct vme_dma_vme
*)dest
->private;
967 pci_attr
= (struct vme_dma_pci
*)src
->private;
969 vme_attr
= (struct vme_dma_vme
*)src
->private;
970 pci_attr
= (struct vme_dma_pci
*)dest
->private;
973 /* Check we can do fullfill required attributes */
974 if ((vme_attr
->aspace
& ~(VME_A16
| VME_A24
| VME_A32
| VME_USER1
|
977 dev_err(dev
, "Unsupported cycle type\n");
982 if ((vme_attr
->cycle
& ~(VME_SCT
| VME_BLT
| VME_SUPER
| VME_USER
|
983 VME_PROG
| VME_DATA
)) != 0) {
985 dev_err(dev
, "Unsupported cycle type\n");
990 /* Check to see if we can fullfill source and destination */
991 if (!(((src
->type
== VME_DMA_PCI
) && (dest
->type
== VME_DMA_VME
)) ||
992 ((src
->type
== VME_DMA_VME
) && (dest
->type
== VME_DMA_PCI
)))) {
994 dev_err(dev
, "Cannot perform transfer with this "
995 "source-destination combination\n");
1000 /* Setup cycle types */
1001 if (vme_attr
->cycle
& VME_BLT
)
1002 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VCT_BLT
;
1004 /* Setup data width */
1005 switch (vme_attr
->dwidth
) {
1007 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VDW_D8
;
1010 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VDW_D16
;
1013 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VDW_D32
;
1016 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VDW_D64
;
1019 dev_err(dev
, "Invalid data width\n");
1023 /* Setup address space */
1024 switch (vme_attr
->aspace
) {
1026 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_A16
;
1029 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_A24
;
1032 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_A32
;
1035 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_USER1
;
1038 entry
->descriptor
.dctl
|= CA91CX42_DCTL_VAS_USER2
;
1041 dev_err(dev
, "Invalid address space\n");
1046 if (vme_attr
->cycle
& VME_SUPER
)
1047 entry
->descriptor
.dctl
|= CA91CX42_DCTL_SUPER_SUPR
;
1048 if (vme_attr
->cycle
& VME_PROG
)
1049 entry
->descriptor
.dctl
|= CA91CX42_DCTL_PGM_PGM
;
1051 entry
->descriptor
.dtbc
= count
;
1052 entry
->descriptor
.dla
= pci_attr
->address
;
1053 entry
->descriptor
.dva
= vme_attr
->address
;
1054 entry
->descriptor
.dcpp
= CA91CX42_DCPP_NULL
;
1057 list_add_tail(&(entry
->list
), &(list
->entries
));
1059 /* Fill out previous descriptors "Next Address" */
1060 if (entry
->list
.prev
!= &(list
->entries
)) {
1061 prev
= list_entry(entry
->list
.prev
, struct ca91cx42_dma_entry
,
1063 /* We need the bus address for the pointer */
1064 desc_ptr
= virt_to_bus(&(entry
->descriptor
));
1065 prev
->descriptor
.dcpp
= desc_ptr
& ~CA91CX42_DCPP_M
;
1079 static int ca91cx42_dma_busy(struct vme_bridge
*ca91cx42_bridge
)
1082 struct ca91cx42_driver
*bridge
;
1084 bridge
= ca91cx42_bridge
->driver_priv
;
1086 tmp
= ioread32(bridge
->base
+ DGCS
);
1088 if (tmp
& CA91CX42_DGCS_ACT
)
1094 int ca91cx42_dma_list_exec(struct vme_dma_list
*list
)
1096 struct vme_dma_resource
*ctrlr
;
1097 struct ca91cx42_dma_entry
*entry
;
1099 dma_addr_t bus_addr
;
1102 struct ca91cx42_driver
*bridge
;
1104 ctrlr
= list
->parent
;
1106 bridge
= ctrlr
->parent
->driver_priv
;
1107 dev
= ctrlr
->parent
->parent
;
1109 mutex_lock(&(ctrlr
->mtx
));
1111 if (!(list_empty(&(ctrlr
->running
)))) {
1113 * XXX We have an active DMA transfer and currently haven't
1114 * sorted out the mechanism for "pending" DMA transfers.
1117 /* Need to add to pending here */
1118 mutex_unlock(&(ctrlr
->mtx
));
1121 list_add(&(list
->list
), &(ctrlr
->running
));
1124 /* Get first bus address and write into registers */
1125 entry
= list_first_entry(&(list
->entries
), struct ca91cx42_dma_entry
,
1128 bus_addr
= virt_to_bus(&(entry
->descriptor
));
1130 mutex_unlock(&(ctrlr
->mtx
));
1132 iowrite32(0, bridge
->base
+ DTBC
);
1133 iowrite32(bus_addr
& ~CA91CX42_DCPP_M
, bridge
->base
+ DCPP
);
1135 /* Start the operation */
1136 val
= ioread32(bridge
->base
+ DGCS
);
1138 /* XXX Could set VMEbus On and Off Counters here */
1139 val
&= (CA91CX42_DGCS_VON_M
| CA91CX42_DGCS_VOFF_M
);
1141 val
|= (CA91CX42_DGCS_CHAIN
| CA91CX42_DGCS_STOP
| CA91CX42_DGCS_HALT
|
1142 CA91CX42_DGCS_DONE
| CA91CX42_DGCS_LERR
| CA91CX42_DGCS_VERR
|
1143 CA91CX42_DGCS_PERR
);
1145 iowrite32(val
, bridge
->base
+ DGCS
);
1147 val
|= CA91CX42_DGCS_GO
;
1149 iowrite32(val
, bridge
->base
+ DGCS
);
1151 wait_event_interruptible(bridge
->dma_queue
,
1152 ca91cx42_dma_busy(ctrlr
->parent
));
1155 * Read status register, this register is valid until we kick off a
1158 val
= ioread32(bridge
->base
+ DGCS
);
1160 if (val
& (CA91CX42_DGCS_LERR
| CA91CX42_DGCS_VERR
|
1161 CA91CX42_DGCS_PERR
)) {
1163 dev_err(dev
, "ca91c042: DMA Error. DGCS=%08X\n", val
);
1164 val
= ioread32(bridge
->base
+ DCTL
);
1167 /* Remove list from running list */
1168 mutex_lock(&(ctrlr
->mtx
));
1169 list_del(&(list
->list
));
1170 mutex_unlock(&(ctrlr
->mtx
));
1176 int ca91cx42_dma_list_empty(struct vme_dma_list
*list
)
1178 struct list_head
*pos
, *temp
;
1179 struct ca91cx42_dma_entry
*entry
;
1181 /* detach and free each entry */
1182 list_for_each_safe(pos
, temp
, &(list
->entries
)) {
1184 entry
= list_entry(pos
, struct ca91cx42_dma_entry
, list
);
1192 * All 4 location monitors reside at the same base - this is therefore a
1193 * system wide configuration.
1195 * This does not enable the LM monitor - that should be done when the first
1196 * callback is attached and disabled when the last callback is removed.
1198 int ca91cx42_lm_set(struct vme_lm_resource
*lm
, unsigned long long lm_base
,
1199 vme_address_t aspace
, vme_cycle_t cycle
)
1201 u32 temp_base
, lm_ctl
= 0;
1203 struct ca91cx42_driver
*bridge
;
1206 bridge
= lm
->parent
->driver_priv
;
1207 dev
= lm
->parent
->parent
;
1209 /* Check the alignment of the location monitor */
1210 temp_base
= (u32
)lm_base
;
1211 if (temp_base
& 0xffff) {
1212 dev_err(dev
, "Location monitor must be aligned to 64KB "
1217 mutex_lock(&(lm
->mtx
));
1219 /* If we already have a callback attached, we can't move it! */
1220 for (i
= 0; i
< lm
->monitors
; i
++) {
1221 if (bridge
->lm_callback
[i
] != NULL
) {
1222 mutex_unlock(&(lm
->mtx
));
1223 dev_err(dev
, "Location monitor callback attached, "
1231 lm_ctl
|= CA91CX42_LM_CTL_AS_A16
;
1234 lm_ctl
|= CA91CX42_LM_CTL_AS_A24
;
1237 lm_ctl
|= CA91CX42_LM_CTL_AS_A32
;
1240 mutex_unlock(&(lm
->mtx
));
1241 dev_err(dev
, "Invalid address space\n");
1246 if (cycle
& VME_SUPER
)
1247 lm_ctl
|= CA91CX42_LM_CTL_SUPR
;
1248 if (cycle
& VME_USER
)
1249 lm_ctl
|= CA91CX42_LM_CTL_NPRIV
;
1250 if (cycle
& VME_PROG
)
1251 lm_ctl
|= CA91CX42_LM_CTL_PGM
;
1252 if (cycle
& VME_DATA
)
1253 lm_ctl
|= CA91CX42_LM_CTL_DATA
;
1255 iowrite32(lm_base
, bridge
->base
+ LM_BS
);
1256 iowrite32(lm_ctl
, bridge
->base
+ LM_CTL
);
1258 mutex_unlock(&(lm
->mtx
));
1263 /* Get configuration of the callback monitor and return whether it is enabled
1266 int ca91cx42_lm_get(struct vme_lm_resource
*lm
, unsigned long long *lm_base
,
1267 vme_address_t
*aspace
, vme_cycle_t
*cycle
)
1269 u32 lm_ctl
, enabled
= 0;
1270 struct ca91cx42_driver
*bridge
;
1272 bridge
= lm
->parent
->driver_priv
;
1274 mutex_lock(&(lm
->mtx
));
1276 *lm_base
= (unsigned long long)ioread32(bridge
->base
+ LM_BS
);
1277 lm_ctl
= ioread32(bridge
->base
+ LM_CTL
);
1279 if (lm_ctl
& CA91CX42_LM_CTL_EN
)
1282 if ((lm_ctl
& CA91CX42_LM_CTL_AS_M
) == CA91CX42_LM_CTL_AS_A16
)
1284 if ((lm_ctl
& CA91CX42_LM_CTL_AS_M
) == CA91CX42_LM_CTL_AS_A24
)
1286 if ((lm_ctl
& CA91CX42_LM_CTL_AS_M
) == CA91CX42_LM_CTL_AS_A32
)
1290 if (lm_ctl
& CA91CX42_LM_CTL_SUPR
)
1291 *cycle
|= VME_SUPER
;
1292 if (lm_ctl
& CA91CX42_LM_CTL_NPRIV
)
1294 if (lm_ctl
& CA91CX42_LM_CTL_PGM
)
1296 if (lm_ctl
& CA91CX42_LM_CTL_DATA
)
1299 mutex_unlock(&(lm
->mtx
));
1305 * Attach a callback to a specific location monitor.
1307 * Callback will be passed the monitor triggered.
1309 int ca91cx42_lm_attach(struct vme_lm_resource
*lm
, int monitor
,
1310 void (*callback
)(int))
1313 struct ca91cx42_driver
*bridge
;
1316 bridge
= lm
->parent
->driver_priv
;
1317 dev
= lm
->parent
->parent
;
1319 mutex_lock(&(lm
->mtx
));
1321 /* Ensure that the location monitor is configured - need PGM or DATA */
1322 lm_ctl
= ioread32(bridge
->base
+ LM_CTL
);
1323 if ((lm_ctl
& (CA91CX42_LM_CTL_PGM
| CA91CX42_LM_CTL_DATA
)) == 0) {
1324 mutex_unlock(&(lm
->mtx
));
1325 dev_err(dev
, "Location monitor not properly configured\n");
1329 /* Check that a callback isn't already attached */
1330 if (bridge
->lm_callback
[monitor
] != NULL
) {
1331 mutex_unlock(&(lm
->mtx
));
1332 dev_err(dev
, "Existing callback attached\n");
1336 /* Attach callback */
1337 bridge
->lm_callback
[monitor
] = callback
;
1339 /* Enable Location Monitor interrupt */
1340 tmp
= ioread32(bridge
->base
+ LINT_EN
);
1341 tmp
|= CA91CX42_LINT_LM
[monitor
];
1342 iowrite32(tmp
, bridge
->base
+ LINT_EN
);
1344 /* Ensure that global Location Monitor Enable set */
1345 if ((lm_ctl
& CA91CX42_LM_CTL_EN
) == 0) {
1346 lm_ctl
|= CA91CX42_LM_CTL_EN
;
1347 iowrite32(lm_ctl
, bridge
->base
+ LM_CTL
);
1350 mutex_unlock(&(lm
->mtx
));
1356 * Detach a callback function forn a specific location monitor.
1358 int ca91cx42_lm_detach(struct vme_lm_resource
*lm
, int monitor
)
1361 struct ca91cx42_driver
*bridge
;
1363 bridge
= lm
->parent
->driver_priv
;
1365 mutex_lock(&(lm
->mtx
));
1367 /* Disable Location Monitor and ensure previous interrupts are clear */
1368 tmp
= ioread32(bridge
->base
+ LINT_EN
);
1369 tmp
&= ~CA91CX42_LINT_LM
[monitor
];
1370 iowrite32(tmp
, bridge
->base
+ LINT_EN
);
1372 iowrite32(CA91CX42_LINT_LM
[monitor
],
1373 bridge
->base
+ LINT_STAT
);
1375 /* Detach callback */
1376 bridge
->lm_callback
[monitor
] = NULL
;
1378 /* If all location monitors disabled, disable global Location Monitor */
1379 if ((tmp
& (CA91CX42_LINT_LM0
| CA91CX42_LINT_LM1
| CA91CX42_LINT_LM2
|
1380 CA91CX42_LINT_LM3
)) == 0) {
1381 tmp
= ioread32(bridge
->base
+ LM_CTL
);
1382 tmp
&= ~CA91CX42_LM_CTL_EN
;
1383 iowrite32(tmp
, bridge
->base
+ LM_CTL
);
1386 mutex_unlock(&(lm
->mtx
));
1391 int ca91cx42_slot_get(struct vme_bridge
*ca91cx42_bridge
)
1394 struct ca91cx42_driver
*bridge
;
1396 bridge
= ca91cx42_bridge
->driver_priv
;
1399 slot
= ioread32(bridge
->base
+ VCSR_BS
);
1400 slot
= ((slot
& CA91CX42_VCSR_BS_SLOT_M
) >> 27);
1408 static int __init
ca91cx42_init(void)
1410 return pci_register_driver(&ca91cx42_driver
);
1414 * Configure CR/CSR space
1416 * Access to the CR/CSR can be configured at power-up. The location of the
1417 * CR/CSR registers in the CR/CSR address space is determined by the boards
1418 * Auto-ID or Geographic address. This function ensures that the window is
1419 * enabled at an offset consistent with the boards geopgraphic address.
1421 static int ca91cx42_crcsr_init(struct vme_bridge
*ca91cx42_bridge
,
1422 struct pci_dev
*pdev
)
1424 unsigned int crcsr_addr
;
1426 struct ca91cx42_driver
*bridge
;
1428 bridge
= ca91cx42_bridge
->driver_priv
;
1430 slot
= ca91cx42_slot_get(ca91cx42_bridge
);
1432 /* Write CSR Base Address if slot ID is supplied as a module param */
1434 iowrite32(geoid
<< 27, bridge
->base
+ VCSR_BS
);
1436 dev_info(&pdev
->dev
, "CR/CSR Offset: %d\n", slot
);
1438 dev_err(&pdev
->dev
, "Slot number is unset, not configuring "
1443 /* Allocate mem for CR/CSR image */
1444 bridge
->crcsr_kernel
= pci_alloc_consistent(pdev
, VME_CRCSR_BUF_SIZE
,
1445 &(bridge
->crcsr_bus
));
1446 if (bridge
->crcsr_kernel
== NULL
) {
1447 dev_err(&pdev
->dev
, "Failed to allocate memory for CR/CSR "
1452 memset(bridge
->crcsr_kernel
, 0, VME_CRCSR_BUF_SIZE
);
1454 crcsr_addr
= slot
* (512 * 1024);
1455 iowrite32(bridge
->crcsr_bus
- crcsr_addr
, bridge
->base
+ VCSR_TO
);
1457 tmp
= ioread32(bridge
->base
+ VCSR_CTL
);
1458 tmp
|= CA91CX42_VCSR_CTL_EN
;
1459 iowrite32(tmp
, bridge
->base
+ VCSR_CTL
);
1464 static void ca91cx42_crcsr_exit(struct vme_bridge
*ca91cx42_bridge
,
1465 struct pci_dev
*pdev
)
1468 struct ca91cx42_driver
*bridge
;
1470 bridge
= ca91cx42_bridge
->driver_priv
;
1472 /* Turn off CR/CSR space */
1473 tmp
= ioread32(bridge
->base
+ VCSR_CTL
);
1474 tmp
&= ~CA91CX42_VCSR_CTL_EN
;
1475 iowrite32(tmp
, bridge
->base
+ VCSR_CTL
);
1478 iowrite32(0, bridge
->base
+ VCSR_TO
);
1480 pci_free_consistent(pdev
, VME_CRCSR_BUF_SIZE
, bridge
->crcsr_kernel
,
1484 static int ca91cx42_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1488 struct list_head
*pos
= NULL
;
1489 struct vme_bridge
*ca91cx42_bridge
;
1490 struct ca91cx42_driver
*ca91cx42_device
;
1491 struct vme_master_resource
*master_image
;
1492 struct vme_slave_resource
*slave_image
;
1493 struct vme_dma_resource
*dma_ctrlr
;
1494 struct vme_lm_resource
*lm
;
1496 /* We want to support more than one of each bridge so we need to
1497 * dynamically allocate the bridge structure
1499 ca91cx42_bridge
= kzalloc(sizeof(struct vme_bridge
), GFP_KERNEL
);
1501 if (ca91cx42_bridge
== NULL
) {
1502 dev_err(&pdev
->dev
, "Failed to allocate memory for device "
1508 ca91cx42_device
= kzalloc(sizeof(struct ca91cx42_driver
), GFP_KERNEL
);
1510 if (ca91cx42_device
== NULL
) {
1511 dev_err(&pdev
->dev
, "Failed to allocate memory for device "
1517 ca91cx42_bridge
->driver_priv
= ca91cx42_device
;
1519 /* Enable the device */
1520 retval
= pci_enable_device(pdev
);
1522 dev_err(&pdev
->dev
, "Unable to enable device\n");
1527 retval
= pci_request_regions(pdev
, driver_name
);
1529 dev_err(&pdev
->dev
, "Unable to reserve resources\n");
1533 /* map registers in BAR 0 */
1534 ca91cx42_device
->base
= ioremap_nocache(pci_resource_start(pdev
, 0),
1536 if (!ca91cx42_device
->base
) {
1537 dev_err(&pdev
->dev
, "Unable to remap CRG region\n");
1542 /* Check to see if the mapping worked out */
1543 data
= ioread32(ca91cx42_device
->base
+ CA91CX42_PCI_ID
) & 0x0000FFFF;
1544 if (data
!= PCI_VENDOR_ID_TUNDRA
) {
1545 dev_err(&pdev
->dev
, "PCI_ID check failed\n");
1550 /* Initialize wait queues & mutual exclusion flags */
1551 init_waitqueue_head(&(ca91cx42_device
->dma_queue
));
1552 init_waitqueue_head(&(ca91cx42_device
->iack_queue
));
1553 mutex_init(&(ca91cx42_device
->vme_int
));
1554 mutex_init(&(ca91cx42_device
->vme_rmw
));
1556 ca91cx42_bridge
->parent
= &(pdev
->dev
);
1557 strcpy(ca91cx42_bridge
->name
, driver_name
);
1560 retval
= ca91cx42_irq_init(ca91cx42_bridge
);
1562 dev_err(&pdev
->dev
, "Chip Initialization failed.\n");
1566 /* Add master windows to list */
1567 INIT_LIST_HEAD(&(ca91cx42_bridge
->master_resources
));
1568 for (i
= 0; i
< CA91C142_MAX_MASTER
; i
++) {
1569 master_image
= kmalloc(sizeof(struct vme_master_resource
),
1571 if (master_image
== NULL
) {
1572 dev_err(&pdev
->dev
, "Failed to allocate memory for "
1573 "master resource structure\n");
1577 master_image
->parent
= ca91cx42_bridge
;
1578 spin_lock_init(&(master_image
->lock
));
1579 master_image
->locked
= 0;
1580 master_image
->number
= i
;
1581 master_image
->address_attr
= VME_A16
| VME_A24
| VME_A32
|
1582 VME_CRCSR
| VME_USER1
| VME_USER2
;
1583 master_image
->cycle_attr
= VME_SCT
| VME_BLT
| VME_MBLT
|
1584 VME_SUPER
| VME_USER
| VME_PROG
| VME_DATA
;
1585 master_image
->width_attr
= VME_D8
| VME_D16
| VME_D32
| VME_D64
;
1586 memset(&(master_image
->bus_resource
), 0,
1587 sizeof(struct resource
));
1588 master_image
->kern_base
= NULL
;
1589 list_add_tail(&(master_image
->list
),
1590 &(ca91cx42_bridge
->master_resources
));
1593 /* Add slave windows to list */
1594 INIT_LIST_HEAD(&(ca91cx42_bridge
->slave_resources
));
1595 for (i
= 0; i
< CA91C142_MAX_SLAVE
; i
++) {
1596 slave_image
= kmalloc(sizeof(struct vme_slave_resource
),
1598 if (slave_image
== NULL
) {
1599 dev_err(&pdev
->dev
, "Failed to allocate memory for "
1600 "slave resource structure\n");
1604 slave_image
->parent
= ca91cx42_bridge
;
1605 mutex_init(&(slave_image
->mtx
));
1606 slave_image
->locked
= 0;
1607 slave_image
->number
= i
;
1608 slave_image
->address_attr
= VME_A24
| VME_A32
| VME_USER1
|
1611 /* Only windows 0 and 4 support A16 */
1612 if (i
== 0 || i
== 4)
1613 slave_image
->address_attr
|= VME_A16
;
1615 slave_image
->cycle_attr
= VME_SCT
| VME_BLT
| VME_MBLT
|
1616 VME_SUPER
| VME_USER
| VME_PROG
| VME_DATA
;
1617 list_add_tail(&(slave_image
->list
),
1618 &(ca91cx42_bridge
->slave_resources
));
1621 /* Add dma engines to list */
1622 INIT_LIST_HEAD(&(ca91cx42_bridge
->dma_resources
));
1623 for (i
= 0; i
< CA91C142_MAX_DMA
; i
++) {
1624 dma_ctrlr
= kmalloc(sizeof(struct vme_dma_resource
),
1626 if (dma_ctrlr
== NULL
) {
1627 dev_err(&pdev
->dev
, "Failed to allocate memory for "
1628 "dma resource structure\n");
1632 dma_ctrlr
->parent
= ca91cx42_bridge
;
1633 mutex_init(&(dma_ctrlr
->mtx
));
1634 dma_ctrlr
->locked
= 0;
1635 dma_ctrlr
->number
= i
;
1636 dma_ctrlr
->route_attr
= VME_DMA_VME_TO_MEM
|
1638 INIT_LIST_HEAD(&(dma_ctrlr
->pending
));
1639 INIT_LIST_HEAD(&(dma_ctrlr
->running
));
1640 list_add_tail(&(dma_ctrlr
->list
),
1641 &(ca91cx42_bridge
->dma_resources
));
1644 /* Add location monitor to list */
1645 INIT_LIST_HEAD(&(ca91cx42_bridge
->lm_resources
));
1646 lm
= kmalloc(sizeof(struct vme_lm_resource
), GFP_KERNEL
);
1648 dev_err(&pdev
->dev
, "Failed to allocate memory for "
1649 "location monitor resource structure\n");
1653 lm
->parent
= ca91cx42_bridge
;
1654 mutex_init(&(lm
->mtx
));
1658 list_add_tail(&(lm
->list
), &(ca91cx42_bridge
->lm_resources
));
1660 ca91cx42_bridge
->slave_get
= ca91cx42_slave_get
;
1661 ca91cx42_bridge
->slave_set
= ca91cx42_slave_set
;
1662 ca91cx42_bridge
->master_get
= ca91cx42_master_get
;
1663 ca91cx42_bridge
->master_set
= ca91cx42_master_set
;
1664 ca91cx42_bridge
->master_read
= ca91cx42_master_read
;
1665 ca91cx42_bridge
->master_write
= ca91cx42_master_write
;
1666 ca91cx42_bridge
->master_rmw
= ca91cx42_master_rmw
;
1667 ca91cx42_bridge
->dma_list_add
= ca91cx42_dma_list_add
;
1668 ca91cx42_bridge
->dma_list_exec
= ca91cx42_dma_list_exec
;
1669 ca91cx42_bridge
->dma_list_empty
= ca91cx42_dma_list_empty
;
1670 ca91cx42_bridge
->irq_set
= ca91cx42_irq_set
;
1671 ca91cx42_bridge
->irq_generate
= ca91cx42_irq_generate
;
1672 ca91cx42_bridge
->lm_set
= ca91cx42_lm_set
;
1673 ca91cx42_bridge
->lm_get
= ca91cx42_lm_get
;
1674 ca91cx42_bridge
->lm_attach
= ca91cx42_lm_attach
;
1675 ca91cx42_bridge
->lm_detach
= ca91cx42_lm_detach
;
1676 ca91cx42_bridge
->slot_get
= ca91cx42_slot_get
;
1678 data
= ioread32(ca91cx42_device
->base
+ MISC_CTL
);
1679 dev_info(&pdev
->dev
, "Board is%s the VME system controller\n",
1680 (data
& CA91CX42_MISC_CTL_SYSCON
) ? "" : " not");
1681 dev_info(&pdev
->dev
, "Slot ID is %d\n",
1682 ca91cx42_slot_get(ca91cx42_bridge
));
1684 if (ca91cx42_crcsr_init(ca91cx42_bridge
, pdev
))
1685 dev_err(&pdev
->dev
, "CR/CSR configuration failed.\n");
1687 /* Need to save ca91cx42_bridge pointer locally in link list for use in
1690 retval
= vme_register_bridge(ca91cx42_bridge
);
1692 dev_err(&pdev
->dev
, "Chip Registration failed.\n");
1696 pci_set_drvdata(pdev
, ca91cx42_bridge
);
1700 vme_unregister_bridge(ca91cx42_bridge
);
1702 ca91cx42_crcsr_exit(ca91cx42_bridge
, pdev
);
1704 /* resources are stored in link list */
1705 list_for_each(pos
, &(ca91cx42_bridge
->lm_resources
)) {
1706 lm
= list_entry(pos
, struct vme_lm_resource
, list
);
1711 /* resources are stored in link list */
1712 list_for_each(pos
, &(ca91cx42_bridge
->dma_resources
)) {
1713 dma_ctrlr
= list_entry(pos
, struct vme_dma_resource
, list
);
1718 /* resources are stored in link list */
1719 list_for_each(pos
, &(ca91cx42_bridge
->slave_resources
)) {
1720 slave_image
= list_entry(pos
, struct vme_slave_resource
, list
);
1725 /* resources are stored in link list */
1726 list_for_each(pos
, &(ca91cx42_bridge
->master_resources
)) {
1727 master_image
= list_entry(pos
, struct vme_master_resource
,
1730 kfree(master_image
);
1733 ca91cx42_irq_exit(ca91cx42_device
, pdev
);
1736 iounmap(ca91cx42_device
->base
);
1738 pci_release_regions(pdev
);
1740 pci_disable_device(pdev
);
1742 kfree(ca91cx42_device
);
1744 kfree(ca91cx42_bridge
);
1750 void ca91cx42_remove(struct pci_dev
*pdev
)
1752 struct list_head
*pos
= NULL
;
1753 struct vme_master_resource
*master_image
;
1754 struct vme_slave_resource
*slave_image
;
1755 struct vme_dma_resource
*dma_ctrlr
;
1756 struct vme_lm_resource
*lm
;
1757 struct ca91cx42_driver
*bridge
;
1758 struct vme_bridge
*ca91cx42_bridge
= pci_get_drvdata(pdev
);
1760 bridge
= ca91cx42_bridge
->driver_priv
;
1764 iowrite32(0, bridge
->base
+ LINT_EN
);
1766 /* Turn off the windows */
1767 iowrite32(0x00800000, bridge
->base
+ LSI0_CTL
);
1768 iowrite32(0x00800000, bridge
->base
+ LSI1_CTL
);
1769 iowrite32(0x00800000, bridge
->base
+ LSI2_CTL
);
1770 iowrite32(0x00800000, bridge
->base
+ LSI3_CTL
);
1771 iowrite32(0x00800000, bridge
->base
+ LSI4_CTL
);
1772 iowrite32(0x00800000, bridge
->base
+ LSI5_CTL
);
1773 iowrite32(0x00800000, bridge
->base
+ LSI6_CTL
);
1774 iowrite32(0x00800000, bridge
->base
+ LSI7_CTL
);
1775 iowrite32(0x00F00000, bridge
->base
+ VSI0_CTL
);
1776 iowrite32(0x00F00000, bridge
->base
+ VSI1_CTL
);
1777 iowrite32(0x00F00000, bridge
->base
+ VSI2_CTL
);
1778 iowrite32(0x00F00000, bridge
->base
+ VSI3_CTL
);
1779 iowrite32(0x00F00000, bridge
->base
+ VSI4_CTL
);
1780 iowrite32(0x00F00000, bridge
->base
+ VSI5_CTL
);
1781 iowrite32(0x00F00000, bridge
->base
+ VSI6_CTL
);
1782 iowrite32(0x00F00000, bridge
->base
+ VSI7_CTL
);
1784 vme_unregister_bridge(ca91cx42_bridge
);
1786 ca91cx42_crcsr_exit(ca91cx42_bridge
, pdev
);
1788 /* resources are stored in link list */
1789 list_for_each(pos
, &(ca91cx42_bridge
->lm_resources
)) {
1790 lm
= list_entry(pos
, struct vme_lm_resource
, list
);
1795 /* resources are stored in link list */
1796 list_for_each(pos
, &(ca91cx42_bridge
->dma_resources
)) {
1797 dma_ctrlr
= list_entry(pos
, struct vme_dma_resource
, list
);
1802 /* resources are stored in link list */
1803 list_for_each(pos
, &(ca91cx42_bridge
->slave_resources
)) {
1804 slave_image
= list_entry(pos
, struct vme_slave_resource
, list
);
1809 /* resources are stored in link list */
1810 list_for_each(pos
, &(ca91cx42_bridge
->master_resources
)) {
1811 master_image
= list_entry(pos
, struct vme_master_resource
,
1814 kfree(master_image
);
1817 ca91cx42_irq_exit(bridge
, pdev
);
1819 iounmap(bridge
->base
);
1821 pci_release_regions(pdev
);
1823 pci_disable_device(pdev
);
1825 kfree(ca91cx42_bridge
);
1828 static void __exit
ca91cx42_exit(void)
1830 pci_unregister_driver(&ca91cx42_driver
);
1833 MODULE_PARM_DESC(geoid
, "Override geographical addressing");
1834 module_param(geoid
, int, 0);
1836 MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1837 MODULE_LICENSE("GPL");
1839 module_init(ca91cx42_init
);
1840 module_exit(ca91cx42_exit
);