2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4,5 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
92 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
93 * 0.40: 19 Jul 2005: Add support for mac address change.
94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
97 * in the second (and later) nv_open call
98 * 0.43: 10 Aug 2005: Add support for tx checksum.
99 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
101 * 0.46: 20 Oct 2005: Add irq optimization modes.
102 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
103 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
104 * 0.49: 10 Dec 2005: Fix tso for large buffers.
105 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
106 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
107 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
108 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
111 * We suspect that on some hardware no TX done interrupts are generated.
112 * This means recovery from netif_stop_queue only happens if the hw timer
113 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
114 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
115 * If your hardware reliably generates tx done interrupts, then you can remove
116 * DEV_NEED_TIMERIRQ from the driver_data flags.
117 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
118 * superfluous timer interrupts from the nic.
120 #define FORCEDETH_VERSION "0.53"
121 #define DRV_NAME "forcedeth"
123 #include <linux/module.h>
124 #include <linux/types.h>
125 #include <linux/pci.h>
126 #include <linux/interrupt.h>
127 #include <linux/netdevice.h>
128 #include <linux/etherdevice.h>
129 #include <linux/delay.h>
130 #include <linux/spinlock.h>
131 #include <linux/ethtool.h>
132 #include <linux/timer.h>
133 #include <linux/skbuff.h>
134 #include <linux/mii.h>
135 #include <linux/random.h>
136 #include <linux/init.h>
137 #include <linux/if_vlan.h>
138 #include <linux/dma-mapping.h>
142 #include <asm/uaccess.h>
143 #include <asm/system.h>
146 #define dprintk printk
148 #define dprintk(x...) do { } while (0)
156 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
157 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
158 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
159 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
160 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
161 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
162 #define DEV_HAS_MSI 0x0040 /* device supports MSI */
163 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
164 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
167 NvRegIrqStatus
= 0x000,
168 #define NVREG_IRQSTAT_MIIEVENT 0x040
169 #define NVREG_IRQSTAT_MASK 0x1ff
170 NvRegIrqMask
= 0x004,
171 #define NVREG_IRQ_RX_ERROR 0x0001
172 #define NVREG_IRQ_RX 0x0002
173 #define NVREG_IRQ_RX_NOBUF 0x0004
174 #define NVREG_IRQ_TX_ERR 0x0008
175 #define NVREG_IRQ_TX_OK 0x0010
176 #define NVREG_IRQ_TIMER 0x0020
177 #define NVREG_IRQ_LINK 0x0040
178 #define NVREG_IRQ_RX_FORCED 0x0080
179 #define NVREG_IRQ_TX_FORCED 0x0100
180 #define NVREG_IRQMASK_THROUGHPUT 0x00df
181 #define NVREG_IRQMASK_CPU 0x0040
182 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
183 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
184 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
186 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
187 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
188 NVREG_IRQ_TX_FORCED))
190 NvRegUnknownSetupReg6
= 0x008,
191 #define NVREG_UNKSETUP6_VAL 3
194 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
195 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
197 NvRegPollingInterval
= 0x00c,
198 #define NVREG_POLL_DEFAULT_THROUGHPUT 970
199 #define NVREG_POLL_DEFAULT_CPU 13
200 NvRegMSIMap0
= 0x020,
201 NvRegMSIMap1
= 0x024,
202 NvRegMSIIrqMask
= 0x030,
203 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
205 #define NVREG_MISC1_HD 0x02
206 #define NVREG_MISC1_FORCE 0x3b0f3c
208 NvRegMacReset
= 0x3c,
209 #define NVREG_MAC_RESET_ASSERT 0x0F3
210 NvRegTransmitterControl
= 0x084,
211 #define NVREG_XMITCTL_START 0x01
212 NvRegTransmitterStatus
= 0x088,
213 #define NVREG_XMITSTAT_BUSY 0x01
215 NvRegPacketFilterFlags
= 0x8c,
216 #define NVREG_PFF_ALWAYS 0x7F0008
217 #define NVREG_PFF_PROMISC 0x80
218 #define NVREG_PFF_MYADDR 0x20
220 NvRegOffloadConfig
= 0x90,
221 #define NVREG_OFFLOAD_HOMEPHY 0x601
222 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
223 NvRegReceiverControl
= 0x094,
224 #define NVREG_RCVCTL_START 0x01
225 NvRegReceiverStatus
= 0x98,
226 #define NVREG_RCVSTAT_BUSY 0x01
228 NvRegRandomSeed
= 0x9c,
229 #define NVREG_RNDSEED_MASK 0x00ff
230 #define NVREG_RNDSEED_FORCE 0x7f00
231 #define NVREG_RNDSEED_FORCE2 0x2d00
232 #define NVREG_RNDSEED_FORCE3 0x7400
234 NvRegUnknownSetupReg1
= 0xA0,
235 #define NVREG_UNKSETUP1_VAL 0x16070f
236 NvRegUnknownSetupReg2
= 0xA4,
237 #define NVREG_UNKSETUP2_VAL 0x16
238 NvRegMacAddrA
= 0xA8,
239 NvRegMacAddrB
= 0xAC,
240 NvRegMulticastAddrA
= 0xB0,
241 #define NVREG_MCASTADDRA_FORCE 0x01
242 NvRegMulticastAddrB
= 0xB4,
243 NvRegMulticastMaskA
= 0xB8,
244 NvRegMulticastMaskB
= 0xBC,
246 NvRegPhyInterface
= 0xC0,
247 #define PHY_RGMII 0x10000000
249 NvRegTxRingPhysAddr
= 0x100,
250 NvRegRxRingPhysAddr
= 0x104,
251 NvRegRingSizes
= 0x108,
252 #define NVREG_RINGSZ_TXSHIFT 0
253 #define NVREG_RINGSZ_RXSHIFT 16
254 NvRegUnknownTransmitterReg
= 0x10c,
255 NvRegLinkSpeed
= 0x110,
256 #define NVREG_LINKSPEED_FORCE 0x10000
257 #define NVREG_LINKSPEED_10 1000
258 #define NVREG_LINKSPEED_100 100
259 #define NVREG_LINKSPEED_1000 50
260 #define NVREG_LINKSPEED_MASK (0xFFF)
261 NvRegUnknownSetupReg5
= 0x130,
262 #define NVREG_UNKSETUP5_BIT31 (1<<31)
263 NvRegUnknownSetupReg3
= 0x13c,
264 #define NVREG_UNKSETUP3_VAL1 0x200010
265 NvRegTxRxControl
= 0x144,
266 #define NVREG_TXRXCTL_KICK 0x0001
267 #define NVREG_TXRXCTL_BIT1 0x0002
268 #define NVREG_TXRXCTL_BIT2 0x0004
269 #define NVREG_TXRXCTL_IDLE 0x0008
270 #define NVREG_TXRXCTL_RESET 0x0010
271 #define NVREG_TXRXCTL_RXCHECK 0x0400
272 #define NVREG_TXRXCTL_DESC_1 0
273 #define NVREG_TXRXCTL_DESC_2 0x02100
274 #define NVREG_TXRXCTL_DESC_3 0x02200
275 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
276 #define NVREG_TXRXCTL_VLANINS 0x00080
277 NvRegTxRingPhysAddrHigh
= 0x148,
278 NvRegRxRingPhysAddrHigh
= 0x14C,
279 NvRegMIIStatus
= 0x180,
280 #define NVREG_MIISTAT_ERROR 0x0001
281 #define NVREG_MIISTAT_LINKCHANGE 0x0008
282 #define NVREG_MIISTAT_MASK 0x000f
283 #define NVREG_MIISTAT_MASK2 0x000f
284 NvRegUnknownSetupReg4
= 0x184,
285 #define NVREG_UNKSETUP4_VAL 8
287 NvRegAdapterControl
= 0x188,
288 #define NVREG_ADAPTCTL_START 0x02
289 #define NVREG_ADAPTCTL_LINKUP 0x04
290 #define NVREG_ADAPTCTL_PHYVALID 0x40000
291 #define NVREG_ADAPTCTL_RUNNING 0x100000
292 #define NVREG_ADAPTCTL_PHYSHIFT 24
293 NvRegMIISpeed
= 0x18c,
294 #define NVREG_MIISPEED_BIT8 (1<<8)
295 #define NVREG_MIIDELAY 5
296 NvRegMIIControl
= 0x190,
297 #define NVREG_MIICTL_INUSE 0x08000
298 #define NVREG_MIICTL_WRITE 0x00400
299 #define NVREG_MIICTL_ADDRSHIFT 5
300 NvRegMIIData
= 0x194,
301 NvRegWakeUpFlags
= 0x200,
302 #define NVREG_WAKEUPFLAGS_VAL 0x7770
303 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
304 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
305 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
306 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
307 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
308 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
309 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
310 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
311 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
312 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
314 NvRegPatternCRC
= 0x204,
315 NvRegPatternMask
= 0x208,
316 NvRegPowerCap
= 0x268,
317 #define NVREG_POWERCAP_D3SUPP (1<<30)
318 #define NVREG_POWERCAP_D2SUPP (1<<26)
319 #define NVREG_POWERCAP_D1SUPP (1<<25)
320 NvRegPowerState
= 0x26c,
321 #define NVREG_POWERSTATE_POWEREDUP 0x8000
322 #define NVREG_POWERSTATE_VALID 0x0100
323 #define NVREG_POWERSTATE_MASK 0x0003
324 #define NVREG_POWERSTATE_D0 0x0000
325 #define NVREG_POWERSTATE_D1 0x0001
326 #define NVREG_POWERSTATE_D2 0x0002
327 #define NVREG_POWERSTATE_D3 0x0003
328 NvRegVlanControl
= 0x300,
329 #define NVREG_VLANCONTROL_ENABLE 0x2000
330 NvRegMSIXMap0
= 0x3e0,
331 NvRegMSIXMap1
= 0x3e4,
332 NvRegMSIXIrqStatus
= 0x3f0,
334 NvRegPowerState2
= 0x600,
335 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
336 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
339 /* Big endian: should work, but is untested */
345 struct ring_desc_ex
{
346 u32 PacketBufferHigh
;
352 typedef union _ring_type
{
353 struct ring_desc
* orig
;
354 struct ring_desc_ex
* ex
;
357 #define FLAG_MASK_V1 0xffff0000
358 #define FLAG_MASK_V2 0xffffc000
359 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
360 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
362 #define NV_TX_LASTPACKET (1<<16)
363 #define NV_TX_RETRYERROR (1<<19)
364 #define NV_TX_FORCED_INTERRUPT (1<<24)
365 #define NV_TX_DEFERRED (1<<26)
366 #define NV_TX_CARRIERLOST (1<<27)
367 #define NV_TX_LATECOLLISION (1<<28)
368 #define NV_TX_UNDERFLOW (1<<29)
369 #define NV_TX_ERROR (1<<30)
370 #define NV_TX_VALID (1<<31)
372 #define NV_TX2_LASTPACKET (1<<29)
373 #define NV_TX2_RETRYERROR (1<<18)
374 #define NV_TX2_FORCED_INTERRUPT (1<<30)
375 #define NV_TX2_DEFERRED (1<<25)
376 #define NV_TX2_CARRIERLOST (1<<26)
377 #define NV_TX2_LATECOLLISION (1<<27)
378 #define NV_TX2_UNDERFLOW (1<<28)
379 /* error and valid are the same for both */
380 #define NV_TX2_ERROR (1<<30)
381 #define NV_TX2_VALID (1<<31)
382 #define NV_TX2_TSO (1<<28)
383 #define NV_TX2_TSO_SHIFT 14
384 #define NV_TX2_TSO_MAX_SHIFT 14
385 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
386 #define NV_TX2_CHECKSUM_L3 (1<<27)
387 #define NV_TX2_CHECKSUM_L4 (1<<26)
389 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
391 #define NV_RX_DESCRIPTORVALID (1<<16)
392 #define NV_RX_MISSEDFRAME (1<<17)
393 #define NV_RX_SUBSTRACT1 (1<<18)
394 #define NV_RX_ERROR1 (1<<23)
395 #define NV_RX_ERROR2 (1<<24)
396 #define NV_RX_ERROR3 (1<<25)
397 #define NV_RX_ERROR4 (1<<26)
398 #define NV_RX_CRCERR (1<<27)
399 #define NV_RX_OVERFLOW (1<<28)
400 #define NV_RX_FRAMINGERR (1<<29)
401 #define NV_RX_ERROR (1<<30)
402 #define NV_RX_AVAIL (1<<31)
404 #define NV_RX2_CHECKSUMMASK (0x1C000000)
405 #define NV_RX2_CHECKSUMOK1 (0x10000000)
406 #define NV_RX2_CHECKSUMOK2 (0x14000000)
407 #define NV_RX2_CHECKSUMOK3 (0x18000000)
408 #define NV_RX2_DESCRIPTORVALID (1<<29)
409 #define NV_RX2_SUBSTRACT1 (1<<25)
410 #define NV_RX2_ERROR1 (1<<18)
411 #define NV_RX2_ERROR2 (1<<19)
412 #define NV_RX2_ERROR3 (1<<20)
413 #define NV_RX2_ERROR4 (1<<21)
414 #define NV_RX2_CRCERR (1<<22)
415 #define NV_RX2_OVERFLOW (1<<23)
416 #define NV_RX2_FRAMINGERR (1<<24)
417 /* error and avail are the same for both */
418 #define NV_RX2_ERROR (1<<30)
419 #define NV_RX2_AVAIL (1<<31)
421 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
422 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
424 /* Miscelaneous hardware related defines: */
425 #define NV_PCI_REGSZ_VER1 0x270
426 #define NV_PCI_REGSZ_VER2 0x604
428 /* various timeout delays: all in usec */
429 #define NV_TXRX_RESET_DELAY 4
430 #define NV_TXSTOP_DELAY1 10
431 #define NV_TXSTOP_DELAY1MAX 500000
432 #define NV_TXSTOP_DELAY2 100
433 #define NV_RXSTOP_DELAY1 10
434 #define NV_RXSTOP_DELAY1MAX 500000
435 #define NV_RXSTOP_DELAY2 100
436 #define NV_SETUP5_DELAY 5
437 #define NV_SETUP5_DELAYMAX 50000
438 #define NV_POWERUP_DELAY 5
439 #define NV_POWERUP_DELAYMAX 5000
440 #define NV_MIIBUSY_DELAY 50
441 #define NV_MIIPHY_DELAY 10
442 #define NV_MIIPHY_DELAYMAX 10000
443 #define NV_MAC_RESET_DELAY 64
445 #define NV_WAKEUPPATTERNS 5
446 #define NV_WAKEUPMASKENTRIES 4
448 /* General driver defaults */
449 #define NV_WATCHDOG_TIMEO (5*HZ)
454 * If your nic mysteriously hangs then try to reduce the limits
455 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
456 * last valid ring entry. But this would be impossible to
457 * implement - probably a disassembly error.
459 #define TX_LIMIT_STOP 255
460 #define TX_LIMIT_START 254
462 /* rx/tx mac addr + type + vlan + align + slack*/
463 #define NV_RX_HEADERS (64)
464 /* even more slack. */
465 #define NV_RX_ALLOC_PAD (64)
467 /* maximum mtu size */
468 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
469 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
471 #define OOM_REFILL (1+HZ/20)
472 #define POLL_WAIT (1+HZ/100)
473 #define LINK_TIMEOUT (3*HZ)
477 * The nic supports three different descriptor types:
478 * - DESC_VER_1: Original
479 * - DESC_VER_2: support for jumbo frames.
480 * - DESC_VER_3: 64-bit format.
487 #define PHY_OUI_MARVELL 0x5043
488 #define PHY_OUI_CICADA 0x03f1
489 #define PHYID1_OUI_MASK 0x03ff
490 #define PHYID1_OUI_SHFT 6
491 #define PHYID2_OUI_MASK 0xfc00
492 #define PHYID2_OUI_SHFT 10
493 #define PHY_INIT1 0x0f000
494 #define PHY_INIT2 0x0e00
495 #define PHY_INIT3 0x01000
496 #define PHY_INIT4 0x0200
497 #define PHY_INIT5 0x0004
498 #define PHY_INIT6 0x02000
499 #define PHY_GIGABIT 0x0100
501 #define PHY_TIMEOUT 0x1
502 #define PHY_ERROR 0x2
506 #define PHY_HALF 0x100
508 /* FIXME: MII defines that should be added to <linux/mii.h> */
509 #define MII_1000BT_CR 0x09
510 #define MII_1000BT_SR 0x0a
511 #define ADVERTISE_1000FULL 0x0200
512 #define ADVERTISE_1000HALF 0x0100
513 #define LPA_1000FULL 0x0800
514 #define LPA_1000HALF 0x0400
516 /* MSI/MSI-X defines */
517 #define NV_MSI_X_MAX_VECTORS 8
518 #define NV_MSI_X_VECTORS_MASK 0x000f
519 #define NV_MSI_CAPABLE 0x0010
520 #define NV_MSI_X_CAPABLE 0x0020
521 #define NV_MSI_ENABLED 0x0040
522 #define NV_MSI_X_ENABLED 0x0080
524 #define NV_MSI_X_VECTOR_ALL 0x0
525 #define NV_MSI_X_VECTOR_RX 0x0
526 #define NV_MSI_X_VECTOR_TX 0x1
527 #define NV_MSI_X_VECTOR_OTHER 0x2
531 * All hardware access under dev->priv->lock, except the performance
533 * - rx is (pseudo-) lockless: it relies on the single-threading provided
534 * by the arch code for interrupts.
535 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
536 * needs dev->priv->lock :-(
537 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
540 /* in dev: base, irq */
545 * Locking: spin_lock(&np->lock); */
546 struct net_device_stats stats
;
554 unsigned int phy_oui
;
557 /* General data: RO fields */
558 dma_addr_t ring_addr
;
559 struct pci_dev
*pci_dev
;
570 /* rx specific fields.
571 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
574 unsigned int cur_rx
, refill_rx
;
575 struct sk_buff
*rx_skbuff
[RX_RING
];
576 dma_addr_t rx_dma
[RX_RING
];
577 unsigned int rx_buf_sz
;
578 unsigned int pkt_limit
;
579 struct timer_list oom_kick
;
580 struct timer_list nic_poll
;
583 /* media detection workaround.
584 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
587 unsigned long link_timeout
;
589 * tx specific fields.
592 unsigned int next_tx
, nic_tx
;
593 struct sk_buff
*tx_skbuff
[TX_RING
];
594 dma_addr_t tx_dma
[TX_RING
];
595 unsigned int tx_dma_len
[TX_RING
];
599 struct vlan_group
*vlangrp
;
601 /* msi/msi-x fields */
603 struct msix_entry msi_x_entry
[NV_MSI_X_MAX_VECTORS
];
607 * Maximum number of loops until we assume that a bit in the irq mask
608 * is stuck. Overridable with module param.
610 static int max_interrupt_work
= 5;
613 * Optimization can be either throuput mode or cpu mode
615 * Throughput Mode: Every tx and rx packet will generate an interrupt.
616 * CPU Mode: Interrupts are controlled by a timer.
618 #define NV_OPTIMIZATION_MODE_THROUGHPUT 0
619 #define NV_OPTIMIZATION_MODE_CPU 1
620 static int optimization_mode
= NV_OPTIMIZATION_MODE_THROUGHPUT
;
623 * Poll interval for timer irq
625 * This interval determines how frequent an interrupt is generated.
626 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
627 * Min = 0, and Max = 65535
629 static int poll_interval
= -1;
632 * Disable MSI interrupts
634 static int disable_msi
= 0;
637 * Disable MSIX interrupts
639 static int disable_msix
= 0;
641 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
643 return netdev_priv(dev
);
646 static inline u8 __iomem
*get_hwbase(struct net_device
*dev
)
648 return ((struct fe_priv
*)netdev_priv(dev
))->base
;
651 static inline void pci_push(u8 __iomem
*base
)
653 /* force out pending posted writes */
657 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
659 return le32_to_cpu(prd
->FlagLen
)
660 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
663 static inline u32
nv_descr_getlength_ex(struct ring_desc_ex
*prd
, u32 v
)
665 return le32_to_cpu(prd
->FlagLen
) & LEN_MASK_V2
;
668 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
669 int delay
, int delaymax
, const char *msg
)
671 u8 __iomem
*base
= get_hwbase(dev
);
682 } while ((readl(base
+ offset
) & mask
) != target
);
686 #define NV_SETUP_RX_RING 0x01
687 #define NV_SETUP_TX_RING 0x02
689 static void setup_hw_rings(struct net_device
*dev
, int rxtx_flags
)
691 struct fe_priv
*np
= get_nvpriv(dev
);
692 u8 __iomem
*base
= get_hwbase(dev
);
694 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
695 if (rxtx_flags
& NV_SETUP_RX_RING
) {
696 writel((u32
) cpu_to_le64(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
698 if (rxtx_flags
& NV_SETUP_TX_RING
) {
699 writel((u32
) cpu_to_le64(np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
702 if (rxtx_flags
& NV_SETUP_RX_RING
) {
703 writel((u32
) cpu_to_le64(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
704 writel((u32
) (cpu_to_le64(np
->ring_addr
) >> 32), base
+ NvRegRxRingPhysAddrHigh
);
706 if (rxtx_flags
& NV_SETUP_TX_RING
) {
707 writel((u32
) cpu_to_le64(np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
708 writel((u32
) (cpu_to_le64(np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc_ex
)) >> 32), base
+ NvRegTxRingPhysAddrHigh
);
713 #define MII_READ (-1)
714 /* mii_rw: read/write a register on the PHY.
716 * Caller must guarantee serialization
718 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
720 u8 __iomem
*base
= get_hwbase(dev
);
724 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
726 reg
= readl(base
+ NvRegMIIControl
);
727 if (reg
& NVREG_MIICTL_INUSE
) {
728 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
729 udelay(NV_MIIBUSY_DELAY
);
732 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
733 if (value
!= MII_READ
) {
734 writel(value
, base
+ NvRegMIIData
);
735 reg
|= NVREG_MIICTL_WRITE
;
737 writel(reg
, base
+ NvRegMIIControl
);
739 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
740 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
, NULL
)) {
741 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d timed out.\n",
742 dev
->name
, miireg
, addr
);
744 } else if (value
!= MII_READ
) {
745 /* it was a write operation - fewer failures are detectable */
746 dprintk(KERN_DEBUG
"%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
747 dev
->name
, value
, miireg
, addr
);
749 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
750 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d failed.\n",
751 dev
->name
, miireg
, addr
);
754 retval
= readl(base
+ NvRegMIIData
);
755 dprintk(KERN_DEBUG
"%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
756 dev
->name
, miireg
, addr
, retval
);
762 static int phy_reset(struct net_device
*dev
)
764 struct fe_priv
*np
= netdev_priv(dev
);
766 unsigned int tries
= 0;
768 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
769 miicontrol
|= BMCR_RESET
;
770 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
)) {
777 /* must wait till reset is deasserted */
778 while (miicontrol
& BMCR_RESET
) {
780 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
781 /* FIXME: 100 tries seem excessive */
788 static int phy_init(struct net_device
*dev
)
790 struct fe_priv
*np
= get_nvpriv(dev
);
791 u8 __iomem
*base
= get_hwbase(dev
);
792 u32 phyinterface
, phy_reserved
, mii_status
, mii_control
, mii_control_1000
,reg
;
794 /* set advertise register */
795 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
796 reg
|= (ADVERTISE_10HALF
|ADVERTISE_10FULL
|ADVERTISE_100HALF
|ADVERTISE_100FULL
|0x800|0x400);
797 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
798 printk(KERN_INFO
"%s: phy write to advertise failed.\n", pci_name(np
->pci_dev
));
802 /* get phy interface type */
803 phyinterface
= readl(base
+ NvRegPhyInterface
);
805 /* see if gigabit phy */
806 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
807 if (mii_status
& PHY_GIGABIT
) {
808 np
->gigabit
= PHY_GIGABIT
;
809 mii_control_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
810 mii_control_1000
&= ~ADVERTISE_1000HALF
;
811 if (phyinterface
& PHY_RGMII
)
812 mii_control_1000
|= ADVERTISE_1000FULL
;
814 mii_control_1000
&= ~ADVERTISE_1000FULL
;
816 if (mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, mii_control_1000
)) {
817 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
825 if (phy_reset(dev
)) {
826 printk(KERN_INFO
"%s: phy reset failed\n", pci_name(np
->pci_dev
));
830 /* phy vendor specific configuration */
831 if ((np
->phy_oui
== PHY_OUI_CICADA
) && (phyinterface
& PHY_RGMII
) ) {
832 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
833 phy_reserved
&= ~(PHY_INIT1
| PHY_INIT2
);
834 phy_reserved
|= (PHY_INIT3
| PHY_INIT4
);
835 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
)) {
836 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
839 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
840 phy_reserved
|= PHY_INIT5
;
841 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
)) {
842 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
846 if (np
->phy_oui
== PHY_OUI_CICADA
) {
847 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
848 phy_reserved
|= PHY_INIT6
;
849 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
)) {
850 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
855 /* restart auto negotiation */
856 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
857 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
858 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
865 static void nv_start_rx(struct net_device
*dev
)
867 struct fe_priv
*np
= netdev_priv(dev
);
868 u8 __iomem
*base
= get_hwbase(dev
);
870 dprintk(KERN_DEBUG
"%s: nv_start_rx\n", dev
->name
);
871 /* Already running? Stop it. */
872 if (readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) {
873 writel(0, base
+ NvRegReceiverControl
);
876 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
878 writel(NVREG_RCVCTL_START
, base
+ NvRegReceiverControl
);
879 dprintk(KERN_DEBUG
"%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
880 dev
->name
, np
->duplex
, np
->linkspeed
);
884 static void nv_stop_rx(struct net_device
*dev
)
886 u8 __iomem
*base
= get_hwbase(dev
);
888 dprintk(KERN_DEBUG
"%s: nv_stop_rx\n", dev
->name
);
889 writel(0, base
+ NvRegReceiverControl
);
890 reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
891 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
,
892 KERN_INFO
"nv_stop_rx: ReceiverStatus remained busy");
894 udelay(NV_RXSTOP_DELAY2
);
895 writel(0, base
+ NvRegLinkSpeed
);
898 static void nv_start_tx(struct net_device
*dev
)
900 u8 __iomem
*base
= get_hwbase(dev
);
902 dprintk(KERN_DEBUG
"%s: nv_start_tx\n", dev
->name
);
903 writel(NVREG_XMITCTL_START
, base
+ NvRegTransmitterControl
);
907 static void nv_stop_tx(struct net_device
*dev
)
909 u8 __iomem
*base
= get_hwbase(dev
);
911 dprintk(KERN_DEBUG
"%s: nv_stop_tx\n", dev
->name
);
912 writel(0, base
+ NvRegTransmitterControl
);
913 reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
914 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
,
915 KERN_INFO
"nv_stop_tx: TransmitterStatus remained busy");
917 udelay(NV_TXSTOP_DELAY2
);
918 writel(0, base
+ NvRegUnknownTransmitterReg
);
921 static void nv_txrx_reset(struct net_device
*dev
)
923 struct fe_priv
*np
= netdev_priv(dev
);
924 u8 __iomem
*base
= get_hwbase(dev
);
926 dprintk(KERN_DEBUG
"%s: nv_txrx_reset\n", dev
->name
);
927 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
929 udelay(NV_TXRX_RESET_DELAY
);
930 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
934 static void nv_mac_reset(struct net_device
*dev
)
936 struct fe_priv
*np
= netdev_priv(dev
);
937 u8 __iomem
*base
= get_hwbase(dev
);
939 dprintk(KERN_DEBUG
"%s: nv_mac_reset\n", dev
->name
);
940 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
942 writel(NVREG_MAC_RESET_ASSERT
, base
+ NvRegMacReset
);
944 udelay(NV_MAC_RESET_DELAY
);
945 writel(0, base
+ NvRegMacReset
);
947 udelay(NV_MAC_RESET_DELAY
);
948 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
953 * nv_get_stats: dev->get_stats function
954 * Get latest stats value from the nic.
955 * Called with read_lock(&dev_base_lock) held for read -
956 * only synchronized against unregister_netdevice.
958 static struct net_device_stats
*nv_get_stats(struct net_device
*dev
)
960 struct fe_priv
*np
= netdev_priv(dev
);
962 /* It seems that the nic always generates interrupts and doesn't
963 * accumulate errors internally. Thus the current values in np->stats
964 * are already up to date.
970 * nv_alloc_rx: fill rx ring entries.
971 * Return 1 if the allocations for the skbs failed and the
972 * rx engine is without Available descriptors
974 static int nv_alloc_rx(struct net_device
*dev
)
976 struct fe_priv
*np
= netdev_priv(dev
);
977 unsigned int refill_rx
= np
->refill_rx
;
980 while (np
->cur_rx
!= refill_rx
) {
983 nr
= refill_rx
% RX_RING
;
984 if (np
->rx_skbuff
[nr
] == NULL
) {
986 skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
991 np
->rx_skbuff
[nr
] = skb
;
993 skb
= np
->rx_skbuff
[nr
];
995 np
->rx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
,
996 skb
->end
-skb
->data
, PCI_DMA_FROMDEVICE
);
997 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
998 np
->rx_ring
.orig
[nr
].PacketBuffer
= cpu_to_le32(np
->rx_dma
[nr
]);
1000 np
->rx_ring
.orig
[nr
].FlagLen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX_AVAIL
);
1002 np
->rx_ring
.ex
[nr
].PacketBufferHigh
= cpu_to_le64(np
->rx_dma
[nr
]) >> 32;
1003 np
->rx_ring
.ex
[nr
].PacketBufferLow
= cpu_to_le64(np
->rx_dma
[nr
]) & 0x0FFFFFFFF;
1005 np
->rx_ring
.ex
[nr
].FlagLen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX2_AVAIL
);
1007 dprintk(KERN_DEBUG
"%s: nv_alloc_rx: Packet %d marked as Available\n",
1008 dev
->name
, refill_rx
);
1011 np
->refill_rx
= refill_rx
;
1012 if (np
->cur_rx
- refill_rx
== RX_RING
)
1017 static void nv_do_rx_refill(unsigned long data
)
1019 struct net_device
*dev
= (struct net_device
*) data
;
1020 struct fe_priv
*np
= netdev_priv(dev
);
1023 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
1024 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
1025 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1))) {
1026 disable_irq(dev
->irq
);
1028 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1030 if (nv_alloc_rx(dev
)) {
1031 spin_lock(&np
->lock
);
1032 if (!np
->in_shutdown
)
1033 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1034 spin_unlock(&np
->lock
);
1036 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
1037 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
1038 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1))) {
1039 enable_irq(dev
->irq
);
1041 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1045 static void nv_init_rx(struct net_device
*dev
)
1047 struct fe_priv
*np
= netdev_priv(dev
);
1050 np
->cur_rx
= RX_RING
;
1052 for (i
= 0; i
< RX_RING
; i
++)
1053 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1054 np
->rx_ring
.orig
[i
].FlagLen
= 0;
1056 np
->rx_ring
.ex
[i
].FlagLen
= 0;
1059 static void nv_init_tx(struct net_device
*dev
)
1061 struct fe_priv
*np
= netdev_priv(dev
);
1064 np
->next_tx
= np
->nic_tx
= 0;
1065 for (i
= 0; i
< TX_RING
; i
++) {
1066 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1067 np
->tx_ring
.orig
[i
].FlagLen
= 0;
1069 np
->tx_ring
.ex
[i
].FlagLen
= 0;
1070 np
->tx_skbuff
[i
] = NULL
;
1075 static int nv_init_ring(struct net_device
*dev
)
1079 return nv_alloc_rx(dev
);
1082 static int nv_release_txskb(struct net_device
*dev
, unsigned int skbnr
)
1084 struct fe_priv
*np
= netdev_priv(dev
);
1086 dprintk(KERN_INFO
"%s: nv_release_txskb for skbnr %d\n",
1089 if (np
->tx_dma
[skbnr
]) {
1090 pci_unmap_page(np
->pci_dev
, np
->tx_dma
[skbnr
],
1091 np
->tx_dma_len
[skbnr
],
1093 np
->tx_dma
[skbnr
] = 0;
1096 if (np
->tx_skbuff
[skbnr
]) {
1097 dev_kfree_skb_any(np
->tx_skbuff
[skbnr
]);
1098 np
->tx_skbuff
[skbnr
] = NULL
;
1105 static void nv_drain_tx(struct net_device
*dev
)
1107 struct fe_priv
*np
= netdev_priv(dev
);
1110 for (i
= 0; i
< TX_RING
; i
++) {
1111 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1112 np
->tx_ring
.orig
[i
].FlagLen
= 0;
1114 np
->tx_ring
.ex
[i
].FlagLen
= 0;
1115 if (nv_release_txskb(dev
, i
))
1116 np
->stats
.tx_dropped
++;
1120 static void nv_drain_rx(struct net_device
*dev
)
1122 struct fe_priv
*np
= netdev_priv(dev
);
1124 for (i
= 0; i
< RX_RING
; i
++) {
1125 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1126 np
->rx_ring
.orig
[i
].FlagLen
= 0;
1128 np
->rx_ring
.ex
[i
].FlagLen
= 0;
1130 if (np
->rx_skbuff
[i
]) {
1131 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
1132 np
->rx_skbuff
[i
]->end
-np
->rx_skbuff
[i
]->data
,
1133 PCI_DMA_FROMDEVICE
);
1134 dev_kfree_skb(np
->rx_skbuff
[i
]);
1135 np
->rx_skbuff
[i
] = NULL
;
1140 static void drain_ring(struct net_device
*dev
)
1147 * nv_start_xmit: dev->hard_start_xmit function
1148 * Called with dev->xmit_lock held.
1150 static int nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1152 struct fe_priv
*np
= netdev_priv(dev
);
1154 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
1155 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
1156 unsigned int nr
= (np
->next_tx
- 1) % TX_RING
;
1157 unsigned int start_nr
= np
->next_tx
% TX_RING
;
1161 u32 size
= skb
->len
-skb
->data_len
;
1162 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
1163 u32 tx_flags_vlan
= 0;
1165 /* add fragments to entries count */
1166 for (i
= 0; i
< fragments
; i
++) {
1167 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
1168 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
1171 spin_lock_irq(&np
->lock
);
1173 if ((np
->next_tx
- np
->nic_tx
+ entries
- 1) > TX_LIMIT_STOP
) {
1174 spin_unlock_irq(&np
->lock
);
1175 netif_stop_queue(dev
);
1176 return NETDEV_TX_BUSY
;
1179 /* setup the header buffer */
1181 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
1182 nr
= (nr
+ 1) % TX_RING
;
1184 np
->tx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
1186 np
->tx_dma_len
[nr
] = bcnt
;
1188 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1189 np
->tx_ring
.orig
[nr
].PacketBuffer
= cpu_to_le32(np
->tx_dma
[nr
]);
1190 np
->tx_ring
.orig
[nr
].FlagLen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1192 np
->tx_ring
.ex
[nr
].PacketBufferHigh
= cpu_to_le64(np
->tx_dma
[nr
]) >> 32;
1193 np
->tx_ring
.ex
[nr
].PacketBufferLow
= cpu_to_le64(np
->tx_dma
[nr
]) & 0x0FFFFFFFF;
1194 np
->tx_ring
.ex
[nr
].FlagLen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1196 tx_flags
= np
->tx_flags
;
1201 /* setup the fragments */
1202 for (i
= 0; i
< fragments
; i
++) {
1203 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1204 u32 size
= frag
->size
;
1208 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
1209 nr
= (nr
+ 1) % TX_RING
;
1211 np
->tx_dma
[nr
] = pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
1213 np
->tx_dma_len
[nr
] = bcnt
;
1215 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1216 np
->tx_ring
.orig
[nr
].PacketBuffer
= cpu_to_le32(np
->tx_dma
[nr
]);
1217 np
->tx_ring
.orig
[nr
].FlagLen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1219 np
->tx_ring
.ex
[nr
].PacketBufferHigh
= cpu_to_le64(np
->tx_dma
[nr
]) >> 32;
1220 np
->tx_ring
.ex
[nr
].PacketBufferLow
= cpu_to_le64(np
->tx_dma
[nr
]) & 0x0FFFFFFFF;
1221 np
->tx_ring
.ex
[nr
].FlagLen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1228 /* set last fragment flag */
1229 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1230 np
->tx_ring
.orig
[nr
].FlagLen
|= cpu_to_le32(tx_flags_extra
);
1232 np
->tx_ring
.ex
[nr
].FlagLen
|= cpu_to_le32(tx_flags_extra
);
1235 np
->tx_skbuff
[nr
] = skb
;
1238 if (skb_shinfo(skb
)->tso_size
)
1239 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->tso_size
<< NV_TX2_TSO_SHIFT
);
1242 tx_flags_extra
= (skb
->ip_summed
== CHECKSUM_HW
? (NV_TX2_CHECKSUM_L3
|NV_TX2_CHECKSUM_L4
) : 0);
1245 if (np
->vlangrp
&& vlan_tx_tag_present(skb
)) {
1246 tx_flags_vlan
= NV_TX3_VLAN_TAG_PRESENT
| vlan_tx_tag_get(skb
);
1250 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1251 np
->tx_ring
.orig
[start_nr
].FlagLen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
1253 np
->tx_ring
.ex
[start_nr
].TxVlan
= cpu_to_le32(tx_flags_vlan
);
1254 np
->tx_ring
.ex
[start_nr
].FlagLen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
1257 dprintk(KERN_DEBUG
"%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1258 dev
->name
, np
->next_tx
, entries
, tx_flags_extra
);
1261 for (j
=0; j
<64; j
++) {
1263 dprintk("\n%03x:", j
);
1264 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
1269 np
->next_tx
+= entries
;
1271 dev
->trans_start
= jiffies
;
1272 spin_unlock_irq(&np
->lock
);
1273 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
1274 pci_push(get_hwbase(dev
));
1275 return NETDEV_TX_OK
;
1279 * nv_tx_done: check for completed packets, release the skbs.
1281 * Caller must own np->lock.
1283 static void nv_tx_done(struct net_device
*dev
)
1285 struct fe_priv
*np
= netdev_priv(dev
);
1288 struct sk_buff
*skb
;
1290 while (np
->nic_tx
!= np
->next_tx
) {
1291 i
= np
->nic_tx
% TX_RING
;
1293 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1294 Flags
= le32_to_cpu(np
->tx_ring
.orig
[i
].FlagLen
);
1296 Flags
= le32_to_cpu(np
->tx_ring
.ex
[i
].FlagLen
);
1298 dprintk(KERN_DEBUG
"%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1299 dev
->name
, np
->nic_tx
, Flags
);
1300 if (Flags
& NV_TX_VALID
)
1302 if (np
->desc_ver
== DESC_VER_1
) {
1303 if (Flags
& NV_TX_LASTPACKET
) {
1304 skb
= np
->tx_skbuff
[i
];
1305 if (Flags
& (NV_TX_RETRYERROR
|NV_TX_CARRIERLOST
|NV_TX_LATECOLLISION
|
1306 NV_TX_UNDERFLOW
|NV_TX_ERROR
)) {
1307 if (Flags
& NV_TX_UNDERFLOW
)
1308 np
->stats
.tx_fifo_errors
++;
1309 if (Flags
& NV_TX_CARRIERLOST
)
1310 np
->stats
.tx_carrier_errors
++;
1311 np
->stats
.tx_errors
++;
1313 np
->stats
.tx_packets
++;
1314 np
->stats
.tx_bytes
+= skb
->len
;
1318 if (Flags
& NV_TX2_LASTPACKET
) {
1319 skb
= np
->tx_skbuff
[i
];
1320 if (Flags
& (NV_TX2_RETRYERROR
|NV_TX2_CARRIERLOST
|NV_TX2_LATECOLLISION
|
1321 NV_TX2_UNDERFLOW
|NV_TX2_ERROR
)) {
1322 if (Flags
& NV_TX2_UNDERFLOW
)
1323 np
->stats
.tx_fifo_errors
++;
1324 if (Flags
& NV_TX2_CARRIERLOST
)
1325 np
->stats
.tx_carrier_errors
++;
1326 np
->stats
.tx_errors
++;
1328 np
->stats
.tx_packets
++;
1329 np
->stats
.tx_bytes
+= skb
->len
;
1333 nv_release_txskb(dev
, i
);
1336 if (np
->next_tx
- np
->nic_tx
< TX_LIMIT_START
)
1337 netif_wake_queue(dev
);
1341 * nv_tx_timeout: dev->tx_timeout function
1342 * Called with dev->xmit_lock held.
1344 static void nv_tx_timeout(struct net_device
*dev
)
1346 struct fe_priv
*np
= netdev_priv(dev
);
1347 u8 __iomem
*base
= get_hwbase(dev
);
1350 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1351 status
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
1353 status
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
1355 printk(KERN_INFO
"%s: Got tx_timeout. irq: %08x\n", dev
->name
, status
);
1360 printk(KERN_INFO
"%s: Ring at %lx: next %d nic %d\n",
1361 dev
->name
, (unsigned long)np
->ring_addr
,
1362 np
->next_tx
, np
->nic_tx
);
1363 printk(KERN_INFO
"%s: Dumping tx registers\n", dev
->name
);
1364 for (i
=0;i
<=np
->register_size
;i
+= 32) {
1365 printk(KERN_INFO
"%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1367 readl(base
+ i
+ 0), readl(base
+ i
+ 4),
1368 readl(base
+ i
+ 8), readl(base
+ i
+ 12),
1369 readl(base
+ i
+ 16), readl(base
+ i
+ 20),
1370 readl(base
+ i
+ 24), readl(base
+ i
+ 28));
1372 printk(KERN_INFO
"%s: Dumping tx ring\n", dev
->name
);
1373 for (i
=0;i
<TX_RING
;i
+= 4) {
1374 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1375 printk(KERN_INFO
"%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1377 le32_to_cpu(np
->tx_ring
.orig
[i
].PacketBuffer
),
1378 le32_to_cpu(np
->tx_ring
.orig
[i
].FlagLen
),
1379 le32_to_cpu(np
->tx_ring
.orig
[i
+1].PacketBuffer
),
1380 le32_to_cpu(np
->tx_ring
.orig
[i
+1].FlagLen
),
1381 le32_to_cpu(np
->tx_ring
.orig
[i
+2].PacketBuffer
),
1382 le32_to_cpu(np
->tx_ring
.orig
[i
+2].FlagLen
),
1383 le32_to_cpu(np
->tx_ring
.orig
[i
+3].PacketBuffer
),
1384 le32_to_cpu(np
->tx_ring
.orig
[i
+3].FlagLen
));
1386 printk(KERN_INFO
"%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1388 le32_to_cpu(np
->tx_ring
.ex
[i
].PacketBufferHigh
),
1389 le32_to_cpu(np
->tx_ring
.ex
[i
].PacketBufferLow
),
1390 le32_to_cpu(np
->tx_ring
.ex
[i
].FlagLen
),
1391 le32_to_cpu(np
->tx_ring
.ex
[i
+1].PacketBufferHigh
),
1392 le32_to_cpu(np
->tx_ring
.ex
[i
+1].PacketBufferLow
),
1393 le32_to_cpu(np
->tx_ring
.ex
[i
+1].FlagLen
),
1394 le32_to_cpu(np
->tx_ring
.ex
[i
+2].PacketBufferHigh
),
1395 le32_to_cpu(np
->tx_ring
.ex
[i
+2].PacketBufferLow
),
1396 le32_to_cpu(np
->tx_ring
.ex
[i
+2].FlagLen
),
1397 le32_to_cpu(np
->tx_ring
.ex
[i
+3].PacketBufferHigh
),
1398 le32_to_cpu(np
->tx_ring
.ex
[i
+3].PacketBufferLow
),
1399 le32_to_cpu(np
->tx_ring
.ex
[i
+3].FlagLen
));
1404 spin_lock_irq(&np
->lock
);
1406 /* 1) stop tx engine */
1409 /* 2) check that the packets were not sent already: */
1412 /* 3) if there are dead entries: clear everything */
1413 if (np
->next_tx
!= np
->nic_tx
) {
1414 printk(KERN_DEBUG
"%s: tx_timeout: dead entries!\n", dev
->name
);
1416 np
->next_tx
= np
->nic_tx
= 0;
1417 setup_hw_rings(dev
, NV_SETUP_TX_RING
);
1418 netif_wake_queue(dev
);
1421 /* 4) restart tx engine */
1423 spin_unlock_irq(&np
->lock
);
1427 * Called when the nic notices a mismatch between the actual data len on the
1428 * wire and the len indicated in the 802 header
1430 static int nv_getlen(struct net_device
*dev
, void *packet
, int datalen
)
1432 int hdrlen
; /* length of the 802 header */
1433 int protolen
; /* length as stored in the proto field */
1435 /* 1) calculate len according to header */
1436 if ( ((struct vlan_ethhdr
*)packet
)->h_vlan_proto
== __constant_htons(ETH_P_8021Q
)) {
1437 protolen
= ntohs( ((struct vlan_ethhdr
*)packet
)->h_vlan_encapsulated_proto
);
1440 protolen
= ntohs( ((struct ethhdr
*)packet
)->h_proto
);
1443 dprintk(KERN_DEBUG
"%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1444 dev
->name
, datalen
, protolen
, hdrlen
);
1445 if (protolen
> ETH_DATA_LEN
)
1446 return datalen
; /* Value in proto field not a len, no checks possible */
1449 /* consistency checks: */
1450 if (datalen
> ETH_ZLEN
) {
1451 if (datalen
>= protolen
) {
1452 /* more data on wire than in 802 header, trim of
1455 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
1456 dev
->name
, protolen
);
1459 /* less data on wire than mentioned in header.
1460 * Discard the packet.
1462 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding long packet.\n",
1467 /* short packet. Accept only if 802 values are also short */
1468 if (protolen
> ETH_ZLEN
) {
1469 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding short packet.\n",
1473 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
1474 dev
->name
, datalen
);
1479 static void nv_rx_process(struct net_device
*dev
)
1481 struct fe_priv
*np
= netdev_priv(dev
);
1487 struct sk_buff
*skb
;
1490 if (np
->cur_rx
- np
->refill_rx
>= RX_RING
)
1491 break; /* we scanned the whole ring - do not continue */
1493 i
= np
->cur_rx
% RX_RING
;
1494 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1495 Flags
= le32_to_cpu(np
->rx_ring
.orig
[i
].FlagLen
);
1496 len
= nv_descr_getlength(&np
->rx_ring
.orig
[i
], np
->desc_ver
);
1498 Flags
= le32_to_cpu(np
->rx_ring
.ex
[i
].FlagLen
);
1499 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[i
], np
->desc_ver
);
1500 vlanflags
= le32_to_cpu(np
->rx_ring
.ex
[i
].PacketBufferLow
);
1503 dprintk(KERN_DEBUG
"%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1504 dev
->name
, np
->cur_rx
, Flags
);
1506 if (Flags
& NV_RX_AVAIL
)
1507 break; /* still owned by hardware, */
1510 * the packet is for us - immediately tear down the pci mapping.
1511 * TODO: check if a prefetch of the first cacheline improves
1514 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
1515 np
->rx_skbuff
[i
]->end
-np
->rx_skbuff
[i
]->data
,
1516 PCI_DMA_FROMDEVICE
);
1520 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",Flags
);
1521 for (j
=0; j
<64; j
++) {
1523 dprintk("\n%03x:", j
);
1524 dprintk(" %02x", ((unsigned char*)np
->rx_skbuff
[i
]->data
)[j
]);
1528 /* look at what we actually got: */
1529 if (np
->desc_ver
== DESC_VER_1
) {
1530 if (!(Flags
& NV_RX_DESCRIPTORVALID
))
1533 if (Flags
& NV_RX_ERROR
) {
1534 if (Flags
& NV_RX_MISSEDFRAME
) {
1535 np
->stats
.rx_missed_errors
++;
1536 np
->stats
.rx_errors
++;
1539 if (Flags
& (NV_RX_ERROR1
|NV_RX_ERROR2
|NV_RX_ERROR3
)) {
1540 np
->stats
.rx_errors
++;
1543 if (Flags
& NV_RX_CRCERR
) {
1544 np
->stats
.rx_crc_errors
++;
1545 np
->stats
.rx_errors
++;
1548 if (Flags
& NV_RX_OVERFLOW
) {
1549 np
->stats
.rx_over_errors
++;
1550 np
->stats
.rx_errors
++;
1553 if (Flags
& NV_RX_ERROR4
) {
1554 len
= nv_getlen(dev
, np
->rx_skbuff
[i
]->data
, len
);
1556 np
->stats
.rx_errors
++;
1560 /* framing errors are soft errors. */
1561 if (Flags
& NV_RX_FRAMINGERR
) {
1562 if (Flags
& NV_RX_SUBSTRACT1
) {
1568 if (!(Flags
& NV_RX2_DESCRIPTORVALID
))
1571 if (Flags
& NV_RX2_ERROR
) {
1572 if (Flags
& (NV_RX2_ERROR1
|NV_RX2_ERROR2
|NV_RX2_ERROR3
)) {
1573 np
->stats
.rx_errors
++;
1576 if (Flags
& NV_RX2_CRCERR
) {
1577 np
->stats
.rx_crc_errors
++;
1578 np
->stats
.rx_errors
++;
1581 if (Flags
& NV_RX2_OVERFLOW
) {
1582 np
->stats
.rx_over_errors
++;
1583 np
->stats
.rx_errors
++;
1586 if (Flags
& NV_RX2_ERROR4
) {
1587 len
= nv_getlen(dev
, np
->rx_skbuff
[i
]->data
, len
);
1589 np
->stats
.rx_errors
++;
1593 /* framing errors are soft errors */
1594 if (Flags
& NV_RX2_FRAMINGERR
) {
1595 if (Flags
& NV_RX2_SUBSTRACT1
) {
1600 Flags
&= NV_RX2_CHECKSUMMASK
;
1601 if (Flags
== NV_RX2_CHECKSUMOK1
||
1602 Flags
== NV_RX2_CHECKSUMOK2
||
1603 Flags
== NV_RX2_CHECKSUMOK3
) {
1604 dprintk(KERN_DEBUG
"%s: hw checksum hit!.\n", dev
->name
);
1605 np
->rx_skbuff
[i
]->ip_summed
= CHECKSUM_UNNECESSARY
;
1607 dprintk(KERN_DEBUG
"%s: hwchecksum miss!.\n", dev
->name
);
1610 /* got a valid packet - forward it to the network core */
1611 skb
= np
->rx_skbuff
[i
];
1612 np
->rx_skbuff
[i
] = NULL
;
1615 skb
->protocol
= eth_type_trans(skb
, dev
);
1616 dprintk(KERN_DEBUG
"%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1617 dev
->name
, np
->cur_rx
, len
, skb
->protocol
);
1618 if (np
->vlangrp
&& (vlanflags
& NV_RX3_VLAN_TAG_PRESENT
)) {
1619 vlan_hwaccel_rx(skb
, np
->vlangrp
, vlanflags
& NV_RX3_VLAN_TAG_MASK
);
1623 dev
->last_rx
= jiffies
;
1624 np
->stats
.rx_packets
++;
1625 np
->stats
.rx_bytes
+= len
;
1631 static void set_bufsize(struct net_device
*dev
)
1633 struct fe_priv
*np
= netdev_priv(dev
);
1635 if (dev
->mtu
<= ETH_DATA_LEN
)
1636 np
->rx_buf_sz
= ETH_DATA_LEN
+ NV_RX_HEADERS
;
1638 np
->rx_buf_sz
= dev
->mtu
+ NV_RX_HEADERS
;
1642 * nv_change_mtu: dev->change_mtu function
1643 * Called with dev_base_lock held for read.
1645 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
1647 struct fe_priv
*np
= netdev_priv(dev
);
1650 if (new_mtu
< 64 || new_mtu
> np
->pkt_limit
)
1656 /* return early if the buffer sizes will not change */
1657 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
1659 if (old_mtu
== new_mtu
)
1662 /* synchronized against open : rtnl_lock() held by caller */
1663 if (netif_running(dev
)) {
1664 u8 __iomem
*base
= get_hwbase(dev
);
1666 * It seems that the nic preloads valid ring entries into an
1667 * internal buffer. The procedure for flushing everything is
1668 * guessed, there is probably a simpler approach.
1669 * Changing the MTU is a rare event, it shouldn't matter.
1671 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
1672 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
1673 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1))) {
1674 disable_irq(dev
->irq
);
1676 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1677 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1678 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1680 spin_lock_bh(&dev
->xmit_lock
);
1681 spin_lock(&np
->lock
);
1686 /* drain rx queue */
1689 /* reinit driver view of the rx queue */
1692 /* alloc new rx buffers */
1694 if (nv_alloc_rx(dev
)) {
1695 if (!np
->in_shutdown
)
1696 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1698 /* reinit nic view of the rx queue */
1699 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
1700 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
1701 writel( ((RX_RING
-1) << NVREG_RINGSZ_RXSHIFT
) + ((TX_RING
-1) << NVREG_RINGSZ_TXSHIFT
),
1702 base
+ NvRegRingSizes
);
1704 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
1707 /* restart rx engine */
1710 spin_unlock(&np
->lock
);
1711 spin_unlock_bh(&dev
->xmit_lock
);
1712 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
1713 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
1714 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1))) {
1715 enable_irq(dev
->irq
);
1717 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1718 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1719 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1725 static void nv_copy_mac_to_hw(struct net_device
*dev
)
1727 u8 __iomem
*base
= get_hwbase(dev
);
1730 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
1731 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
1732 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
1734 writel(mac
[0], base
+ NvRegMacAddrA
);
1735 writel(mac
[1], base
+ NvRegMacAddrB
);
1739 * nv_set_mac_address: dev->set_mac_address function
1740 * Called with rtnl_lock() held.
1742 static int nv_set_mac_address(struct net_device
*dev
, void *addr
)
1744 struct fe_priv
*np
= netdev_priv(dev
);
1745 struct sockaddr
*macaddr
= (struct sockaddr
*)addr
;
1747 if(!is_valid_ether_addr(macaddr
->sa_data
))
1748 return -EADDRNOTAVAIL
;
1750 /* synchronized against open : rtnl_lock() held by caller */
1751 memcpy(dev
->dev_addr
, macaddr
->sa_data
, ETH_ALEN
);
1753 if (netif_running(dev
)) {
1754 spin_lock_bh(&dev
->xmit_lock
);
1755 spin_lock_irq(&np
->lock
);
1757 /* stop rx engine */
1760 /* set mac address */
1761 nv_copy_mac_to_hw(dev
);
1763 /* restart rx engine */
1765 spin_unlock_irq(&np
->lock
);
1766 spin_unlock_bh(&dev
->xmit_lock
);
1768 nv_copy_mac_to_hw(dev
);
1774 * nv_set_multicast: dev->set_multicast function
1775 * Called with dev->xmit_lock held.
1777 static void nv_set_multicast(struct net_device
*dev
)
1779 struct fe_priv
*np
= netdev_priv(dev
);
1780 u8 __iomem
*base
= get_hwbase(dev
);
1785 memset(addr
, 0, sizeof(addr
));
1786 memset(mask
, 0, sizeof(mask
));
1788 if (dev
->flags
& IFF_PROMISC
) {
1789 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n", dev
->name
);
1790 pff
= NVREG_PFF_PROMISC
;
1792 pff
= NVREG_PFF_MYADDR
;
1794 if (dev
->flags
& IFF_ALLMULTI
|| dev
->mc_list
) {
1798 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
1799 if (dev
->flags
& IFF_ALLMULTI
) {
1800 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
1802 struct dev_mc_list
*walk
;
1804 walk
= dev
->mc_list
;
1805 while (walk
!= NULL
) {
1807 a
= le32_to_cpu(*(u32
*) walk
->dmi_addr
);
1808 b
= le16_to_cpu(*(u16
*) (&walk
->dmi_addr
[4]));
1816 addr
[0] = alwaysOn
[0];
1817 addr
[1] = alwaysOn
[1];
1818 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
1819 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
1822 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
1823 pff
|= NVREG_PFF_ALWAYS
;
1824 spin_lock_irq(&np
->lock
);
1826 writel(addr
[0], base
+ NvRegMulticastAddrA
);
1827 writel(addr
[1], base
+ NvRegMulticastAddrB
);
1828 writel(mask
[0], base
+ NvRegMulticastMaskA
);
1829 writel(mask
[1], base
+ NvRegMulticastMaskB
);
1830 writel(pff
, base
+ NvRegPacketFilterFlags
);
1831 dprintk(KERN_INFO
"%s: reconfiguration for multicast lists.\n",
1834 spin_unlock_irq(&np
->lock
);
1838 * nv_update_linkspeed: Setup the MAC according to the link partner
1839 * @dev: Network device to be configured
1841 * The function queries the PHY and checks if there is a link partner.
1842 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
1843 * set to 10 MBit HD.
1845 * The function returns 0 if there is no link partner and 1 if there is
1846 * a good link partner.
1848 static int nv_update_linkspeed(struct net_device
*dev
)
1850 struct fe_priv
*np
= netdev_priv(dev
);
1851 u8 __iomem
*base
= get_hwbase(dev
);
1853 int newls
= np
->linkspeed
;
1854 int newdup
= np
->duplex
;
1857 u32 control_1000
, status_1000
, phyreg
;
1859 /* BMSR_LSTATUS is latched, read it twice:
1860 * we want the current value.
1862 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1863 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1865 if (!(mii_status
& BMSR_LSTATUS
)) {
1866 dprintk(KERN_DEBUG
"%s: no link detected by phy - falling back to 10HD.\n",
1868 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1874 if (np
->autoneg
== 0) {
1875 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1876 dev
->name
, np
->fixed_mode
);
1877 if (np
->fixed_mode
& LPA_100FULL
) {
1878 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1880 } else if (np
->fixed_mode
& LPA_100HALF
) {
1881 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1883 } else if (np
->fixed_mode
& LPA_10FULL
) {
1884 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1887 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1893 /* check auto negotiation is complete */
1894 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
1895 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1896 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1899 dprintk(KERN_DEBUG
"%s: autoneg not completed - falling back to 10HD.\n", dev
->name
);
1904 if (np
->gigabit
== PHY_GIGABIT
) {
1905 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
1906 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_SR
, MII_READ
);
1908 if ((control_1000
& ADVERTISE_1000FULL
) &&
1909 (status_1000
& LPA_1000FULL
)) {
1910 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: GBit ethernet detected.\n",
1912 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
1918 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1919 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
1920 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1921 dev
->name
, adv
, lpa
);
1923 /* FIXME: handle parallel detection properly */
1925 if (lpa
& LPA_100FULL
) {
1926 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1928 } else if (lpa
& LPA_100HALF
) {
1929 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1931 } else if (lpa
& LPA_10FULL
) {
1932 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1934 } else if (lpa
& LPA_10HALF
) {
1935 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1938 dprintk(KERN_DEBUG
"%s: bad ability %04x - falling back to 10HD.\n", dev
->name
, lpa
);
1939 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1944 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
1947 dprintk(KERN_INFO
"%s: changing link setting from %d/%d to %d/%d.\n",
1948 dev
->name
, np
->linkspeed
, np
->duplex
, newls
, newdup
);
1950 np
->duplex
= newdup
;
1951 np
->linkspeed
= newls
;
1953 if (np
->gigabit
== PHY_GIGABIT
) {
1954 phyreg
= readl(base
+ NvRegRandomSeed
);
1955 phyreg
&= ~(0x3FF00);
1956 if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
)
1957 phyreg
|= NVREG_RNDSEED_FORCE3
;
1958 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
)
1959 phyreg
|= NVREG_RNDSEED_FORCE2
;
1960 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
1961 phyreg
|= NVREG_RNDSEED_FORCE
;
1962 writel(phyreg
, base
+ NvRegRandomSeed
);
1965 phyreg
= readl(base
+ NvRegPhyInterface
);
1966 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
1967 if (np
->duplex
== 0)
1969 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
1971 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
1973 writel(phyreg
, base
+ NvRegPhyInterface
);
1975 writel(NVREG_MISC1_FORCE
| ( np
->duplex
? 0 : NVREG_MISC1_HD
),
1978 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1984 static void nv_linkchange(struct net_device
*dev
)
1986 if (nv_update_linkspeed(dev
)) {
1987 if (!netif_carrier_ok(dev
)) {
1988 netif_carrier_on(dev
);
1989 printk(KERN_INFO
"%s: link up.\n", dev
->name
);
1993 if (netif_carrier_ok(dev
)) {
1994 netif_carrier_off(dev
);
1995 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
2001 static void nv_link_irq(struct net_device
*dev
)
2003 u8 __iomem
*base
= get_hwbase(dev
);
2006 miistat
= readl(base
+ NvRegMIIStatus
);
2007 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
2008 dprintk(KERN_INFO
"%s: link change irq, status 0x%x.\n", dev
->name
, miistat
);
2010 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
2012 dprintk(KERN_DEBUG
"%s: link change notification done.\n", dev
->name
);
2015 static irqreturn_t
nv_nic_irq(int foo
, void *data
, struct pt_regs
*regs
)
2017 struct net_device
*dev
= (struct net_device
*) data
;
2018 struct fe_priv
*np
= netdev_priv(dev
);
2019 u8 __iomem
*base
= get_hwbase(dev
);
2023 dprintk(KERN_DEBUG
"%s: nv_nic_irq\n", dev
->name
);
2026 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
2027 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
2028 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
2030 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
2031 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
2034 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
2035 if (!(events
& np
->irqmask
))
2038 spin_lock(&np
->lock
);
2040 spin_unlock(&np
->lock
);
2043 if (nv_alloc_rx(dev
)) {
2044 spin_lock(&np
->lock
);
2045 if (!np
->in_shutdown
)
2046 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2047 spin_unlock(&np
->lock
);
2050 if (events
& NVREG_IRQ_LINK
) {
2051 spin_lock(&np
->lock
);
2053 spin_unlock(&np
->lock
);
2055 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
2056 spin_lock(&np
->lock
);
2058 spin_unlock(&np
->lock
);
2059 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
2061 if (events
& (NVREG_IRQ_TX_ERR
)) {
2062 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
2065 if (events
& (NVREG_IRQ_UNKNOWN
)) {
2066 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
2069 if (i
> max_interrupt_work
) {
2070 spin_lock(&np
->lock
);
2071 /* disable interrupts on the nic */
2072 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
2073 writel(0, base
+ NvRegIrqMask
);
2075 writel(np
->irqmask
, base
+ NvRegIrqMask
);
2078 if (!np
->in_shutdown
) {
2079 np
->nic_poll_irq
= np
->irqmask
;
2080 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2082 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq.\n", dev
->name
, i
);
2083 spin_unlock(&np
->lock
);
2088 dprintk(KERN_DEBUG
"%s: nv_nic_irq completed\n", dev
->name
);
2090 return IRQ_RETVAL(i
);
2093 static irqreturn_t
nv_nic_irq_tx(int foo
, void *data
, struct pt_regs
*regs
)
2095 struct net_device
*dev
= (struct net_device
*) data
;
2096 struct fe_priv
*np
= netdev_priv(dev
);
2097 u8 __iomem
*base
= get_hwbase(dev
);
2101 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx\n", dev
->name
);
2104 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_TX_ALL
;
2105 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegMSIXIrqStatus
);
2107 dprintk(KERN_DEBUG
"%s: tx irq: %08x\n", dev
->name
, events
);
2108 if (!(events
& np
->irqmask
))
2111 spin_lock(&np
->lock
);
2113 spin_unlock(&np
->lock
);
2115 if (events
& (NVREG_IRQ_TX_ERR
)) {
2116 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
2119 if (i
> max_interrupt_work
) {
2120 spin_lock(&np
->lock
);
2121 /* disable interrupts on the nic */
2122 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegIrqMask
);
2125 if (!np
->in_shutdown
) {
2126 np
->nic_poll_irq
|= NVREG_IRQ_TX_ALL
;
2127 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2129 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev
->name
, i
);
2130 spin_unlock(&np
->lock
);
2135 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx completed\n", dev
->name
);
2137 return IRQ_RETVAL(i
);
2140 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
, struct pt_regs
*regs
)
2142 struct net_device
*dev
= (struct net_device
*) data
;
2143 struct fe_priv
*np
= netdev_priv(dev
);
2144 u8 __iomem
*base
= get_hwbase(dev
);
2148 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx\n", dev
->name
);
2151 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
2152 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegMSIXIrqStatus
);
2154 dprintk(KERN_DEBUG
"%s: rx irq: %08x\n", dev
->name
, events
);
2155 if (!(events
& np
->irqmask
))
2159 if (nv_alloc_rx(dev
)) {
2160 spin_lock(&np
->lock
);
2161 if (!np
->in_shutdown
)
2162 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2163 spin_unlock(&np
->lock
);
2166 if (i
> max_interrupt_work
) {
2167 spin_lock(&np
->lock
);
2168 /* disable interrupts on the nic */
2169 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
2172 if (!np
->in_shutdown
) {
2173 np
->nic_poll_irq
|= NVREG_IRQ_RX_ALL
;
2174 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2176 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev
->name
, i
);
2177 spin_unlock(&np
->lock
);
2182 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx completed\n", dev
->name
);
2184 return IRQ_RETVAL(i
);
2187 static irqreturn_t
nv_nic_irq_other(int foo
, void *data
, struct pt_regs
*regs
)
2189 struct net_device
*dev
= (struct net_device
*) data
;
2190 struct fe_priv
*np
= netdev_priv(dev
);
2191 u8 __iomem
*base
= get_hwbase(dev
);
2195 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other\n", dev
->name
);
2198 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_OTHER
;
2199 writel(NVREG_IRQ_OTHER
, base
+ NvRegMSIXIrqStatus
);
2201 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
2202 if (!(events
& np
->irqmask
))
2205 if (events
& NVREG_IRQ_LINK
) {
2206 spin_lock(&np
->lock
);
2208 spin_unlock(&np
->lock
);
2210 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
2211 spin_lock(&np
->lock
);
2213 spin_unlock(&np
->lock
);
2214 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
2216 if (events
& (NVREG_IRQ_UNKNOWN
)) {
2217 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
2220 if (i
> max_interrupt_work
) {
2221 spin_lock(&np
->lock
);
2222 /* disable interrupts on the nic */
2223 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
2226 if (!np
->in_shutdown
) {
2227 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
2228 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2230 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_other.\n", dev
->name
, i
);
2231 spin_unlock(&np
->lock
);
2236 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other completed\n", dev
->name
);
2238 return IRQ_RETVAL(i
);
2241 static void nv_do_nic_poll(unsigned long data
)
2243 struct net_device
*dev
= (struct net_device
*) data
;
2244 struct fe_priv
*np
= netdev_priv(dev
);
2245 u8 __iomem
*base
= get_hwbase(dev
);
2249 * First disable irq(s) and then
2250 * reenable interrupts on the nic, we have to do this before calling
2251 * nv_nic_irq because that may decide to do otherwise
2254 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
2255 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
2256 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1))) {
2257 disable_irq(dev
->irq
);
2260 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
2261 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
2262 mask
|= NVREG_IRQ_RX_ALL
;
2264 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
2265 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
2266 mask
|= NVREG_IRQ_TX_ALL
;
2268 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
2269 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
2270 mask
|= NVREG_IRQ_OTHER
;
2273 np
->nic_poll_irq
= 0;
2275 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2277 writel(mask
, base
+ NvRegIrqMask
);
2280 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
2281 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
2282 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1))) {
2283 nv_nic_irq((int) 0, (void *) data
, (struct pt_regs
*) NULL
);
2284 enable_irq(dev
->irq
);
2286 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
2287 nv_nic_irq_rx((int) 0, (void *) data
, (struct pt_regs
*) NULL
);
2288 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
2290 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
2291 nv_nic_irq_tx((int) 0, (void *) data
, (struct pt_regs
*) NULL
);
2292 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
2294 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
2295 nv_nic_irq_other((int) 0, (void *) data
, (struct pt_regs
*) NULL
);
2296 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
2301 #ifdef CONFIG_NET_POLL_CONTROLLER
2302 static void nv_poll_controller(struct net_device
*dev
)
2304 nv_do_nic_poll((unsigned long) dev
);
2308 static void nv_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
2310 struct fe_priv
*np
= netdev_priv(dev
);
2311 strcpy(info
->driver
, "forcedeth");
2312 strcpy(info
->version
, FORCEDETH_VERSION
);
2313 strcpy(info
->bus_info
, pci_name(np
->pci_dev
));
2316 static void nv_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
2318 struct fe_priv
*np
= netdev_priv(dev
);
2319 wolinfo
->supported
= WAKE_MAGIC
;
2321 spin_lock_irq(&np
->lock
);
2323 wolinfo
->wolopts
= WAKE_MAGIC
;
2324 spin_unlock_irq(&np
->lock
);
2327 static int nv_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
2329 struct fe_priv
*np
= netdev_priv(dev
);
2330 u8 __iomem
*base
= get_hwbase(dev
);
2332 spin_lock_irq(&np
->lock
);
2333 if (wolinfo
->wolopts
== 0) {
2334 writel(0, base
+ NvRegWakeUpFlags
);
2337 if (wolinfo
->wolopts
& WAKE_MAGIC
) {
2338 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
2341 spin_unlock_irq(&np
->lock
);
2345 static int nv_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2347 struct fe_priv
*np
= netdev_priv(dev
);
2350 spin_lock_irq(&np
->lock
);
2351 ecmd
->port
= PORT_MII
;
2352 if (!netif_running(dev
)) {
2353 /* We do not track link speed / duplex setting if the
2354 * interface is disabled. Force a link check */
2355 nv_update_linkspeed(dev
);
2357 switch(np
->linkspeed
& (NVREG_LINKSPEED_MASK
)) {
2358 case NVREG_LINKSPEED_10
:
2359 ecmd
->speed
= SPEED_10
;
2361 case NVREG_LINKSPEED_100
:
2362 ecmd
->speed
= SPEED_100
;
2364 case NVREG_LINKSPEED_1000
:
2365 ecmd
->speed
= SPEED_1000
;
2368 ecmd
->duplex
= DUPLEX_HALF
;
2370 ecmd
->duplex
= DUPLEX_FULL
;
2372 ecmd
->autoneg
= np
->autoneg
;
2374 ecmd
->advertising
= ADVERTISED_MII
;
2376 ecmd
->advertising
|= ADVERTISED_Autoneg
;
2377 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
2379 adv
= np
->fixed_mode
;
2381 if (adv
& ADVERTISE_10HALF
)
2382 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
2383 if (adv
& ADVERTISE_10FULL
)
2384 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
2385 if (adv
& ADVERTISE_100HALF
)
2386 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
2387 if (adv
& ADVERTISE_100FULL
)
2388 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
2389 if (np
->autoneg
&& np
->gigabit
== PHY_GIGABIT
) {
2390 adv
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
2391 if (adv
& ADVERTISE_1000FULL
)
2392 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
2395 ecmd
->supported
= (SUPPORTED_Autoneg
|
2396 SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
2397 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
2399 if (np
->gigabit
== PHY_GIGABIT
)
2400 ecmd
->supported
|= SUPPORTED_1000baseT_Full
;
2402 ecmd
->phy_address
= np
->phyaddr
;
2403 ecmd
->transceiver
= XCVR_EXTERNAL
;
2405 /* ignore maxtxpkt, maxrxpkt for now */
2406 spin_unlock_irq(&np
->lock
);
2410 static int nv_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2412 struct fe_priv
*np
= netdev_priv(dev
);
2414 if (ecmd
->port
!= PORT_MII
)
2416 if (ecmd
->transceiver
!= XCVR_EXTERNAL
)
2418 if (ecmd
->phy_address
!= np
->phyaddr
) {
2419 /* TODO: support switching between multiple phys. Should be
2420 * trivial, but not enabled due to lack of test hardware. */
2423 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2426 mask
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
2427 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
2428 if (np
->gigabit
== PHY_GIGABIT
)
2429 mask
|= ADVERTISED_1000baseT_Full
;
2431 if ((ecmd
->advertising
& mask
) == 0)
2434 } else if (ecmd
->autoneg
== AUTONEG_DISABLE
) {
2435 /* Note: autonegotiation disable, speed 1000 intentionally
2436 * forbidden - noone should need that. */
2438 if (ecmd
->speed
!= SPEED_10
&& ecmd
->speed
!= SPEED_100
)
2440 if (ecmd
->duplex
!= DUPLEX_HALF
&& ecmd
->duplex
!= DUPLEX_FULL
)
2446 spin_lock_irq(&np
->lock
);
2447 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2452 /* advertise only what has been requested */
2453 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
2454 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
);
2455 if (ecmd
->advertising
& ADVERTISED_10baseT_Half
)
2456 adv
|= ADVERTISE_10HALF
;
2457 if (ecmd
->advertising
& ADVERTISED_10baseT_Full
)
2458 adv
|= ADVERTISE_10FULL
;
2459 if (ecmd
->advertising
& ADVERTISED_100baseT_Half
)
2460 adv
|= ADVERTISE_100HALF
;
2461 if (ecmd
->advertising
& ADVERTISED_100baseT_Full
)
2462 adv
|= ADVERTISE_100FULL
;
2463 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
2465 if (np
->gigabit
== PHY_GIGABIT
) {
2466 adv
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
2467 adv
&= ~ADVERTISE_1000FULL
;
2468 if (ecmd
->advertising
& ADVERTISED_1000baseT_Full
)
2469 adv
|= ADVERTISE_1000FULL
;
2470 mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, adv
);
2473 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
2474 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
2475 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
2482 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
2483 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
);
2484 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_HALF
)
2485 adv
|= ADVERTISE_10HALF
;
2486 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_FULL
)
2487 adv
|= ADVERTISE_10FULL
;
2488 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_HALF
)
2489 adv
|= ADVERTISE_100HALF
;
2490 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_FULL
)
2491 adv
|= ADVERTISE_100FULL
;
2492 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
2493 np
->fixed_mode
= adv
;
2495 if (np
->gigabit
== PHY_GIGABIT
) {
2496 adv
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
2497 adv
&= ~ADVERTISE_1000FULL
;
2498 mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, adv
);
2501 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
2502 bmcr
|= ~(BMCR_ANENABLE
|BMCR_SPEED100
|BMCR_FULLDPLX
);
2503 if (adv
& (ADVERTISE_10FULL
|ADVERTISE_100FULL
))
2504 bmcr
|= BMCR_FULLDPLX
;
2505 if (adv
& (ADVERTISE_100HALF
|ADVERTISE_100FULL
))
2506 bmcr
|= BMCR_SPEED100
;
2507 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
2509 if (netif_running(dev
)) {
2510 /* Wait a bit and then reconfigure the nic. */
2515 spin_unlock_irq(&np
->lock
);
2520 #define FORCEDETH_REGS_VER 1
2522 static int nv_get_regs_len(struct net_device
*dev
)
2524 struct fe_priv
*np
= netdev_priv(dev
);
2525 return np
->register_size
;
2528 static void nv_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *buf
)
2530 struct fe_priv
*np
= netdev_priv(dev
);
2531 u8 __iomem
*base
= get_hwbase(dev
);
2535 regs
->version
= FORCEDETH_REGS_VER
;
2536 spin_lock_irq(&np
->lock
);
2537 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
2538 rbuf
[i
] = readl(base
+ i
*sizeof(u32
));
2539 spin_unlock_irq(&np
->lock
);
2542 static int nv_nway_reset(struct net_device
*dev
)
2544 struct fe_priv
*np
= netdev_priv(dev
);
2547 spin_lock_irq(&np
->lock
);
2551 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
2552 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
2553 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
2559 spin_unlock_irq(&np
->lock
);
2564 static struct ethtool_ops ops
= {
2565 .get_drvinfo
= nv_get_drvinfo
,
2566 .get_link
= ethtool_op_get_link
,
2567 .get_wol
= nv_get_wol
,
2568 .set_wol
= nv_set_wol
,
2569 .get_settings
= nv_get_settings
,
2570 .set_settings
= nv_set_settings
,
2571 .get_regs_len
= nv_get_regs_len
,
2572 .get_regs
= nv_get_regs
,
2573 .nway_reset
= nv_nway_reset
,
2574 .get_perm_addr
= ethtool_op_get_perm_addr
,
2577 static void nv_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
2579 struct fe_priv
*np
= get_nvpriv(dev
);
2581 spin_lock_irq(&np
->lock
);
2583 /* save vlan group */
2587 /* enable vlan on MAC */
2588 np
->txrxctl_bits
|= NVREG_TXRXCTL_VLANSTRIP
| NVREG_TXRXCTL_VLANINS
;
2590 /* disable vlan on MAC */
2591 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANSTRIP
;
2592 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANINS
;
2595 writel(np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2597 spin_unlock_irq(&np
->lock
);
2600 static void nv_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
2605 static void set_msix_vector_map(struct net_device
*dev
, u32 vector
, u32 irqmask
)
2607 u8 __iomem
*base
= get_hwbase(dev
);
2611 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2612 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2613 * the remaining 8 interrupts.
2615 for (i
= 0; i
< 8; i
++) {
2616 if ((irqmask
>> i
) & 0x1) {
2617 msixmap
|= vector
<< (i
<< 2);
2620 writel(readl(base
+ NvRegMSIXMap0
) | msixmap
, base
+ NvRegMSIXMap0
);
2623 for (i
= 0; i
< 8; i
++) {
2624 if ((irqmask
>> (i
+ 8)) & 0x1) {
2625 msixmap
|= vector
<< (i
<< 2);
2628 writel(readl(base
+ NvRegMSIXMap1
) | msixmap
, base
+ NvRegMSIXMap1
);
2631 static int nv_open(struct net_device
*dev
)
2633 struct fe_priv
*np
= netdev_priv(dev
);
2634 u8 __iomem
*base
= get_hwbase(dev
);
2638 dprintk(KERN_DEBUG
"nv_open: begin\n");
2640 /* 1) erase previous misconfiguration */
2641 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
2643 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2644 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
2645 writel(0, base
+ NvRegMulticastAddrB
);
2646 writel(0, base
+ NvRegMulticastMaskA
);
2647 writel(0, base
+ NvRegMulticastMaskB
);
2648 writel(0, base
+ NvRegPacketFilterFlags
);
2650 writel(0, base
+ NvRegTransmitterControl
);
2651 writel(0, base
+ NvRegReceiverControl
);
2653 writel(0, base
+ NvRegAdapterControl
);
2655 /* 2) initialize descriptor rings */
2657 oom
= nv_init_ring(dev
);
2659 writel(0, base
+ NvRegLinkSpeed
);
2660 writel(0, base
+ NvRegUnknownTransmitterReg
);
2662 writel(0, base
+ NvRegUnknownSetupReg6
);
2664 np
->in_shutdown
= 0;
2666 /* 3) set mac address */
2667 nv_copy_mac_to_hw(dev
);
2669 /* 4) give hw rings */
2670 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
2671 writel( ((RX_RING
-1) << NVREG_RINGSZ_RXSHIFT
) + ((TX_RING
-1) << NVREG_RINGSZ_TXSHIFT
),
2672 base
+ NvRegRingSizes
);
2674 /* 5) continue setup */
2675 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
2676 writel(NVREG_UNKSETUP3_VAL1
, base
+ NvRegUnknownSetupReg3
);
2677 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
2678 writel(np
->vlanctl_bits
, base
+ NvRegVlanControl
);
2680 writel(NVREG_TXRXCTL_BIT1
|np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
2681 reg_delay(dev
, NvRegUnknownSetupReg5
, NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
2682 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
,
2683 KERN_INFO
"open: SetupReg5, Bit 31 remained off\n");
2685 writel(0, base
+ NvRegUnknownSetupReg4
);
2686 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
2687 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
2689 /* 6) continue setup */
2690 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
2691 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
2692 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
2693 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
2695 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
2696 get_random_bytes(&i
, sizeof(i
));
2697 writel(NVREG_RNDSEED_FORCE
| (i
&NVREG_RNDSEED_MASK
), base
+ NvRegRandomSeed
);
2698 writel(NVREG_UNKSETUP1_VAL
, base
+ NvRegUnknownSetupReg1
);
2699 writel(NVREG_UNKSETUP2_VAL
, base
+ NvRegUnknownSetupReg2
);
2700 if (poll_interval
== -1) {
2701 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
)
2702 writel(NVREG_POLL_DEFAULT_THROUGHPUT
, base
+ NvRegPollingInterval
);
2704 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
2707 writel(poll_interval
& 0xFFFF, base
+ NvRegPollingInterval
);
2708 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
2709 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
2710 base
+ NvRegAdapterControl
);
2711 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
2712 writel(NVREG_UNKSETUP4_VAL
, base
+ NvRegUnknownSetupReg4
);
2713 writel(NVREG_WAKEUPFLAGS_VAL
, base
+ NvRegWakeUpFlags
);
2715 i
= readl(base
+ NvRegPowerState
);
2716 if ( (i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
2717 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
2721 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
2723 writel(0, base
+ NvRegIrqMask
);
2725 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
2726 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
2729 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) {
2730 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
2731 np
->msi_x_entry
[i
].entry
= i
;
2733 if ((ret
= pci_enable_msix(np
->pci_dev
, np
->msi_x_entry
, (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
))) == 0) {
2734 np
->msi_flags
|= NV_MSI_X_ENABLED
;
2735 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
) {
2736 /* Request irq for rx handling */
2737 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, &nv_nic_irq_rx
, SA_SHIRQ
, dev
->name
, dev
) != 0) {
2738 printk(KERN_INFO
"forcedeth: request_irq failed for rx %d\n", ret
);
2739 pci_disable_msix(np
->pci_dev
);
2740 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2743 /* Request irq for tx handling */
2744 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, &nv_nic_irq_tx
, SA_SHIRQ
, dev
->name
, dev
) != 0) {
2745 printk(KERN_INFO
"forcedeth: request_irq failed for tx %d\n", ret
);
2746 pci_disable_msix(np
->pci_dev
);
2747 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2750 /* Request irq for link and timer handling */
2751 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
, &nv_nic_irq_other
, SA_SHIRQ
, dev
->name
, dev
) != 0) {
2752 printk(KERN_INFO
"forcedeth: request_irq failed for link %d\n", ret
);
2753 pci_disable_msix(np
->pci_dev
);
2754 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2758 /* map interrupts to their respective vector */
2759 writel(0, base
+ NvRegMSIXMap0
);
2760 writel(0, base
+ NvRegMSIXMap1
);
2761 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_RX
, NVREG_IRQ_RX_ALL
);
2762 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_TX
, NVREG_IRQ_TX_ALL
);
2763 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_OTHER
, NVREG_IRQ_OTHER
);
2765 /* Request irq for all interrupts */
2766 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
, &nv_nic_irq
, SA_SHIRQ
, dev
->name
, dev
) != 0) {
2767 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
2768 pci_disable_msix(np
->pci_dev
);
2769 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2773 /* map interrupts to vector 0 */
2774 writel(0, base
+ NvRegMSIXMap0
);
2775 writel(0, base
+ NvRegMSIXMap1
);
2779 if (ret
!= 0 && np
->msi_flags
& NV_MSI_CAPABLE
) {
2780 if ((ret
= pci_enable_msi(np
->pci_dev
)) == 0) {
2781 np
->msi_flags
|= NV_MSI_ENABLED
;
2782 if (request_irq(np
->pci_dev
->irq
, &nv_nic_irq
, SA_SHIRQ
, dev
->name
, dev
) != 0) {
2783 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
2784 pci_disable_msi(np
->pci_dev
);
2785 np
->msi_flags
&= ~NV_MSI_ENABLED
;
2789 /* map interrupts to vector 0 */
2790 writel(0, base
+ NvRegMSIMap0
);
2791 writel(0, base
+ NvRegMSIMap1
);
2792 /* enable msi vector 0 */
2793 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
2797 if (request_irq(np
->pci_dev
->irq
, &nv_nic_irq
, SA_SHIRQ
, dev
->name
, dev
) != 0)
2801 /* ask for interrupts */
2802 writel(np
->irqmask
, base
+ NvRegIrqMask
);
2804 spin_lock_irq(&np
->lock
);
2805 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
2806 writel(0, base
+ NvRegMulticastAddrB
);
2807 writel(0, base
+ NvRegMulticastMaskA
);
2808 writel(0, base
+ NvRegMulticastMaskB
);
2809 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
2810 /* One manual link speed update: Interrupts are enabled, future link
2811 * speed changes cause interrupts and are handled by nv_link_irq().
2815 miistat
= readl(base
+ NvRegMIIStatus
);
2816 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
2817 dprintk(KERN_INFO
"startup: got 0x%08x.\n", miistat
);
2819 /* set linkspeed to invalid value, thus force nv_update_linkspeed
2822 ret
= nv_update_linkspeed(dev
);
2825 netif_start_queue(dev
);
2827 netif_carrier_on(dev
);
2829 printk("%s: no link during initialization.\n", dev
->name
);
2830 netif_carrier_off(dev
);
2833 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2834 spin_unlock_irq(&np
->lock
);
2842 static int nv_close(struct net_device
*dev
)
2844 struct fe_priv
*np
= netdev_priv(dev
);
2848 spin_lock_irq(&np
->lock
);
2849 np
->in_shutdown
= 1;
2850 spin_unlock_irq(&np
->lock
);
2851 synchronize_irq(dev
->irq
);
2853 del_timer_sync(&np
->oom_kick
);
2854 del_timer_sync(&np
->nic_poll
);
2856 netif_stop_queue(dev
);
2857 spin_lock_irq(&np
->lock
);
2862 /* disable interrupts on the nic or we will lock up */
2863 base
= get_hwbase(dev
);
2864 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
2865 writel(np
->irqmask
, base
+ NvRegIrqMask
);
2867 if (np
->msi_flags
& NV_MSI_ENABLED
)
2868 writel(0, base
+ NvRegMSIIrqMask
);
2869 writel(0, base
+ NvRegIrqMask
);
2872 dprintk(KERN_INFO
"%s: Irqmask is zero again\n", dev
->name
);
2874 spin_unlock_irq(&np
->lock
);
2876 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
2877 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
2878 free_irq(np
->msi_x_entry
[i
].vector
, dev
);
2880 pci_disable_msix(np
->pci_dev
);
2881 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2883 free_irq(np
->pci_dev
->irq
, dev
);
2884 if (np
->msi_flags
& NV_MSI_ENABLED
) {
2885 pci_disable_msi(np
->pci_dev
);
2886 np
->msi_flags
&= ~NV_MSI_ENABLED
;
2895 /* special op: write back the misordered MAC address - otherwise
2896 * the next nv_probe would see a wrong address.
2898 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
2899 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
2901 /* FIXME: power down nic */
2906 static int __devinit
nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
2908 struct net_device
*dev
;
2915 dev
= alloc_etherdev(sizeof(struct fe_priv
));
2920 np
= netdev_priv(dev
);
2921 np
->pci_dev
= pci_dev
;
2922 spin_lock_init(&np
->lock
);
2923 SET_MODULE_OWNER(dev
);
2924 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
2926 init_timer(&np
->oom_kick
);
2927 np
->oom_kick
.data
= (unsigned long) dev
;
2928 np
->oom_kick
.function
= &nv_do_rx_refill
; /* timer handler */
2929 init_timer(&np
->nic_poll
);
2930 np
->nic_poll
.data
= (unsigned long) dev
;
2931 np
->nic_poll
.function
= &nv_do_nic_poll
; /* timer handler */
2933 err
= pci_enable_device(pci_dev
);
2935 printk(KERN_INFO
"forcedeth: pci_enable_dev failed (%d) for device %s\n",
2936 err
, pci_name(pci_dev
));
2940 pci_set_master(pci_dev
);
2942 err
= pci_request_regions(pci_dev
, DRV_NAME
);
2946 if (id
->driver_data
& (DEV_HAS_VLAN
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
))
2947 np
->register_size
= NV_PCI_REGSZ_VER2
;
2949 np
->register_size
= NV_PCI_REGSZ_VER1
;
2953 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
2954 dprintk(KERN_DEBUG
"%s: resource %d start %p len %ld flags 0x%08lx.\n",
2955 pci_name(pci_dev
), i
, (void*)pci_resource_start(pci_dev
, i
),
2956 pci_resource_len(pci_dev
, i
),
2957 pci_resource_flags(pci_dev
, i
));
2958 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
2959 pci_resource_len(pci_dev
, i
) >= np
->register_size
) {
2960 addr
= pci_resource_start(pci_dev
, i
);
2964 if (i
== DEVICE_COUNT_RESOURCE
) {
2965 printk(KERN_INFO
"forcedeth: Couldn't find register window for device %s.\n",
2970 /* copy of driver data */
2971 np
->driver_data
= id
->driver_data
;
2973 /* handle different descriptor versions */
2974 if (id
->driver_data
& DEV_HAS_HIGH_DMA
) {
2975 /* packet format 3: supports 40-bit addressing */
2976 np
->desc_ver
= DESC_VER_3
;
2977 if (pci_set_dma_mask(pci_dev
, DMA_39BIT_MASK
)) {
2978 printk(KERN_INFO
"forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2981 if (pci_set_consistent_dma_mask(pci_dev
, 0x0000007fffffffffULL
)) {
2982 printk(KERN_INFO
"forcedeth: 64-bit DMA (consistent) failed for device %s.\n",
2986 dev
->features
|= NETIF_F_HIGHDMA
;
2987 printk(KERN_INFO
"forcedeth: using HIGHDMA\n");
2990 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_3
;
2991 } else if (id
->driver_data
& DEV_HAS_LARGEDESC
) {
2992 /* packet format 2: supports jumbo frames */
2993 np
->desc_ver
= DESC_VER_2
;
2994 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_2
;
2996 /* original packet format */
2997 np
->desc_ver
= DESC_VER_1
;
2998 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_1
;
3001 np
->pkt_limit
= NV_PKTLIMIT_1
;
3002 if (id
->driver_data
& DEV_HAS_LARGEDESC
)
3003 np
->pkt_limit
= NV_PKTLIMIT_2
;
3005 if (id
->driver_data
& DEV_HAS_CHECKSUM
) {
3006 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
3007 dev
->features
|= NETIF_F_HW_CSUM
| NETIF_F_SG
;
3009 dev
->features
|= NETIF_F_TSO
;
3013 np
->vlanctl_bits
= 0;
3014 if (id
->driver_data
& DEV_HAS_VLAN
) {
3015 np
->vlanctl_bits
= NVREG_VLANCONTROL_ENABLE
;
3016 dev
->features
|= NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
;
3017 dev
->vlan_rx_register
= nv_vlan_rx_register
;
3018 dev
->vlan_rx_kill_vid
= nv_vlan_rx_kill_vid
;
3022 if ((id
->driver_data
& DEV_HAS_MSI
) && !disable_msi
) {
3023 np
->msi_flags
|= NV_MSI_CAPABLE
;
3025 if ((id
->driver_data
& DEV_HAS_MSI_X
) && !disable_msix
) {
3026 np
->msi_flags
|= NV_MSI_X_CAPABLE
;
3030 np
->base
= ioremap(addr
, np
->register_size
);
3033 dev
->base_addr
= (unsigned long)np
->base
;
3035 dev
->irq
= pci_dev
->irq
;
3037 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
3038 np
->rx_ring
.orig
= pci_alloc_consistent(pci_dev
,
3039 sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
),
3041 if (!np
->rx_ring
.orig
)
3043 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[RX_RING
];
3045 np
->rx_ring
.ex
= pci_alloc_consistent(pci_dev
,
3046 sizeof(struct ring_desc_ex
) * (RX_RING
+ TX_RING
),
3048 if (!np
->rx_ring
.ex
)
3050 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[RX_RING
];
3053 dev
->open
= nv_open
;
3054 dev
->stop
= nv_close
;
3055 dev
->hard_start_xmit
= nv_start_xmit
;
3056 dev
->get_stats
= nv_get_stats
;
3057 dev
->change_mtu
= nv_change_mtu
;
3058 dev
->set_mac_address
= nv_set_mac_address
;
3059 dev
->set_multicast_list
= nv_set_multicast
;
3060 #ifdef CONFIG_NET_POLL_CONTROLLER
3061 dev
->poll_controller
= nv_poll_controller
;
3063 SET_ETHTOOL_OPS(dev
, &ops
);
3064 dev
->tx_timeout
= nv_tx_timeout
;
3065 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
3067 pci_set_drvdata(pci_dev
, dev
);
3069 /* read the mac address */
3070 base
= get_hwbase(dev
);
3071 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
3072 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
3074 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
3075 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
3076 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
3077 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
3078 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
3079 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
3080 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3082 if (!is_valid_ether_addr(dev
->perm_addr
)) {
3084 * Bad mac address. At least one bios sets the mac address
3085 * to 01:23:45:67:89:ab
3087 printk(KERN_ERR
"%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
3089 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3090 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3091 printk(KERN_ERR
"Please complain to your hardware vendor. Switching to a random MAC.\n");
3092 dev
->dev_addr
[0] = 0x00;
3093 dev
->dev_addr
[1] = 0x00;
3094 dev
->dev_addr
[2] = 0x6c;
3095 get_random_bytes(&dev
->dev_addr
[3], 3);
3098 dprintk(KERN_DEBUG
"%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev
),
3099 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3100 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3103 writel(0, base
+ NvRegWakeUpFlags
);
3106 if (id
->driver_data
& DEV_HAS_POWER_CNTRL
) {
3108 pci_read_config_byte(pci_dev
, PCI_REVISION_ID
, &revision_id
);
3110 /* take phy and nic out of low power mode */
3111 powerstate
= readl(base
+ NvRegPowerState2
);
3112 powerstate
&= ~NVREG_POWERSTATE2_POWERUP_MASK
;
3113 if ((id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_12
||
3114 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_13
) &&
3115 revision_id
>= 0xA3)
3116 powerstate
|= NVREG_POWERSTATE2_POWERUP_REV_A3
;
3117 writel(powerstate
, base
+ NvRegPowerState2
);
3120 if (np
->desc_ver
== DESC_VER_1
) {
3121 np
->tx_flags
= NV_TX_VALID
;
3123 np
->tx_flags
= NV_TX2_VALID
;
3125 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
) {
3126 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
3127 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
3128 np
->msi_flags
|= 0x0003;
3130 np
->irqmask
= NVREG_IRQMASK_CPU
;
3131 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
3132 np
->msi_flags
|= 0x0001;
3135 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
3136 np
->irqmask
|= NVREG_IRQ_TIMER
;
3137 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
3138 dprintk(KERN_INFO
"%s: link timer on.\n", pci_name(pci_dev
));
3139 np
->need_linktimer
= 1;
3140 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3142 dprintk(KERN_INFO
"%s: link timer off.\n", pci_name(pci_dev
));
3143 np
->need_linktimer
= 0;
3146 /* find a suitable phy */
3147 for (i
= 1; i
<= 32; i
++) {
3149 int phyaddr
= i
& 0x1F;
3151 spin_lock_irq(&np
->lock
);
3152 id1
= mii_rw(dev
, phyaddr
, MII_PHYSID1
, MII_READ
);
3153 spin_unlock_irq(&np
->lock
);
3154 if (id1
< 0 || id1
== 0xffff)
3156 spin_lock_irq(&np
->lock
);
3157 id2
= mii_rw(dev
, phyaddr
, MII_PHYSID2
, MII_READ
);
3158 spin_unlock_irq(&np
->lock
);
3159 if (id2
< 0 || id2
== 0xffff)
3162 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
3163 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
3164 dprintk(KERN_DEBUG
"%s: open: Found PHY %04x:%04x at address %d.\n",
3165 pci_name(pci_dev
), id1
, id2
, phyaddr
);
3166 np
->phyaddr
= phyaddr
;
3167 np
->phy_oui
= id1
| id2
;
3171 printk(KERN_INFO
"%s: open: Could not find a valid PHY.\n",
3179 /* set default link speed settings */
3180 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3184 err
= register_netdev(dev
);
3186 printk(KERN_INFO
"forcedeth: unable to register netdev: %d\n", err
);
3189 printk(KERN_INFO
"%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
3190 dev
->name
, pci_dev
->subsystem_vendor
, pci_dev
->subsystem_device
,
3196 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
3197 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
),
3198 np
->rx_ring
.orig
, np
->ring_addr
);
3200 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (RX_RING
+ TX_RING
),
3201 np
->rx_ring
.ex
, np
->ring_addr
);
3202 pci_set_drvdata(pci_dev
, NULL
);
3204 iounmap(get_hwbase(dev
));
3206 pci_release_regions(pci_dev
);
3208 pci_disable_device(pci_dev
);
3215 static void __devexit
nv_remove(struct pci_dev
*pci_dev
)
3217 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
3218 struct fe_priv
*np
= netdev_priv(dev
);
3220 unregister_netdev(dev
);
3222 /* free all structures */
3223 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
3224 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
), np
->rx_ring
.orig
, np
->ring_addr
);
3226 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (RX_RING
+ TX_RING
), np
->rx_ring
.ex
, np
->ring_addr
);
3227 iounmap(get_hwbase(dev
));
3228 pci_release_regions(pci_dev
);
3229 pci_disable_device(pci_dev
);
3231 pci_set_drvdata(pci_dev
, NULL
);
3234 static struct pci_device_id pci_tbl
[] = {
3235 { /* nForce Ethernet Controller */
3236 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_1
),
3237 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
3239 { /* nForce2 Ethernet Controller */
3240 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_2
),
3241 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
3243 { /* nForce3 Ethernet Controller */
3244 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_3
),
3245 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
3247 { /* nForce3 Ethernet Controller */
3248 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_4
),
3249 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
3251 { /* nForce3 Ethernet Controller */
3252 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_5
),
3253 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
3255 { /* nForce3 Ethernet Controller */
3256 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_6
),
3257 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
3259 { /* nForce3 Ethernet Controller */
3260 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_7
),
3261 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
3263 { /* CK804 Ethernet Controller */
3264 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_8
),
3265 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
3267 { /* CK804 Ethernet Controller */
3268 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_9
),
3269 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
3271 { /* MCP04 Ethernet Controller */
3272 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_10
),
3273 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
3275 { /* MCP04 Ethernet Controller */
3276 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_11
),
3277 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
3279 { /* MCP51 Ethernet Controller */
3280 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_12
),
3281 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
,
3283 { /* MCP51 Ethernet Controller */
3284 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_13
),
3285 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
,
3287 { /* MCP55 Ethernet Controller */
3288 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_14
),
3289 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
,
3291 { /* MCP55 Ethernet Controller */
3292 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_15
),
3293 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
,
3298 static struct pci_driver driver
= {
3299 .name
= "forcedeth",
3300 .id_table
= pci_tbl
,
3302 .remove
= __devexit_p(nv_remove
),
3306 static int __init
init_nic(void)
3308 printk(KERN_INFO
"forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION
);
3309 return pci_module_init(&driver
);
3312 static void __exit
exit_nic(void)
3314 pci_unregister_driver(&driver
);
3317 module_param(max_interrupt_work
, int, 0);
3318 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
3319 module_param(optimization_mode
, int, 0);
3320 MODULE_PARM_DESC(optimization_mode
, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
3321 module_param(poll_interval
, int, 0);
3322 MODULE_PARM_DESC(poll_interval
, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
3323 module_param(disable_msi
, int, 0);
3324 MODULE_PARM_DESC(disable_msi
, "Disable MSI interrupts by setting to 1.");
3325 module_param(disable_msix
, int, 0);
3326 MODULE_PARM_DESC(disable_msix
, "Disable MSIX interrupts by setting to 1.");
3328 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
3329 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
3330 MODULE_LICENSE("GPL");
3332 MODULE_DEVICE_TABLE(pci
, pci_tbl
);
3334 module_init(init_nic
);
3335 module_exit(exit_nic
);