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[SCSI] mpt2sas: Update driver to MPI2 REV K headers.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / scsi / mpt2sas / mpi / mpi2_cnfg.h
blobab47c4679640be3042ce1fa239355cad438ef221
1 /*
2 * Copyright (c) 2000-2009 LSI Corporation.
3 *
4 *
5 * Name: mpi2_cnfg.h
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
8 *
9 * mpi2_cnfg.h Version: 02.00.11
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
18 * Added Manufacturing Page 11.
19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
20 * define.
21 * 06-26-07 02.00.02 Adding generic structure for product-specific
22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
23 * Rework of BIOS Page 2 configuration page.
24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
25 * forms.
26 * Added configuration pages IOC Page 8 and Driver
27 * Persistent Mapping Page 0.
28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
30 * RAID Physical Disk Pages 0 and 1, RAID Configuration
31 * Page 0).
32 * Added new value for AccessStatus field of SAS Device
33 * Page 0 (_SATA_NEEDS_INITIALIZATION).
34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
37 * NVDATA.
38 * Modified IOC Page 7 to use masks and added field for
39 * SASBroadcastPrimitiveMasks.
40 * Added MPI2_CONFIG_PAGE_BIOS_4.
41 * Added MPI2_CONFIG_PAGE_LOG_0.
42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
43 * Added SAS Device IDs.
44 * Updated Integrated RAID configuration pages including
45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
46 * Page 0.
47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
50 * Added missing MaxNumRoutedSasAddresses field to
51 * MPI2_CONFIG_PAGE_EXPANDER_0.
52 * Added SAS Port Page 0.
53 * Modified structure layout for
54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
58 * to 0x000000FF.
59 * Added two new values for the Physical Disk Coercion Size
60 * bits in the Flags field of Manufacturing Page 4.
61 * Added product-specific Manufacturing pages 16 to 31.
62 * Modified Flags bits for controlling write cache on SATA
63 * drives in IO Unit Page 1.
64 * Added new bit to AdditionalControlFlags of SAS IO Unit
65 * Page 1 to control Invalid Topology Correction.
66 * Added additional defines for RAID Volume Page 0
67 * VolumeStatusFlags field.
68 * Modified meaning of RAID Volume Page 0 VolumeSettings
69 * define for auto-configure of hot-swap drives.
70 * Added SupportedPhysDisks field to RAID Volume Page 1 and
71 * added related defines.
72 * Added PhysDiskAttributes field (and related defines) to
73 * RAID Physical Disk Page 0.
74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
75 * Added three new DiscoveryStatus bits for SAS IO Unit
76 * Page 0 and SAS Expander Page 0.
77 * Removed multiplexing information from SAS IO Unit pages.
78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
79 * Removed Zone Address Resolved bit from PhyInfo and from
80 * Expander Page 0 Flags field.
81 * Added two new AccessStatus values to SAS Device Page 0
82 * for indicating routing problems. Added 3 reserved words
83 * to this page.
84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
85 * Inserted missing reserved field into structure for IOC
86 * Page 6.
87 * Added more pending task bits to RAID Volume Page 0
88 * VolumeStatusFlags defines.
89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
91 * and SAS Expander Page 0 to flag a downstream initiator
92 * when in simplified routing mode.
93 * Removed SATA Init Failure defines for DiscoveryStatus
94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
96 * Added PortGroups, DmaGroup, and ControlGroup fields to
97 * SAS Device Page 0.
98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
99 * Unit Page 6.
100 * Added expander reduced functionality data to SAS
101 * Expander Page 0.
102 * Added SAS PHY Page 2 and SAS PHY Page 3.
103 * --------------------------------------------------------------------------
104 */
105
106 #ifndef MPI2_CNFG_H
107 #define MPI2_CNFG_H
108
109 /*****************************************************************************
110 * Configuration Page Header and defines
111 *****************************************************************************/
112
113 /* Config Page Header */
114 typedef struct _MPI2_CONFIG_PAGE_HEADER
115 {
116 U8 PageVersion; /* 0x00 */
117 U8 PageLength; /* 0x01 */
118 U8 PageNumber; /* 0x02 */
119 U8 PageType; /* 0x03 */
120 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
121 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
122
123 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
124 {
125 MPI2_CONFIG_PAGE_HEADER Struct;
126 U8 Bytes[4];
127 U16 Word16[2];
128 U32 Word32;
129 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
130 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
131
132 /* Extended Config Page Header */
133 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
134 {
135 U8 PageVersion; /* 0x00 */
136 U8 Reserved1; /* 0x01 */
137 U8 PageNumber; /* 0x02 */
138 U8 PageType; /* 0x03 */
139 U16 ExtPageLength; /* 0x04 */
140 U8 ExtPageType; /* 0x06 */
141 U8 Reserved2; /* 0x07 */
142 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
143 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
144 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
145
146 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
147 {
148 MPI2_CONFIG_PAGE_HEADER Struct;
149 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
150 U8 Bytes[8];
151 U16 Word16[4];
152 U32 Word32[2];
153 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
154 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
155
156
157 /* PageType field values */
158 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
159 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
160 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
161 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
162
163 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
164 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
165 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
166 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
167 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
168 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
169 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
170 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
171
172 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
173
174
175 /* ExtPageType field values */
176 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
177 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
178 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
179 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
180 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
181 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
182 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
183 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
184 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
185
186
187 /*****************************************************************************
188 * PageAddress defines
189 *****************************************************************************/
190
191 /* RAID Volume PageAddress format */
192 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
193 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
194 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
195
196 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
197
198
199 /* RAID Physical Disk PageAddress format */
200 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
201 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
202 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
203 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
204
205 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
206 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
207
208
209 /* SAS Expander PageAddress format */
210 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
211 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
212 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
213 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
214
215 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
216 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
217 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
218
219
220 /* SAS Device PageAddress format */
221 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
222 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
223 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
224
225 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
226
227
228 /* SAS PHY PageAddress format */
229 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
230 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
231 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
232
233 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
234 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
235
236
237 /* SAS Port PageAddress format */
238 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
239 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
240 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
241
242 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
243
244
245 /* SAS Enclosure PageAddress format */
246 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
247 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
248 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
249
250 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
251
252
253 /* RAID Configuration PageAddress format */
254 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
255 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
256 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
257 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
258
259 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
260
261
262 /* Driver Persistent Mapping PageAddress format */
263 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
264 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
265
266 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
267 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
268 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
269
270
271 /****************************************************************************
272 * Configuration messages
273 ****************************************************************************/
274
275 /* Configuration Request Message */
276 typedef struct _MPI2_CONFIG_REQUEST
277 {
278 U8 Action; /* 0x00 */
279 U8 SGLFlags; /* 0x01 */
280 U8 ChainOffset; /* 0x02 */
281 U8 Function; /* 0x03 */
282 U16 ExtPageLength; /* 0x04 */
283 U8 ExtPageType; /* 0x06 */
284 U8 MsgFlags; /* 0x07 */
285 U8 VP_ID; /* 0x08 */
286 U8 VF_ID; /* 0x09 */
287 U16 Reserved1; /* 0x0A */
288 U32 Reserved2; /* 0x0C */
289 U32 Reserved3; /* 0x10 */
290 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
291 U32 PageAddress; /* 0x18 */
292 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
293 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
294 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
295
296 /* values for the Action field */
297 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
298 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
299 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
300 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
301 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
302 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
303 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
304 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
305
306 /* values for SGLFlags field are in the SGL section of mpi2.h */
307
308
309 /* Config Reply Message */
310 typedef struct _MPI2_CONFIG_REPLY
311 {
312 U8 Action; /* 0x00 */
313 U8 SGLFlags; /* 0x01 */
314 U8 MsgLength; /* 0x02 */
315 U8 Function; /* 0x03 */
316 U16 ExtPageLength; /* 0x04 */
317 U8 ExtPageType; /* 0x06 */
318 U8 MsgFlags; /* 0x07 */
319 U8 VP_ID; /* 0x08 */
320 U8 VF_ID; /* 0x09 */
321 U16 Reserved1; /* 0x0A */
322 U16 Reserved2; /* 0x0C */
323 U16 IOCStatus; /* 0x0E */
324 U32 IOCLogInfo; /* 0x10 */
325 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
326 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
327 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
328
329
330
331 /*****************************************************************************
332 *
333 * C o n f i g u r a t i o n P a g e s
334 *
335 *****************************************************************************/
336
337 /****************************************************************************
338 * Manufacturing Config pages
339 ****************************************************************************/
340
341 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
342
343 /* SAS */
344 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
345 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
346 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
347 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
348 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
349 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
350 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
351
352
353 /* Manufacturing Page 0 */
354
355 typedef struct _MPI2_CONFIG_PAGE_MAN_0
356 {
357 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
358 U8 ChipName[16]; /* 0x04 */
359 U8 ChipRevision[8]; /* 0x14 */
360 U8 BoardName[16]; /* 0x1C */
361 U8 BoardAssembly[16]; /* 0x2C */
362 U8 BoardTracerNumber[16]; /* 0x3C */
363 } MPI2_CONFIG_PAGE_MAN_0,
364 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
365 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
366
367 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
368
369
370 /* Manufacturing Page 1 */
371
372 typedef struct _MPI2_CONFIG_PAGE_MAN_1
373 {
374 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
375 U8 VPD[256]; /* 0x04 */
376 } MPI2_CONFIG_PAGE_MAN_1,
377 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
378 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
379
380 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
381
382
383 typedef struct _MPI2_CHIP_REVISION_ID
384 {
385 U16 DeviceID; /* 0x00 */
386 U8 PCIRevisionID; /* 0x02 */
387 U8 Reserved; /* 0x03 */
388 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
389 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
390
391
392 /* Manufacturing Page 2 */
393
394 /*
395 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
396 * one and check Header.PageLength at runtime.
397 */
398 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
399 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
400 #endif
401
402 typedef struct _MPI2_CONFIG_PAGE_MAN_2
403 {
404 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
405 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
406 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
407 } MPI2_CONFIG_PAGE_MAN_2,
408 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
409 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
410
411 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
412
413
414 /* Manufacturing Page 3 */
415
416 /*
417 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
418 * one and check Header.PageLength at runtime.
419 */
420 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
421 #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
422 #endif
423
424 typedef struct _MPI2_CONFIG_PAGE_MAN_3
425 {
426 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
427 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
428 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
429 } MPI2_CONFIG_PAGE_MAN_3,
430 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
431 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
432
433 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
434
435
436 /* Manufacturing Page 4 */
437
438 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
439 {
440 U8 PowerSaveFlags; /* 0x00 */
441 U8 InternalOperationsSleepTime; /* 0x01 */
442 U8 InternalOperationsRunTime; /* 0x02 */
443 U8 HostIdleTime; /* 0x03 */
444 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
445 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
446 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
447
448 /* defines for the PowerSaveFlags field */
449 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
450 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
451 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
452 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
453
454 typedef struct _MPI2_CONFIG_PAGE_MAN_4
455 {
456 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
457 U32 Reserved1; /* 0x04 */
458 U32 Flags; /* 0x08 */
459 U8 InquirySize; /* 0x0C */
460 U8 Reserved2; /* 0x0D */
461 U16 Reserved3; /* 0x0E */
462 U8 InquiryData[56]; /* 0x10 */
463 U32 RAID0VolumeSettings; /* 0x48 */
464 U32 RAID1EVolumeSettings; /* 0x4C */
465 U32 RAID1VolumeSettings; /* 0x50 */
466 U32 RAID10VolumeSettings; /* 0x54 */
467 U32 Reserved4; /* 0x58 */
468 U32 Reserved5; /* 0x5C */
469 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
470 U8 MaxOCEDisks; /* 0x64 */
471 U8 ResyncRate; /* 0x65 */
472 U16 DataScrubDuration; /* 0x66 */
473 U8 MaxHotSpares; /* 0x68 */
474 U8 MaxPhysDisksPerVol; /* 0x69 */
475 U8 MaxPhysDisks; /* 0x6A */
476 U8 MaxVolumes; /* 0x6B */
477 } MPI2_CONFIG_PAGE_MAN_4,
478 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
479 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
480
481 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
482
483 /* Manufacturing Page 4 Flags field */
484 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
485 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
486
487 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
488 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
489 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
490
491 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
492 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
493 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
494 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
495 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
496
497 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
498 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
499 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
500 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
501
502 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
503 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
504 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
505 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
506 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
507 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
508 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
509 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
510
511
512 /* Manufacturing Page 5 */
513
514 /*
515 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
516 * one and check Header.PageLength or NumPhys at runtime.
517 */
518 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
519 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
520 #endif
521
522 typedef struct _MPI2_MANUFACTURING5_ENTRY
523 {
524 U64 WWID; /* 0x00 */
525 U64 DeviceName; /* 0x08 */
526 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
527 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
528
529 typedef struct _MPI2_CONFIG_PAGE_MAN_5
530 {
531 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
532 U8 NumPhys; /* 0x04 */
533 U8 Reserved1; /* 0x05 */
534 U16 Reserved2; /* 0x06 */
535 U32 Reserved3; /* 0x08 */
536 U32 Reserved4; /* 0x0C */
537 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
538 } MPI2_CONFIG_PAGE_MAN_5,
539 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
540 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
541
542 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
543
544
545 /* Manufacturing Page 6 */
546
547 typedef struct _MPI2_CONFIG_PAGE_MAN_6
548 {
549 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
550 U32 ProductSpecificInfo;/* 0x04 */
551 } MPI2_CONFIG_PAGE_MAN_6,
552 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
553 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
554
555 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
556
557
558 /* Manufacturing Page 7 */
559
560 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
561 {
562 U32 Pinout; /* 0x00 */
563 U8 Connector[16]; /* 0x04 */
564 U8 Location; /* 0x14 */
565 U8 Reserved1; /* 0x15 */
566 U16 Slot; /* 0x16 */
567 U32 Reserved2; /* 0x18 */
568 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
569 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
570
571 /* defines for the Pinout field */
572 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
573 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
574 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
575 #define MPI2_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
576 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
577 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
578 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
579 #define MPI2_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
580 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
581 #define MPI2_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
582
583 /* defines for the Location field */
584 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
585 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
586 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
587 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
588 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
589 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
590 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
591
592 /*
593 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
594 * one and check NumPhys at runtime.
595 */
596 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
597 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
598 #endif
599
600 typedef struct _MPI2_CONFIG_PAGE_MAN_7
601 {
602 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
603 U32 Reserved1; /* 0x04 */
604 U32 Reserved2; /* 0x08 */
605 U32 Flags; /* 0x0C */
606 U8 EnclosureName[16]; /* 0x10 */
607 U8 NumPhys; /* 0x20 */
608 U8 Reserved3; /* 0x21 */
609 U16 Reserved4; /* 0x22 */
610 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
611 } MPI2_CONFIG_PAGE_MAN_7,
612 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
613 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
614
615 #define MPI2_MANUFACTURING7_PAGEVERSION (0x00)
616
617 /* defines for the Flags field */
618 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
619
620
621 /*
622 * Generic structure to use for product-specific manufacturing pages
623 * (currently Manufacturing Page 8 through Manufacturing Page 31).
624 */
625
626 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
627 {
628 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
629 U32 ProductSpecificInfo;/* 0x04 */
630 } MPI2_CONFIG_PAGE_MAN_PS,
631 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
632 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
633
634 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
635 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
636 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
637 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
638 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
639 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
640 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
641 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
642 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
643 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
644 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
645 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
646 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
647 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
648 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
649 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
650 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
651 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
652 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
653 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
654 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
655 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
656 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
657 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
658
659
660 /****************************************************************************
661 * IO Unit Config Pages
662 ****************************************************************************/
663
664 /* IO Unit Page 0 */
665
666 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
667 {
668 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
669 U64 UniqueValue; /* 0x04 */
670 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
671 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
672 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
673 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
674
675 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
676
677
678 /* IO Unit Page 1 */
679
680 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
681 {
682 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
683 U32 Flags; /* 0x04 */
684 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
685 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
686
687 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
688
689 /* IO Unit Page 1 Flags defines */
690 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
691 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
692 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
693 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
694 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
695 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
696 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
697 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
698 #define MPI2_IOUNITPAGE1_MULTI_PATHING (0x00000002)
699 #define MPI2_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
700
701
702 /* IO Unit Page 3 */
703
704 /*
705 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
706 * one and check Header.PageLength at runtime.
707 */
708 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
709 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
710 #endif
711
712 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
713 {
714 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
715 U8 GPIOCount; /* 0x04 */
716 U8 Reserved1; /* 0x05 */
717 U16 Reserved2; /* 0x06 */
718 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
719 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
720 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
721
722 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
723
724 /* defines for IO Unit Page 3 GPIOVal field */
725 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
726 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
727 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
728 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
729
730
731 /* IO Unit Page 5 */
732
733 /*
734 * Upper layer code (drivers, utilities, etc.) should leave this define set to
735 * one and check Header.PageLength or NumDmaEngines at runtime.
736 */
737 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
738 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
739 #endif
740
741 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
742 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
743 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
744 U64 RaidAcceleratorBufferSize; /* 0x0C */
745 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
746 U8 RAControlSize; /* 0x1C */
747 U8 NumDmaEngines; /* 0x1D */
748 U8 RAMinControlSize; /* 0x1E */
749 U8 RAMaxControlSize; /* 0x1F */
750 U32 Reserved1; /* 0x20 */
751 U32 Reserved2; /* 0x24 */
752 U32 Reserved3; /* 0x28 */
753 U32 DmaEngineCapabilities
754 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
755 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
756 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
757
758 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
759
760 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
761 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
762 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
763
764 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
765 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
766 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
767 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
768
769
770 /* IO Unit Page 6 */
771
772 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
773 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
774 U16 Flags; /* 0x04 */
775 U8 RAHostControlSize; /* 0x06 */
776 U8 Reserved0; /* 0x07 */
777 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
778 U32 Reserved1; /* 0x10 */
779 U32 Reserved2; /* 0x14 */
780 U32 Reserved3; /* 0x18 */
781 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
782 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
783
784 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
785
786 /* defines for IO Unit Page 6 Flags field */
787 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
788
789
790 /****************************************************************************
791 * IOC Config Pages
792 ****************************************************************************/
793
794 /* IOC Page 0 */
795
796 typedef struct _MPI2_CONFIG_PAGE_IOC_0
797 {
798 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
799 U32 Reserved1; /* 0x04 */
800 U32 Reserved2; /* 0x08 */
801 U16 VendorID; /* 0x0C */
802 U16 DeviceID; /* 0x0E */
803 U8 RevisionID; /* 0x10 */
804 U8 Reserved3; /* 0x11 */
805 U16 Reserved4; /* 0x12 */
806 U32 ClassCode; /* 0x14 */
807 U16 SubsystemVendorID; /* 0x18 */
808 U16 SubsystemID; /* 0x1A */
809 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
810 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
811
812 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
813
814
815 /* IOC Page 1 */
816
817 typedef struct _MPI2_CONFIG_PAGE_IOC_1
818 {
819 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
820 U32 Flags; /* 0x04 */
821 U32 CoalescingTimeout; /* 0x08 */
822 U8 CoalescingDepth; /* 0x0C */
823 U8 PCISlotNum; /* 0x0D */
824 U8 PCIBusNum; /* 0x0E */
825 U8 PCIDomainSegment; /* 0x0F */
826 U32 Reserved1; /* 0x10 */
827 U32 Reserved2; /* 0x14 */
828 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
829 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
830
831 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
832
833 /* defines for IOC Page 1 Flags field */
834 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
835
836 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
837 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
838 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
839
840 /* IOC Page 6 */
841
842 typedef struct _MPI2_CONFIG_PAGE_IOC_6
843 {
844 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
845 U32 CapabilitiesFlags; /* 0x04 */
846 U8 MaxDrivesRAID0; /* 0x08 */
847 U8 MaxDrivesRAID1; /* 0x09 */
848 U8 MaxDrivesRAID1E; /* 0x0A */
849 U8 MaxDrivesRAID10; /* 0x0B */
850 U8 MinDrivesRAID0; /* 0x0C */
851 U8 MinDrivesRAID1; /* 0x0D */
852 U8 MinDrivesRAID1E; /* 0x0E */
853 U8 MinDrivesRAID10; /* 0x0F */
854 U32 Reserved1; /* 0x10 */
855 U8 MaxGlobalHotSpares; /* 0x14 */
856 U8 MaxPhysDisks; /* 0x15 */
857 U8 MaxVolumes; /* 0x16 */
858 U8 MaxConfigs; /* 0x17 */
859 U8 MaxOCEDisks; /* 0x18 */
860 U8 Reserved2; /* 0x19 */
861 U16 Reserved3; /* 0x1A */
862 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
863 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
864 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
865 U32 Reserved4; /* 0x28 */
866 U32 Reserved5; /* 0x2C */
867 U16 DefaultMetadataSize; /* 0x30 */
868 U16 Reserved6; /* 0x32 */
869 U16 MaxBadBlockTableEntries; /* 0x34 */
870 U16 Reserved7; /* 0x36 */
871 U32 IRNvsramVersion; /* 0x38 */
872 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
873 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
874
875 #define MPI2_IOCPAGE6_PAGEVERSION (0x04)
876
877 /* defines for IOC Page 6 CapabilitiesFlags */
878 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
879 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
880 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
881 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
882 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
883
884
885 /* IOC Page 7 */
886
887 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
888
889 typedef struct _MPI2_CONFIG_PAGE_IOC_7
890 {
891 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
892 U32 Reserved1; /* 0x04 */
893 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
894 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
895 U16 Reserved2; /* 0x1A */
896 U32 Reserved3; /* 0x1C */
897 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
898 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
899
900 #define MPI2_IOCPAGE7_PAGEVERSION (0x01)
901
902
903 /* IOC Page 8 */
904
905 typedef struct _MPI2_CONFIG_PAGE_IOC_8
906 {
907 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
908 U8 NumDevsPerEnclosure; /* 0x04 */
909 U8 Reserved1; /* 0x05 */
910 U16 Reserved2; /* 0x06 */
911 U16 MaxPersistentEntries; /* 0x08 */
912 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
913 U16 Flags; /* 0x0C */
914 U16 Reserved3; /* 0x0E */
915 U16 IRVolumeMappingFlags; /* 0x10 */
916 U16 Reserved4; /* 0x12 */
917 U32 Reserved5; /* 0x14 */
918 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
919 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
920
921 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
922
923 /* defines for IOC Page 8 Flags field */
924 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
925 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
926
927 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
928 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
929 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
930
931 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
932 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
933
934 /* defines for IOC Page 8 IRVolumeMappingFlags */
935 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
936 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
937 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
938
939
940 /****************************************************************************
941 * BIOS Config Pages
942 ****************************************************************************/
943
944 /* BIOS Page 1 */
945
946 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
947 {
948 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
949 U32 BiosOptions; /* 0x04 */
950 U32 IOCSettings; /* 0x08 */
951 U32 Reserved1; /* 0x0C */
952 U32 DeviceSettings; /* 0x10 */
953 U16 NumberOfDevices; /* 0x14 */
954 U16 Reserved2; /* 0x16 */
955 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
956 U16 IOTimeoutSequential; /* 0x1A */
957 U16 IOTimeoutOther; /* 0x1C */
958 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
959 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
960 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
961
962 #define MPI2_BIOSPAGE1_PAGEVERSION (0x04)
963
964 /* values for BIOS Page 1 BiosOptions field */
965 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
966
967 /* values for BIOS Page 1 IOCSettings field */
968 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
969 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
970 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
971
972 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
973 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
974 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
975 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
976
977 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
978 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
979 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
980 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
981 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
982
983 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
984
985 /* values for BIOS Page 1 DeviceSettings field */
986 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
987 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
988 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
989 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
990 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
991
992
993 /* BIOS Page 2 */
994
995 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
996 {
997 U32 Reserved1; /* 0x00 */
998 U32 Reserved2; /* 0x04 */
999 U32 Reserved3; /* 0x08 */
1000 U32 Reserved4; /* 0x0C */
1001 U32 Reserved5; /* 0x10 */
1002 U32 Reserved6; /* 0x14 */
1003 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1004 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1005 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1006
1007 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1008 {
1009 U64 SASAddress; /* 0x00 */
1010 U8 LUN[8]; /* 0x08 */
1011 U32 Reserved1; /* 0x10 */
1012 U32 Reserved2; /* 0x14 */
1013 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1014 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1015
1016 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1017 {
1018 U64 EnclosureLogicalID; /* 0x00 */
1019 U32 Reserved1; /* 0x08 */
1020 U32 Reserved2; /* 0x0C */
1021 U16 SlotNumber; /* 0x10 */
1022 U16 Reserved3; /* 0x12 */
1023 U32 Reserved4; /* 0x14 */
1024 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1025 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1026 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1027
1028 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1029 {
1030 U64 DeviceName; /* 0x00 */
1031 U8 LUN[8]; /* 0x08 */
1032 U32 Reserved1; /* 0x10 */
1033 U32 Reserved2; /* 0x14 */
1034 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1035 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1036
1037 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1038 {
1039 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1040 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1041 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1042 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1043 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1044 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1045
1046 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1047 {
1048 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1049 U32 Reserved1; /* 0x04 */
1050 U32 Reserved2; /* 0x08 */
1051 U32 Reserved3; /* 0x0C */
1052 U32 Reserved4; /* 0x10 */
1053 U32 Reserved5; /* 0x14 */
1054 U32 Reserved6; /* 0x18 */
1055 U8 ReqBootDeviceForm; /* 0x1C */
1056 U8 Reserved7; /* 0x1D */
1057 U16 Reserved8; /* 0x1E */
1058 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1059 U8 ReqAltBootDeviceForm; /* 0x38 */
1060 U8 Reserved9; /* 0x39 */
1061 U16 Reserved10; /* 0x3A */
1062 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1063 U8 CurrentBootDeviceForm; /* 0x58 */
1064 U8 Reserved11; /* 0x59 */
1065 U16 Reserved12; /* 0x5A */
1066 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1067 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1068 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1069
1070 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1071
1072 /* values for BIOS Page 2 BootDeviceForm fields */
1073 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1074 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1075 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1076 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1077 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1078
1079
1080 /* BIOS Page 3 */
1081
1082 typedef struct _MPI2_ADAPTER_INFO
1083 {
1084 U8 PciBusNumber; /* 0x00 */
1085 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1086 U16 AdapterFlags; /* 0x02 */
1087 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1088 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1089
1090 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1091 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1092
1093 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1094 {
1095 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1096 U32 GlobalFlags; /* 0x04 */
1097 U32 BiosVersion; /* 0x08 */
1098 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1099 U32 Reserved1; /* 0x1C */
1100 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1101 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1102
1103 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1104
1105 /* values for BIOS Page 3 GlobalFlags */
1106 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1107 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1108 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1109
1110 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1111 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1112 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1113 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1114
1115
1116 /* BIOS Page 4 */
1117
1118 /*
1119 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1120 * one and check Header.PageLength or NumPhys at runtime.
1121 */
1122 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1123 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1124 #endif
1125
1126 typedef struct _MPI2_BIOS4_ENTRY
1127 {
1128 U64 ReassignmentWWID; /* 0x00 */
1129 U64 ReassignmentDeviceName; /* 0x08 */
1130 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1131 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1132
1133 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1134 {
1135 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1136 U8 NumPhys; /* 0x04 */
1137 U8 Reserved1; /* 0x05 */
1138 U16 Reserved2; /* 0x06 */
1139 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1140 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1141 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1142
1143 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1144
1145
1146 /****************************************************************************
1147 * RAID Volume Config Pages
1148 ****************************************************************************/
1149
1150 /* RAID Volume Page 0 */
1151
1152 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1153 {
1154 U8 RAIDSetNum; /* 0x00 */
1155 U8 PhysDiskMap; /* 0x01 */
1156 U8 PhysDiskNum; /* 0x02 */
1157 U8 Reserved; /* 0x03 */
1158 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1159 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1160
1161 /* defines for the PhysDiskMap field */
1162 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1163 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1164
1165 typedef struct _MPI2_RAIDVOL0_SETTINGS
1166 {
1167 U16 Settings; /* 0x00 */
1168 U8 HotSparePool; /* 0x01 */
1169 U8 Reserved; /* 0x02 */
1170 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1171 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1172
1173 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1174 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1175 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1176 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1177 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1178 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1179 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1180 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1181 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1182
1183 /* RAID Volume Page 0 VolumeSettings defines */
1184 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1185 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1186
1187 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1188 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1189 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1190 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1191
1192 /*
1193 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1194 * one and check Header.PageLength at runtime.
1195 */
1196 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1197 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1198 #endif
1199
1200 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1201 {
1202 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1203 U16 DevHandle; /* 0x04 */
1204 U8 VolumeState; /* 0x06 */
1205 U8 VolumeType; /* 0x07 */
1206 U32 VolumeStatusFlags; /* 0x08 */
1207 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1208 U64 MaxLBA; /* 0x10 */
1209 U32 StripeSize; /* 0x18 */
1210 U16 BlockSize; /* 0x1C */
1211 U16 Reserved1; /* 0x1E */
1212 U8 SupportedPhysDisks; /* 0x20 */
1213 U8 ResyncRate; /* 0x21 */
1214 U16 DataScrubDuration; /* 0x22 */
1215 U8 NumPhysDisks; /* 0x24 */
1216 U8 Reserved2; /* 0x25 */
1217 U8 Reserved3; /* 0x26 */
1218 U8 InactiveStatus; /* 0x27 */
1219 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1220 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1221 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1222
1223 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1224
1225 /* values for RAID VolumeState */
1226 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1227 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1228 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1229 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1230 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1231 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1232
1233 /* values for RAID VolumeType */
1234 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1235 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1236 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1237 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1238 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1239
1240 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1241 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1242 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1243 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1244 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1245 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1246 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1247 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1248 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1249 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1250 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1251 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1252 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1253 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1254 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1255 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1256 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1257 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1258 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1259
1260 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1261 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1262 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1263 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1264 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1265
1266 /* values for RAID Volume Page 0 InactiveStatus field */
1267 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1268 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1269 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1270 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1271 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1272 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1273 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1274
1275
1276 /* RAID Volume Page 1 */
1277
1278 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1279 {
1280 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1281 U16 DevHandle; /* 0x04 */
1282 U16 Reserved0; /* 0x06 */
1283 U8 GUID[24]; /* 0x08 */
1284 U8 Name[16]; /* 0x20 */
1285 U64 WWID; /* 0x30 */
1286 U32 Reserved1; /* 0x38 */
1287 U32 Reserved2; /* 0x3C */
1288 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1289 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1290
1291 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1292
1293
1294 /****************************************************************************
1295 * RAID Physical Disk Config Pages
1296 ****************************************************************************/
1297
1298 /* RAID Physical Disk Page 0 */
1299
1300 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1301 {
1302 U16 Reserved1; /* 0x00 */
1303 U8 HotSparePool; /* 0x02 */
1304 U8 Reserved2; /* 0x03 */
1305 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1306 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1307
1308 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1309
1310 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1311 {
1312 U8 VendorID[8]; /* 0x00 */
1313 U8 ProductID[16]; /* 0x08 */
1314 U8 ProductRevLevel[4]; /* 0x18 */
1315 U8 SerialNum[32]; /* 0x1C */
1316 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1317 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1318 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1319
1320 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1321 {
1322 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1323 U16 DevHandle; /* 0x04 */
1324 U8 Reserved1; /* 0x06 */
1325 U8 PhysDiskNum; /* 0x07 */
1326 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1327 U32 Reserved2; /* 0x0C */
1328 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1329 U32 Reserved3; /* 0x4C */
1330 U8 PhysDiskState; /* 0x50 */
1331 U8 OfflineReason; /* 0x51 */
1332 U8 IncompatibleReason; /* 0x52 */
1333 U8 PhysDiskAttributes; /* 0x53 */
1334 U32 PhysDiskStatusFlags; /* 0x54 */
1335 U64 DeviceMaxLBA; /* 0x58 */
1336 U64 HostMaxLBA; /* 0x60 */
1337 U64 CoercedMaxLBA; /* 0x68 */
1338 U16 BlockSize; /* 0x70 */
1339 U16 Reserved5; /* 0x72 */
1340 U32 Reserved6; /* 0x74 */
1341 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1342 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1343 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1344
1345 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1346
1347 /* PhysDiskState defines */
1348 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1349 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1350 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1351 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1352 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1353 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1354 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1355 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1356
1357 /* OfflineReason defines */
1358 #define MPI2_PHYSDISK0_ONLINE (0x00)
1359 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1360 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1361 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1362 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1363 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1364 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1365
1366 /* IncompatibleReason defines */
1367 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1368 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1369 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1370 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1371 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1372 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1373 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1374
1375 /* PhysDiskAttributes defines */
1376 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1377 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1378 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1379 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1380
1381 /* PhysDiskStatusFlags defines */
1382 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1383 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1384 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1385 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1386 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1387 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1388 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1389 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1390
1391
1392 /* RAID Physical Disk Page 1 */
1393
1394 /*
1395 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1396 * one and check Header.PageLength or NumPhysDiskPaths at runtime.
1397 */
1398 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1399 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1400 #endif
1401
1402 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1403 {
1404 U16 DevHandle; /* 0x00 */
1405 U16 Reserved1; /* 0x02 */
1406 U64 WWID; /* 0x04 */
1407 U64 OwnerWWID; /* 0x0C */
1408 U8 OwnerIdentifier; /* 0x14 */
1409 U8 Reserved2; /* 0x15 */
1410 U16 Flags; /* 0x16 */
1411 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1412 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1413
1414 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1415 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1416 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1417 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1418
1419 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1420 {
1421 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1422 U8 NumPhysDiskPaths; /* 0x04 */
1423 U8 PhysDiskNum; /* 0x05 */
1424 U16 Reserved1; /* 0x06 */
1425 U32 Reserved2; /* 0x08 */
1426 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1427 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1428 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1429 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1430
1431 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1432
1433
1434 /****************************************************************************
1435 * values for fields used by several types of SAS Config Pages
1436 ****************************************************************************/
1437
1438 /* values for NegotiatedLinkRates fields */
1439 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1440 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1441 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1442 /* link rates used for Negotiated Physical and Logical Link Rate */
1443 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1444 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1445 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1446 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1447 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1448 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1449 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1450 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1451 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1452
1453
1454 /* values for AttachedPhyInfo fields */
1455 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1456 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1457 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1458
1459 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1460 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1461 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1462 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1463 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1464 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1465 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1466 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1467 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1468 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1469
1470
1471 /* values for PhyInfo fields */
1472 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1473 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1474 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1475 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1476 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1477 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1478 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1479
1480 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1481 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1482 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1483 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1484 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1485 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1486 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1487 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1488 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1489 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1490
1491 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1492 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1493 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1494 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1495
1496 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1497 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1498
1499 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1500 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1501 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1502 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1503
1504
1505 /* values for SAS ProgrammedLinkRate fields */
1506 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1507 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1508 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1509 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1510 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1511 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1512 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1513 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1514 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1515 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1516
1517
1518 /* values for SAS HwLinkRate fields */
1519 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1520 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1521 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1522 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1523 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1524 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1525 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1526 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1527
1528
1529
1530 /****************************************************************************
1531 * SAS IO Unit Config Pages
1532 ****************************************************************************/
1533
1534 /* SAS IO Unit Page 0 */
1535
1536 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1537 {
1538 U8 Port; /* 0x00 */
1539 U8 PortFlags; /* 0x01 */
1540 U8 PhyFlags; /* 0x02 */
1541 U8 NegotiatedLinkRate; /* 0x03 */
1542 U32 ControllerPhyDeviceInfo;/* 0x04 */
1543 U16 AttachedDevHandle; /* 0x08 */
1544 U16 ControllerDevHandle; /* 0x0A */
1545 U32 DiscoveryStatus; /* 0x0C */
1546 U32 Reserved; /* 0x10 */
1547 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1548 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1549
1550 /*
1551 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1552 * one and check Header.ExtPageLength or NumPhys at runtime.
1553 */
1554 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1555 #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1556 #endif
1557
1558 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1559 {
1560 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1561 U32 Reserved1; /* 0x08 */
1562 U8 NumPhys; /* 0x0C */
1563 U8 Reserved2; /* 0x0D */
1564 U16 Reserved3; /* 0x0E */
1565 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1566 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1567 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1568 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1569
1570 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1571
1572 /* values for SAS IO Unit Page 0 PortFlags */
1573 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1574 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1575
1576 /* values for SAS IO Unit Page 0 PhyFlags */
1577 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1578 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1579
1580 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1581
1582 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1583
1584 /* values for SAS IO Unit Page 0 DiscoveryStatus */
1585 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1586 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1587 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1588 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1589 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1590 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1591 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1592 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1593 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1594 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1595 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1596 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1597 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1598 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1599 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1600 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1601 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1602 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1603 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1604 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1605
1606
1607 /* SAS IO Unit Page 1 */
1608
1609 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1610 {
1611 U8 Port; /* 0x00 */
1612 U8 PortFlags; /* 0x01 */
1613 U8 PhyFlags; /* 0x02 */
1614 U8 MaxMinLinkRate; /* 0x03 */
1615 U32 ControllerPhyDeviceInfo; /* 0x04 */
1616 U16 MaxTargetPortConnectTime; /* 0x08 */
1617 U16 Reserved1; /* 0x0A */
1618 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1619 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1620
1621 /*
1622 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1623 * one and check Header.ExtPageLength or NumPhys at runtime.
1624 */
1625 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1626 #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1627 #endif
1628
1629 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1630 {
1631 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1632 U16 ControlFlags; /* 0x08 */
1633 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1634 U16 AdditionalControlFlags; /* 0x0C */
1635 U16 SASWideMaxQueueDepth; /* 0x0E */
1636 U8 NumPhys; /* 0x10 */
1637 U8 SATAMaxQDepth; /* 0x11 */
1638 U8 ReportDeviceMissingDelay; /* 0x12 */
1639 U8 IODeviceMissingDelay; /* 0x13 */
1640 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1641 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
1642 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1643 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1644
1645 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1646
1647 /* values for SAS IO Unit Page 1 ControlFlags */
1648 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1649 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1650 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1651 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1652
1653 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1654 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1655 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1656 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1657 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1658
1659 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1660 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1661 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1662 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1663 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1664 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1665 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1666 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
1667
1668 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
1669 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1670 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1671 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1672 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1673 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1674 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1675 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1676 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1677
1678 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1679 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1680 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1681
1682 /* values for SAS IO Unit Page 1 PortFlags */
1683 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1684
1685 /* values for SAS IO Unit Page 2 PhyFlags */
1686 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1687 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1688
1689 /* values for SAS IO Unit Page 0 MaxMinLinkRate */
1690 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1691 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1692 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1693 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1694 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1695 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1696 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1697 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1698
1699 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1700
1701
1702 /* SAS IO Unit Page 4 */
1703
1704 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1705 {
1706 U8 MaxTargetSpinup; /* 0x00 */
1707 U8 SpinupDelay; /* 0x01 */
1708 U16 Reserved1; /* 0x02 */
1709 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1710 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1711
1712 /*
1713 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1714 * four and check Header.ExtPageLength or NumPhys at runtime.
1715 */
1716 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1717 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
1718 #endif
1719
1720 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1721 {
1722 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1723 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
1724 U32 Reserved1; /* 0x18 */
1725 U32 Reserved2; /* 0x1C */
1726 U32 Reserved3; /* 0x20 */
1727 U8 BootDeviceWaitTime; /* 0x24 */
1728 U8 Reserved4; /* 0x25 */
1729 U16 Reserved5; /* 0x26 */
1730 U8 NumPhys; /* 0x28 */
1731 U8 PEInitialSpinupDelay; /* 0x29 */
1732 U8 PEReplyDelay; /* 0x2A */
1733 U8 Flags; /* 0x2B */
1734 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
1735 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
1736 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
1737 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
1738
1739 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
1740
1741 /* defines for Flags field */
1742 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
1743
1744 /* defines for PHY field */
1745 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
1746
1747
1748 /****************************************************************************
1749 * SAS Expander Config Pages
1750 ****************************************************************************/
1751
1752 /* SAS Expander Page 0 */
1753
1754 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
1755 {
1756 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1757 U8 PhysicalPort; /* 0x08 */
1758 U8 ReportGenLength; /* 0x09 */
1759 U16 EnclosureHandle; /* 0x0A */
1760 U64 SASAddress; /* 0x0C */
1761 U32 DiscoveryStatus; /* 0x14 */
1762 U16 DevHandle; /* 0x18 */
1763 U16 ParentDevHandle; /* 0x1A */
1764 U16 ExpanderChangeCount; /* 0x1C */
1765 U16 ExpanderRouteIndexes; /* 0x1E */
1766 U8 NumPhys; /* 0x20 */
1767 U8 SASLevel; /* 0x21 */
1768 U16 Flags; /* 0x22 */
1769 U16 STPBusInactivityTimeLimit; /* 0x24 */
1770 U16 STPMaxConnectTimeLimit; /* 0x26 */
1771 U16 STP_SMP_NexusLossTime; /* 0x28 */
1772 U16 MaxNumRoutedSasAddresses; /* 0x2A */
1773 U64 ActiveZoneManagerSASAddress;/* 0x2C */
1774 U16 ZoneLockInactivityLimit; /* 0x34 */
1775 U16 Reserved1; /* 0x36 */
1776 U8 TimeToReducedFunc; /* 0x38 */
1777 U8 InitialTimeToReducedFunc; /* 0x39 */
1778 U8 MaxReducedFuncTime; /* 0x3A */
1779 U8 Reserved2; /* 0x3B */
1780 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
1781 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
1782
1783 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
1784
1785 /* values for SAS Expander Page 0 DiscoveryStatus field */
1786 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1787 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1788 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
1789 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1790 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1791 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1792 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1793 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
1794 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1795 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
1796 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
1797 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
1798 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
1799 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
1800 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
1801 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1802 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
1803 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
1804 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1805 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
1806
1807 /* values for SAS Expander Page 0 Flags field */
1808 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
1809 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
1810 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
1811 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
1812 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
1813 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
1814 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
1815 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
1816 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
1817 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
1818 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
1819
1820
1821 /* SAS Expander Page 1 */
1822
1823 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
1824 {
1825 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1826 U8 PhysicalPort; /* 0x08 */
1827 U8 Reserved1; /* 0x09 */
1828 U16 Reserved2; /* 0x0A */
1829 U8 NumPhys; /* 0x0C */
1830 U8 Phy; /* 0x0D */
1831 U16 NumTableEntriesProgrammed; /* 0x0E */
1832 U8 ProgrammedLinkRate; /* 0x10 */
1833 U8 HwLinkRate; /* 0x11 */
1834 U16 AttachedDevHandle; /* 0x12 */
1835 U32 PhyInfo; /* 0x14 */
1836 U32 AttachedDeviceInfo; /* 0x18 */
1837 U16 ExpanderDevHandle; /* 0x1C */
1838 U8 ChangeCount; /* 0x1E */
1839 U8 NegotiatedLinkRate; /* 0x1F */
1840 U8 PhyIdentifier; /* 0x20 */
1841 U8 AttachedPhyIdentifier; /* 0x21 */
1842 U8 Reserved3; /* 0x22 */
1843 U8 DiscoveryInfo; /* 0x23 */
1844 U32 AttachedPhyInfo; /* 0x24 */
1845 U8 ZoneGroup; /* 0x28 */
1846 U8 SelfConfigStatus; /* 0x29 */
1847 U16 Reserved4; /* 0x2A */
1848 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
1849 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
1850
1851 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
1852
1853 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
1854
1855 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
1856
1857 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
1858
1859 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
1860
1861 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1862
1863 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
1864
1865 /* values for SAS Expander Page 1 DiscoveryInfo field */
1866 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
1867 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
1868 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
1869
1870
1871 /****************************************************************************
1872 * SAS Device Config Pages
1873 ****************************************************************************/
1874
1875 /* SAS Device Page 0 */
1876
1877 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
1878 {
1879 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1880 U16 Slot; /* 0x08 */
1881 U16 EnclosureHandle; /* 0x0A */
1882 U64 SASAddress; /* 0x0C */
1883 U16 ParentDevHandle; /* 0x14 */
1884 U8 PhyNum; /* 0x16 */
1885 U8 AccessStatus; /* 0x17 */
1886 U16 DevHandle; /* 0x18 */
1887 U8 AttachedPhyIdentifier; /* 0x1A */
1888 U8 ZoneGroup; /* 0x1B */
1889 U32 DeviceInfo; /* 0x1C */
1890 U16 Flags; /* 0x20 */
1891 U8 PhysicalPort; /* 0x22 */
1892 U8 MaxPortConnections; /* 0x23 */
1893 U64 DeviceName; /* 0x24 */
1894 U8 PortGroups; /* 0x2C */
1895 U8 DmaGroup; /* 0x2D */
1896 U8 ControlGroup; /* 0x2E */
1897 U8 Reserved1; /* 0x2F */
1898 U32 Reserved2; /* 0x30 */
1899 U32 Reserved3; /* 0x34 */
1900 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
1901 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
1902
1903 #define MPI2_SASDEVICE0_PAGEVERSION (0x08)
1904
1905 /* values for SAS Device Page 0 AccessStatus field */
1906 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
1907 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
1908 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
1909 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
1910 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
1911 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
1912 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
1913 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
1914 /* specific values for SATA Init failures */
1915 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
1916 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
1917 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
1918 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
1919 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
1920 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
1921 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
1922 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
1923 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
1924 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
1925 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
1926
1927 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
1928
1929 /* values for SAS Device Page 0 Flags field */
1930 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
1931 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
1932 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
1933 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
1934 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
1935 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
1936 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
1937 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
1938 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
1939
1940
1941 /* SAS Device Page 1 */
1942
1943 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
1944 {
1945 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1946 U32 Reserved1; /* 0x08 */
1947 U64 SASAddress; /* 0x0C */
1948 U32 Reserved2; /* 0x14 */
1949 U16 DevHandle; /* 0x18 */
1950 U16 Reserved3; /* 0x1A */
1951 U8 InitialRegDeviceFIS[20];/* 0x1C */
1952 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
1953 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
1954
1955 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
1956
1957
1958 /****************************************************************************
1959 * SAS PHY Config Pages
1960 ****************************************************************************/
1961
1962 /* SAS PHY Page 0 */
1963
1964 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
1965 {
1966 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1967 U16 OwnerDevHandle; /* 0x08 */
1968 U16 Reserved1; /* 0x0A */
1969 U16 AttachedDevHandle; /* 0x0C */
1970 U8 AttachedPhyIdentifier; /* 0x0E */
1971 U8 Reserved2; /* 0x0F */
1972 U32 AttachedPhyInfo; /* 0x10 */
1973 U8 ProgrammedLinkRate; /* 0x14 */
1974 U8 HwLinkRate; /* 0x15 */
1975 U8 ChangeCount; /* 0x16 */
1976 U8 Flags; /* 0x17 */
1977 U32 PhyInfo; /* 0x18 */
1978 U8 NegotiatedLinkRate; /* 0x1C */
1979 U8 Reserved3; /* 0x1D */
1980 U16 Reserved4; /* 0x1E */
1981 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
1982 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
1983
1984 #define MPI2_SASPHY0_PAGEVERSION (0x03)
1985
1986 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
1987
1988 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
1989
1990 /* values for SAS PHY Page 0 Flags field */
1991 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
1992
1993 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
1994
1995 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1996
1997 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
1998
1999
2000 /* SAS PHY Page 1 */
2001
2002 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2003 {
2004 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2005 U32 Reserved1; /* 0x08 */
2006 U32 InvalidDwordCount; /* 0x0C */
2007 U32 RunningDisparityErrorCount; /* 0x10 */
2008 U32 LossDwordSynchCount; /* 0x14 */
2009 U32 PhyResetProblemCount; /* 0x18 */
2010 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2011 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2012
2013 #define MPI2_SASPHY1_PAGEVERSION (0x01)
2014
2015
2016 /* SAS PHY Page 2 */
2017
2018 typedef struct _MPI2_SASPHY2_PHY_EVENT {
2019 U8 PhyEventCode; /* 0x00 */
2020 U8 Reserved1; /* 0x01 */
2021 U16 Reserved2; /* 0x02 */
2022 U32 PhyEventInfo; /* 0x04 */
2023 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2024 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2025
2026 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2027
2028
2029 /*
2030 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2031 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2032 */
2033 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2034 #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2035 #endif
2036
2037 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2038 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2039 U32 Reserved1; /* 0x08 */
2040 U8 NumPhyEvents; /* 0x0C */
2041 U8 Reserved2; /* 0x0D */
2042 U16 Reserved3; /* 0x0E */
2043 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
2044 /* 0x10 */
2045 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2046 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2047
2048 #define MPI2_SASPHY2_PAGEVERSION (0x00)
2049
2050
2051 /* SAS PHY Page 3 */
2052
2053 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2054 U8 PhyEventCode; /* 0x00 */
2055 U8 Reserved1; /* 0x01 */
2056 U16 Reserved2; /* 0x02 */
2057 U8 CounterType; /* 0x04 */
2058 U8 ThresholdWindow; /* 0x05 */
2059 U8 TimeUnits; /* 0x06 */
2060 U8 Reserved3; /* 0x07 */
2061 U32 EventThreshold; /* 0x08 */
2062 U16 ThresholdFlags; /* 0x0C */
2063 U16 Reserved4; /* 0x0E */
2064 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2065 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2066
2067 /* values for PhyEventCode field */
2068 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2069 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2070 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2071 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2072 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2073 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2074 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2075 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2076 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2077 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2078 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2079 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2080 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2081 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2082 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2083 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2084 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2085 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2086 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2087 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2088 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2089 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2090 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2091 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2092 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2093 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2094 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2095 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2096 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2097 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2098 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2099 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2100 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2101 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2102 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2103 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2104 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2105
2106 /* values for the CounterType field */
2107 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2108 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2109 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2110
2111 /* values for the TimeUnits field */
2112 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2113 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2114 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2115 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2116
2117 /* values for the ThresholdFlags field */
2118 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2119 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2120
2121 /*
2122 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2123 * one and check Header.ExtPageLength or NumPhyEvents at runtime.
2124 */
2125 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2126 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2127 #endif
2128
2129 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2130 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2131 U32 Reserved1; /* 0x08 */
2132 U8 NumPhyEvents; /* 0x0C */
2133 U8 Reserved2; /* 0x0D */
2134 U16 Reserved3; /* 0x0E */
2135 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig
2136 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2137 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2138 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2139
2140 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2141
2142
2143 /****************************************************************************
2144 * SAS Port Config Pages
2145 ****************************************************************************/
2146
2147 /* SAS Port Page 0 */
2148
2149 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2150 {
2151 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2152 U8 PortNumber; /* 0x08 */
2153 U8 PhysicalPort; /* 0x09 */
2154 U8 PortWidth; /* 0x0A */
2155 U8 PhysicalPortWidth; /* 0x0B */
2156 U8 ZoneGroup; /* 0x0C */
2157 U8 Reserved1; /* 0x0D */
2158 U16 Reserved2; /* 0x0E */
2159 U64 SASAddress; /* 0x10 */
2160 U32 DeviceInfo; /* 0x18 */
2161 U32 Reserved3; /* 0x1C */
2162 U32 Reserved4; /* 0x20 */
2163 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2164 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2165
2166 #define MPI2_SASPORT0_PAGEVERSION (0x00)
2167
2168 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2169
2170
2171 /****************************************************************************
2172 * SAS Enclosure Config Pages
2173 ****************************************************************************/
2174
2175 /* SAS Enclosure Page 0 */
2176
2177 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2178 {
2179 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2180 U32 Reserved1; /* 0x08 */
2181 U64 EnclosureLogicalID; /* 0x0C */
2182 U16 Flags; /* 0x14 */
2183 U16 EnclosureHandle; /* 0x16 */
2184 U16 NumSlots; /* 0x18 */
2185 U16 StartSlot; /* 0x1A */
2186 U16 Reserved2; /* 0x1C */
2187 U16 SEPDevHandle; /* 0x1E */
2188 U32 Reserved3; /* 0x20 */
2189 U32 Reserved4; /* 0x24 */
2190 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2191 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2192 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2193
2194 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
2195
2196 /* values for SAS Enclosure Page 0 Flags field */
2197 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2198 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2199 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2200 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2201 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2202 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2203 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2204
2205
2206 /****************************************************************************
2207 * Log Config Page
2208 ****************************************************************************/
2209
2210 /* Log Page 0 */
2211
2212 /*
2213 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2214 * one and check Header.ExtPageLength or NumPhys at runtime.
2215 */
2216 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2217 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2218 #endif
2219
2220 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2221
2222 typedef struct _MPI2_LOG_0_ENTRY
2223 {
2224 U64 TimeStamp; /* 0x00 */
2225 U32 Reserved1; /* 0x08 */
2226 U16 LogSequence; /* 0x0C */
2227 U16 LogEntryQualifier; /* 0x0E */
2228 U8 VP_ID; /* 0x10 */
2229 U8 VF_ID; /* 0x11 */
2230 U16 Reserved2; /* 0x12 */
2231 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2232 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2233 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2234
2235 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2236 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2237 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2238 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2239 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2240 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2241
2242 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2243 {
2244 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2245 U32 Reserved1; /* 0x08 */
2246 U32 Reserved2; /* 0x0C */
2247 U16 NumLogEntries; /* 0x10 */
2248 U16 Reserved3; /* 0x12 */
2249 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2250 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2251 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2252
2253 #define MPI2_LOG_0_PAGEVERSION (0x02)
2254
2255
2256 /****************************************************************************
2257 * RAID Config Page
2258 ****************************************************************************/
2259
2260 /* RAID Page 0 */
2261
2262 /*
2263 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2264 * one and check Header.ExtPageLength or NumPhys at runtime.
2265 */
2266 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2267 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2268 #endif
2269
2270 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2271 {
2272 U16 ElementFlags; /* 0x00 */
2273 U16 VolDevHandle; /* 0x02 */
2274 U8 HotSparePool; /* 0x04 */
2275 U8 PhysDiskNum; /* 0x05 */
2276 U16 PhysDiskDevHandle; /* 0x06 */
2277 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2278 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2279 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2280
2281 /* values for the ElementFlags field */
2282 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2283 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2284 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2285 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2286 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2287
2288
2289 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2290 {
2291 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2292 U8 NumHotSpares; /* 0x08 */
2293 U8 NumPhysDisks; /* 0x09 */
2294 U8 NumVolumes; /* 0x0A */
2295 U8 ConfigNum; /* 0x0B */
2296 U32 Flags; /* 0x0C */
2297 U8 ConfigGUID[24]; /* 0x10 */
2298 U32 Reserved1; /* 0x28 */
2299 U8 NumElements; /* 0x2C */
2300 U8 Reserved2; /* 0x2D */
2301 U16 Reserved3; /* 0x2E */
2302 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2303 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2304 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2305 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2306
2307 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2308
2309 /* values for RAID Configuration Page 0 Flags field */
2310 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2311
2312
2313 /****************************************************************************
2314 * Driver Persistent Mapping Config Pages
2315 ****************************************************************************/
2316
2317 /* Driver Persistent Mapping Page 0 */
2318
2319 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2320 {
2321 U64 PhysicalIdentifier; /* 0x00 */
2322 U16 MappingInformation; /* 0x08 */
2323 U16 DeviceIndex; /* 0x0A */
2324 U32 PhysicalBitsMapping; /* 0x0C */
2325 U32 Reserved1; /* 0x10 */
2326 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2327 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2328 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2329
2330 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2331 {
2332 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2333 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2334 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2335 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2336 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2337
2338 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2339
2340 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
2341 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2342 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2343 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2344
2345
2346 #endif
2347
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