?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[SCSI] qla2xxx: Refactor qla data structures
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / scsi / qla2xxx / qla_sup.c
blob6d6c02129a5337059b2e0d61561787248c7eefae
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10 #include <linux/vmalloc.h>
11 #include <asm/uaccess.h>
12
13 /*
14 * NVRAM support routines
15 */
16
17 /**
18 * qla2x00_lock_nvram_access() -
19 * @ha: HA context
20 */
21 static void
22 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
23 {
24 uint16_t data;
25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
26
27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
28 data = RD_REG_WORD(&reg->nvram);
29 while (data & NVR_BUSY) {
30 udelay(100);
31 data = RD_REG_WORD(&reg->nvram);
32 }
33
34 /* Lock resource */
35 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
36 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
37 udelay(5);
38 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
39 while ((data & BIT_0) == 0) {
40 /* Lock failed */
41 udelay(100);
42 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
43 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
44 udelay(5);
45 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
46 }
47 }
48 }
49
50 /**
51 * qla2x00_unlock_nvram_access() -
52 * @ha: HA context
53 */
54 static void
55 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
56 {
57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
58
59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
60 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
61 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
62 }
63 }
64
65 /**
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
67 * @ha: HA context
68 * @data: Serial interface selector
69 */
70 static void
71 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
72 {
73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
74
75 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
76 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
77 NVRAM_DELAY();
78 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
79 NVR_WRT_ENABLE);
80 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
81 NVRAM_DELAY();
82 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
83 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
84 NVRAM_DELAY();
85 }
86
87 /**
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
89 * NVRAM.
90 * @ha: HA context
91 * @nv_cmd: NVRAM command
92 *
93 * Bit definitions for NVRAM command:
94 *
95 * Bit 26 = start bit
96 * Bit 25, 24 = opcode
97 * Bit 23-16 = address
98 * Bit 15-0 = write data
99 *
100 * Returns the word read from nvram @addr.
101 */
102 static uint16_t
103 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
104 {
105 uint8_t cnt;
106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
107 uint16_t data = 0;
108 uint16_t reg_data;
109
110 /* Send command to NVRAM. */
111 nv_cmd <<= 5;
112 for (cnt = 0; cnt < 11; cnt++) {
113 if (nv_cmd & BIT_31)
114 qla2x00_nv_write(ha, NVR_DATA_OUT);
115 else
116 qla2x00_nv_write(ha, 0);
117 nv_cmd <<= 1;
118 }
119
120 /* Read data from NVRAM. */
121 for (cnt = 0; cnt < 16; cnt++) {
122 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
123 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
124 NVRAM_DELAY();
125 data <<= 1;
126 reg_data = RD_REG_WORD(&reg->nvram);
127 if (reg_data & NVR_DATA_IN)
128 data |= BIT_0;
129 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
130 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
131 NVRAM_DELAY();
132 }
133
134 /* Deselect chip. */
135 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
136 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
137 NVRAM_DELAY();
138
139 return data;
140 }
141
142
143 /**
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145 * request routine to get the word from NVRAM.
146 * @ha: HA context
147 * @addr: Address in NVRAM to read
148 *
149 * Returns the word read from nvram @addr.
150 */
151 static uint16_t
152 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
153 {
154 uint16_t data;
155 uint32_t nv_cmd;
156
157 nv_cmd = addr << 16;
158 nv_cmd |= NV_READ_OP;
159 data = qla2x00_nvram_request(ha, nv_cmd);
160
161 return (data);
162 }
163
164 /**
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
166 * @ha: HA context
167 */
168 static void
169 qla2x00_nv_deselect(struct qla_hw_data *ha)
170 {
171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
172
173 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
174 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
175 NVRAM_DELAY();
176 }
177
178 /**
179 * qla2x00_write_nvram_word() - Write NVRAM data.
180 * @ha: HA context
181 * @addr: Address in NVRAM to write
182 * @data: word to program
183 */
184 static void
185 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
186 {
187 int count;
188 uint16_t word;
189 uint32_t nv_cmd, wait_cnt;
190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
191
192 qla2x00_nv_write(ha, NVR_DATA_OUT);
193 qla2x00_nv_write(ha, 0);
194 qla2x00_nv_write(ha, 0);
195
196 for (word = 0; word < 8; word++)
197 qla2x00_nv_write(ha, NVR_DATA_OUT);
198
199 qla2x00_nv_deselect(ha);
200
201 /* Write data */
202 nv_cmd = (addr << 16) | NV_WRITE_OP;
203 nv_cmd |= data;
204 nv_cmd <<= 5;
205 for (count = 0; count < 27; count++) {
206 if (nv_cmd & BIT_31)
207 qla2x00_nv_write(ha, NVR_DATA_OUT);
208 else
209 qla2x00_nv_write(ha, 0);
210
211 nv_cmd <<= 1;
212 }
213
214 qla2x00_nv_deselect(ha);
215
216 /* Wait for NVRAM to become ready */
217 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
218 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
219 wait_cnt = NVR_WAIT_CNT;
220 do {
221 if (!--wait_cnt) {
222 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
223 __func__, vha->host_no));
224 break;
225 }
226 NVRAM_DELAY();
227 word = RD_REG_WORD(&reg->nvram);
228 } while ((word & NVR_DATA_IN) == 0);
229
230 qla2x00_nv_deselect(ha);
231
232 /* Disable writes */
233 qla2x00_nv_write(ha, NVR_DATA_OUT);
234 for (count = 0; count < 10; count++)
235 qla2x00_nv_write(ha, 0);
236
237 qla2x00_nv_deselect(ha);
238 }
239
240 static int
241 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
242 uint16_t data, uint32_t tmo)
243 {
244 int ret, count;
245 uint16_t word;
246 uint32_t nv_cmd;
247 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
248
249 ret = QLA_SUCCESS;
250
251 qla2x00_nv_write(ha, NVR_DATA_OUT);
252 qla2x00_nv_write(ha, 0);
253 qla2x00_nv_write(ha, 0);
254
255 for (word = 0; word < 8; word++)
256 qla2x00_nv_write(ha, NVR_DATA_OUT);
257
258 qla2x00_nv_deselect(ha);
259
260 /* Write data */
261 nv_cmd = (addr << 16) | NV_WRITE_OP;
262 nv_cmd |= data;
263 nv_cmd <<= 5;
264 for (count = 0; count < 27; count++) {
265 if (nv_cmd & BIT_31)
266 qla2x00_nv_write(ha, NVR_DATA_OUT);
267 else
268 qla2x00_nv_write(ha, 0);
269
270 nv_cmd <<= 1;
271 }
272
273 qla2x00_nv_deselect(ha);
274
275 /* Wait for NVRAM to become ready */
276 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
277 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
278 do {
279 NVRAM_DELAY();
280 word = RD_REG_WORD(&reg->nvram);
281 if (!--tmo) {
282 ret = QLA_FUNCTION_FAILED;
283 break;
284 }
285 } while ((word & NVR_DATA_IN) == 0);
286
287 qla2x00_nv_deselect(ha);
288
289 /* Disable writes */
290 qla2x00_nv_write(ha, NVR_DATA_OUT);
291 for (count = 0; count < 10; count++)
292 qla2x00_nv_write(ha, 0);
293
294 qla2x00_nv_deselect(ha);
295
296 return ret;
297 }
298
299 /**
300 * qla2x00_clear_nvram_protection() -
301 * @ha: HA context
302 */
303 static int
304 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
305 {
306 int ret, stat;
307 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
308 uint32_t word, wait_cnt;
309 uint16_t wprot, wprot_old;
310
311 /* Clear NVRAM write protection. */
312 ret = QLA_FUNCTION_FAILED;
313
314 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
315 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
316 __constant_cpu_to_le16(0x1234), 100000);
317 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 if (stat != QLA_SUCCESS || wprot != 0x1234) {
319 /* Write enable. */
320 qla2x00_nv_write(ha, NVR_DATA_OUT);
321 qla2x00_nv_write(ha, 0);
322 qla2x00_nv_write(ha, 0);
323 for (word = 0; word < 8; word++)
324 qla2x00_nv_write(ha, NVR_DATA_OUT);
325
326 qla2x00_nv_deselect(ha);
327
328 /* Enable protection register. */
329 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
330 qla2x00_nv_write(ha, NVR_PR_ENABLE);
331 qla2x00_nv_write(ha, NVR_PR_ENABLE);
332 for (word = 0; word < 8; word++)
333 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
334
335 qla2x00_nv_deselect(ha);
336
337 /* Clear protection register (ffff is cleared). */
338 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
339 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 for (word = 0; word < 8; word++)
342 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
343
344 qla2x00_nv_deselect(ha);
345
346 /* Wait for NVRAM to become ready. */
347 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
348 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
349 wait_cnt = NVR_WAIT_CNT;
350 do {
351 if (!--wait_cnt) {
352 DEBUG9_10(qla_printk(
353 "NVRAM didn't go ready...\n"));
354 break;
355 }
356 NVRAM_DELAY();
357 word = RD_REG_WORD(&reg->nvram);
358 } while ((word & NVR_DATA_IN) == 0);
359
360 if (wait_cnt)
361 ret = QLA_SUCCESS;
362 } else
363 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
364
365 return ret;
366 }
367
368 static void
369 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
370 {
371 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
372 uint32_t word, wait_cnt;
373
374 if (stat != QLA_SUCCESS)
375 return;
376
377 /* Set NVRAM write protection. */
378 /* Write enable. */
379 qla2x00_nv_write(ha, NVR_DATA_OUT);
380 qla2x00_nv_write(ha, 0);
381 qla2x00_nv_write(ha, 0);
382 for (word = 0; word < 8; word++)
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384
385 qla2x00_nv_deselect(ha);
386
387 /* Enable protection register. */
388 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
389 qla2x00_nv_write(ha, NVR_PR_ENABLE);
390 qla2x00_nv_write(ha, NVR_PR_ENABLE);
391 for (word = 0; word < 8; word++)
392 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
393
394 qla2x00_nv_deselect(ha);
395
396 /* Enable protection register. */
397 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
398 qla2x00_nv_write(ha, NVR_PR_ENABLE);
399 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
400 for (word = 0; word < 8; word++)
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402
403 qla2x00_nv_deselect(ha);
404
405 /* Wait for NVRAM to become ready. */
406 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
407 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
408 wait_cnt = NVR_WAIT_CNT;
409 do {
410 if (!--wait_cnt) {
411 DEBUG9_10(qla_printk("NVRAM didn't go ready...\n"));
412 break;
413 }
414 NVRAM_DELAY();
415 word = RD_REG_WORD(&reg->nvram);
416 } while ((word & NVR_DATA_IN) == 0);
417 }
418
419
420 /*****************************************************************************/
421 /* Flash Manipulation Routines */
422 /*****************************************************************************/
423
424 #define OPTROM_BURST_SIZE 0x1000
425 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
426
427 static inline uint32_t
428 flash_conf_to_access_addr(uint32_t faddr)
429 {
430 return FARX_ACCESS_FLASH_CONF | faddr;
431 }
432
433 static inline uint32_t
434 flash_data_to_access_addr(uint32_t faddr)
435 {
436 return FARX_ACCESS_FLASH_DATA | faddr;
437 }
438
439 static inline uint32_t
440 nvram_conf_to_access_addr(uint32_t naddr)
441 {
442 return FARX_ACCESS_NVRAM_CONF | naddr;
443 }
444
445 static inline uint32_t
446 nvram_data_to_access_addr(uint32_t naddr)
447 {
448 return FARX_ACCESS_NVRAM_DATA | naddr;
449 }
450
451 static uint32_t
452 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
453 {
454 int rval;
455 uint32_t cnt, data;
456 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
457
458 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
459 /* Wait for READ cycle to complete. */
460 rval = QLA_SUCCESS;
461 for (cnt = 3000;
462 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
463 rval == QLA_SUCCESS; cnt--) {
464 if (cnt)
465 udelay(10);
466 else
467 rval = QLA_FUNCTION_TIMEOUT;
468 cond_resched();
469 }
470
471 /* TODO: What happens if we time out? */
472 data = 0xDEADDEAD;
473 if (rval == QLA_SUCCESS)
474 data = RD_REG_DWORD(&reg->flash_data);
475
476 return data;
477 }
478
479 uint32_t *
480 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
481 uint32_t dwords)
482 {
483 uint32_t i;
484 /* Dword reads to flash. */
485 for (i = 0; i < dwords; i++, faddr++)
486 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(vha->hw,
487 flash_data_to_access_addr(faddr)));
488
489 return dwptr;
490 }
491
492 static int
493 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
494 {
495 int rval;
496 uint32_t cnt;
497 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
498
499 WRT_REG_DWORD(&reg->flash_data, data);
500 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
501 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
502 /* Wait for Write cycle to complete. */
503 rval = QLA_SUCCESS;
504 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
505 rval == QLA_SUCCESS; cnt--) {
506 if (cnt)
507 udelay(10);
508 else
509 rval = QLA_FUNCTION_TIMEOUT;
510 cond_resched();
511 }
512 return rval;
513 }
514
515 static void
516 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
517 uint8_t *flash_id)
518 {
519 uint32_t ids;
520
521 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
522 *man_id = LSB(ids);
523 *flash_id = MSB(ids);
524
525 /* Check if man_id and flash_id are valid. */
526 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
527 /* Read information using 0x9f opcode
528 * Device ID, Mfg ID would be read in the format:
529 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
530 * Example: ATMEL 0x00 01 45 1F
531 * Extract MFG and Dev ID from last two bytes.
532 */
533 ids = qla24xx_read_flash_dword(ha,
534 flash_data_to_access_addr(0xd009f));
535 *man_id = LSB(ids);
536 *flash_id = MSB(ids);
537 }
538 }
539
540 static int
541 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
542 {
543 const char *loc, *locations[] = { "DEF", "PCI" };
544 uint32_t pcihdr, pcids;
545 uint32_t *dcode;
546 uint8_t *buf, *bcode, last_image;
547 uint16_t cnt, chksum, *wptr;
548 struct qla_flt_location *fltl;
549 struct qla_hw_data *ha = vha->hw;
550 struct req_que *req = ha->req;
551
552 /*
553 * FLT-location structure resides after the last PCI region.
554 */
555
556 /* Begin with sane defaults. */
557 loc = locations[0];
558 *start = IS_QLA24XX_TYPE(ha) ? FA_FLASH_LAYOUT_ADDR_24:
559 FA_FLASH_LAYOUT_ADDR;
560
561 /* Begin with first PCI expansion ROM header. */
562 buf = (uint8_t *)req->ring;
563 dcode = (uint32_t *)req->ring;
564 pcihdr = 0;
565 last_image = 1;
566 do {
567 /* Verify PCI expansion ROM header. */
568 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
569 bcode = buf + (pcihdr % 4);
570 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
571 goto end;
572
573 /* Locate PCI data structure. */
574 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
575 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
576 bcode = buf + (pcihdr % 4);
577
578 /* Validate signature of PCI data structure. */
579 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
580 bcode[0x2] != 'I' || bcode[0x3] != 'R')
581 goto end;
582
583 last_image = bcode[0x15] & BIT_7;
584
585 /* Locate next PCI expansion ROM. */
586 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
587 } while (!last_image);
588
589 /* Now verify FLT-location structure. */
590 fltl = (struct qla_flt_location *)req->ring;
591 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
592 sizeof(struct qla_flt_location) >> 2);
593 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
594 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
595 goto end;
596
597 wptr = (uint16_t *)req->ring;
598 cnt = sizeof(struct qla_flt_location) >> 1;
599 for (chksum = 0; cnt; cnt--)
600 chksum += le16_to_cpu(*wptr++);
601 if (chksum) {
602 qla_printk(KERN_ERR, ha,
603 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
604 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
605 return QLA_FUNCTION_FAILED;
606 }
607
608 /* Good data. Use specified location. */
609 loc = locations[1];
610 *start = le16_to_cpu(fltl->start_hi) << 16 |
611 le16_to_cpu(fltl->start_lo);
612 end:
613 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
614 return QLA_SUCCESS;
615 }
616
617 static void
618 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
619 {
620 const char *loc, *locations[] = { "DEF", "FLT" };
621 uint16_t *wptr;
622 uint16_t cnt, chksum;
623 uint32_t start;
624 struct qla_flt_header *flt;
625 struct qla_flt_region *region;
626 struct qla_hw_data *ha = vha->hw;
627 struct req_que *req = ha->req;
628
629 ha->flt_region_flt = flt_addr;
630 wptr = (uint16_t *)req->ring;
631 flt = (struct qla_flt_header *)req->ring;
632 region = (struct qla_flt_region *)&flt[1];
633 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
634 flt_addr << 2, OPTROM_BURST_SIZE);
635 if (*wptr == __constant_cpu_to_le16(0xffff))
636 goto no_flash_data;
637 if (flt->version != __constant_cpu_to_le16(1)) {
638 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
639 "version=0x%x length=0x%x checksum=0x%x.\n",
640 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
641 le16_to_cpu(flt->checksum)));
642 goto no_flash_data;
643 }
644
645 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
646 for (chksum = 0; cnt; cnt--)
647 chksum += le16_to_cpu(*wptr++);
648 if (chksum) {
649 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
650 "version=0x%x length=0x%x checksum=0x%x.\n",
651 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
652 chksum));
653 goto no_flash_data;
654 }
655
656 loc = locations[1];
657 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
658 for ( ; cnt; cnt--, region++) {
659 /* Store addresses as DWORD offsets. */
660 start = le32_to_cpu(region->start) >> 2;
661
662 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
663 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
664 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
665
666 switch (le32_to_cpu(region->code)) {
667 case FLT_REG_FW:
668 ha->flt_region_fw = start;
669 break;
670 case FLT_REG_BOOT_CODE:
671 ha->flt_region_boot = start;
672 break;
673 case FLT_REG_VPD_0:
674 ha->flt_region_vpd_nvram = start;
675 break;
676 case FLT_REG_FDT:
677 ha->flt_region_fdt = start;
678 break;
679 case FLT_REG_HW_EVENT_0:
680 if (!PCI_FUNC(ha->pdev->devfn))
681 ha->flt_region_hw_event = start;
682 break;
683 case FLT_REG_HW_EVENT_1:
684 if (PCI_FUNC(ha->pdev->devfn))
685 ha->flt_region_hw_event = start;
686 break;
687 case FLT_REG_NPIV_CONF_0:
688 if (!PCI_FUNC(ha->pdev->devfn))
689 ha->flt_region_npiv_conf = start;
690 break;
691 case FLT_REG_NPIV_CONF_1:
692 if (PCI_FUNC(ha->pdev->devfn))
693 ha->flt_region_npiv_conf = start;
694 break;
695 }
696 }
697 goto done;
698
699 no_flash_data:
700 /* Use hardcoded defaults. */
701 loc = locations[0];
702 ha->flt_region_fw = FA_RISC_CODE_ADDR;
703 ha->flt_region_boot = FA_BOOT_CODE_ADDR;
704 ha->flt_region_vpd_nvram = FA_VPD_NVRAM_ADDR;
705 ha->flt_region_fdt = IS_QLA24XX_TYPE(ha) ? FA_FLASH_DESCR_ADDR_24:
706 FA_FLASH_DESCR_ADDR;
707 ha->flt_region_hw_event = !PCI_FUNC(ha->pdev->devfn) ?
708 FA_HW_EVENT0_ADDR: FA_HW_EVENT1_ADDR;
709 ha->flt_region_npiv_conf = !PCI_FUNC(ha->pdev->devfn) ?
710 (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF0_ADDR_24: FA_NPIV_CONF0_ADDR):
711 (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF1_ADDR_24: FA_NPIV_CONF1_ADDR);
712 done:
713 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
714 "vpd_nvram=0x%x fdt=0x%x flt=0x%x hwe=0x%x npiv=0x%x.\n", loc,
715 ha->flt_region_boot, ha->flt_region_fw, ha->flt_region_vpd_nvram,
716 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_hw_event,
717 ha->flt_region_npiv_conf));
718 }
719
720 static void
721 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
722 {
723 #define FLASH_BLK_SIZE_4K 0x1000
724 #define FLASH_BLK_SIZE_32K 0x8000
725 #define FLASH_BLK_SIZE_64K 0x10000
726 const char *loc, *locations[] = { "MID", "FDT" };
727 uint16_t cnt, chksum;
728 uint16_t *wptr;
729 struct qla_fdt_layout *fdt;
730 uint8_t man_id, flash_id;
731 uint16_t mid, fid;
732 struct qla_hw_data *ha = vha->hw;
733 struct req_que *req = ha->req;
734
735 wptr = (uint16_t *)req->ring;
736 fdt = (struct qla_fdt_layout *)req->ring;
737 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
738 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
739 if (*wptr == __constant_cpu_to_le16(0xffff))
740 goto no_flash_data;
741 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
742 fdt->sig[3] != 'D')
743 goto no_flash_data;
744
745 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
746 cnt++)
747 chksum += le16_to_cpu(*wptr++);
748 if (chksum) {
749 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
750 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
751 le16_to_cpu(fdt->version)));
752 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
753 goto no_flash_data;
754 }
755
756 loc = locations[1];
757 mid = le16_to_cpu(fdt->man_id);
758 fid = le16_to_cpu(fdt->id);
759 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
760 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0300 | fdt->erase_cmd);
761 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
762 if (fdt->unprotect_sec_cmd) {
763 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0300 |
764 fdt->unprotect_sec_cmd);
765 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
766 flash_conf_to_access_addr(0x0300 | fdt->protect_sec_cmd):
767 flash_conf_to_access_addr(0x0336);
768 }
769 goto done;
770 no_flash_data:
771 loc = locations[0];
772 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
773 mid = man_id;
774 fid = flash_id;
775 ha->fdt_wrt_disable = 0x9c;
776 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x03d8);
777 switch (man_id) {
778 case 0xbf: /* STT flash. */
779 if (flash_id == 0x8e)
780 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
781 else
782 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
783
784 if (flash_id == 0x80)
785 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0352);
786 break;
787 case 0x13: /* ST M25P80. */
788 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
789 break;
790 case 0x1f: /* Atmel 26DF081A. */
791 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
792 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0320);
793 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0339);
794 ha->fdt_protect_sec_cmd = flash_conf_to_access_addr(0x0336);
795 break;
796 default:
797 /* Default to 64 kb sector size. */
798 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
799 break;
800 }
801 done:
802 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
803 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
804 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
805 ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
806 ha->fdt_block_size));
807 }
808
809 int
810 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
811 {
812 int ret;
813 uint32_t flt_addr;
814 struct qla_hw_data *ha = vha->hw;
815
816 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
817 return QLA_SUCCESS;
818
819 ret = qla2xxx_find_flt_start(vha, &flt_addr);
820 if (ret != QLA_SUCCESS)
821 return ret;
822
823 qla2xxx_get_flt_info(vha, flt_addr);
824 qla2xxx_get_fdt_info(vha);
825
826 return QLA_SUCCESS;
827 }
828
829 void
830 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
831 {
832 #define NPIV_CONFIG_SIZE (16*1024)
833 void *data;
834 uint16_t *wptr;
835 uint16_t cnt, chksum;
836 struct qla_npiv_header hdr;
837 struct qla_npiv_entry *entry;
838 struct qla_hw_data *ha = vha->hw;
839
840 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
841 return;
842
843 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
844 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
845 if (hdr.version == __constant_cpu_to_le16(0xffff))
846 return;
847 if (hdr.version != __constant_cpu_to_le16(1)) {
848 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
849 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
850 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
851 le16_to_cpu(hdr.checksum)));
852 return;
853 }
854
855 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
856 if (!data) {
857 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
858 "allocate memory.\n"));
859 return;
860 }
861
862 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
863 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
864
865 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
866 sizeof(struct qla_npiv_entry)) >> 1;
867 for (wptr = data, chksum = 0; cnt; cnt--)
868 chksum += le16_to_cpu(*wptr++);
869 if (chksum) {
870 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
871 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
872 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
873 chksum));
874 goto done;
875 }
876
877 entry = data + sizeof(struct qla_npiv_header);
878 cnt = le16_to_cpu(hdr.entries);
879 for ( ; cnt; cnt--, entry++) {
880 uint16_t flags;
881 struct fc_vport_identifiers vid;
882 struct fc_vport *vport;
883
884 flags = le16_to_cpu(entry->flags);
885 if (flags == 0xffff)
886 continue;
887 if ((flags & BIT_0) == 0)
888 continue;
889
890 memset(&vid, 0, sizeof(vid));
891 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
892 vid.vport_type = FC_PORTTYPE_NPIV;
893 vid.disable = false;
894 vid.port_name = wwn_to_u64(entry->port_name);
895 vid.node_name = wwn_to_u64(entry->node_name);
896
897 DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx "
898 "wwnn=%llx vf_id=0x%x qos=0x%x.\n", cnt, vid.port_name,
899 vid.node_name, le16_to_cpu(entry->vf_id),
900 le16_to_cpu(entry->qos)));
901
902 vport = fc_vport_create(vha->host, 0, &vid);
903 if (!vport)
904 qla_printk(KERN_INFO, ha, "NPIV-Config: Failed to "
905 "create vport [%02x]: wwpn=%llx wwnn=%llx.\n", cnt,
906 vid.port_name, vid.node_name);
907 }
908 done:
909 kfree(data);
910 }
911
912 static void
913 qla24xx_unprotect_flash(struct qla_hw_data *ha)
914 {
915 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
916
917 /* Enable flash write. */
918 WRT_REG_DWORD(&reg->ctrl_status,
919 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
920 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
921
922 if (!ha->fdt_wrt_disable)
923 return;
924
925 /* Disable flash write-protection. */
926 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
927 /* Some flash parts need an additional zero-write to clear bits.*/
928 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
929 }
930
931 static void
932 qla24xx_protect_flash(struct qla_hw_data *ha)
933 {
934 uint32_t cnt;
935 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
936
937 if (!ha->fdt_wrt_disable)
938 goto skip_wrt_protect;
939
940 /* Enable flash write-protection and wait for completion. */
941 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101),
942 ha->fdt_wrt_disable);
943 for (cnt = 300; cnt &&
944 qla24xx_read_flash_dword(ha,
945 flash_conf_to_access_addr(0x005)) & BIT_0;
946 cnt--) {
947 udelay(10);
948 }
949
950 skip_wrt_protect:
951 /* Disable flash write. */
952 WRT_REG_DWORD(&reg->ctrl_status,
953 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
954 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
955 }
956
957 static int
958 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
959 uint32_t dwords)
960 {
961 int ret;
962 uint32_t liter, miter;
963 uint32_t sec_mask, rest_addr;
964 uint32_t fdata, findex;
965 dma_addr_t optrom_dma;
966 void *optrom = NULL;
967 uint32_t *s, *d;
968 struct qla_hw_data *ha = vha->hw;
969
970 ret = QLA_SUCCESS;
971
972 /* Prepare burst-capable write on supported ISPs. */
973 if (IS_QLA25XX(ha) && !(faddr & 0xfff) &&
974 dwords > OPTROM_BURST_DWORDS) {
975 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
976 &optrom_dma, GFP_KERNEL);
977 if (!optrom) {
978 qla_printk(KERN_DEBUG, ha,
979 "Unable to allocate memory for optrom burst write "
980 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
981 }
982 }
983
984 rest_addr = (ha->fdt_block_size >> 2) - 1;
985 sec_mask = 0x80000 - (ha->fdt_block_size >> 2);
986
987 qla24xx_unprotect_flash(ha);
988
989 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
990
991 findex = faddr;
992 fdata = (findex & sec_mask) << 2;
993
994 /* Are we at the beginning of a sector? */
995 if ((findex & rest_addr) == 0) {
996 /* Do sector unprotect. */
997 if (ha->fdt_unprotect_sec_cmd)
998 qla24xx_write_flash_dword(ha,
999 ha->fdt_unprotect_sec_cmd,
1000 (fdata & 0xff00) | ((fdata << 16) &
1001 0xff0000) | ((fdata >> 16) & 0xff));
1002 ret = qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1003 (fdata & 0xff00) |((fdata << 16) &
1004 0xff0000) | ((fdata >> 16) & 0xff));
1005 if (ret != QLA_SUCCESS) {
1006 DEBUG9(qla_printk("Unable to flash sector: "
1007 "address=%x.\n", faddr));
1008 break;
1009 }
1010 }
1011
1012 /* Go with burst-write. */
1013 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1014 /* Copy data to DMA'ble buffer. */
1015 for (miter = 0, s = optrom, d = dwptr;
1016 miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
1017 *s = cpu_to_le32(*d);
1018
1019 ret = qla2x00_load_ram(vha, optrom_dma,
1020 flash_data_to_access_addr(faddr),
1021 OPTROM_BURST_DWORDS);
1022 if (ret != QLA_SUCCESS) {
1023 qla_printk(KERN_WARNING, ha,
1024 "Unable to burst-write optrom segment "
1025 "(%x/%x/%llx).\n", ret,
1026 flash_data_to_access_addr(faddr),
1027 (unsigned long long)optrom_dma);
1028 qla_printk(KERN_WARNING, ha,
1029 "Reverting to slow-write.\n");
1030
1031 dma_free_coherent(&ha->pdev->dev,
1032 OPTROM_BURST_SIZE, optrom, optrom_dma);
1033 optrom = NULL;
1034 } else {
1035 liter += OPTROM_BURST_DWORDS - 1;
1036 faddr += OPTROM_BURST_DWORDS - 1;
1037 dwptr += OPTROM_BURST_DWORDS - 1;
1038 continue;
1039 }
1040 }
1041
1042 ret = qla24xx_write_flash_dword(ha,
1043 flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr));
1044 if (ret != QLA_SUCCESS) {
1045 DEBUG9(printk("%s(%ld) Unable to program flash "
1046 "address=%x data=%x.\n", __func__,
1047 vha->host_no, faddr, *dwptr));
1048 break;
1049 }
1050
1051 /* Do sector protect. */
1052 if (ha->fdt_unprotect_sec_cmd &&
1053 ((faddr & rest_addr) == rest_addr))
1054 qla24xx_write_flash_dword(ha,
1055 ha->fdt_protect_sec_cmd,
1056 (fdata & 0xff00) | ((fdata << 16) &
1057 0xff0000) | ((fdata >> 16) & 0xff));
1058 }
1059
1060 qla24xx_protect_flash(ha);
1061
1062 if (optrom)
1063 dma_free_coherent(&ha->pdev->dev,
1064 OPTROM_BURST_SIZE, optrom, optrom_dma);
1065
1066 return ret;
1067 }
1068
1069 uint8_t *
1070 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1071 uint32_t bytes)
1072 {
1073 uint32_t i;
1074 uint16_t *wptr;
1075 struct qla_hw_data *ha = vha->hw;
1076
1077 /* Word reads to NVRAM via registers. */
1078 wptr = (uint16_t *)buf;
1079 qla2x00_lock_nvram_access(ha);
1080 for (i = 0; i < bytes >> 1; i++, naddr++)
1081 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1082 naddr));
1083 qla2x00_unlock_nvram_access(ha);
1084
1085 return buf;
1086 }
1087
1088 uint8_t *
1089 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1090 uint32_t bytes)
1091 {
1092 uint32_t i;
1093 uint32_t *dwptr;
1094
1095 /* Dword reads to flash. */
1096 dwptr = (uint32_t *)buf;
1097 for (i = 0; i < bytes >> 2; i++, naddr++)
1098 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(vha->hw,
1099 nvram_data_to_access_addr(naddr)));
1100
1101 return buf;
1102 }
1103
1104 int
1105 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1106 uint32_t bytes)
1107 {
1108 int ret, stat;
1109 uint32_t i;
1110 uint16_t *wptr;
1111 unsigned long flags;
1112 struct qla_hw_data *ha = vha->hw;
1113
1114 ret = QLA_SUCCESS;
1115
1116 spin_lock_irqsave(&ha->hardware_lock, flags);
1117 qla2x00_lock_nvram_access(ha);
1118
1119 /* Disable NVRAM write-protection. */
1120 stat = qla2x00_clear_nvram_protection(ha);
1121
1122 wptr = (uint16_t *)buf;
1123 for (i = 0; i < bytes >> 1; i++, naddr++) {
1124 qla2x00_write_nvram_word(ha, naddr,
1125 cpu_to_le16(*wptr));
1126 wptr++;
1127 }
1128
1129 /* Enable NVRAM write-protection. */
1130 qla2x00_set_nvram_protection(ha, stat);
1131
1132 qla2x00_unlock_nvram_access(ha);
1133 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1134
1135 return ret;
1136 }
1137
1138 int
1139 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1140 uint32_t bytes)
1141 {
1142 int ret;
1143 uint32_t i;
1144 uint32_t *dwptr;
1145 struct qla_hw_data *ha = vha->hw;
1146 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1147
1148 ret = QLA_SUCCESS;
1149
1150 /* Enable flash write. */
1151 WRT_REG_DWORD(&reg->ctrl_status,
1152 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1153 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1154
1155 /* Disable NVRAM write-protection. */
1156 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1157 0);
1158 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1159 0);
1160
1161 /* Dword writes to flash. */
1162 dwptr = (uint32_t *)buf;
1163 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1164 ret = qla24xx_write_flash_dword(ha,
1165 nvram_data_to_access_addr(naddr),
1166 cpu_to_le32(*dwptr));
1167 if (ret != QLA_SUCCESS) {
1168 DEBUG9(qla_printk("Unable to program nvram address=%x "
1169 "data=%x.\n", naddr, *dwptr));
1170 break;
1171 }
1172 }
1173
1174 /* Enable NVRAM write-protection. */
1175 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1176 0x8c);
1177
1178 /* Disable flash write. */
1179 WRT_REG_DWORD(&reg->ctrl_status,
1180 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1181 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1182
1183 return ret;
1184 }
1185
1186 uint8_t *
1187 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1188 uint32_t bytes)
1189 {
1190 uint32_t i;
1191 uint32_t *dwptr;
1192 struct qla_hw_data *ha = vha->hw;
1193
1194 /* Dword reads to flash. */
1195 dwptr = (uint32_t *)buf;
1196 for (i = 0; i < bytes >> 2; i++, naddr++)
1197 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1198 flash_data_to_access_addr(ha->flt_region_vpd_nvram |
1199 naddr)));
1200
1201 return buf;
1202 }
1203
1204 int
1205 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1206 uint32_t bytes)
1207 {
1208 struct qla_hw_data *ha = vha->hw;
1209 #define RMW_BUFFER_SIZE (64 * 1024)
1210 uint8_t *dbuf;
1211
1212 dbuf = vmalloc(RMW_BUFFER_SIZE);
1213 if (!dbuf)
1214 return QLA_MEMORY_ALLOC_FAILED;
1215 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1216 RMW_BUFFER_SIZE);
1217 memcpy(dbuf + (naddr << 2), buf, bytes);
1218 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1219 RMW_BUFFER_SIZE);
1220 vfree(dbuf);
1221
1222 return QLA_SUCCESS;
1223 }
1224
1225 static inline void
1226 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1227 {
1228 if (IS_QLA2322(ha)) {
1229 /* Flip all colors. */
1230 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1231 /* Turn off. */
1232 ha->beacon_color_state = 0;
1233 *pflags = GPIO_LED_ALL_OFF;
1234 } else {
1235 /* Turn on. */
1236 ha->beacon_color_state = QLA_LED_ALL_ON;
1237 *pflags = GPIO_LED_RGA_ON;
1238 }
1239 } else {
1240 /* Flip green led only. */
1241 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1242 /* Turn off. */
1243 ha->beacon_color_state = 0;
1244 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1245 } else {
1246 /* Turn on. */
1247 ha->beacon_color_state = QLA_LED_GRN_ON;
1248 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1249 }
1250 }
1251 }
1252
1253 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1254
1255 void
1256 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1257 {
1258 uint16_t gpio_enable;
1259 uint16_t gpio_data;
1260 uint16_t led_color = 0;
1261 unsigned long flags;
1262 struct qla_hw_data *ha = vha->hw;
1263 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1264
1265 spin_lock_irqsave(&ha->hardware_lock, flags);
1266
1267 /* Save the Original GPIOE. */
1268 if (ha->pio_address) {
1269 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1270 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1271 } else {
1272 gpio_enable = RD_REG_WORD(&reg->gpioe);
1273 gpio_data = RD_REG_WORD(&reg->gpiod);
1274 }
1275
1276 /* Set the modified gpio_enable values */
1277 gpio_enable |= GPIO_LED_MASK;
1278
1279 if (ha->pio_address) {
1280 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1281 } else {
1282 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1283 RD_REG_WORD(&reg->gpioe);
1284 }
1285
1286 qla2x00_flip_colors(ha, &led_color);
1287
1288 /* Clear out any previously set LED color. */
1289 gpio_data &= ~GPIO_LED_MASK;
1290
1291 /* Set the new input LED color to GPIOD. */
1292 gpio_data |= led_color;
1293
1294 /* Set the modified gpio_data values */
1295 if (ha->pio_address) {
1296 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1297 } else {
1298 WRT_REG_WORD(&reg->gpiod, gpio_data);
1299 RD_REG_WORD(&reg->gpiod);
1300 }
1301
1302 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1303 }
1304
1305 int
1306 qla2x00_beacon_on(struct scsi_qla_host *vha)
1307 {
1308 uint16_t gpio_enable;
1309 uint16_t gpio_data;
1310 unsigned long flags;
1311 struct qla_hw_data *ha = vha->hw;
1312 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1313
1314 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1315 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1316
1317 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1318 qla_printk(KERN_WARNING, ha,
1319 "Unable to update fw options (beacon on).\n");
1320 return QLA_FUNCTION_FAILED;
1321 }
1322
1323 /* Turn off LEDs. */
1324 spin_lock_irqsave(&ha->hardware_lock, flags);
1325 if (ha->pio_address) {
1326 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1327 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1328 } else {
1329 gpio_enable = RD_REG_WORD(&reg->gpioe);
1330 gpio_data = RD_REG_WORD(&reg->gpiod);
1331 }
1332 gpio_enable |= GPIO_LED_MASK;
1333
1334 /* Set the modified gpio_enable values. */
1335 if (ha->pio_address) {
1336 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1337 } else {
1338 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1339 RD_REG_WORD(&reg->gpioe);
1340 }
1341
1342 /* Clear out previously set LED colour. */
1343 gpio_data &= ~GPIO_LED_MASK;
1344 if (ha->pio_address) {
1345 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1346 } else {
1347 WRT_REG_WORD(&reg->gpiod, gpio_data);
1348 RD_REG_WORD(&reg->gpiod);
1349 }
1350 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1351
1352 /*
1353 * Let the per HBA timer kick off the blinking process based on
1354 * the following flags. No need to do anything else now.
1355 */
1356 ha->beacon_blink_led = 1;
1357 ha->beacon_color_state = 0;
1358
1359 return QLA_SUCCESS;
1360 }
1361
1362 int
1363 qla2x00_beacon_off(struct scsi_qla_host *vha)
1364 {
1365 int rval = QLA_SUCCESS;
1366 struct qla_hw_data *ha = vha->hw;
1367
1368 ha->beacon_blink_led = 0;
1369
1370 /* Set the on flag so when it gets flipped it will be off. */
1371 if (IS_QLA2322(ha))
1372 ha->beacon_color_state = QLA_LED_ALL_ON;
1373 else
1374 ha->beacon_color_state = QLA_LED_GRN_ON;
1375
1376 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1377
1378 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1379 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1380
1381 rval = qla2x00_set_fw_options(vha, ha->fw_options);
1382 if (rval != QLA_SUCCESS)
1383 qla_printk(KERN_WARNING, ha,
1384 "Unable to update fw options (beacon off).\n");
1385 return rval;
1386 }
1387
1388
1389 static inline void
1390 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1391 {
1392 /* Flip all colors. */
1393 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1394 /* Turn off. */
1395 ha->beacon_color_state = 0;
1396 *pflags = 0;
1397 } else {
1398 /* Turn on. */
1399 ha->beacon_color_state = QLA_LED_ALL_ON;
1400 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1401 }
1402 }
1403
1404 void
1405 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1406 {
1407 uint16_t led_color = 0;
1408 uint32_t gpio_data;
1409 unsigned long flags;
1410 struct qla_hw_data *ha = vha->hw;
1411 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1412
1413 /* Save the Original GPIOD. */
1414 spin_lock_irqsave(&ha->hardware_lock, flags);
1415 gpio_data = RD_REG_DWORD(&reg->gpiod);
1416
1417 /* Enable the gpio_data reg for update. */
1418 gpio_data |= GPDX_LED_UPDATE_MASK;
1419
1420 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1421 gpio_data = RD_REG_DWORD(&reg->gpiod);
1422
1423 /* Set the color bits. */
1424 qla24xx_flip_colors(ha, &led_color);
1425
1426 /* Clear out any previously set LED color. */
1427 gpio_data &= ~GPDX_LED_COLOR_MASK;
1428
1429 /* Set the new input LED color to GPIOD. */
1430 gpio_data |= led_color;
1431
1432 /* Set the modified gpio_data values. */
1433 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1434 gpio_data = RD_REG_DWORD(&reg->gpiod);
1435 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1436 }
1437
1438 int
1439 qla24xx_beacon_on(struct scsi_qla_host *vha)
1440 {
1441 uint32_t gpio_data;
1442 unsigned long flags;
1443 struct qla_hw_data *ha = vha->hw;
1444 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1445
1446 if (ha->beacon_blink_led == 0) {
1447 /* Enable firmware for update */
1448 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1449
1450 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1451 return QLA_FUNCTION_FAILED;
1452
1453 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1454 QLA_SUCCESS) {
1455 qla_printk(KERN_WARNING, ha,
1456 "Unable to update fw options (beacon on).\n");
1457 return QLA_FUNCTION_FAILED;
1458 }
1459
1460 spin_lock_irqsave(&ha->hardware_lock, flags);
1461 gpio_data = RD_REG_DWORD(&reg->gpiod);
1462
1463 /* Enable the gpio_data reg for update. */
1464 gpio_data |= GPDX_LED_UPDATE_MASK;
1465 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1466 RD_REG_DWORD(&reg->gpiod);
1467
1468 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1469 }
1470
1471 /* So all colors blink together. */
1472 ha->beacon_color_state = 0;
1473
1474 /* Let the per HBA timer kick off the blinking process. */
1475 ha->beacon_blink_led = 1;
1476
1477 return QLA_SUCCESS;
1478 }
1479
1480 int
1481 qla24xx_beacon_off(struct scsi_qla_host *vha)
1482 {
1483 uint32_t gpio_data;
1484 unsigned long flags;
1485 struct qla_hw_data *ha = vha->hw;
1486 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1487
1488 ha->beacon_blink_led = 0;
1489 ha->beacon_color_state = QLA_LED_ALL_ON;
1490
1491 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1492
1493 /* Give control back to firmware. */
1494 spin_lock_irqsave(&ha->hardware_lock, flags);
1495 gpio_data = RD_REG_DWORD(&reg->gpiod);
1496
1497 /* Disable the gpio_data reg for update. */
1498 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1499 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1500 RD_REG_DWORD(&reg->gpiod);
1501 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1502
1503 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1504
1505 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1506 qla_printk(KERN_WARNING, ha,
1507 "Unable to update fw options (beacon off).\n");
1508 return QLA_FUNCTION_FAILED;
1509 }
1510
1511 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1512 qla_printk(KERN_WARNING, ha,
1513 "Unable to get fw options (beacon off).\n");
1514 return QLA_FUNCTION_FAILED;
1515 }
1516
1517 return QLA_SUCCESS;
1518 }
1519
1520
1521 /*
1522 * Flash support routines
1523 */
1524
1525 /**
1526 * qla2x00_flash_enable() - Setup flash for reading and writing.
1527 * @ha: HA context
1528 */
1529 static void
1530 qla2x00_flash_enable(struct qla_hw_data *ha)
1531 {
1532 uint16_t data;
1533 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1534
1535 data = RD_REG_WORD(&reg->ctrl_status);
1536 data |= CSR_FLASH_ENABLE;
1537 WRT_REG_WORD(&reg->ctrl_status, data);
1538 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1539 }
1540
1541 /**
1542 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1543 * @ha: HA context
1544 */
1545 static void
1546 qla2x00_flash_disable(struct qla_hw_data *ha)
1547 {
1548 uint16_t data;
1549 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1550
1551 data = RD_REG_WORD(&reg->ctrl_status);
1552 data &= ~(CSR_FLASH_ENABLE);
1553 WRT_REG_WORD(&reg->ctrl_status, data);
1554 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1555 }
1556
1557 /**
1558 * qla2x00_read_flash_byte() - Reads a byte from flash
1559 * @ha: HA context
1560 * @addr: Address in flash to read
1561 *
1562 * A word is read from the chip, but, only the lower byte is valid.
1563 *
1564 * Returns the byte read from flash @addr.
1565 */
1566 static uint8_t
1567 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1568 {
1569 uint16_t data;
1570 uint16_t bank_select;
1571 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1572
1573 bank_select = RD_REG_WORD(&reg->ctrl_status);
1574
1575 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1576 /* Specify 64K address range: */
1577 /* clear out Module Select and Flash Address bits [19:16]. */
1578 bank_select &= ~0xf8;
1579 bank_select |= addr >> 12 & 0xf0;
1580 bank_select |= CSR_FLASH_64K_BANK;
1581 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1582 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1583
1584 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1585 data = RD_REG_WORD(&reg->flash_data);
1586
1587 return (uint8_t)data;
1588 }
1589
1590 /* Setup bit 16 of flash address. */
1591 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1592 bank_select |= CSR_FLASH_64K_BANK;
1593 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1594 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1595 } else if (((addr & BIT_16) == 0) &&
1596 (bank_select & CSR_FLASH_64K_BANK)) {
1597 bank_select &= ~(CSR_FLASH_64K_BANK);
1598 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1599 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1600 }
1601
1602 /* Always perform IO mapped accesses to the FLASH registers. */
1603 if (ha->pio_address) {
1604 uint16_t data2;
1605
1606 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1607 do {
1608 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1609 barrier();
1610 cpu_relax();
1611 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1612 } while (data != data2);
1613 } else {
1614 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1615 data = qla2x00_debounce_register(&reg->flash_data);
1616 }
1617
1618 return (uint8_t)data;
1619 }
1620
1621 /**
1622 * qla2x00_write_flash_byte() - Write a byte to flash
1623 * @ha: HA context
1624 * @addr: Address in flash to write
1625 * @data: Data to write
1626 */
1627 static void
1628 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1629 {
1630 uint16_t bank_select;
1631 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1632
1633 bank_select = RD_REG_WORD(&reg->ctrl_status);
1634 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1635 /* Specify 64K address range: */
1636 /* clear out Module Select and Flash Address bits [19:16]. */
1637 bank_select &= ~0xf8;
1638 bank_select |= addr >> 12 & 0xf0;
1639 bank_select |= CSR_FLASH_64K_BANK;
1640 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1641 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1642
1643 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1644 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1645 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1646 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1647
1648 return;
1649 }
1650
1651 /* Setup bit 16 of flash address. */
1652 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1653 bank_select |= CSR_FLASH_64K_BANK;
1654 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1655 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1656 } else if (((addr & BIT_16) == 0) &&
1657 (bank_select & CSR_FLASH_64K_BANK)) {
1658 bank_select &= ~(CSR_FLASH_64K_BANK);
1659 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1660 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1661 }
1662
1663 /* Always perform IO mapped accesses to the FLASH registers. */
1664 if (ha->pio_address) {
1665 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1666 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1667 } else {
1668 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1669 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1670 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1671 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1672 }
1673 }
1674
1675 /**
1676 * qla2x00_poll_flash() - Polls flash for completion.
1677 * @ha: HA context
1678 * @addr: Address in flash to poll
1679 * @poll_data: Data to be polled
1680 * @man_id: Flash manufacturer ID
1681 * @flash_id: Flash ID
1682 *
1683 * This function polls the device until bit 7 of what is read matches data
1684 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1685 * out (a fatal error). The flash book recommeds reading bit 7 again after
1686 * reading bit 5 as a 1.
1687 *
1688 * Returns 0 on success, else non-zero.
1689 */
1690 static int
1691 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1692 uint8_t man_id, uint8_t flash_id)
1693 {
1694 int status;
1695 uint8_t flash_data;
1696 uint32_t cnt;
1697
1698 status = 1;
1699
1700 /* Wait for 30 seconds for command to finish. */
1701 poll_data &= BIT_7;
1702 for (cnt = 3000000; cnt; cnt--) {
1703 flash_data = qla2x00_read_flash_byte(ha, addr);
1704 if ((flash_data & BIT_7) == poll_data) {
1705 status = 0;
1706 break;
1707 }
1708
1709 if (man_id != 0x40 && man_id != 0xda) {
1710 if ((flash_data & BIT_5) && cnt > 2)
1711 cnt = 2;
1712 }
1713 udelay(10);
1714 barrier();
1715 cond_resched();
1716 }
1717 return status;
1718 }
1719
1720 /**
1721 * qla2x00_program_flash_address() - Programs a flash address
1722 * @ha: HA context
1723 * @addr: Address in flash to program
1724 * @data: Data to be written in flash
1725 * @man_id: Flash manufacturer ID
1726 * @flash_id: Flash ID
1727 *
1728 * Returns 0 on success, else non-zero.
1729 */
1730 static int
1731 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1732 uint8_t data, uint8_t man_id, uint8_t flash_id)
1733 {
1734 /* Write Program Command Sequence. */
1735 if (IS_OEM_001(ha)) {
1736 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1737 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1738 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1739 qla2x00_write_flash_byte(ha, addr, data);
1740 } else {
1741 if (man_id == 0xda && flash_id == 0xc1) {
1742 qla2x00_write_flash_byte(ha, addr, data);
1743 if (addr & 0x7e)
1744 return 0;
1745 } else {
1746 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1747 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1748 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1749 qla2x00_write_flash_byte(ha, addr, data);
1750 }
1751 }
1752
1753 udelay(150);
1754
1755 /* Wait for write to complete. */
1756 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1757 }
1758
1759 /**
1760 * qla2x00_erase_flash() - Erase the flash.
1761 * @ha: HA context
1762 * @man_id: Flash manufacturer ID
1763 * @flash_id: Flash ID
1764 *
1765 * Returns 0 on success, else non-zero.
1766 */
1767 static int
1768 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1769 {
1770 /* Individual Sector Erase Command Sequence */
1771 if (IS_OEM_001(ha)) {
1772 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1773 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1774 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1775 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1776 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1777 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1778 } else {
1779 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1780 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1781 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1782 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1783 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1784 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1785 }
1786
1787 udelay(150);
1788
1789 /* Wait for erase to complete. */
1790 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1791 }
1792
1793 /**
1794 * qla2x00_erase_flash_sector() - Erase a flash sector.
1795 * @ha: HA context
1796 * @addr: Flash sector to erase
1797 * @sec_mask: Sector address mask
1798 * @man_id: Flash manufacturer ID
1799 * @flash_id: Flash ID
1800 *
1801 * Returns 0 on success, else non-zero.
1802 */
1803 static int
1804 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1805 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1806 {
1807 /* Individual Sector Erase Command Sequence */
1808 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1809 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1810 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1811 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1812 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1813 if (man_id == 0x1f && flash_id == 0x13)
1814 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1815 else
1816 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1817
1818 udelay(150);
1819
1820 /* Wait for erase to complete. */
1821 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1822 }
1823
1824 /**
1825 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1826 * @man_id: Flash manufacturer ID
1827 * @flash_id: Flash ID
1828 */
1829 static void
1830 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
1831 uint8_t *flash_id)
1832 {
1833 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1834 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1835 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1836 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1837 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1838 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1839 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1840 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1841 }
1842
1843 static void
1844 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1845 uint32_t saddr, uint32_t length)
1846 {
1847 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1848 uint32_t midpoint, ilength;
1849 uint8_t data;
1850
1851 midpoint = length / 2;
1852
1853 WRT_REG_WORD(&reg->nvram, 0);
1854 RD_REG_WORD(&reg->nvram);
1855 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1856 if (ilength == midpoint) {
1857 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1858 RD_REG_WORD(&reg->nvram);
1859 }
1860 data = qla2x00_read_flash_byte(ha, saddr);
1861 if (saddr % 100)
1862 udelay(10);
1863 *tmp_buf = data;
1864 cond_resched();
1865 }
1866 }
1867
1868 static inline void
1869 qla2x00_suspend_hba(struct scsi_qla_host *vha)
1870 {
1871 int cnt;
1872 unsigned long flags;
1873 struct qla_hw_data *ha = vha->hw;
1874 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1875
1876 /* Suspend HBA. */
1877 scsi_block_requests(vha->host);
1878 ha->isp_ops->disable_intrs(ha);
1879 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1880
1881 /* Pause RISC. */
1882 spin_lock_irqsave(&ha->hardware_lock, flags);
1883 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1884 RD_REG_WORD(&reg->hccr);
1885 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1886 for (cnt = 0; cnt < 30000; cnt++) {
1887 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1888 break;
1889 udelay(100);
1890 }
1891 } else {
1892 udelay(10);
1893 }
1894 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1895 }
1896
1897 static inline void
1898 qla2x00_resume_hba(struct scsi_qla_host *vha)
1899 {
1900 struct qla_hw_data *ha = vha->hw;
1901
1902 /* Resume HBA. */
1903 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1904 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1905 qla2xxx_wake_dpc(vha);
1906 qla2x00_wait_for_hba_online(vha);
1907 scsi_unblock_requests(vha->host);
1908 }
1909
1910 uint8_t *
1911 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1912 uint32_t offset, uint32_t length)
1913 {
1914 uint32_t addr, midpoint;
1915 uint8_t *data;
1916 struct qla_hw_data *ha = vha->hw;
1917 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1918
1919 /* Suspend HBA. */
1920 qla2x00_suspend_hba(vha);
1921
1922 /* Go with read. */
1923 midpoint = ha->optrom_size / 2;
1924
1925 qla2x00_flash_enable(ha);
1926 WRT_REG_WORD(&reg->nvram, 0);
1927 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1928 for (addr = offset, data = buf; addr < length; addr++, data++) {
1929 if (addr == midpoint) {
1930 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1931 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1932 }
1933
1934 *data = qla2x00_read_flash_byte(ha, addr);
1935 }
1936 qla2x00_flash_disable(ha);
1937
1938 /* Resume HBA. */
1939 qla2x00_resume_hba(vha);
1940
1941 return buf;
1942 }
1943
1944 int
1945 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1946 uint32_t offset, uint32_t length)
1947 {
1948
1949 int rval;
1950 uint8_t man_id, flash_id, sec_number, data;
1951 uint16_t wd;
1952 uint32_t addr, liter, sec_mask, rest_addr;
1953 struct qla_hw_data *ha = vha->hw;
1954 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1955
1956 /* Suspend HBA. */
1957 qla2x00_suspend_hba(vha);
1958
1959 rval = QLA_SUCCESS;
1960 sec_number = 0;
1961
1962 /* Reset ISP chip. */
1963 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1964 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1965
1966 /* Go with write. */
1967 qla2x00_flash_enable(ha);
1968 do { /* Loop once to provide quick error exit */
1969 /* Structure of flash memory based on manufacturer */
1970 if (IS_OEM_001(ha)) {
1971 /* OEM variant with special flash part. */
1972 man_id = flash_id = 0;
1973 rest_addr = 0xffff;
1974 sec_mask = 0x10000;
1975 goto update_flash;
1976 }
1977 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1978 switch (man_id) {
1979 case 0x20: /* ST flash. */
1980 if (flash_id == 0xd2 || flash_id == 0xe3) {
1981 /*
1982 * ST m29w008at part - 64kb sector size with
1983 * 32kb,8kb,8kb,16kb sectors at memory address
1984 * 0xf0000.
1985 */
1986 rest_addr = 0xffff;
1987 sec_mask = 0x10000;
1988 break;
1989 }
1990 /*
1991 * ST m29w010b part - 16kb sector size
1992 * Default to 16kb sectors
1993 */
1994 rest_addr = 0x3fff;
1995 sec_mask = 0x1c000;
1996 break;
1997 case 0x40: /* Mostel flash. */
1998 /* Mostel v29c51001 part - 512 byte sector size. */
1999 rest_addr = 0x1ff;
2000 sec_mask = 0x1fe00;
2001 break;
2002 case 0xbf: /* SST flash. */
2003 /* SST39sf10 part - 4kb sector size. */
2004 rest_addr = 0xfff;
2005 sec_mask = 0x1f000;
2006 break;
2007 case 0xda: /* Winbond flash. */
2008 /* Winbond W29EE011 part - 256 byte sector size. */
2009 rest_addr = 0x7f;
2010 sec_mask = 0x1ff80;
2011 break;
2012 case 0xc2: /* Macronix flash. */
2013 /* 64k sector size. */
2014 if (flash_id == 0x38 || flash_id == 0x4f) {
2015 rest_addr = 0xffff;
2016 sec_mask = 0x10000;
2017 break;
2018 }
2019 /* Fall through... */
2020
2021 case 0x1f: /* Atmel flash. */
2022 /* 512k sector size. */
2023 if (flash_id == 0x13) {
2024 rest_addr = 0x7fffffff;
2025 sec_mask = 0x80000000;
2026 break;
2027 }
2028 /* Fall through... */
2029
2030 case 0x01: /* AMD flash. */
2031 if (flash_id == 0x38 || flash_id == 0x40 ||
2032 flash_id == 0x4f) {
2033 /* Am29LV081 part - 64kb sector size. */
2034 /* Am29LV002BT part - 64kb sector size. */
2035 rest_addr = 0xffff;
2036 sec_mask = 0x10000;
2037 break;
2038 } else if (flash_id == 0x3e) {
2039 /*
2040 * Am29LV008b part - 64kb sector size with
2041 * 32kb,8kb,8kb,16kb sector at memory address
2042 * h0xf0000.
2043 */
2044 rest_addr = 0xffff;
2045 sec_mask = 0x10000;
2046 break;
2047 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2048 /*
2049 * Am29LV010 part or AM29f010 - 16kb sector
2050 * size.
2051 */
2052 rest_addr = 0x3fff;
2053 sec_mask = 0x1c000;
2054 break;
2055 } else if (flash_id == 0x6d) {
2056 /* Am29LV001 part - 8kb sector size. */
2057 rest_addr = 0x1fff;
2058 sec_mask = 0x1e000;
2059 break;
2060 }
2061 default:
2062 /* Default to 16 kb sector size. */
2063 rest_addr = 0x3fff;
2064 sec_mask = 0x1c000;
2065 break;
2066 }
2067
2068 update_flash:
2069 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2070 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2071 rval = QLA_FUNCTION_FAILED;
2072 break;
2073 }
2074 }
2075
2076 for (addr = offset, liter = 0; liter < length; liter++,
2077 addr++) {
2078 data = buf[liter];
2079 /* Are we at the beginning of a sector? */
2080 if ((addr & rest_addr) == 0) {
2081 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2082 if (addr >= 0x10000UL) {
2083 if (((addr >> 12) & 0xf0) &&
2084 ((man_id == 0x01 &&
2085 flash_id == 0x3e) ||
2086 (man_id == 0x20 &&
2087 flash_id == 0xd2))) {
2088 sec_number++;
2089 if (sec_number == 1) {
2090 rest_addr =
2091 0x7fff;
2092 sec_mask =
2093 0x18000;
2094 } else if (
2095 sec_number == 2 ||
2096 sec_number == 3) {
2097 rest_addr =
2098 0x1fff;
2099 sec_mask =
2100 0x1e000;
2101 } else if (
2102 sec_number == 4) {
2103 rest_addr =
2104 0x3fff;
2105 sec_mask =
2106 0x1c000;
2107 }
2108 }
2109 }
2110 } else if (addr == ha->optrom_size / 2) {
2111 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2112 RD_REG_WORD(&reg->nvram);
2113 }
2114
2115 if (flash_id == 0xda && man_id == 0xc1) {
2116 qla2x00_write_flash_byte(ha, 0x5555,
2117 0xaa);
2118 qla2x00_write_flash_byte(ha, 0x2aaa,
2119 0x55);
2120 qla2x00_write_flash_byte(ha, 0x5555,
2121 0xa0);
2122 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2123 /* Then erase it */
2124 if (qla2x00_erase_flash_sector(ha,
2125 addr, sec_mask, man_id,
2126 flash_id)) {
2127 rval = QLA_FUNCTION_FAILED;
2128 break;
2129 }
2130 if (man_id == 0x01 && flash_id == 0x6d)
2131 sec_number++;
2132 }
2133 }
2134
2135 if (man_id == 0x01 && flash_id == 0x6d) {
2136 if (sec_number == 1 &&
2137 addr == (rest_addr - 1)) {
2138 rest_addr = 0x0fff;
2139 sec_mask = 0x1f000;
2140 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2141 rest_addr = 0x3fff;
2142 sec_mask = 0x1c000;
2143 }
2144 }
2145
2146 if (qla2x00_program_flash_address(ha, addr, data,
2147 man_id, flash_id)) {
2148 rval = QLA_FUNCTION_FAILED;
2149 break;
2150 }
2151 cond_resched();
2152 }
2153 } while (0);
2154 qla2x00_flash_disable(ha);
2155
2156 /* Resume HBA. */
2157 qla2x00_resume_hba(vha);
2158
2159 return rval;
2160 }
2161
2162 uint8_t *
2163 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2164 uint32_t offset, uint32_t length)
2165 {
2166 struct qla_hw_data *ha = vha->hw;
2167
2168 /* Suspend HBA. */
2169 scsi_block_requests(vha->host);
2170 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2171
2172 /* Go with read. */
2173 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2174
2175 /* Resume HBA. */
2176 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2177 scsi_unblock_requests(vha->host);
2178
2179 return buf;
2180 }
2181
2182 int
2183 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2184 uint32_t offset, uint32_t length)
2185 {
2186 int rval;
2187 struct qla_hw_data *ha = vha->hw;
2188
2189 /* Suspend HBA. */
2190 scsi_block_requests(vha->host);
2191 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2192
2193 /* Go with write. */
2194 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2195 length >> 2);
2196
2197 /* Resume HBA -- RISC reset needed. */
2198 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2199 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2200 qla2xxx_wake_dpc(vha);
2201 qla2x00_wait_for_hba_online(vha);
2202 scsi_unblock_requests(vha->host);
2203
2204 return rval;
2205 }
2206
2207 uint8_t *
2208 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2209 uint32_t offset, uint32_t length)
2210 {
2211 int rval;
2212 dma_addr_t optrom_dma;
2213 void *optrom;
2214 uint8_t *pbuf;
2215 uint32_t faddr, left, burst;
2216 struct qla_hw_data *ha = vha->hw;
2217
2218 if (offset & 0xfff)
2219 goto slow_read;
2220 if (length < OPTROM_BURST_SIZE)
2221 goto slow_read;
2222
2223 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2224 &optrom_dma, GFP_KERNEL);
2225 if (!optrom) {
2226 qla_printk(KERN_DEBUG, ha,
2227 "Unable to allocate memory for optrom burst read "
2228 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2229
2230 goto slow_read;
2231 }
2232
2233 pbuf = buf;
2234 faddr = offset >> 2;
2235 left = length >> 2;
2236 burst = OPTROM_BURST_DWORDS;
2237 while (left != 0) {
2238 if (burst > left)
2239 burst = left;
2240
2241 rval = qla2x00_dump_ram(vha, optrom_dma,
2242 flash_data_to_access_addr(faddr), burst);
2243 if (rval) {
2244 qla_printk(KERN_WARNING, ha,
2245 "Unable to burst-read optrom segment "
2246 "(%x/%x/%llx).\n", rval,
2247 flash_data_to_access_addr(faddr),
2248 (unsigned long long)optrom_dma);
2249 qla_printk(KERN_WARNING, ha,
2250 "Reverting to slow-read.\n");
2251
2252 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2253 optrom, optrom_dma);
2254 goto slow_read;
2255 }
2256
2257 memcpy(pbuf, optrom, burst * 4);
2258
2259 left -= burst;
2260 faddr += burst;
2261 pbuf += burst * 4;
2262 }
2263
2264 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2265 optrom_dma);
2266
2267 return buf;
2268
2269 slow_read:
2270 return qla24xx_read_optrom_data(vha, buf, offset, length);
2271 }
2272
2273 /**
2274 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2275 * @ha: HA context
2276 * @pcids: Pointer to the FCODE PCI data structure
2277 *
2278 * The process of retrieving the FCODE version information is at best
2279 * described as interesting.
2280 *
2281 * Within the first 100h bytes of the image an ASCII string is present
2282 * which contains several pieces of information including the FCODE
2283 * version. Unfortunately it seems the only reliable way to retrieve
2284 * the version is by scanning for another sentinel within the string,
2285 * the FCODE build date:
2286 *
2287 * ... 2.00.02 10/17/02 ...
2288 *
2289 * Returns QLA_SUCCESS on successful retrieval of version.
2290 */
2291 static void
2292 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2293 {
2294 int ret = QLA_FUNCTION_FAILED;
2295 uint32_t istart, iend, iter, vend;
2296 uint8_t do_next, rbyte, *vbyte;
2297
2298 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2299
2300 /* Skip the PCI data structure. */
2301 istart = pcids +
2302 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2303 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2304 iend = istart + 0x100;
2305 do {
2306 /* Scan for the sentinel date string...eeewww. */
2307 do_next = 0;
2308 iter = istart;
2309 while ((iter < iend) && !do_next) {
2310 iter++;
2311 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2312 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2313 '/')
2314 do_next++;
2315 else if (qla2x00_read_flash_byte(ha,
2316 iter + 3) == '/')
2317 do_next++;
2318 }
2319 }
2320 if (!do_next)
2321 break;
2322
2323 /* Backtrack to previous ' ' (space). */
2324 do_next = 0;
2325 while ((iter > istart) && !do_next) {
2326 iter--;
2327 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2328 do_next++;
2329 }
2330 if (!do_next)
2331 break;
2332
2333 /*
2334 * Mark end of version tag, and find previous ' ' (space) or
2335 * string length (recent FCODE images -- major hack ahead!!!).
2336 */
2337 vend = iter - 1;
2338 do_next = 0;
2339 while ((iter > istart) && !do_next) {
2340 iter--;
2341 rbyte = qla2x00_read_flash_byte(ha, iter);
2342 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2343 do_next++;
2344 }
2345 if (!do_next)
2346 break;
2347
2348 /* Mark beginning of version tag, and copy data. */
2349 iter++;
2350 if ((vend - iter) &&
2351 ((vend - iter) < sizeof(ha->fcode_revision))) {
2352 vbyte = ha->fcode_revision;
2353 while (iter <= vend) {
2354 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2355 iter++;
2356 }
2357 ret = QLA_SUCCESS;
2358 }
2359 } while (0);
2360
2361 if (ret != QLA_SUCCESS)
2362 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2363 }
2364
2365 int
2366 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2367 {
2368 int ret = QLA_SUCCESS;
2369 uint8_t code_type, last_image;
2370 uint32_t pcihdr, pcids;
2371 uint8_t *dbyte;
2372 uint16_t *dcode;
2373 struct qla_hw_data *ha = vha->hw;
2374
2375 if (!ha->pio_address || !mbuf)
2376 return QLA_FUNCTION_FAILED;
2377
2378 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2379 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2380 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2381 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2382
2383 qla2x00_flash_enable(ha);
2384
2385 /* Begin with first PCI expansion ROM header. */
2386 pcihdr = 0;
2387 last_image = 1;
2388 do {
2389 /* Verify PCI expansion ROM header. */
2390 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2391 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2392 /* No signature */
2393 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2394 "signature.\n"));
2395 ret = QLA_FUNCTION_FAILED;
2396 break;
2397 }
2398
2399 /* Locate PCI data structure. */
2400 pcids = pcihdr +
2401 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2402 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2403
2404 /* Validate signature of PCI data structure. */
2405 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2406 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2407 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2408 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2409 /* Incorrect header. */
2410 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2411 "found pcir_adr=%x.\n", pcids));
2412 ret = QLA_FUNCTION_FAILED;
2413 break;
2414 }
2415
2416 /* Read version */
2417 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2418 switch (code_type) {
2419 case ROM_CODE_TYPE_BIOS:
2420 /* Intel x86, PC-AT compatible. */
2421 ha->bios_revision[0] =
2422 qla2x00_read_flash_byte(ha, pcids + 0x12);
2423 ha->bios_revision[1] =
2424 qla2x00_read_flash_byte(ha, pcids + 0x13);
2425 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2426 ha->bios_revision[1], ha->bios_revision[0]));
2427 break;
2428 case ROM_CODE_TYPE_FCODE:
2429 /* Open Firmware standard for PCI (FCode). */
2430 /* Eeeewww... */
2431 qla2x00_get_fcode_version(ha, pcids);
2432 break;
2433 case ROM_CODE_TYPE_EFI:
2434 /* Extensible Firmware Interface (EFI). */
2435 ha->efi_revision[0] =
2436 qla2x00_read_flash_byte(ha, pcids + 0x12);
2437 ha->efi_revision[1] =
2438 qla2x00_read_flash_byte(ha, pcids + 0x13);
2439 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2440 ha->efi_revision[1], ha->efi_revision[0]));
2441 break;
2442 default:
2443 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2444 "type %x at pcids %x.\n", code_type, pcids));
2445 break;
2446 }
2447
2448 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2449
2450 /* Locate next PCI expansion ROM. */
2451 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2452 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2453 } while (!last_image);
2454
2455 if (IS_QLA2322(ha)) {
2456 /* Read firmware image information. */
2457 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2458 dbyte = mbuf;
2459 memset(dbyte, 0, 8);
2460 dcode = (uint16_t *)dbyte;
2461
2462 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2463 8);
2464 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2465 "flash:\n"));
2466 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2467
2468 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2469 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2470 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2471 dcode[3] == 0)) {
2472 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2473 "revision at %x.\n", ha->flt_region_fw * 4));
2474 } else {
2475 /* values are in big endian */
2476 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2477 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2478 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2479 }
2480 }
2481
2482 qla2x00_flash_disable(ha);
2483
2484 return ret;
2485 }
2486
2487 int
2488 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2489 {
2490 int ret = QLA_SUCCESS;
2491 uint32_t pcihdr, pcids;
2492 uint32_t *dcode;
2493 uint8_t *bcode;
2494 uint8_t code_type, last_image;
2495 int i;
2496 struct qla_hw_data *ha = vha->hw;
2497
2498 if (!mbuf)
2499 return QLA_FUNCTION_FAILED;
2500
2501 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2502 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2503 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2504 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2505
2506 dcode = mbuf;
2507
2508 /* Begin with first PCI expansion ROM header. */
2509 pcihdr = ha->flt_region_boot;
2510 last_image = 1;
2511 do {
2512 /* Verify PCI expansion ROM header. */
2513 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2514 bcode = mbuf + (pcihdr % 4);
2515 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2516 /* No signature */
2517 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2518 "signature.\n"));
2519 ret = QLA_FUNCTION_FAILED;
2520 break;
2521 }
2522
2523 /* Locate PCI data structure. */
2524 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2525
2526 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2527 bcode = mbuf + (pcihdr % 4);
2528
2529 /* Validate signature of PCI data structure. */
2530 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2531 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2532 /* Incorrect header. */
2533 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2534 "found pcir_adr=%x.\n", pcids));
2535 ret = QLA_FUNCTION_FAILED;
2536 break;
2537 }
2538
2539 /* Read version */
2540 code_type = bcode[0x14];
2541 switch (code_type) {
2542 case ROM_CODE_TYPE_BIOS:
2543 /* Intel x86, PC-AT compatible. */
2544 ha->bios_revision[0] = bcode[0x12];
2545 ha->bios_revision[1] = bcode[0x13];
2546 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2547 ha->bios_revision[1], ha->bios_revision[0]));
2548 break;
2549 case ROM_CODE_TYPE_FCODE:
2550 /* Open Firmware standard for PCI (FCode). */
2551 ha->fcode_revision[0] = bcode[0x12];
2552 ha->fcode_revision[1] = bcode[0x13];
2553 DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
2554 ha->fcode_revision[1], ha->fcode_revision[0]));
2555 break;
2556 case ROM_CODE_TYPE_EFI:
2557 /* Extensible Firmware Interface (EFI). */
2558 ha->efi_revision[0] = bcode[0x12];
2559 ha->efi_revision[1] = bcode[0x13];
2560 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2561 ha->efi_revision[1], ha->efi_revision[0]));
2562 break;
2563 default:
2564 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2565 "type %x at pcids %x.\n", code_type, pcids));
2566 break;
2567 }
2568
2569 last_image = bcode[0x15] & BIT_7;
2570
2571 /* Locate next PCI expansion ROM. */
2572 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2573 } while (!last_image);
2574
2575 /* Read firmware image information. */
2576 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2577 dcode = mbuf;
2578
2579 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2580 for (i = 0; i < 4; i++)
2581 dcode[i] = be32_to_cpu(dcode[i]);
2582
2583 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2584 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2585 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2586 dcode[3] == 0)) {
2587 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2588 "revision at %x.\n", ha->flt_region_fw * 4));
2589 } else {
2590 ha->fw_revision[0] = dcode[0];
2591 ha->fw_revision[1] = dcode[1];
2592 ha->fw_revision[2] = dcode[2];
2593 ha->fw_revision[3] = dcode[3];
2594 }
2595
2596 return ret;
2597 }
2598
2599 static int
2600 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2601 {
2602 if (pos >= end || *pos != 0x82)
2603 return 0;
2604
2605 pos += 3 + pos[1];
2606 if (pos >= end || *pos != 0x90)
2607 return 0;
2608
2609 pos += 3 + pos[1];
2610 if (pos >= end || *pos != 0x78)
2611 return 0;
2612
2613 return 1;
2614 }
2615
2616 int
2617 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2618 {
2619 struct qla_hw_data *ha = vha->hw;
2620 uint8_t *pos = ha->vpd;
2621 uint8_t *end = pos + ha->vpd_size;
2622 int len = 0;
2623
2624 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2625 return 0;
2626
2627 while (pos < end && *pos != 0x78) {
2628 len = (*pos == 0x82) ? pos[1] : pos[2];
2629
2630 if (!strncmp(pos, key, strlen(key)))
2631 break;
2632
2633 if (*pos != 0x90 && *pos != 0x91)
2634 pos += len;
2635
2636 pos += 3;
2637 }
2638
2639 if (pos < end - len && *pos != 0x78)
2640 return snprintf(str, size, "%.*s", len, pos + 3);
2641
2642 return 0;
2643 }
2644
2645 static int
2646 qla2xxx_hw_event_store(scsi_qla_host_t *vha, uint32_t *fdata)
2647 {
2648 uint32_t d[2], faddr;
2649 struct qla_hw_data *ha = vha->hw;
2650
2651 /* Locate first empty entry. */
2652 for (;;) {
2653 if (ha->hw_event_ptr >=
2654 ha->flt_region_hw_event + FA_HW_EVENT_SIZE) {
2655 DEBUG2(qla_printk(KERN_WARNING, ha,
2656 "HW event -- Log Full!\n"));
2657 return QLA_MEMORY_ALLOC_FAILED;
2658 }
2659
2660 qla24xx_read_flash_data(vha, d, ha->hw_event_ptr, 2);
2661 faddr = flash_data_to_access_addr(ha->hw_event_ptr);
2662 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2663 if (d[0] == __constant_cpu_to_le32(0xffffffff) &&
2664 d[1] == __constant_cpu_to_le32(0xffffffff)) {
2665 qla24xx_unprotect_flash(ha);
2666
2667 qla24xx_write_flash_dword(ha, faddr++,
2668 cpu_to_le32(jiffies));
2669 qla24xx_write_flash_dword(ha, faddr++, 0);
2670 qla24xx_write_flash_dword(ha, faddr++, *fdata++);
2671 qla24xx_write_flash_dword(ha, faddr++, *fdata);
2672
2673 qla24xx_protect_flash(ha);
2674 break;
2675 }
2676 }
2677 return QLA_SUCCESS;
2678 }
2679
2680 int
2681 qla2xxx_hw_event_log(scsi_qla_host_t *vha, uint16_t code, uint16_t d1,
2682 uint16_t d2, uint16_t d3)
2683 {
2684 #define QMARK(a, b, c, d) \
2685 cpu_to_le32(LSB(a) << 24 | LSB(b) << 16 | LSB(c) << 8 | LSB(d))
2686 struct qla_hw_data *ha = vha->hw;
2687 int rval;
2688 uint32_t marker[2], fdata[4];
2689
2690 if (ha->flt_region_hw_event == 0)
2691 return QLA_FUNCTION_FAILED;
2692
2693 DEBUG2(qla_printk(KERN_WARNING, ha,
2694 "HW event -- code=%x, d1=%x, d2=%x, d3=%x.\n", code, d1, d2, d3));
2695
2696 /* If marker not already found, locate or write. */
2697 if (!ha->flags.hw_event_marker_found) {
2698 /* Create marker. */
2699 marker[0] = QMARK('L', ha->fw_major_version,
2700 ha->fw_minor_version, ha->fw_subminor_version);
2701 marker[1] = QMARK(QLA_DRIVER_MAJOR_VER, QLA_DRIVER_MINOR_VER,
2702 QLA_DRIVER_PATCH_VER, QLA_DRIVER_BETA_VER);
2703
2704 /* Locate marker. */
2705 ha->hw_event_ptr = ha->flt_region_hw_event;
2706 for (;;) {
2707 qla24xx_read_flash_data(vha, fdata, ha->hw_event_ptr,
2708 4);
2709 if (fdata[0] == __constant_cpu_to_le32(0xffffffff) &&
2710 fdata[1] == __constant_cpu_to_le32(0xffffffff))
2711 break;
2712 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2713 if (ha->hw_event_ptr >=
2714 ha->flt_region_hw_event + FA_HW_EVENT_SIZE) {
2715 DEBUG2(qla_printk(KERN_WARNING, ha,
2716 "HW event -- Log Full!\n"));
2717 return QLA_MEMORY_ALLOC_FAILED;
2718 }
2719 if (fdata[2] == marker[0] && fdata[3] == marker[1]) {
2720 ha->flags.hw_event_marker_found = 1;
2721 break;
2722 }
2723 }
2724 /* No marker, write it. */
2725 if (!ha->flags.hw_event_marker_found) {
2726 rval = qla2xxx_hw_event_store(vha, marker);
2727 if (rval != QLA_SUCCESS) {
2728 DEBUG2(qla_printk(KERN_WARNING, ha,
2729 "HW event -- Failed marker write=%x.!\n",
2730 rval));
2731 return rval;
2732 }
2733 ha->flags.hw_event_marker_found = 1;
2734 }
2735 }
2736
2737 /* Store error. */
2738 fdata[0] = cpu_to_le32(code << 16 | d1);
2739 fdata[1] = cpu_to_le32(d2 << 16 | d3);
2740 rval = qla2xxx_hw_event_store(vha, fdata);
2741 if (rval != QLA_SUCCESS) {
2742 DEBUG2(qla_printk(KERN_WARNING, ha,
2743 "HW event -- Failed error write=%x.!\n",
2744 rval));
2745 }
2746
2747 return rval;
2748 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree