drivers/scsi/qla2xxx/qla_dbg.h

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 /*
   8  * Driver debug definitions.
   9  */
  10 /* #define QL_DEBUG_LEVEL_1  */ /* Output register accesses to COM1 */
  11 /* #define QL_DEBUG_LEVEL_2  */ /* Output error msgs to COM1 */
  12 /* #define QL_DEBUG_LEVEL_3  */ /* Output function trace msgs to COM1 */
  13 /* #define QL_DEBUG_LEVEL_4  */ /* Output NVRAM trace msgs to COM1 */
  14 /* #define QL_DEBUG_LEVEL_5  */ /* Output ring trace msgs to COM1 */
  15 /* #define QL_DEBUG_LEVEL_6  */ /* Output WATCHDOG timer trace to COM1 */
  16 /* #define QL_DEBUG_LEVEL_7  */ /* Output RISC load trace msgs to COM1 */
  17 /* #define QL_DEBUG_LEVEL_8  */ /* Output ring saturation msgs to COM1 */
  18 /* #define QL_DEBUG_LEVEL_9  */ /* Output IOCTL trace msgs */
  19 /* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
  20 /* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
  21 /* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */
  22 /* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */
  23 /* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */
  24 /* #define QL_DEBUG_LEVEL_15 */ /* Output NPIV trace msgs */
  25 /* #define QL_DEBUG_LEVEL_16 */ /* Output ISP84XX trace msgs */
  26
  27 /*
  28 * Macros use for debugging the driver.
  29 */
  30
  31 #define DEBUG(x)        do { if (ql2xextended_error_logging) { x; } } while (0)
  32
  33 #if defined(QL_DEBUG_LEVEL_1)
  34 #define DEBUG1(x)       do {x;} while (0)
  35 #else
  36 #define DEBUG1(x)       do {} while (0)
  37 #endif
  38
  39 #define DEBUG2(x)       do { if (ql2xextended_error_logging) { x; } } while (0)
  40 #define DEBUG2_3(x)     do { if (ql2xextended_error_logging) { x; } } while (0)
  41 #define DEBUG2_3_11(x)  do { if (ql2xextended_error_logging) { x; } } while (0)
  42 #define DEBUG2_9_10(x)  do { if (ql2xextended_error_logging) { x; } } while (0)
  43 #define DEBUG2_11(x)    do { if (ql2xextended_error_logging) { x; } } while (0)
  44 #define DEBUG2_13(x)    do { if (ql2xextended_error_logging) { x; } } while (0)
  45 #define DEBUG2_16(x)    do { if (ql2xextended_error_logging) { x; } } while (0)
  46
  47 #if defined(QL_DEBUG_LEVEL_3)
  48 #define DEBUG3(x)       do {x;} while (0)
  49 #define DEBUG3_11(x)    do {x;} while (0)
  50 #else
  51 #define DEBUG3(x)       do {} while (0)
  52 #endif
  53
  54 #if defined(QL_DEBUG_LEVEL_4)
  55 #define DEBUG4(x)       do {x;} while (0)
  56 #else
  57 #define DEBUG4(x)       do {} while (0)
  58 #endif
  59
  60 #if defined(QL_DEBUG_LEVEL_5)
  61 #define DEBUG5(x)          do {x;} while (0)
  62 #else
  63 #define DEBUG5(x)       do {} while (0)
  64 #endif
  65
  66 #if defined(QL_DEBUG_LEVEL_7)
  67 #define DEBUG7(x)          do {x;} while (0)
  68 #else
  69 #define DEBUG7(x)          do {} while (0)
  70 #endif
  71
  72 #if defined(QL_DEBUG_LEVEL_9)
  73 #define DEBUG9(x)       do {x;} while (0)
  74 #define DEBUG9_10(x)    do {x;} while (0)
  75 #else
  76 #define DEBUG9(x)       do {} while (0)
  77 #endif
  78
  79 #if defined(QL_DEBUG_LEVEL_10)
  80 #define DEBUG10(x)      do {x;} while (0)
  81 #define DEBUG9_10(x)    do {x;} while (0)
  82 #else
  83 #define DEBUG10(x)      do {} while (0)
  84   #if !defined(DEBUG9_10)
  85   #define DEBUG9_10(x)  do {} while (0)
  86   #endif
  87 #endif
  88
  89 #if defined(QL_DEBUG_LEVEL_11)
  90 #define DEBUG11(x)      do{x;} while(0)
  91 #if !defined(DEBUG3_11)
  92 #define DEBUG3_11(x)    do{x;} while(0)
  93 #endif
  94 #else
  95 #define DEBUG11(x)      do{} while(0)
  96   #if !defined(QL_DEBUG_LEVEL_3)
  97   #define DEBUG3_11(x)  do{} while(0)
  98   #endif
  99 #endif
 100
 101 #if defined(QL_DEBUG_LEVEL_12)
 102 #define DEBUG12(x)      do {x;} while (0)
 103 #else
 104 #define DEBUG12(x)      do {} while (0)
 105 #endif
 106
 107 #if defined(QL_DEBUG_LEVEL_13)
 108 #define DEBUG13(x)      do {x;} while (0)
 109 #else
 110 #define DEBUG13(x)      do {} while (0)
 111 #endif
 112
 113 #if defined(QL_DEBUG_LEVEL_14)
 114 #define DEBUG14(x)      do {x;} while (0)
 115 #else
 116 #define DEBUG14(x)      do {} while (0)
 117 #endif
 118
 119 #if defined(QL_DEBUG_LEVEL_15)
 120 #define DEBUG15(x)      do {x;} while (0)
 121 #else
 122 #define DEBUG15(x)      do {} while (0)
 123 #endif
 124
 125 #if defined(QL_DEBUG_LEVEL_16)
 126 #define DEBUG16(x)      do {x;} while (0)
 127 #else
 128 #define DEBUG16(x)      do {} while (0)
 129 #endif
 130
 131 /*
 132  * Firmware Dump structure definition
 133  */
 134
 135 struct qla2300_fw_dump {
 136         uint16_t hccr;
 137         uint16_t pbiu_reg[8];
 138         uint16_t risc_host_reg[8];
 139         uint16_t mailbox_reg[32];
 140         uint16_t resp_dma_reg[32];
 141         uint16_t dma_reg[48];
 142         uint16_t risc_hdw_reg[16];
 143         uint16_t risc_gp0_reg[16];
 144         uint16_t risc_gp1_reg[16];
 145         uint16_t risc_gp2_reg[16];
 146         uint16_t risc_gp3_reg[16];
 147         uint16_t risc_gp4_reg[16];
 148         uint16_t risc_gp5_reg[16];
 149         uint16_t risc_gp6_reg[16];
 150         uint16_t risc_gp7_reg[16];
 151         uint16_t frame_buf_hdw_reg[64];
 152         uint16_t fpm_b0_reg[64];
 153         uint16_t fpm_b1_reg[64];
 154         uint16_t risc_ram[0xf800];
 155         uint16_t stack_ram[0x1000];
 156         uint16_t data_ram[1];
 157 };
 158
 159 struct qla2100_fw_dump {
 160         uint16_t hccr;
 161         uint16_t pbiu_reg[8];
 162         uint16_t mailbox_reg[32];
 163         uint16_t dma_reg[48];
 164         uint16_t risc_hdw_reg[16];
 165         uint16_t risc_gp0_reg[16];
 166         uint16_t risc_gp1_reg[16];
 167         uint16_t risc_gp2_reg[16];
 168         uint16_t risc_gp3_reg[16];
 169         uint16_t risc_gp4_reg[16];
 170         uint16_t risc_gp5_reg[16];
 171         uint16_t risc_gp6_reg[16];
 172         uint16_t risc_gp7_reg[16];
 173         uint16_t frame_buf_hdw_reg[16];
 174         uint16_t fpm_b0_reg[64];
 175         uint16_t fpm_b1_reg[64];
 176         uint16_t risc_ram[0xf000];
 177 };
 178
 179 struct qla24xx_fw_dump {
 180         uint32_t host_status;
 181         uint32_t host_reg[32];
 182         uint32_t shadow_reg[7];
 183         uint16_t mailbox_reg[32];
 184         uint32_t xseq_gp_reg[128];
 185         uint32_t xseq_0_reg[16];
 186         uint32_t xseq_1_reg[16];
 187         uint32_t rseq_gp_reg[128];
 188         uint32_t rseq_0_reg[16];
 189         uint32_t rseq_1_reg[16];
 190         uint32_t rseq_2_reg[16];
 191         uint32_t cmd_dma_reg[16];
 192         uint32_t req0_dma_reg[15];
 193         uint32_t resp0_dma_reg[15];
 194         uint32_t req1_dma_reg[15];
 195         uint32_t xmt0_dma_reg[32];
 196         uint32_t xmt1_dma_reg[32];
 197         uint32_t xmt2_dma_reg[32];
 198         uint32_t xmt3_dma_reg[32];
 199         uint32_t xmt4_dma_reg[32];
 200         uint32_t xmt_data_dma_reg[16];
 201         uint32_t rcvt0_data_dma_reg[32];
 202         uint32_t rcvt1_data_dma_reg[32];
 203         uint32_t risc_gp_reg[128];
 204         uint32_t lmc_reg[112];
 205         uint32_t fpm_hdw_reg[192];
 206         uint32_t fb_hdw_reg[176];
 207         uint32_t code_ram[0x2000];
 208         uint32_t ext_mem[1];
 209 };
 210
 211 struct qla25xx_fw_dump {
 212         uint32_t host_status;
 213         uint32_t host_risc_reg[32];
 214         uint32_t pcie_regs[4];
 215         uint32_t host_reg[32];
 216         uint32_t shadow_reg[11];
 217         uint32_t risc_io_reg;
 218         uint16_t mailbox_reg[32];
 219         uint32_t xseq_gp_reg[128];
 220         uint32_t xseq_0_reg[48];
 221         uint32_t xseq_1_reg[16];
 222         uint32_t rseq_gp_reg[128];
 223         uint32_t rseq_0_reg[32];
 224         uint32_t rseq_1_reg[16];
 225         uint32_t rseq_2_reg[16];
 226         uint32_t aseq_gp_reg[128];
 227         uint32_t aseq_0_reg[32];
 228         uint32_t aseq_1_reg[16];
 229         uint32_t aseq_2_reg[16];
 230         uint32_t cmd_dma_reg[16];
 231         uint32_t req0_dma_reg[15];
 232         uint32_t resp0_dma_reg[15];
 233         uint32_t req1_dma_reg[15];
 234         uint32_t xmt0_dma_reg[32];
 235         uint32_t xmt1_dma_reg[32];
 236         uint32_t xmt2_dma_reg[32];
 237         uint32_t xmt3_dma_reg[32];
 238         uint32_t xmt4_dma_reg[32];
 239         uint32_t xmt_data_dma_reg[16];
 240         uint32_t rcvt0_data_dma_reg[32];
 241         uint32_t rcvt1_data_dma_reg[32];
 242         uint32_t risc_gp_reg[128];
 243         uint32_t lmc_reg[128];
 244         uint32_t fpm_hdw_reg[192];
 245         uint32_t fb_hdw_reg[192];
 246         uint32_t code_ram[0x2000];
 247         uint32_t ext_mem[1];
 248 };
 249
 250 #define EFT_NUM_BUFFERS         4
 251 #define EFT_BYTES_PER_BUFFER    0x4000
 252 #define EFT_SIZE                ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
 253
 254 #define FCE_NUM_BUFFERS         64
 255 #define FCE_BYTES_PER_BUFFER    0x400
 256 #define FCE_SIZE                ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
 257 #define fce_calc_size(b)        ((FCE_BYTES_PER_BUFFER) * (b))
 258
 259 struct qla2xxx_fce_chain {
 260         uint32_t type;
 261         uint32_t chain_size;
 262
 263         uint32_t size;
 264         uint32_t addr_l;
 265         uint32_t addr_h;
 266         uint32_t eregs[8];
 267 };
 268
 269 #define DUMP_CHAIN_VARIANT      0x80000000
 270 #define DUMP_CHAIN_FCE          0x7FFFFAF0
 271 #define DUMP_CHAIN_LAST         0x80000000
 272
 273 struct qla2xxx_fw_dump {
 274         uint8_t signature[4];
 275         uint32_t version;
 276
 277         uint32_t fw_major_version;
 278         uint32_t fw_minor_version;
 279         uint32_t fw_subminor_version;
 280         uint32_t fw_attributes;
 281
 282         uint32_t vendor;
 283         uint32_t device;
 284         uint32_t subsystem_vendor;
 285         uint32_t subsystem_device;
 286
 287         uint32_t fixed_size;
 288         uint32_t mem_size;
 289         uint32_t req_q_size;
 290         uint32_t rsp_q_size;
 291
 292         uint32_t eft_size;
 293         uint32_t eft_addr_l;
 294         uint32_t eft_addr_h;
 295
 296         uint32_t header_size;
 297
 298         union {
 299                 struct qla2100_fw_dump isp21;
 300                 struct qla2300_fw_dump isp23;
 301                 struct qla24xx_fw_dump isp24;
 302                 struct qla25xx_fw_dump isp25;
 303         } isp;
 304 };