arch/arm/include/asm/ptrace.h

   1 /*
   2  *  arch/arm/include/asm/ptrace.h
   3  *
   4  *  Copyright (C) 1996-2003 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef __ASM_ARM_PTRACE_H
  11 #define __ASM_ARM_PTRACE_H
  12
  13 #include <asm/hwcap.h>
  14
  15 #define PTRACE_GETREGS          12
  16 #define PTRACE_SETREGS          13
  17 #define PTRACE_GETFPREGS        14
  18 #define PTRACE_SETFPREGS        15
  19 /* PTRACE_ATTACH is 16 */
  20 /* PTRACE_DETACH is 17 */
  21 #define PTRACE_GETWMMXREGS      18
  22 #define PTRACE_SETWMMXREGS      19
  23 /* 20 is unused */
  24 #define PTRACE_OLDSETOPTIONS    21
  25 #define PTRACE_GET_THREAD_AREA  22
  26 #define PTRACE_SET_SYSCALL      23
  27 /* PTRACE_SYSCALL is 24 */
  28 #define PTRACE_GETCRUNCHREGS    25
  29 #define PTRACE_SETCRUNCHREGS    26
  30 #define PTRACE_GETVFPREGS       27
  31 #define PTRACE_SETVFPREGS       28
  32
  33 /*
  34  * PSR bits
  35  */
  36 #define USR26_MODE      0x00000000
  37 #define FIQ26_MODE      0x00000001
  38 #define IRQ26_MODE      0x00000002
  39 #define SVC26_MODE      0x00000003
  40 #define USR_MODE        0x00000010
  41 #define FIQ_MODE        0x00000011
  42 #define IRQ_MODE        0x00000012
  43 #define SVC_MODE        0x00000013
  44 #define ABT_MODE        0x00000017
  45 #define UND_MODE        0x0000001b
  46 #define SYSTEM_MODE     0x0000001f
  47 #define MODE32_BIT      0x00000010
  48 #define MODE_MASK       0x0000001f
  49 #define PSR_T_BIT       0x00000020
  50 #define PSR_F_BIT       0x00000040
  51 #define PSR_I_BIT       0x00000080
  52 #define PSR_A_BIT       0x00000100
  53 #define PSR_E_BIT       0x00000200
  54 #define PSR_J_BIT       0x01000000
  55 #define PSR_Q_BIT       0x08000000
  56 #define PSR_V_BIT       0x10000000
  57 #define PSR_C_BIT       0x20000000
  58 #define PSR_Z_BIT       0x40000000
  59 #define PSR_N_BIT       0x80000000
  60
  61 /*
  62  * Groups of PSR bits
  63  */
  64 #define PSR_f           0xff000000      /* Flags                */
  65 #define PSR_s           0x00ff0000      /* Status               */
  66 #define PSR_x           0x0000ff00      /* Extension            */
  67 #define PSR_c           0x000000ff      /* Control              */
  68
  69 /*
  70  * ARMv7 groups of APSR bits
  71  */
  72 #define PSR_ISET_MASK   0x01000010      /* ISA state (J, T) mask */
  73 #define PSR_IT_MASK     0x0600fc00      /* If-Then execution state mask */
  74 #define PSR_ENDIAN_MASK 0x00000200      /* Endianness state mask */
  75
  76 /*
  77  * Default endianness state
  78  */
  79 #ifdef CONFIG_CPU_ENDIAN_BE8
  80 #define PSR_ENDSTATE    PSR_E_BIT
  81 #else
  82 #define PSR_ENDSTATE    0
  83 #endif
  84
  85 #ifndef __ASSEMBLY__
  86
  87 /*
  88  * This struct defines the way the registers are stored on the
  89  * stack during a system call.  Note that sizeof(struct pt_regs)
  90  * has to be a multiple of 8.
  91  */
  92 struct pt_regs {
  93         long uregs[18];
  94 };
  95
  96 #define ARM_cpsr        uregs[16]
  97 #define ARM_pc          uregs[15]
  98 #define ARM_lr          uregs[14]
  99 #define ARM_sp          uregs[13]
 100 #define ARM_ip          uregs[12]
 101 #define ARM_fp          uregs[11]
 102 #define ARM_r10         uregs[10]
 103 #define ARM_r9          uregs[9]
 104 #define ARM_r8          uregs[8]
 105 #define ARM_r7          uregs[7]
 106 #define ARM_r6          uregs[6]
 107 #define ARM_r5          uregs[5]
 108 #define ARM_r4          uregs[4]
 109 #define ARM_r3          uregs[3]
 110 #define ARM_r2          uregs[2]
 111 #define ARM_r1          uregs[1]
 112 #define ARM_r0          uregs[0]
 113 #define ARM_ORIG_r0     uregs[17]
 114
 115 #ifdef __KERNEL__
 116
 117 #define user_mode(regs) \
 118         (((regs)->ARM_cpsr & 0xf) == 0)
 119
 120 #ifdef CONFIG_ARM_THUMB
 121 #define thumb_mode(regs) \
 122         (((regs)->ARM_cpsr & PSR_T_BIT))
 123 #else
 124 #define thumb_mode(regs) (0)
 125 #endif
 126
 127 #define isa_mode(regs) \
 128         ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
 129          (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
 130
 131 #define processor_mode(regs) \
 132         ((regs)->ARM_cpsr & MODE_MASK)
 133
 134 #define interrupts_enabled(regs) \
 135         (!((regs)->ARM_cpsr & PSR_I_BIT))
 136
 137 #define fast_interrupts_enabled(regs) \
 138         (!((regs)->ARM_cpsr & PSR_F_BIT))
 139
 140 /* Are the current registers suitable for user mode?
 141  * (used to maintain security in signal handlers)
 142  */
 143 static inline int valid_user_regs(struct pt_regs *regs)
 144 {
 145         if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) {
 146                 regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
 147                 return 1;
 148         }
 149
 150         /*
 151          * Force CPSR to something logical...
 152          */
 153         regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT;
 154         if (!(elf_hwcap & HWCAP_26BIT))
 155                 regs->ARM_cpsr |= USR_MODE;
 156
 157         return 0;
 158 }
 159
 160 #define instruction_pointer(regs)       (regs)->ARM_pc
 161
 162 #ifdef CONFIG_SMP
 163 extern unsigned long profile_pc(struct pt_regs *regs);
 164 #else
 165 #define profile_pc(regs) instruction_pointer(regs)
 166 #endif
 167
 168 #define predicate(x)            ((x) & 0xf0000000)
 169 #define PREDICATE_ALWAYS        0xe0000000
 170
 171 #endif /* __KERNEL__ */
 172
 173 #endif /* __ASSEMBLY__ */
 174
 175 #endif
 176