drivers/staging/gma500/psb_irq.c

   1 /**************************************************************************
   2  * Copyright (c) 2007, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
  19  * develop this driver.
  20  *
  21  **************************************************************************/
  22 /*
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include "psb_drv.h"
  27 #include "psb_reg.h"
  28 #include "psb_intel_reg.h"
  29 #include "psb_powermgmt.h"
  30
  31
  32 /*
  33  * inline functions
  34  */
  35
  36 static inline u32
  37 psb_pipestat(int pipe)
  38 {
  39         if (pipe == 0)
  40                 return PIPEASTAT;
  41         if (pipe == 1)
  42                 return PIPEBSTAT;
  43         if (pipe == 2)
  44                 return PIPECSTAT;
  45         BUG();
  46 }
  47
  48 static inline u32
  49 mid_pipe_event(int pipe)
  50 {
  51         if (pipe == 0)
  52                 return _PSB_PIPEA_EVENT_FLAG;
  53         if (pipe == 1)
  54                 return _MDFLD_PIPEB_EVENT_FLAG;
  55         if (pipe == 2)
  56                 return _MDFLD_PIPEC_EVENT_FLAG;
  57         BUG();
  58 }
  59
  60 static inline u32
  61 mid_pipe_vsync(int pipe)
  62 {
  63         if (pipe == 0)
  64                 return _PSB_VSYNC_PIPEA_FLAG;
  65         if (pipe == 1)
  66                 return _PSB_VSYNC_PIPEB_FLAG;
  67         if (pipe == 2)
  68                 return _MDFLD_PIPEC_VBLANK_FLAG;
  69         BUG();
  70 }
  71
  72 static inline u32
  73 mid_pipeconf(int pipe)
  74 {
  75         if (pipe == 0)
  76                 return PIPEACONF;
  77         if (pipe == 1)
  78                 return PIPEBCONF;
  79         if (pipe == 2)
  80                 return PIPECCONF;
  81         BUG();
  82 }
  83
  84 void
  85 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
  86 {
  87         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  88                 u32 reg = psb_pipestat(pipe);
  89                 dev_priv->pipestat[pipe] |= mask;
  90                 /* Enable the interrupt, clear any pending status */
  91                 if (gma_power_begin(dev_priv->dev, false)) {
  92                         u32 writeVal = PSB_RVDC32(reg);
  93                         writeVal |= (mask | (mask >> 16));
  94                         PSB_WVDC32(writeVal, reg);
  95                         (void) PSB_RVDC32(reg);
  96                         gma_power_end(dev_priv->dev);
  97                 }
  98         }
  99 }
 100
 101 void
 102 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
 103 {
 104         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 105                 u32 reg = psb_pipestat(pipe);
 106                 dev_priv->pipestat[pipe] &= ~mask;
 107                 if (gma_power_begin(dev_priv->dev, false)) {
 108                         u32 writeVal = PSB_RVDC32(reg);
 109                         writeVal &= ~mask;
 110                         PSB_WVDC32(writeVal, reg);
 111                         (void) PSB_RVDC32(reg);
 112                         gma_power_end(dev_priv->dev);
 113                 }
 114         }
 115 }
 116
 117 void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 118 {
 119         if (gma_power_begin(dev_priv->dev, false)) {
 120                 u32 pipe_event = mid_pipe_event(pipe);
 121                 dev_priv->vdc_irq_mask |= pipe_event;
 122                 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 123                 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 124                 gma_power_end(dev_priv->dev);
 125         }
 126 }
 127
 128 void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 129 {
 130         if (dev_priv->pipestat[pipe] == 0) {
 131                 if (gma_power_begin(dev_priv->dev, false)) {
 132                         u32 pipe_event = mid_pipe_event(pipe);
 133                         dev_priv->vdc_irq_mask &= ~pipe_event;
 134                         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 135                         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 136                         gma_power_end(dev_priv->dev);
 137                 }
 138         }
 139 }
 140
 141 /**
 142  * Display controller interrupt handler for vsync/vblank.
 143  *
 144  */
 145 static void mid_vblank_handler(struct drm_device *dev, uint32_t pipe)
 146 {
 147         drm_handle_vblank(dev, pipe);
 148 }
 149
 150
 151 /**
 152  * Display controller interrupt handler for pipe event.
 153  *
 154  */
 155 #define WAIT_STATUS_CLEAR_LOOP_COUNT 0xffff
 156 static void mid_pipe_event_handler(struct drm_device *dev, uint32_t pipe)
 157 {
 158         struct drm_psb_private *dev_priv =
 159             (struct drm_psb_private *) dev->dev_private;
 160
 161         uint32_t pipe_stat_val = 0;
 162         uint32_t pipe_stat_reg = psb_pipestat(pipe);
 163         uint32_t pipe_enable = dev_priv->pipestat[pipe];
 164         uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
 165         uint32_t i = 0;
 166
 167         spin_lock(&dev_priv->irqmask_lock);
 168
 169         pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
 170         pipe_stat_val &= pipe_enable | pipe_status;
 171         pipe_stat_val &= pipe_stat_val >> 16;
 172
 173         spin_unlock(&dev_priv->irqmask_lock);
 174
 175         /* clear the 2nd level interrupt status bits */
 176         /**
 177         * FIXME: shouldn't use while loop here. However, the interrupt
 178         * status 'sticky' bits cannot be cleared by setting '1' to that
 179         * bit once...
 180         */
 181         for (i = 0; i < WAIT_STATUS_CLEAR_LOOP_COUNT; i++) {
 182                 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
 183                 (void) PSB_RVDC32(pipe_stat_reg);
 184
 185                 if ((PSB_RVDC32(pipe_stat_reg) & pipe_status) == 0)
 186                         break;
 187         }
 188
 189         if (i == WAIT_STATUS_CLEAR_LOOP_COUNT)
 190                 DRM_ERROR("%s, can't clear the status bits in pipe_stat_reg, its value = 0x%x.\n",
 191                         __func__, PSB_RVDC32(pipe_stat_reg));
 192
 193         if (pipe_stat_val & PIPE_VBLANK_STATUS)
 194                 mid_vblank_handler(dev, pipe);
 195
 196         if (pipe_stat_val & PIPE_TE_STATUS)
 197                 drm_handle_vblank(dev, pipe);
 198 }
 199
 200 /*
 201  * Display controller interrupt handler.
 202  */
 203 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
 204 {
 205         if (vdc_stat & _PSB_PIPEA_EVENT_FLAG)
 206                 mid_pipe_event_handler(dev, 0);
 207 }
 208
 209 irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
 210 {
 211         struct drm_device *dev = (struct drm_device *) arg;
 212         struct drm_psb_private *dev_priv =
 213             (struct drm_psb_private *) dev->dev_private;
 214
 215         uint32_t vdc_stat, dsp_int = 0, sgx_int = 0;
 216         int handled = 0;
 217
 218         spin_lock(&dev_priv->irqmask_lock);
 219
 220         vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
 221
 222         if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG) {
 223                 PSB_DEBUG_IRQ("Got DISP interrupt\n");
 224                 dsp_int = 1;
 225         }
 226
 227         if (vdc_stat & _PSB_IRQ_SGX_FLAG) {
 228                 PSB_DEBUG_IRQ("Got SGX interrupt\n");
 229                 sgx_int = 1;
 230         }
 231         if (vdc_stat & _PSB_IRQ_MSVDX_FLAG)
 232                 PSB_DEBUG_IRQ("Got MSVDX interrupt\n");
 233
 234         if (vdc_stat & _LNC_IRQ_TOPAZ_FLAG)
 235                 PSB_DEBUG_IRQ("Got TOPAZ interrupt\n");
 236
 237
 238         vdc_stat &= dev_priv->vdc_irq_mask;
 239         spin_unlock(&dev_priv->irqmask_lock);
 240
 241         if (dsp_int && gma_power_is_on(dev)) {
 242                 psb_vdc_interrupt(dev, vdc_stat);
 243                 handled = 1;
 244         }
 245
 246         if (sgx_int) {
 247                 /* Not expected - we have it masked, shut it up */
 248                 u32 s, s2;
 249                 s = PSB_RSGX32(PSB_CR_EVENT_STATUS);
 250                 s2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
 251                 PSB_WSGX32(s, PSB_CR_EVENT_HOST_CLEAR);
 252                 PSB_WSGX32(s2, PSB_CR_EVENT_HOST_CLEAR2);
 253                 /* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
 254                    we may as well poll even if we add that ! */
 255                 handled = 1;
 256         }
 257
 258         PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
 259         (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
 260         DRM_READMEMORYBARRIER();
 261
 262         if (!handled)
 263                 return IRQ_NONE;
 264
 265         return IRQ_HANDLED;
 266 }
 267
 268 void psb_irq_preinstall(struct drm_device *dev)
 269 {
 270         struct drm_psb_private *dev_priv =
 271             (struct drm_psb_private *) dev->dev_private;
 272         unsigned long irqflags;
 273
 274         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 275
 276         if (gma_power_is_on(dev))
 277                 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 278         if (dev->vblank_enabled[0])
 279                 dev_priv->vdc_irq_mask |= _PSB_PIPEA_EVENT_FLAG;
 280         if (dev->vblank_enabled[1])
 281                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
 282         if (dev->vblank_enabled[2])
 283                 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
 284
 285         /*This register is safe even if display island is off*/
 286         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 287         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 288 }
 289
 290 int psb_irq_postinstall(struct drm_device *dev)
 291 {
 292         struct drm_psb_private *dev_priv =
 293             (struct drm_psb_private *) dev->dev_private;
 294         unsigned long irqflags;
 295
 296         PSB_DEBUG_ENTRY("\n");
 297
 298         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 299
 300         /* This register is safe even if display island is off */
 301         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 302         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 303
 304         if (dev->vblank_enabled[0])
 305                 psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 306         else
 307                 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 308
 309         if (dev->vblank_enabled[1])
 310                 psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 311         else
 312                 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 313
 314         if (dev->vblank_enabled[2])
 315                 psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
 316         else
 317                 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
 318
 319         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 320         return 0;
 321 }
 322
 323 void psb_irq_uninstall(struct drm_device *dev)
 324 {
 325         struct drm_psb_private *dev_priv =
 326             (struct drm_psb_private *) dev->dev_private;
 327         unsigned long irqflags;
 328
 329         PSB_DEBUG_ENTRY("\n");
 330
 331         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 332
 333         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 334
 335         if (dev->vblank_enabled[0])
 336                 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
 337
 338         if (dev->vblank_enabled[1])
 339                 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
 340
 341         if (dev->vblank_enabled[2])
 342                 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
 343
 344         dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
 345                                   _PSB_IRQ_MSVDX_FLAG |
 346                                   _LNC_IRQ_TOPAZ_FLAG;
 347
 348         /* These two registers are safe even if display island is off */
 349         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 350         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 351
 352         wmb();
 353
 354         /* This register is safe even if display island is off */
 355         PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
 356         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 357 }
 358
 359 void psb_irq_turn_on_dpst(struct drm_device *dev)
 360 {
 361         struct drm_psb_private *dev_priv =
 362                 (struct drm_psb_private *) dev->dev_private;
 363         u32 hist_reg;
 364         u32 pwm_reg;
 365
 366         if (gma_power_begin(dev, false)) {
 367                 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
 368                 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
 369                 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
 370                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 371
 372                 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
 373                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 374                 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
 375                                                 | PWM_PHASEIN_INT_ENABLE,
 376                                                            PWM_CONTROL_LOGIC);
 377                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 378
 379                 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 380
 381                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 382                 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
 383                                                         HISTOGRAM_INT_CONTROL);
 384                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 385                 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
 386                                                         PWM_CONTROL_LOGIC);
 387
 388                 gma_power_end(dev);
 389         }
 390 }
 391
 392 int psb_irq_enable_dpst(struct drm_device *dev)
 393 {
 394         struct drm_psb_private *dev_priv =
 395                 (struct drm_psb_private *) dev->dev_private;
 396         unsigned long irqflags;
 397
 398         PSB_DEBUG_ENTRY("\n");
 399
 400         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 401
 402         /* enable DPST */
 403         mid_enable_pipe_event(dev_priv, 0);
 404         psb_irq_turn_on_dpst(dev);
 405
 406         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 407         return 0;
 408 }
 409
 410 void psb_irq_turn_off_dpst(struct drm_device *dev)
 411 {
 412         struct drm_psb_private *dev_priv =
 413             (struct drm_psb_private *) dev->dev_private;
 414         u32 hist_reg;
 415         u32 pwm_reg;
 416
 417         if (gma_power_begin(dev, false)) {
 418                 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
 419                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 420
 421                 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 422
 423                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 424                 PSB_WVDC32(pwm_reg & !(PWM_PHASEIN_INT_ENABLE),
 425                                                         PWM_CONTROL_LOGIC);
 426                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 427
 428                 gma_power_end(dev);
 429         }
 430 }
 431
 432 int psb_irq_disable_dpst(struct drm_device *dev)
 433 {
 434         struct drm_psb_private *dev_priv =
 435             (struct drm_psb_private *) dev->dev_private;
 436         unsigned long irqflags;
 437
 438         PSB_DEBUG_ENTRY("\n");
 439
 440         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 441
 442         mid_disable_pipe_event(dev_priv, 0);
 443         psb_irq_turn_off_dpst(dev);
 444
 445         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 446
 447         return 0;
 448 }
 449
 450 #ifdef PSB_FIXME
 451 static int psb_vblank_do_wait(struct drm_device *dev,
 452                               unsigned int *sequence, atomic_t *counter)
 453 {
 454         unsigned int cur_vblank;
 455         int ret = 0;
 456         DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
 457                     (((cur_vblank = atomic_read(counter))
 458                       - *sequence) <= (1 << 23)));
 459         *sequence = cur_vblank;
 460
 461         return ret;
 462 }
 463 #endif
 464
 465 /*
 466  * It is used to enable VBLANK interrupt
 467  */
 468 int psb_enable_vblank(struct drm_device *dev, int pipe)
 469 {
 470         struct drm_psb_private *dev_priv = dev->dev_private;
 471         unsigned long irqflags;
 472         uint32_t reg_val = 0;
 473         uint32_t pipeconf_reg = mid_pipeconf(pipe);
 474
 475         PSB_DEBUG_ENTRY("\n");
 476
 477         if (gma_power_begin(dev, false)) {
 478                 reg_val = REG_READ(pipeconf_reg);
 479                 gma_power_end(dev);
 480         }
 481
 482         if (!(reg_val & PIPEACONF_ENABLE))
 483                 return -EINVAL;
 484
 485         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 486
 487         mid_enable_pipe_event(dev_priv, pipe);
 488         psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 489
 490         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 491
 492         return 0;
 493 }
 494
 495 /*
 496  * It is used to disable VBLANK interrupt
 497  */
 498 void psb_disable_vblank(struct drm_device *dev, int pipe)
 499 {
 500         struct drm_psb_private *dev_priv = dev->dev_private;
 501         unsigned long irqflags;
 502
 503         PSB_DEBUG_ENTRY("\n");
 504
 505         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 506
 507         mid_disable_pipe_event(dev_priv, pipe);
 508         psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 509
 510         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 511 }
 512
 513 /* Called from drm generic code, passed a 'crtc', which
 514  * we use as a pipe index
 515  */
 516 u32 psb_get_vblank_counter(struct drm_device *dev, int pipe)
 517 {
 518         uint32_t high_frame = PIPEAFRAMEHIGH;
 519         uint32_t low_frame = PIPEAFRAMEPIXEL;
 520         uint32_t pipeconf_reg = PIPEACONF;
 521         uint32_t reg_val = 0;
 522         uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
 523
 524         switch (pipe) {
 525         case 0:
 526                 break;
 527         case 1:
 528                 high_frame = PIPEBFRAMEHIGH;
 529                 low_frame = PIPEBFRAMEPIXEL;
 530                 pipeconf_reg = PIPEBCONF;
 531                 break;
 532         case 2:
 533                 high_frame = PIPECFRAMEHIGH;
 534                 low_frame = PIPECFRAMEPIXEL;
 535                 pipeconf_reg = PIPECCONF;
 536                 break;
 537         default:
 538                 DRM_ERROR("%s, invalded pipe.\n", __func__);
 539                 return 0;
 540         }
 541
 542         if (!gma_power_begin(dev, false))
 543                 return 0;
 544
 545         reg_val = REG_READ(pipeconf_reg);
 546
 547         if (!(reg_val & PIPEACONF_ENABLE)) {
 548                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n",
 549                                                                 pipe);
 550                 goto psb_get_vblank_counter_exit;
 551         }
 552
 553         /*
 554          * High & low register fields aren't synchronized, so make sure
 555          * we get a low value that's stable across two reads of the high
 556          * register.
 557          */
 558         do {
 559                 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 560                          PIPE_FRAME_HIGH_SHIFT);
 561                 low =  ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 562                         PIPE_FRAME_LOW_SHIFT);
 563                 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 564                          PIPE_FRAME_HIGH_SHIFT);
 565         } while (high1 != high2);
 566
 567         count = (high1 << 8) | low;
 568
 569 psb_get_vblank_counter_exit:
 570
 571         gma_power_end(dev);
 572
 573         return count;
 574 }
 575