2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
33 #define ATHEROS_VENDOR_ID 0x168c
34 #define AR5416_DEVID_PCI 0x0023
35 #define AR5416_DEVID_PCIE 0x0024
36 #define AR9160_DEVID_PCI 0x0027
37 #define AR9280_DEVID_PCI 0x0029
38 #define AR9280_DEVID_PCIE 0x002a
39 #define AR9285_DEVID_PCIE 0x002b
40 #define AR5416_AR9100_DEVID 0x000b
41 #define AR_SUBVENDOR_ID_NOG 0x0e11
42 #define AR_SUBVENDOR_ID_NEW_A 0x7065
43 #define AR5416_MAGIC 0x19641014
45 #define AR5416_DEVID_AR9287_PCI 0x002D
46 #define AR5416_DEVID_AR9287_PCIE 0x002E
48 /* Register read/write primitives */
49 #define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val))
50 #define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg))
52 #define SM(_v, _f) (((_v) << _f##_S) & _f)
53 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
54 #define REG_RMW(_a, _r, _set, _clr) \
55 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
56 #define REG_RMW_FIELD(_a, _r, _f, _v) \
58 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
59 #define REG_SET_BIT(_a, _r, _f) \
60 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
61 #define REG_CLR_BIT(_a, _r, _f) \
62 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
64 #define DO_DELAY(x) do { \
65 if ((++(x) % 64) == 0) \
69 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
71 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
72 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
73 INI_RA((iniarray), r, (column))); \
78 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
79 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
80 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
81 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
82 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
83 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
84 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
86 #define AR_GPIOD_MASK 0x00001FFF
87 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
89 #define BASE_ACTIVATE_DELAY 100
90 #define RTC_PLL_SETTLE_DELAY 1000
91 #define COEF_SCALE_S 24
92 #define HT40_CHANNEL_CENTER_SHIFT 10
94 #define ATH9K_ANTENNA0_CHAINMASK 0x1
95 #define ATH9K_ANTENNA1_CHAINMASK 0x2
97 #define ATH9K_NUM_DMA_DEBUG_REGS 8
98 #define ATH9K_NUM_QUEUES 10
100 #define MAX_RATE_POWER 63
101 #define AH_WAIT_TIMEOUT 100000 /* (us) */
102 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
103 #define AH_TIME_QUANTUM 10
104 #define AR_KEYTABLE_SIZE 128
105 #define POWER_UP_TIME 200000
106 #define SPUR_RSSI_THRESH 40
108 #define CAB_TIMEOUT_VAL 10
109 #define BEACON_TIMEOUT_VAL 10
110 #define MIN_BEACON_TIMEOUT_VAL 1
113 #define INIT_CONFIG_STATUS 0x00000000
114 #define INIT_RSSI_THR 0x00000700
115 #define INIT_BCON_CNTRL_REG 0x00000000
117 #define TU_TO_USEC(_tu) ((_tu) << 10)
122 ATH9K_MODE_11NA_HT20
,
123 ATH9K_MODE_11NG_HT20
,
124 ATH9K_MODE_11NA_HT40PLUS
,
125 ATH9K_MODE_11NA_HT40MINUS
,
126 ATH9K_MODE_11NG_HT40PLUS
,
127 ATH9K_MODE_11NG_HT40MINUS
,
131 enum ath9k_ant_setting
{
132 ATH9K_ANT_VARIABLE
= 0,
138 ATH9K_HW_CAP_MIC_AESCCM
= BIT(0),
139 ATH9K_HW_CAP_MIC_CKIP
= BIT(1),
140 ATH9K_HW_CAP_MIC_TKIP
= BIT(2),
141 ATH9K_HW_CAP_CIPHER_AESCCM
= BIT(3),
142 ATH9K_HW_CAP_CIPHER_CKIP
= BIT(4),
143 ATH9K_HW_CAP_CIPHER_TKIP
= BIT(5),
144 ATH9K_HW_CAP_VEOL
= BIT(6),
145 ATH9K_HW_CAP_BSSIDMASK
= BIT(7),
146 ATH9K_HW_CAP_MCAST_KEYSEARCH
= BIT(8),
147 ATH9K_HW_CAP_HT
= BIT(9),
148 ATH9K_HW_CAP_GTT
= BIT(10),
149 ATH9K_HW_CAP_FASTCC
= BIT(11),
150 ATH9K_HW_CAP_RFSILENT
= BIT(12),
151 ATH9K_HW_CAP_CST
= BIT(13),
152 ATH9K_HW_CAP_ENHANCEDPM
= BIT(14),
153 ATH9K_HW_CAP_AUTOSLEEP
= BIT(15),
154 ATH9K_HW_CAP_4KB_SPLITTRANS
= BIT(16),
157 enum ath9k_capability_type
{
158 ATH9K_CAP_CIPHER
= 0,
160 ATH9K_CAP_TKIP_SPLIT
,
163 ATH9K_CAP_MCAST_KEYSRCH
,
167 struct ath9k_hw_capabilities
{
168 u32 hw_caps
; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
169 DECLARE_BITMAP(wireless_modes
, ATH9K_MODE_MAX
); /* ATH9K_MODE_* */
172 u16 low_5ghz_chan
, high_5ghz_chan
;
173 u16 low_2ghz_chan
, high_2ghz_chan
;
177 u16 tx_triglevel_max
;
184 struct ath9k_ops_config
{
185 int dma_beacon_response_time
;
186 int sw_beacon_response_time
;
187 int additional_swba_backoff
;
189 int cwm_ignore_extcca
;
190 u8 pcie_powersave_enable
;
200 enum ath9k_ant_setting diversity_control
;
201 u16 antenna_switch_swap
;
202 int serialize_regmode
;
203 bool intr_mitigation
;
204 #define SPUR_DISABLE 0
205 #define SPUR_ENABLE_IOCTL 1
206 #define SPUR_ENABLE_EEPROM 2
207 #define AR_EEPROM_MODAL_SPURS 5
208 #define AR_SPUR_5413_1 1640
209 #define AR_SPUR_5413_2 1200
210 #define AR_NO_SPUR 0x8000
211 #define AR_BASE_FREQ_2GHZ 2300
212 #define AR_BASE_FREQ_5GHZ 4900
213 #define AR_SPUR_FEEQ_BOUND_HT40 19
214 #define AR_SPUR_FEEQ_BOUND_HT20 10
216 u16 spurchans
[AR_EEPROM_MODAL_SPURS
][2];
220 ATH9K_INT_RX
= 0x00000001,
221 ATH9K_INT_RXDESC
= 0x00000002,
222 ATH9K_INT_RXNOFRM
= 0x00000008,
223 ATH9K_INT_RXEOL
= 0x00000010,
224 ATH9K_INT_RXORN
= 0x00000020,
225 ATH9K_INT_TX
= 0x00000040,
226 ATH9K_INT_TXDESC
= 0x00000080,
227 ATH9K_INT_TIM_TIMER
= 0x00000100,
228 ATH9K_INT_TXURN
= 0x00000800,
229 ATH9K_INT_MIB
= 0x00001000,
230 ATH9K_INT_RXPHY
= 0x00004000,
231 ATH9K_INT_RXKCM
= 0x00008000,
232 ATH9K_INT_SWBA
= 0x00010000,
233 ATH9K_INT_BMISS
= 0x00040000,
234 ATH9K_INT_BNR
= 0x00100000,
235 ATH9K_INT_TIM
= 0x00200000,
236 ATH9K_INT_DTIM
= 0x00400000,
237 ATH9K_INT_DTIMSYNC
= 0x00800000,
238 ATH9K_INT_GPIO
= 0x01000000,
239 ATH9K_INT_CABEND
= 0x02000000,
240 ATH9K_INT_TSFOOR
= 0x04000000,
241 ATH9K_INT_GENTIMER
= 0x08000000,
242 ATH9K_INT_CST
= 0x10000000,
243 ATH9K_INT_GTT
= 0x20000000,
244 ATH9K_INT_FATAL
= 0x40000000,
245 ATH9K_INT_GLOBAL
= 0x80000000,
246 ATH9K_INT_BMISC
= ATH9K_INT_TIM
|
251 ATH9K_INT_COMMON
= ATH9K_INT_RXNOFRM
|
263 ATH9K_INT_NOCARD
= 0xffffffff
266 #define CHANNEL_CW_INT 0x00002
267 #define CHANNEL_CCK 0x00020
268 #define CHANNEL_OFDM 0x00040
269 #define CHANNEL_2GHZ 0x00080
270 #define CHANNEL_5GHZ 0x00100
271 #define CHANNEL_PASSIVE 0x00200
272 #define CHANNEL_DYN 0x00400
273 #define CHANNEL_HALF 0x04000
274 #define CHANNEL_QUARTER 0x08000
275 #define CHANNEL_HT20 0x10000
276 #define CHANNEL_HT40PLUS 0x20000
277 #define CHANNEL_HT40MINUS 0x40000
279 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
280 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
281 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
282 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
283 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
284 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
285 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
286 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
287 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
288 #define CHANNEL_ALL \
297 struct ath9k_channel
{
298 struct ieee80211_channel
*chan
;
303 bool oneTimeCalsDone
;
306 int16_t rawNoiseFloor
;
309 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
310 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
311 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
312 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
313 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
314 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
315 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
316 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
317 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
318 #define IS_CHAN_A_5MHZ_SPACED(_c) \
319 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
320 (((_c)->channel % 20) != 0) && \
321 (((_c)->channel % 10) != 0))
323 /* These macros check chanmode and not channelFlags */
324 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
325 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
326 ((_c)->chanmode == CHANNEL_G_HT20))
327 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
328 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
329 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
330 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
331 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
333 enum ath9k_power_mode
{
336 ATH9K_PM_NETWORK_SLEEP
,
340 enum ath9k_tp_scale
{
341 ATH9K_TP_SCALE_MAX
= 0,
349 SER_REG_MODE_OFF
= 0,
351 SER_REG_MODE_AUTO
= 2,
354 struct ath9k_beacon_state
{
358 #define ATH9K_BEACON_PERIOD 0x0000ffff
359 #define ATH9K_BEACON_ENA 0x00800000
360 #define ATH9K_BEACON_RESET_TSF 0x01000000
361 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
364 u16 bs_cfpmaxduration
;
367 u16 bs_bmissthreshold
;
368 u32 bs_sleepduration
;
369 u32 bs_tsfoor_threshold
;
372 struct chan_centers
{
379 ATH9K_RESET_POWER_ON
,
384 struct ath9k_hw_version
{
395 /* Generic TSF timer definitions */
397 #define ATH_MAX_GEN_TIMER 16
399 #define AR_GENTMR_BIT(_index) (1 << (_index))
402 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
403 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
405 #define debruijn32 0x077CB531UL
407 struct ath_gen_timer_configuration
{
414 struct ath_gen_timer
{
415 void (*trigger
)(void *arg
);
416 void (*overflow
)(void *arg
);
421 struct ath_gen_timer_table
{
422 u32 gen_timer_index
[32];
423 struct ath_gen_timer
*timers
[ATH_MAX_GEN_TIMER
];
425 unsigned long timer_bits
;
431 struct ath_softc
*ah_sc
;
432 struct ath9k_hw_version hw_version
;
433 struct ath9k_ops_config config
;
434 struct ath9k_hw_capabilities caps
;
435 struct ath9k_channel channels
[38];
436 struct ath9k_channel
*curchan
;
439 struct ar5416_eeprom_def def
;
440 struct ar5416_eeprom_4k map4k
;
441 struct ar9287_eeprom map9287
;
443 const struct eeprom_ops
*eep_ops
;
444 enum ath9k_eep_map eep_map
;
448 u8 macaddr
[ETH_ALEN
];
457 enum nl80211_iftype opmode
;
458 enum ath9k_power_mode power_mode
;
460 struct ath9k_nfcal_hist nfCalHist
[NUM_NF_READINGS
];
461 struct ath9k_pacal_info pacal_info
;
462 struct ar5416Stats stats
;
463 struct ath9k_tx_queue_info txq
[ATH9K_NUM_TX_QUEUES
];
465 int16_t curchan_rad_index
;
467 u32 txok_interrupt_mask
;
468 u32 txerr_interrupt_mask
;
469 u32 txdesc_interrupt_mask
;
470 u32 txeol_interrupt_mask
;
471 u32 txurn_interrupt_mask
;
476 enum ath9k_cal_types supp_cals
;
477 struct ath9k_cal_list iq_caldata
;
478 struct ath9k_cal_list adcgain_caldata
;
479 struct ath9k_cal_list adcdc_calinitdata
;
480 struct ath9k_cal_list adcdc_caldata
;
481 struct ath9k_cal_list
*cal_list
;
482 struct ath9k_cal_list
*cal_list_last
;
483 struct ath9k_cal_list
*cal_list_curr
;
484 #define totalPowerMeasI meas0.unsign
485 #define totalPowerMeasQ meas1.unsign
486 #define totalIqCorrMeas meas2.sign
487 #define totalAdcIOddPhase meas0.unsign
488 #define totalAdcIEvenPhase meas1.unsign
489 #define totalAdcQOddPhase meas2.unsign
490 #define totalAdcQEvenPhase meas3.unsign
491 #define totalAdcDcOffsetIOddPhase meas0.sign
492 #define totalAdcDcOffsetIEvenPhase meas1.sign
493 #define totalAdcDcOffsetQOddPhase meas2.sign
494 #define totalAdcDcOffsetQEvenPhase meas3.sign
496 u32 unsign
[AR5416_MAX_CHAINS
];
497 int32_t sign
[AR5416_MAX_CHAINS
];
500 u32 unsign
[AR5416_MAX_CHAINS
];
501 int32_t sign
[AR5416_MAX_CHAINS
];
504 u32 unsign
[AR5416_MAX_CHAINS
];
505 int32_t sign
[AR5416_MAX_CHAINS
];
508 u32 unsign
[AR5416_MAX_CHAINS
];
509 int32_t sign
[AR5416_MAX_CHAINS
];
513 u32 sta_id1_defaults
;
519 } enable_32kHz_clock
;
522 u32
*analogBank0Data
;
523 u32
*analogBank1Data
;
524 u32
*analogBank2Data
;
525 u32
*analogBank3Data
;
526 u32
*analogBank6Data
;
527 u32
*analogBank6TPCData
;
528 u32
*analogBank7Data
;
532 int16_t txpower_indexoffset
;
543 struct ar5416AniState
*curani
;
544 struct ar5416AniState ani
[255];
545 int totalSizeDesired
[5];
549 enum ath9k_ani_cmd ani_function
;
552 enum ath9k_ht_extprotspacing extprotspacing
;
556 u32 originalGain
[22];
561 struct ar5416IniArray iniModes
;
562 struct ar5416IniArray iniCommon
;
563 struct ar5416IniArray iniBank0
;
564 struct ar5416IniArray iniBB_RfGain
;
565 struct ar5416IniArray iniBank1
;
566 struct ar5416IniArray iniBank2
;
567 struct ar5416IniArray iniBank3
;
568 struct ar5416IniArray iniBank6
;
569 struct ar5416IniArray iniBank6TPC
;
570 struct ar5416IniArray iniBank7
;
571 struct ar5416IniArray iniAddac
;
572 struct ar5416IniArray iniPcieSerdes
;
573 struct ar5416IniArray iniModesAdditional
;
574 struct ar5416IniArray iniModesRxGain
;
575 struct ar5416IniArray iniModesTxGain
;
577 u32 intr_gen_timer_trigger
;
578 u32 intr_gen_timer_thresh
;
579 struct ath_gen_timer_table hw_gen_timers
;
582 /* Initialization, Detach, Reset */
583 const char *ath9k_hw_probe(u16 vendorid
, u16 devid
);
584 void ath9k_hw_detach(struct ath_hw
*ah
);
585 int ath9k_hw_init(struct ath_hw
*ah
);
586 void ath9k_hw_rf_free(struct ath_hw
*ah
);
587 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
588 bool bChannelChange
);
589 void ath9k_hw_fill_cap_info(struct ath_hw
*ah
);
590 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
591 u32 capability
, u32
*result
);
592 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
593 u32 capability
, u32 setting
, int *status
);
595 /* Key Cache Management */
596 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
);
597 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
);
598 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
599 const struct ath9k_keyval
*k
,
601 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
);
603 /* GPIO / RFKILL / Antennae */
604 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
);
605 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
);
606 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
608 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
);
609 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
);
610 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
);
611 bool ath9k_hw_setantennaswitch(struct ath_hw
*ah
,
612 enum ath9k_ant_setting settings
,
613 struct ath9k_channel
*chan
,
614 u8
*tx_chainmask
, u8
*rx_chainmask
,
617 /* General Operation */
618 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
);
619 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
);
620 bool ath9k_get_channel_edges(struct ath_hw
*ah
, u16 flags
, u16
*low
, u16
*high
);
621 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
622 const struct ath_rate_table
*rates
,
623 u32 frameLen
, u16 rateix
, bool shortPreamble
);
624 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
625 struct ath9k_channel
*chan
,
626 struct chan_centers
*centers
);
627 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
);
628 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
);
629 bool ath9k_hw_phy_disable(struct ath_hw
*ah
);
630 bool ath9k_hw_disable(struct ath_hw
*ah
);
631 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
);
632 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
);
633 void ath9k_hw_setopmode(struct ath_hw
*ah
);
634 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
);
635 void ath9k_hw_setbssidmask(struct ath_softc
*sc
);
636 void ath9k_hw_write_associd(struct ath_softc
*sc
);
637 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
);
638 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
);
639 void ath9k_hw_reset_tsf(struct ath_hw
*ah
);
640 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
);
641 bool ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
);
642 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
, enum ath9k_ht_macmode mode
);
643 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
);
644 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
645 const struct ath9k_beacon_state
*bs
);
646 bool ath9k_hw_setpower(struct ath_hw
*ah
,
647 enum ath9k_power_mode mode
);
648 void ath9k_hw_configpcipowersave(struct ath_hw
*ah
, int restore
);
650 /* Interrupt Handling */
651 bool ath9k_hw_intrpend(struct ath_hw
*ah
);
652 bool ath9k_hw_getisr(struct ath_hw
*ah
, enum ath9k_int
*masked
);
653 enum ath9k_int
ath9k_hw_set_interrupts(struct ath_hw
*ah
, enum ath9k_int ints
);
655 /* Generic hw timer primitives */
656 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
657 void (*trigger
)(void *),
658 void (*overflow
)(void *),
661 void ath_gen_timer_start(struct ath_hw
*ah
, struct ath_gen_timer
*timer
,
662 u32 timer_next
, u32 timer_period
);
663 void ath_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
664 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
);
665 void ath_gen_timer_isr(struct ath_hw
*hw
);
666 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
);
668 #define ATH_PCIE_CAP_LINK_CTRL 0x70
669 #define ATH_PCIE_CAP_LINK_L0S 1
670 #define ATH_PCIE_CAP_LINK_L1 2
672 void ath_pcie_aspm_disable(struct ath_softc
*sc
);