arch/x86/boot/cpucheck.c

   1 /* -*- linux-c -*- ------------------------------------------------------- *
   2  *
   3  *   Copyright (C) 1991, 1992 Linus Torvalds
   4  *   Copyright 2007 rPath, Inc. - All Rights Reserved
   5  *
   6  *   This file is part of the Linux kernel, and is made available under
   7  *   the terms of the GNU General Public License version 2.
   8  *
   9  * ----------------------------------------------------------------------- */
  10
  11 /*
  12  * Check for obligatory CPU features and abort if the features are not
  13  * present.  This code should be compilable as 16-, 32- or 64-bit
  14  * code, so be very careful with types and inline assembly.
  15  *
  16  * This code should not contain any messages; that requires an
  17  * additional wrapper.
  18  *
  19  * As written, this code is not safe for inclusion into the kernel
  20  * proper (after FPU initialization, in particular).
  21  */
  22
  23 #ifdef _SETUP
  24 # include "boot.h"
  25 # include "bitops.h"
  26 #endif
  27 #include <linux/types.h>
  28 #include <asm/cpufeature.h>
  29 #include <asm/processor-flags.h>
  30 #include <asm/required-features.h>
  31 #include <asm/msr-index.h>
  32
  33 struct cpu_features cpu;
  34 static u32 cpu_vendor[3];
  35 static u32 err_flags[NCAPINTS];
  36
  37 static const int req_level = CONFIG_X86_MINIMUM_CPU_FAMILY;
  38
  39 static const u32 req_flags[NCAPINTS] =
  40 {
  41         REQUIRED_MASK0,
  42         REQUIRED_MASK1,
  43         REQUIRED_MASK2,
  44         REQUIRED_MASK3,
  45         REQUIRED_MASK4,
  46         REQUIRED_MASK5,
  47         REQUIRED_MASK6,
  48         REQUIRED_MASK7,
  49 };
  50
  51 #define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a))
  52
  53 static int is_amd(void)
  54 {
  55         return cpu_vendor[0] == A32('A', 'u', 't', 'h') &&
  56                cpu_vendor[1] == A32('e', 'n', 't', 'i') &&
  57                cpu_vendor[2] == A32('c', 'A', 'M', 'D');
  58 }
  59
  60 static int is_centaur(void)
  61 {
  62         return cpu_vendor[0] == A32('C', 'e', 'n', 't') &&
  63                cpu_vendor[1] == A32('a', 'u', 'r', 'H') &&
  64                cpu_vendor[2] == A32('a', 'u', 'l', 's');
  65 }
  66
  67 static int is_transmeta(void)
  68 {
  69         return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
  70                cpu_vendor[1] == A32('i', 'n', 'e', 'T') &&
  71                cpu_vendor[2] == A32('M', 'x', '8', '6');
  72 }
  73
  74 static int has_fpu(void)
  75 {
  76         u16 fcw = -1, fsw = -1;
  77         u32 cr0;
  78
  79         asm("movl %%cr0,%0" : "=r" (cr0));
  80         if (cr0 & (X86_CR0_EM|X86_CR0_TS)) {
  81                 cr0 &= ~(X86_CR0_EM|X86_CR0_TS);
  82                 asm volatile("movl %0,%%cr0" : : "r" (cr0));
  83         }
  84
  85         asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
  86                      : "+m" (fsw), "+m" (fcw));
  87
  88         return fsw == 0 && (fcw & 0x103f) == 0x003f;
  89 }
  90
  91 static int has_eflag(u32 mask)
  92 {
  93         u32 f0, f1;
  94
  95         asm("pushfl ; "
  96             "pushfl ; "
  97             "popl %0 ; "
  98             "movl %0,%1 ; "
  99             "xorl %2,%1 ; "
 100             "pushl %1 ; "
 101             "popfl ; "
 102             "pushfl ; "
 103             "popl %1 ; "
 104             "popfl"
 105             : "=&r" (f0), "=&r" (f1)
 106             : "ri" (mask));
 107
 108         return !!((f0^f1) & mask);
 109 }
 110
 111 static void get_flags(void)
 112 {
 113         u32 max_intel_level, max_amd_level;
 114         u32 tfms;
 115
 116         if (has_fpu())
 117                 set_bit(X86_FEATURE_FPU, cpu.flags);
 118
 119         if (has_eflag(X86_EFLAGS_ID)) {
 120                 asm("cpuid"
 121                     : "=a" (max_intel_level),
 122                       "=b" (cpu_vendor[0]),
 123                       "=d" (cpu_vendor[1]),
 124                       "=c" (cpu_vendor[2])
 125                     : "a" (0));
 126
 127                 if (max_intel_level >= 0x00000001 &&
 128                     max_intel_level <= 0x0000ffff) {
 129                         asm("cpuid"
 130                             : "=a" (tfms),
 131                               "=c" (cpu.flags[4]),
 132                               "=d" (cpu.flags[0])
 133                             : "a" (0x00000001)
 134                             : "ebx");
 135                         cpu.level = (tfms >> 8) & 15;
 136                         cpu.model = (tfms >> 4) & 15;
 137                         if (cpu.level >= 6)
 138                                 cpu.model += ((tfms >> 16) & 0xf) << 4;
 139                 }
 140
 141                 asm("cpuid"
 142                     : "=a" (max_amd_level)
 143                     : "a" (0x80000000)
 144                     : "ebx", "ecx", "edx");
 145
 146                 if (max_amd_level >= 0x80000001 &&
 147                     max_amd_level <= 0x8000ffff) {
 148                         u32 eax = 0x80000001;
 149                         asm("cpuid"
 150                             : "+a" (eax),
 151                               "=c" (cpu.flags[6]),
 152                               "=d" (cpu.flags[1])
 153                             : : "ebx");
 154                 }
 155         }
 156 }
 157
 158 /* Returns a bitmask of which words we have error bits in */
 159 static int check_flags(void)
 160 {
 161         u32 err;
 162         int i;
 163
 164         err = 0;
 165         for (i = 0; i < NCAPINTS; i++) {
 166                 err_flags[i] = req_flags[i] & ~cpu.flags[i];
 167                 if (err_flags[i])
 168                         err |= 1 << i;
 169         }
 170
 171         return err;
 172 }
 173
 174 /*
 175  * Returns -1 on error.
 176  *
 177  * *cpu_level is set to the current CPU level; *req_level to the required
 178  * level.  x86-64 is considered level 64 for this purpose.
 179  *
 180  * *err_flags_ptr is set to the flags error array if there are flags missing.
 181  */
 182 int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr)
 183 {
 184         int err;
 185
 186         memset(&cpu.flags, 0, sizeof cpu.flags);
 187         cpu.level = 3;
 188
 189         if (has_eflag(X86_EFLAGS_AC))
 190                 cpu.level = 4;
 191
 192         get_flags();
 193         err = check_flags();
 194
 195         if (test_bit(X86_FEATURE_LM, cpu.flags))
 196                 cpu.level = 64;
 197
 198         if (err == 0x01 &&
 199             !(err_flags[0] &
 200               ~((1 << X86_FEATURE_XMM)|(1 << X86_FEATURE_XMM2))) &&
 201             is_amd()) {
 202                 /* If this is an AMD and we're only missing SSE+SSE2, try to
 203                    turn them on */
 204
 205                 u32 ecx = MSR_K7_HWCR;
 206                 u32 eax, edx;
 207
 208                 asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
 209                 eax &= ~(1 << 15);
 210                 asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
 211
 212                 get_flags();    /* Make sure it really did something */
 213                 err = check_flags();
 214         } else if (err == 0x01 &&
 215                    !(err_flags[0] & ~(1 << X86_FEATURE_CX8)) &&
 216                    is_centaur() && cpu.model >= 6) {
 217                 /* If this is a VIA C3, we might have to enable CX8
 218                    explicitly */
 219
 220                 u32 ecx = MSR_VIA_FCR;
 221                 u32 eax, edx;
 222
 223                 asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
 224                 eax |= (1<<1)|(1<<7);
 225                 asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
 226
 227                 set_bit(X86_FEATURE_CX8, cpu.flags);
 228                 err = check_flags();
 229         } else if (err == 0x01 && is_transmeta()) {
 230                 /* Transmeta might have masked feature bits in word 0 */
 231
 232                 u32 ecx = 0x80860004;
 233                 u32 eax, edx;
 234                 u32 level = 1;
 235
 236                 asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
 237                 asm("wrmsr" : : "a" (~0), "d" (edx), "c" (ecx));
 238                 asm("cpuid"
 239                     : "+a" (level), "=d" (cpu.flags[0])
 240                     : : "ecx", "ebx");
 241                 asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
 242
 243                 err = check_flags();
 244         }
 245
 246         if (err_flags_ptr)
 247                 *err_flags_ptr = err ? err_flags : NULL;
 248         if (cpu_level_ptr)
 249                 *cpu_level_ptr = cpu.level;
 250         if (req_level_ptr)
 251                 *req_level_ptr = req_level;
 252
 253         return (cpu.level < req_level || err) ? -1 : 0;
 254 }