2 * linux/arch/arm/mach-omap2/mcbsp.c
4 * Copyright (C) 2008 Instituto Nokia de Tecnologia
5 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Multichannel mode not supported.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
21 #include <mach/irqs.h>
25 #include <plat/mcbsp.h>
27 static void omap2_mcbsp2_mux_setup(void)
29 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX
);
30 omap_cfg_reg(R14_24XX_MCBSP2_FSX
);
31 omap_cfg_reg(W15_24XX_MCBSP2_DR
);
32 omap_cfg_reg(V15_24XX_MCBSP2_DX
);
33 omap_cfg_reg(V14_24XX_GPIO117
);
35 * TODO: Need to add MUX settings for OMAP 2430 SDP
39 static void omap2_mcbsp_request(unsigned int id
)
41 if (cpu_is_omap2420() && (id
== OMAP_MCBSP2
))
42 omap2_mcbsp2_mux_setup();
45 static struct omap_mcbsp_ops omap2_mcbsp_ops
= {
46 .request
= omap2_mcbsp_request
,
49 #ifdef CONFIG_ARCH_OMAP2420
50 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata
[] = {
52 .phys_base
= OMAP24XX_MCBSP1_BASE
,
53 .dma_rx_sync
= OMAP24XX_DMA_MCBSP1_RX
,
54 .dma_tx_sync
= OMAP24XX_DMA_MCBSP1_TX
,
55 .rx_irq
= INT_24XX_MCBSP1_IRQ_RX
,
56 .tx_irq
= INT_24XX_MCBSP1_IRQ_TX
,
57 .ops
= &omap2_mcbsp_ops
,
60 .phys_base
= OMAP24XX_MCBSP2_BASE
,
61 .dma_rx_sync
= OMAP24XX_DMA_MCBSP2_RX
,
62 .dma_tx_sync
= OMAP24XX_DMA_MCBSP2_TX
,
63 .rx_irq
= INT_24XX_MCBSP2_IRQ_RX
,
64 .tx_irq
= INT_24XX_MCBSP2_IRQ_TX
,
65 .ops
= &omap2_mcbsp_ops
,
68 #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
69 #define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
71 #define omap2420_mcbsp_pdata NULL
72 #define OMAP2420_MCBSP_PDATA_SZ 0
73 #define OMAP2420_MCBSP_REG_NUM 0
76 #ifdef CONFIG_ARCH_OMAP2430
77 static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata
[] = {
79 .phys_base
= OMAP24XX_MCBSP1_BASE
,
80 .dma_rx_sync
= OMAP24XX_DMA_MCBSP1_RX
,
81 .dma_tx_sync
= OMAP24XX_DMA_MCBSP1_TX
,
82 .rx_irq
= INT_24XX_MCBSP1_IRQ_RX
,
83 .tx_irq
= INT_24XX_MCBSP1_IRQ_TX
,
84 .ops
= &omap2_mcbsp_ops
,
87 .phys_base
= OMAP24XX_MCBSP2_BASE
,
88 .dma_rx_sync
= OMAP24XX_DMA_MCBSP2_RX
,
89 .dma_tx_sync
= OMAP24XX_DMA_MCBSP2_TX
,
90 .rx_irq
= INT_24XX_MCBSP2_IRQ_RX
,
91 .tx_irq
= INT_24XX_MCBSP2_IRQ_TX
,
92 .ops
= &omap2_mcbsp_ops
,
95 .phys_base
= OMAP2430_MCBSP3_BASE
,
96 .dma_rx_sync
= OMAP24XX_DMA_MCBSP3_RX
,
97 .dma_tx_sync
= OMAP24XX_DMA_MCBSP3_TX
,
98 .rx_irq
= INT_24XX_MCBSP3_IRQ_RX
,
99 .tx_irq
= INT_24XX_MCBSP3_IRQ_TX
,
100 .ops
= &omap2_mcbsp_ops
,
103 .phys_base
= OMAP2430_MCBSP4_BASE
,
104 .dma_rx_sync
= OMAP24XX_DMA_MCBSP4_RX
,
105 .dma_tx_sync
= OMAP24XX_DMA_MCBSP4_TX
,
106 .rx_irq
= INT_24XX_MCBSP4_IRQ_RX
,
107 .tx_irq
= INT_24XX_MCBSP4_IRQ_TX
,
108 .ops
= &omap2_mcbsp_ops
,
111 .phys_base
= OMAP2430_MCBSP5_BASE
,
112 .dma_rx_sync
= OMAP24XX_DMA_MCBSP5_RX
,
113 .dma_tx_sync
= OMAP24XX_DMA_MCBSP5_TX
,
114 .rx_irq
= INT_24XX_MCBSP5_IRQ_RX
,
115 .tx_irq
= INT_24XX_MCBSP5_IRQ_TX
,
116 .ops
= &omap2_mcbsp_ops
,
119 #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
120 #define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
122 #define omap2430_mcbsp_pdata NULL
123 #define OMAP2430_MCBSP_PDATA_SZ 0
124 #define OMAP2430_MCBSP_REG_NUM 0
127 #ifdef CONFIG_ARCH_OMAP3
128 static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata
[] = {
130 .phys_base
= OMAP34XX_MCBSP1_BASE
,
131 .dma_rx_sync
= OMAP24XX_DMA_MCBSP1_RX
,
132 .dma_tx_sync
= OMAP24XX_DMA_MCBSP1_TX
,
133 .rx_irq
= INT_24XX_MCBSP1_IRQ_RX
,
134 .tx_irq
= INT_24XX_MCBSP1_IRQ_TX
,
135 .ops
= &omap2_mcbsp_ops
,
139 .phys_base
= OMAP34XX_MCBSP2_BASE
,
140 .phys_base_st
= OMAP34XX_MCBSP2_ST_BASE
,
141 .dma_rx_sync
= OMAP24XX_DMA_MCBSP2_RX
,
142 .dma_tx_sync
= OMAP24XX_DMA_MCBSP2_TX
,
143 .rx_irq
= INT_24XX_MCBSP2_IRQ_RX
,
144 .tx_irq
= INT_24XX_MCBSP2_IRQ_TX
,
145 .ops
= &omap2_mcbsp_ops
,
146 .buffer_size
= 0x3FF,
149 .phys_base
= OMAP34XX_MCBSP3_BASE
,
150 .phys_base_st
= OMAP34XX_MCBSP3_ST_BASE
,
151 .dma_rx_sync
= OMAP24XX_DMA_MCBSP3_RX
,
152 .dma_tx_sync
= OMAP24XX_DMA_MCBSP3_TX
,
153 .rx_irq
= INT_24XX_MCBSP3_IRQ_RX
,
154 .tx_irq
= INT_24XX_MCBSP3_IRQ_TX
,
155 .ops
= &omap2_mcbsp_ops
,
159 .phys_base
= OMAP34XX_MCBSP4_BASE
,
160 .dma_rx_sync
= OMAP24XX_DMA_MCBSP4_RX
,
161 .dma_tx_sync
= OMAP24XX_DMA_MCBSP4_TX
,
162 .rx_irq
= INT_24XX_MCBSP4_IRQ_RX
,
163 .tx_irq
= INT_24XX_MCBSP4_IRQ_TX
,
164 .ops
= &omap2_mcbsp_ops
,
168 .phys_base
= OMAP34XX_MCBSP5_BASE
,
169 .dma_rx_sync
= OMAP24XX_DMA_MCBSP5_RX
,
170 .dma_tx_sync
= OMAP24XX_DMA_MCBSP5_TX
,
171 .rx_irq
= INT_24XX_MCBSP5_IRQ_RX
,
172 .tx_irq
= INT_24XX_MCBSP5_IRQ_TX
,
173 .ops
= &omap2_mcbsp_ops
,
177 #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
178 #define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
180 #define omap34xx_mcbsp_pdata NULL
181 #define OMAP34XX_MCBSP_PDATA_SZ 0
182 #define OMAP34XX_MCBSP_REG_NUM 0
185 static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata
[] = {
187 .phys_base
= OMAP44XX_MCBSP1_BASE
,
188 .dma_rx_sync
= OMAP44XX_DMA_MCBSP1_RX
,
189 .dma_tx_sync
= OMAP44XX_DMA_MCBSP1_TX
,
190 .tx_irq
= OMAP44XX_IRQ_MCBSP1
,
191 .ops
= &omap2_mcbsp_ops
,
194 .phys_base
= OMAP44XX_MCBSP2_BASE
,
195 .dma_rx_sync
= OMAP44XX_DMA_MCBSP2_RX
,
196 .dma_tx_sync
= OMAP44XX_DMA_MCBSP2_TX
,
197 .tx_irq
= OMAP44XX_IRQ_MCBSP2
,
198 .ops
= &omap2_mcbsp_ops
,
201 .phys_base
= OMAP44XX_MCBSP3_BASE
,
202 .dma_rx_sync
= OMAP44XX_DMA_MCBSP3_RX
,
203 .dma_tx_sync
= OMAP44XX_DMA_MCBSP3_TX
,
204 .tx_irq
= OMAP44XX_IRQ_MCBSP3
,
205 .ops
= &omap2_mcbsp_ops
,
208 .phys_base
= OMAP44XX_MCBSP4_BASE
,
209 .dma_rx_sync
= OMAP44XX_DMA_MCBSP4_RX
,
210 .dma_tx_sync
= OMAP44XX_DMA_MCBSP4_TX
,
211 .tx_irq
= OMAP44XX_IRQ_MCBSP4
,
212 .ops
= &omap2_mcbsp_ops
,
215 #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata)
216 #define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
218 static int __init
omap2_mcbsp_init(void)
220 if (cpu_is_omap2420()) {
221 omap_mcbsp_count
= OMAP2420_MCBSP_PDATA_SZ
;
222 omap_mcbsp_cache_size
= OMAP2420_MCBSP_REG_NUM
* sizeof(u16
);
223 } else if (cpu_is_omap2430()) {
224 omap_mcbsp_count
= OMAP2430_MCBSP_PDATA_SZ
;
225 omap_mcbsp_cache_size
= OMAP2430_MCBSP_REG_NUM
* sizeof(u32
);
226 } else if (cpu_is_omap34xx()) {
227 omap_mcbsp_count
= OMAP34XX_MCBSP_PDATA_SZ
;
228 omap_mcbsp_cache_size
= OMAP34XX_MCBSP_REG_NUM
* sizeof(u32
);
229 } else if (cpu_is_omap44xx()) {
230 omap_mcbsp_count
= OMAP44XX_MCBSP_PDATA_SZ
;
231 omap_mcbsp_cache_size
= OMAP44XX_MCBSP_REG_NUM
* sizeof(u32
);
234 mcbsp_ptr
= kzalloc(omap_mcbsp_count
* sizeof(struct omap_mcbsp
*),
239 if (cpu_is_omap2420())
240 omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata
,
241 OMAP2420_MCBSP_PDATA_SZ
);
242 if (cpu_is_omap2430())
243 omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata
,
244 OMAP2430_MCBSP_PDATA_SZ
);
245 if (cpu_is_omap34xx())
246 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata
,
247 OMAP34XX_MCBSP_PDATA_SZ
);
248 if (cpu_is_omap44xx())
249 omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata
,
250 OMAP44XX_MCBSP_PDATA_SZ
);
252 return omap_mcbsp_init();
254 arch_initcall(omap2_mcbsp_init
);