arch/arm/mach-omap2/mailbox.c

   1 /*
   2  * Mailbox reservation modules for OMAP2/3
   3  *
   4  * Copyright (C) 2006-2009 Nokia Corporation
   5  * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
   6  *        and  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/io.h>
  18 #include <plat/mailbox.h>
  19 #include <mach/irqs.h>
  20
  21 #define DRV_NAME "omap2-mailbox"
  22
  23 #define MAILBOX_REVISION                0x000
  24 #define MAILBOX_SYSCONFIG               0x010
  25 #define MAILBOX_SYSSTATUS               0x014
  26 #define MAILBOX_MESSAGE(m)              (0x040 + 4 * (m))
  27 #define MAILBOX_FIFOSTATUS(m)           (0x080 + 4 * (m))
  28 #define MAILBOX_MSGSTATUS(m)            (0x0c0 + 4 * (m))
  29 #define MAILBOX_IRQSTATUS(u)            (0x100 + 8 * (u))
  30 #define MAILBOX_IRQENABLE(u)            (0x104 + 8 * (u))
  31
  32 #define OMAP4_MAILBOX_IRQSTATUS(u)      (0x104 + 10 * (u))
  33 #define OMAP4_MAILBOX_IRQENABLE(u)      (0x108 + 10 * (u))
  34 #define OMAP4_MAILBOX_IRQENABLE_CLR(u)  (0x10c + 10 * (u))
  35
  36 #define MAILBOX_IRQ_NEWMSG(m)           (1 << (2 * (m)))
  37 #define MAILBOX_IRQ_NOTFULL(m)          (1 << (2 * (m) + 1))
  38
  39 /* SYSCONFIG: register bit definition */
  40 #define AUTOIDLE        (1 << 0)
  41 #define SOFTRESET       (1 << 1)
  42 #define SMARTIDLE       (2 << 3)
  43 #define OMAP4_SOFTRESET (1 << 0)
  44 #define OMAP4_NOIDLE    (1 << 2)
  45 #define OMAP4_SMARTIDLE (2 << 2)
  46
  47 /* SYSSTATUS: register bit definition */
  48 #define RESETDONE       (1 << 0)
  49
  50 #define MBOX_REG_SIZE                   0x120
  51
  52 #define OMAP4_MBOX_REG_SIZE             0x130
  53
  54 #define MBOX_NR_REGS                    (MBOX_REG_SIZE / sizeof(u32))
  55 #define OMAP4_MBOX_NR_REGS              (OMAP4_MBOX_REG_SIZE / sizeof(u32))
  56
  57 static void __iomem *mbox_base;
  58
  59 struct omap_mbox2_fifo {
  60         unsigned long msg;
  61         unsigned long fifo_stat;
  62         unsigned long msg_stat;
  63 };
  64
  65 struct omap_mbox2_priv {
  66         struct omap_mbox2_fifo tx_fifo;
  67         struct omap_mbox2_fifo rx_fifo;
  68         unsigned long irqenable;
  69         unsigned long irqstatus;
  70         u32 newmsg_bit;
  71         u32 notfull_bit;
  72         u32 ctx[OMAP4_MBOX_NR_REGS];
  73         unsigned long irqdisable;
  74 };
  75
  76 static struct clk *mbox_ick_handle;
  77
  78 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
  79                                   omap_mbox_type_t irq);
  80
  81 static inline unsigned int mbox_read_reg(size_t ofs)
  82 {
  83         return __raw_readl(mbox_base + ofs);
  84 }
  85
  86 static inline void mbox_write_reg(u32 val, size_t ofs)
  87 {
  88         __raw_writel(val, mbox_base + ofs);
  89 }
  90
  91 /* Mailbox H/W preparations */
  92 static int omap2_mbox_startup(struct omap_mbox *mbox)
  93 {
  94         u32 l;
  95         unsigned long timeout;
  96
  97         mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
  98         if (IS_ERR(mbox_ick_handle)) {
  99                 printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
 100                         PTR_ERR(mbox_ick_handle));
 101                 return PTR_ERR(mbox_ick_handle);
 102         }
 103         clk_enable(mbox_ick_handle);
 104
 105         if (cpu_is_omap44xx()) {
 106                 mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
 107                 timeout = jiffies + msecs_to_jiffies(20);
 108                 do {
 109                         l = mbox_read_reg(MAILBOX_SYSCONFIG);
 110                         if (!(l & OMAP4_SOFTRESET))
 111                                 break;
 112                 } while (!time_after(jiffies, timeout));
 113
 114                 if (l & OMAP4_SOFTRESET) {
 115                         pr_err("Can't take mailbox out of reset\n");
 116                         return -ENODEV;
 117                 }
 118         } else {
 119                 mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
 120                 timeout = jiffies + msecs_to_jiffies(20);
 121                 do {
 122                         l = mbox_read_reg(MAILBOX_SYSSTATUS);
 123                         if (l & RESETDONE)
 124                                 break;
 125                 } while (!time_after(jiffies, timeout));
 126
 127                 if (!(l & RESETDONE)) {
 128                         pr_err("Can't take mailbox out of reset\n");
 129                         return -ENODEV;
 130                 }
 131         }
 132
 133         l = mbox_read_reg(MAILBOX_REVISION);
 134         pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
 135
 136         if (cpu_is_omap44xx())
 137                 l = OMAP4_SMARTIDLE;
 138         else
 139                 l = SMARTIDLE | AUTOIDLE;
 140         mbox_write_reg(l, MAILBOX_SYSCONFIG);
 141
 142         omap2_mbox_enable_irq(mbox, IRQ_RX);
 143
 144         return 0;
 145 }
 146
 147 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
 148 {
 149         clk_disable(mbox_ick_handle);
 150         clk_put(mbox_ick_handle);
 151         mbox_ick_handle = NULL;
 152 }
 153
 154 /* Mailbox FIFO handle functions */
 155 static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
 156 {
 157         struct omap_mbox2_fifo *fifo =
 158                 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
 159         return (mbox_msg_t) mbox_read_reg(fifo->msg);
 160 }
 161
 162 static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
 163 {
 164         struct omap_mbox2_fifo *fifo =
 165                 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
 166         mbox_write_reg(msg, fifo->msg);
 167 }
 168
 169 static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
 170 {
 171         struct omap_mbox2_fifo *fifo =
 172                 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
 173         return (mbox_read_reg(fifo->msg_stat) == 0);
 174 }
 175
 176 static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
 177 {
 178         struct omap_mbox2_fifo *fifo =
 179                 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
 180         return mbox_read_reg(fifo->fifo_stat);
 181 }
 182
 183 /* Mailbox IRQ handle functions */
 184 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
 185                 omap_mbox_type_t irq)
 186 {
 187         struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
 188         u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 189
 190         l = mbox_read_reg(p->irqenable);
 191         l |= bit;
 192         mbox_write_reg(l, p->irqenable);
 193 }
 194
 195 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
 196                 omap_mbox_type_t irq)
 197 {
 198         struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
 199         u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 200         l = mbox_read_reg(p->irqdisable);
 201         l &= ~bit;
 202         mbox_write_reg(l, p->irqdisable);
 203 }
 204
 205 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
 206                 omap_mbox_type_t irq)
 207 {
 208         struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
 209         u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 210
 211         mbox_write_reg(bit, p->irqstatus);
 212
 213         /* Flush posted write for irq status to avoid spurious interrupts */
 214         mbox_read_reg(p->irqstatus);
 215 }
 216
 217 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
 218                 omap_mbox_type_t irq)
 219 {
 220         struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
 221         u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 222         u32 enable = mbox_read_reg(p->irqenable);
 223         u32 status = mbox_read_reg(p->irqstatus);
 224
 225         return (int)(enable & status & bit);
 226 }
 227
 228 static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
 229 {
 230         int i;
 231         struct omap_mbox2_priv *p = mbox->priv;
 232         int nr_regs;
 233         if (cpu_is_omap44xx())
 234                 nr_regs = OMAP4_MBOX_NR_REGS;
 235         else
 236                 nr_regs = MBOX_NR_REGS;
 237         for (i = 0; i < nr_regs; i++) {
 238                 p->ctx[i] = mbox_read_reg(i * sizeof(u32));
 239
 240                 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
 241                         i, p->ctx[i]);
 242         }
 243 }
 244
 245 static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
 246 {
 247         int i;
 248         struct omap_mbox2_priv *p = mbox->priv;
 249         int nr_regs;
 250         if (cpu_is_omap44xx())
 251                 nr_regs = OMAP4_MBOX_NR_REGS;
 252         else
 253                 nr_regs = MBOX_NR_REGS;
 254         for (i = 0; i < nr_regs; i++) {
 255                 mbox_write_reg(p->ctx[i], i * sizeof(u32));
 256
 257                 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
 258                         i, p->ctx[i]);
 259         }
 260 }
 261
 262 static struct omap_mbox_ops omap2_mbox_ops = {
 263         .type           = OMAP_MBOX_TYPE2,
 264         .startup        = omap2_mbox_startup,
 265         .shutdown       = omap2_mbox_shutdown,
 266         .fifo_read      = omap2_mbox_fifo_read,
 267         .fifo_write     = omap2_mbox_fifo_write,
 268         .fifo_empty     = omap2_mbox_fifo_empty,
 269         .fifo_full      = omap2_mbox_fifo_full,
 270         .enable_irq     = omap2_mbox_enable_irq,
 271         .disable_irq    = omap2_mbox_disable_irq,
 272         .ack_irq        = omap2_mbox_ack_irq,
 273         .is_irq         = omap2_mbox_is_irq,
 274         .save_ctx       = omap2_mbox_save_ctx,
 275         .restore_ctx    = omap2_mbox_restore_ctx,
 276 };
 277
 278 /*
 279  * MAILBOX 0: ARM -> DSP,
 280  * MAILBOX 1: ARM <- DSP.
 281  * MAILBOX 2: ARM -> IVA,
 282  * MAILBOX 3: ARM <- IVA.
 283  */
 284
 285 /* FIXME: the following structs should be filled automatically by the user id */
 286
 287 /* DSP */
 288 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
 289         .tx_fifo = {
 290                 .msg            = MAILBOX_MESSAGE(0),
 291                 .fifo_stat      = MAILBOX_FIFOSTATUS(0),
 292         },
 293         .rx_fifo = {
 294                 .msg            = MAILBOX_MESSAGE(1),
 295                 .msg_stat       = MAILBOX_MSGSTATUS(1),
 296         },
 297         .irqenable      = MAILBOX_IRQENABLE(0),
 298         .irqstatus      = MAILBOX_IRQSTATUS(0),
 299         .notfull_bit    = MAILBOX_IRQ_NOTFULL(0),
 300         .newmsg_bit     = MAILBOX_IRQ_NEWMSG(1),
 301         .irqdisable     = MAILBOX_IRQENABLE(0),
 302 };
 303
 304 struct omap_mbox mbox_dsp_info = {
 305         .name   = "dsp",
 306         .ops    = &omap2_mbox_ops,
 307         .priv   = &omap2_mbox_dsp_priv,
 308 };
 309 EXPORT_SYMBOL(mbox_dsp_info);
 310
 311 #if defined(CONFIG_ARCH_OMAP2420)
 312
 313 /* IVA */
 314 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
 315         .tx_fifo = {
 316                 .msg            = MAILBOX_MESSAGE(2),
 317                 .fifo_stat      = MAILBOX_FIFOSTATUS(2),
 318         },
 319         .rx_fifo = {
 320                 .msg            = MAILBOX_MESSAGE(3),
 321                 .msg_stat       = MAILBOX_MSGSTATUS(3),
 322         },
 323         .irqenable      = MAILBOX_IRQENABLE(3),
 324         .irqstatus      = MAILBOX_IRQSTATUS(3),
 325         .notfull_bit    = MAILBOX_IRQ_NOTFULL(2),
 326         .newmsg_bit     = MAILBOX_IRQ_NEWMSG(3),
 327         .irqdisable     = MAILBOX_IRQENABLE(3),
 328 };
 329
 330 static struct omap_mbox mbox_iva_info = {
 331         .name   = "iva",
 332         .ops    = &omap2_mbox_ops,
 333         .priv   = &omap2_mbox_iva_priv,
 334 };
 335 #endif
 336
 337 /* OMAP4 */
 338 static struct omap_mbox2_priv omap2_mbox_1_priv = {
 339         .tx_fifo = {
 340                 .msg            = MAILBOX_MESSAGE(0),
 341                 .fifo_stat      = MAILBOX_FIFOSTATUS(0),
 342         },
 343         .rx_fifo = {
 344                 .msg            = MAILBOX_MESSAGE(1),
 345                 .msg_stat       = MAILBOX_MSGSTATUS(1),
 346         },
 347         .irqenable      = OMAP4_MAILBOX_IRQENABLE(0),
 348         .irqstatus      = OMAP4_MAILBOX_IRQSTATUS(0),
 349         .notfull_bit    = MAILBOX_IRQ_NOTFULL(0),
 350         .newmsg_bit     = MAILBOX_IRQ_NEWMSG(1),
 351         .irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
 352 };
 353
 354 struct omap_mbox mbox_1_info = {
 355         .name   = "mailbox-1",
 356         .ops    = &omap2_mbox_ops,
 357         .priv   = &omap2_mbox_1_priv,
 358 };
 359 EXPORT_SYMBOL(mbox_1_info);
 360
 361 static struct omap_mbox2_priv omap2_mbox_2_priv = {
 362         .tx_fifo = {
 363                 .msg            = MAILBOX_MESSAGE(3),
 364                 .fifo_stat      = MAILBOX_FIFOSTATUS(3),
 365         },
 366         .rx_fifo = {
 367                 .msg            = MAILBOX_MESSAGE(2),
 368                 .msg_stat       = MAILBOX_MSGSTATUS(2),
 369         },
 370         .irqenable      = OMAP4_MAILBOX_IRQENABLE(0),
 371         .irqstatus      = OMAP4_MAILBOX_IRQSTATUS(0),
 372         .notfull_bit    = MAILBOX_IRQ_NOTFULL(3),
 373         .newmsg_bit     = MAILBOX_IRQ_NEWMSG(2),
 374         .irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
 375 };
 376
 377 struct omap_mbox mbox_2_info = {
 378         .name   = "mailbox-2",
 379         .ops    = &omap2_mbox_ops,
 380         .priv   = &omap2_mbox_2_priv,
 381 };
 382 EXPORT_SYMBOL(mbox_2_info);
 383
 384 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 385 {
 386         struct resource *res;
 387         int ret;
 388
 389         /* MBOX base */
 390         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 391         if (unlikely(!res)) {
 392                 dev_err(&pdev->dev, "invalid mem resource\n");
 393                 return -ENODEV;
 394         }
 395         mbox_base = ioremap(res->start, resource_size(res));
 396         if (!mbox_base)
 397                 return -ENOMEM;
 398
 399         /* DSP or IVA2 IRQ */
 400         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 401
 402         if (unlikely(!res)) {
 403                 dev_err(&pdev->dev, "invalid irq resource\n");
 404                 ret = -ENODEV;
 405                 goto err_dsp;
 406         }
 407         if (cpu_is_omap44xx()) {
 408                 mbox_1_info.irq = res->start;
 409                 ret = omap_mbox_register(&pdev->dev, &mbox_1_info);
 410         } else {
 411                 mbox_dsp_info.irq = res->start;
 412                 ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
 413         }
 414         if (ret)
 415                 goto err_dsp;
 416
 417         if (cpu_is_omap44xx()) {
 418                 mbox_2_info.irq = res->start;
 419                 ret = omap_mbox_register(&pdev->dev, &mbox_2_info);
 420                 if (ret) {
 421                         omap_mbox_unregister(&mbox_1_info);
 422                         goto err_dsp;
 423                 }
 424         }
 425 #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
 426         if (cpu_is_omap2420()) {
 427                 /* IVA IRQ */
 428                 res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 429                 if (unlikely(!res)) {
 430                         dev_err(&pdev->dev, "invalid irq resource\n");
 431                         ret = -ENODEV;
 432                         omap_mbox_unregister(&mbox_dsp_info);
 433                         goto err_dsp;
 434                 }
 435                 mbox_iva_info.irq = res->start;
 436                 ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
 437                 if (ret) {
 438                         omap_mbox_unregister(&mbox_dsp_info);
 439                         goto err_dsp;
 440                 }
 441         }
 442 #endif
 443         return 0;
 444
 445 #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
 446 err_iva1:
 447         omap_mbox_unregister(&mbox_dsp_info);
 448 #endif
 449
 450 err_dsp:
 451         iounmap(mbox_base);
 452         return ret;
 453 }
 454
 455 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
 456 {
 457 #if defined(CONFIG_ARCH_OMAP2420)
 458         if (cpu_is_omap2420())
 459                 omap_mbox_unregister(&mbox_iva_info);
 460 #endif
 461
 462         if (cpu_is_omap44xx()) {
 463                 omap_mbox_unregister(&mbox_2_info);
 464                 omap_mbox_unregister(&mbox_1_info);
 465         } else
 466                 omap_mbox_unregister(&mbox_dsp_info);
 467         iounmap(mbox_base);
 468         return 0;
 469 }
 470
 471 static struct platform_driver omap2_mbox_driver = {
 472         .probe = omap2_mbox_probe,
 473         .remove = __devexit_p(omap2_mbox_remove),
 474         .driver = {
 475                 .name = DRV_NAME,
 476         },
 477 };
 478
 479 static int __init omap2_mbox_init(void)
 480 {
 481         return platform_driver_register(&omap2_mbox_driver);
 482 }
 483
 484 static void __exit omap2_mbox_exit(void)
 485 {
 486         platform_driver_unregister(&omap2_mbox_driver);
 487 }
 488
 489 module_init(omap2_mbox_init);
 490 module_exit(omap2_mbox_exit);
 491
 492 MODULE_LICENSE("GPL v2");
 493 MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
 494 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
 495 MODULE_AUTHOR("Paul Mundt");
 496 MODULE_ALIAS("platform:"DRV_NAME);